c64ba425d1680846c715b6a4c6b4def784155cae
13 #include "targ-vals.h"
15 extern char *strrchr ();
47 PSW_MASK
= (PSW_SM_BIT
62 move_to_cr (int cr
, reg_t mask
, reg_t val
)
64 /* A MASK bit is set when the corresponding bit in the CR should
66 /* This assumes that (VAL & MASK) == 0 */
71 if ((mask
& PSW_SM_BIT
) == 0)
73 int new_sm
= (val
& PSW_SM_BIT
) != 0;
74 SET_HELD_SP (PSW_SM
, GPR (SP_IDX
)); /* save old SP */
76 SET_GPR (SP_IDX
, HELD_SP (new_sm
)); /* restore new SP */
78 if ((mask
& (PSW_ST_BIT
| PSW_FX_BIT
)) == 0)
80 if (val
& PSW_ST_BIT
&& !(val
& PSW_FX_BIT
))
82 (*d10v_callback
->printf_filtered
)
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
86 State
.exception
= SIGILL
;
89 /* keep an up-to-date psw around for tracing */
90 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
103 /* only issue an update if the register is being changed */
104 if ((State
.cregs
[cr
] & ~mask
) != val
)
105 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
110 static void trace_input_func
PARAMS ((char *name
,
115 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
117 #ifndef SIZE_INSTRUCTION
118 #define SIZE_INSTRUCTION 8
121 #ifndef SIZE_OPERANDS
122 #define SIZE_OPERANDS 18
126 #define SIZE_VALUES 13
129 #ifndef SIZE_LOCATION
130 #define SIZE_LOCATION 20
137 #ifndef SIZE_LINE_NUMBER
138 #define SIZE_LINE_NUMBER 4
142 trace_input_func (name
, in1
, in2
, in3
)
155 const char *filename
;
156 const char *functionname
;
157 unsigned int linenumber
;
160 if ((d10v_debug
& DEBUG_TRACE
) == 0)
163 switch (State
.ins_type
)
166 case INS_UNKNOWN
: type
= " ?"; break;
167 case INS_LEFT
: type
= " L"; break;
168 case INS_RIGHT
: type
= " R"; break;
169 case INS_LEFT_PARALLEL
: type
= "*L"; break;
170 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
171 case INS_LEFT_COND_TEST
: type
= "?L"; break;
172 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
173 case INS_LEFT_COND_EXE
: type
= "&L"; break;
174 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
175 case INS_LONG
: type
= " B"; break;
178 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
179 (*d10v_callback
->printf_filtered
) (d10v_callback
,
181 SIZE_PC
, (unsigned)PC
,
183 SIZE_INSTRUCTION
, name
);
188 byte_pc
= decode_pc ();
189 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
191 filename
= (const char *)0;
192 functionname
= (const char *)0;
194 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
195 &filename
, &functionname
, &linenumber
))
200 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
205 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
206 p
+= SIZE_LINE_NUMBER
+2;
211 sprintf (p
, "%s ", functionname
);
216 char *q
= strrchr (filename
, '/');
217 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
226 (*d10v_callback
->printf_filtered
) (d10v_callback
,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC
, (unsigned)PC
,
230 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
231 SIZE_INSTRUCTION
, name
);
239 for (i
= 0; i
< 3; i
++)
253 sprintf (p
, "%sr%d", comma
, OP
[i
]);
261 sprintf (p
, "%scr%d", comma
, OP
[i
]);
267 case OP_ACCUM_OUTPUT
:
268 case OP_ACCUM_REVERSE
:
269 sprintf (p
, "%sa%d", comma
, OP
[i
]);
275 sprintf (p
, "%s%d", comma
, OP
[i
]);
281 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
287 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
293 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
299 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
305 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
311 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
317 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
323 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
331 sprintf (p
, "%sf0", comma
);
334 sprintf (p
, "%sf1", comma
);
337 sprintf (p
, "%sc", comma
);
345 if ((d10v_debug
& DEBUG_VALUES
) == 0)
349 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
354 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
357 for (i
= 0; i
< 3; i
++)
363 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
369 case OP_ACCUM_OUTPUT
:
371 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
379 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
380 (uint16
) GPR (OP
[i
]));
384 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
385 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
390 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
391 (uint16
) CREG (OP
[i
]));
395 case OP_ACCUM_REVERSE
:
396 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
397 ((int)(ACC (OP
[i
]) >> 32) & 0xff),
398 ((unsigned long) ACC (OP
[i
])) & 0xffffffff);
402 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
407 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
408 (uint16
)SEXT4(OP
[i
]));
412 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
413 (uint16
)SEXT8(OP
[i
]));
417 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
418 (uint16
)SEXT3(OP
[i
]));
423 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
427 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
431 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
437 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
439 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
440 (uint16
)GPR (OP
[i
+ 1]));
445 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
455 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
463 (*d10v_callback
->flush_stdout
) (d10v_callback
);
467 do_trace_output_flush (void)
469 (*d10v_callback
->flush_stdout
) (d10v_callback
);
473 do_trace_output_finish (void)
475 (*d10v_callback
->printf_filtered
) (d10v_callback
,
476 " F0=%d F1=%d C=%d\n",
477 (State
.trace
.psw
& PSW_F0_BIT
) != 0,
478 (State
.trace
.psw
& PSW_F1_BIT
) != 0,
479 (State
.trace
.psw
& PSW_C_BIT
) != 0);
480 (*d10v_callback
->flush_stdout
) (d10v_callback
);
484 trace_output_40 (uint64 val
)
486 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
488 (*d10v_callback
->printf_filtered
) (d10v_callback
,
489 " :: %*s0x%.2x%.8lx",
492 ((int)(val
>> 32) & 0xff),
493 ((unsigned long) val
) & 0xffffffff);
494 do_trace_output_finish ();
499 trace_output_32 (uint32 val
)
501 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
503 (*d10v_callback
->printf_filtered
) (d10v_callback
,
508 do_trace_output_finish ();
513 trace_output_16 (uint16 val
)
515 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
517 (*d10v_callback
->printf_filtered
) (d10v_callback
,
522 do_trace_output_finish ();
529 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
531 (*d10v_callback
->printf_filtered
) (d10v_callback
, "\n");
532 do_trace_output_flush ();
539 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
541 (*d10v_callback
->printf_filtered
) (d10v_callback
,
545 do_trace_output_finish ();
553 #define trace_input(NAME, IN1, IN2, IN3)
554 #define trace_output(RESULT)
562 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
572 SET_GPR (OP
[0], tmp
);
573 trace_output_16 (tmp
);
581 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
584 tmp
= SEXT40 (ACC (OP
[0]));
590 if (tmp
> SEXT40(MAX32
))
592 else if (tmp
< SEXT40(MIN32
))
595 tmp
= (tmp
& MASK40
);
598 tmp
= (tmp
& MASK40
);
603 tmp
= (tmp
& MASK40
);
606 SET_ACC (OP
[0], tmp
);
607 trace_output_40 (tmp
);
614 uint16 a
= GPR (OP
[0]);
615 uint16 b
= GPR (OP
[1]);
616 uint16 tmp
= (a
+ b
);
617 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
619 SET_GPR (OP
[0], tmp
);
620 trace_output_16 (tmp
);
628 tmp
= SEXT40(ACC (OP
[0])) + (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
630 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
633 if (tmp
> SEXT40(MAX32
))
635 else if (tmp
< SEXT40(MIN32
))
638 tmp
= (tmp
& MASK40
);
641 tmp
= (tmp
& MASK40
);
642 SET_ACC (OP
[0], tmp
);
643 trace_output_40 (tmp
);
651 tmp
= SEXT40(ACC (OP
[0])) + SEXT40(ACC (OP
[1]));
653 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
656 if (tmp
> SEXT40(MAX32
))
658 else if (tmp
< SEXT40(MIN32
))
661 tmp
= (tmp
& MASK40
);
664 tmp
= (tmp
& MASK40
);
665 SET_ACC (OP
[0], tmp
);
666 trace_output_40 (tmp
);
674 uint32 a
= (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1);
675 uint32 b
= (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
676 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
679 SET_GPR (OP
[0] + 0, (tmp
>> 16));
680 SET_GPR (OP
[0] + 1, (tmp
& 0xFFFF));
681 trace_output_32 (tmp
);
688 uint16 a
= GPR (OP
[1]);
690 uint16 tmp
= (a
+ b
);
691 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
693 SET_GPR (OP
[0], tmp
);
694 trace_output_16 (tmp
);
702 tmp
= SEXT40(ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
704 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
705 SET_GPR (OP
[0] + 0, ((tmp
>> 16) & 0xffff));
706 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
707 trace_output_32 (tmp
);
715 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
717 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
718 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
719 SET_GPR (OP
[0] + 1, tmp
& 0xffff);
720 trace_output_32 (tmp
);
730 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
731 tmp
= SEXT40 (ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
732 if (tmp
> SEXT40(MAX32
))
737 else if (tmp
< SEXT40(MIN32
))
746 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
747 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
748 trace_output_32 (tmp
);
758 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
759 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
760 if (tmp
> SEXT40(MAX32
))
765 else if (tmp
< SEXT40(MIN32
))
774 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
775 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
776 trace_output_32 (tmp
);
783 uint16 a
= GPR (OP
[0]);
790 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
792 SET_GPR (OP
[0], tmp
);
793 trace_output_16 (tmp
);
800 uint16 tmp
= GPR (OP
[0]) & GPR (OP
[1]);
801 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
802 SET_GPR (OP
[0], tmp
);
803 trace_output_16 (tmp
);
810 uint16 tmp
= GPR (OP
[1]) & OP
[2];
811 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
812 SET_GPR (OP
[0], tmp
);
813 trace_output_16 (tmp
);
821 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
822 tmp
= (GPR (OP
[0]) &~(0x8000 >> OP
[1]));
823 SET_GPR (OP
[0], tmp
);
824 trace_output_16 (tmp
);
831 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
832 SET_GPR (13, PC
+ 1);
833 JMP( PC
+ SEXT8 (OP
[0]));
834 trace_output_void ();
841 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
842 SET_GPR (13, (PC
+ 1));
844 trace_output_void ();
852 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
853 tmp
= (GPR (OP
[0]) ^ (0x8000 >> OP
[1]));
854 SET_GPR (OP
[0], tmp
);
855 trace_output_16 (tmp
);
862 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
863 JMP (PC
+ SEXT8 (OP
[0]));
864 trace_output_void ();
871 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
873 trace_output_void ();
880 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
882 JMP (PC
+ SEXT8 (OP
[0]));
883 trace_output_flag ();
890 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
893 trace_output_flag ();
900 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
902 JMP (PC
+ SEXT8 (OP
[0]));
903 trace_output_flag ();
910 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
913 trace_output_flag ();
921 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
922 tmp
= (GPR (OP
[0]) | (0x8000 >> OP
[1]));
923 SET_GPR (OP
[0], tmp
);
924 trace_output_16 (tmp
);
931 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
933 SET_PSW_F0 ((GPR (OP
[0]) & (0x8000 >> OP
[1])) ? 1 : 0);
934 trace_output_flag ();
941 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
950 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
952 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(GPR (OP
[1]))) ? 1 : 0);
953 trace_output_flag ();
960 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
962 SET_PSW_F0 ((SEXT40(ACC (OP
[0])) < SEXT40(ACC (OP
[1]))) ? 1 : 0);
963 trace_output_flag ();
970 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
972 SET_PSW_F0 ((GPR (OP
[0]) == GPR (OP
[1])) ? 1 : 0);
973 trace_output_flag ();
980 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
982 SET_PSW_F0 (((ACC (OP
[0]) & MASK40
) == (ACC (OP
[1]) & MASK40
)) ? 1 : 0);
983 trace_output_flag ();
990 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
992 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
) SEXT4 (OP
[1])) ? 1 : 0);
993 trace_output_flag ();
1000 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1001 SET_PSW_F1 (PSW_F0
);
1002 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
)OP
[1]) ? 1 : 0);
1003 trace_output_flag ();
1010 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1011 SET_PSW_F1 (PSW_F0
);
1012 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)SEXT4(OP
[1])) ? 1 : 0);
1013 trace_output_flag ();
1020 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1021 SET_PSW_F1 (PSW_F0
);
1022 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(OP
[1])) ? 1 : 0);
1023 trace_output_flag ();
1030 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1031 SET_PSW_F1 (PSW_F0
);
1032 SET_PSW_F0 ((GPR (OP
[0]) < GPR (OP
[1])) ? 1 : 0);
1033 trace_output_flag ();
1040 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1041 SET_PSW_F1 (PSW_F0
);
1042 SET_PSW_F0 ((GPR (OP
[0]) < (reg_t
)OP
[1]) ? 1 : 0);
1043 trace_output_flag ();
1052 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1056 else if (OP
[1] == 1)
1065 trace_output_flag ();
1072 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1074 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1075 The conditional below is for either of the instruction pairs
1076 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1077 where the dbt instruction should be interpreted.
1079 The module `sim-break' provides a more effective mechanism for
1080 detecting GDB planted breakpoints. The code below may,
1081 eventually, be changed to use that mechanism. */
1083 if (State
.ins_type
== INS_LEFT
1084 || State
.ins_type
== INS_RIGHT
)
1086 trace_input ("dbt", OP_VOID
, OP_VOID
, OP_VOID
);
1089 SET_PSW (PSW_DM_BIT
| (PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1090 JMP (DBT_VECTOR_START
);
1091 trace_output_void ();
1095 State
.exception
= SIGTRAP
;
1103 uint16 foo
, tmp
, tmpf
;
1107 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1108 foo
= (GPR (OP
[0]) << 1) | (GPR (OP
[0] + 1) >> 15);
1109 tmp
= (int16
)foo
- (int16
)(GPR (OP
[1]));
1110 tmpf
= (foo
>= GPR (OP
[1])) ? 1 : 0;
1111 hi
= ((tmpf
== 1) ? tmp
: foo
);
1112 lo
= ((GPR (OP
[0] + 1) << 1) | tmpf
);
1113 SET_GPR (OP
[0] + 0, hi
);
1114 SET_GPR (OP
[0] + 1, lo
);
1115 trace_output_32 (((uint32
) hi
<< 16) | lo
);
1122 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1123 State
.exe
= (PSW_F0
== 0);
1124 trace_output_flag ();
1131 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1132 State
.exe
= (PSW_F0
!= 0);
1133 trace_output_flag ();
1140 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1141 State
.exe
= (PSW_F1
== 0);
1142 trace_output_flag ();
1149 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1150 State
.exe
= (PSW_F1
!= 0);
1151 trace_output_flag ();
1158 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1159 State
.exe
= (PSW_F0
== 0) & (PSW_F1
== 0);
1160 trace_output_flag ();
1167 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1168 State
.exe
= (PSW_F0
== 0) & (PSW_F1
!= 0);
1169 trace_output_flag ();
1176 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1177 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
== 0);
1178 trace_output_flag ();
1185 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1186 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
!= 0);
1187 trace_output_flag ();
1197 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1198 if (((int16
)GPR (OP
[1])) >= 0)
1199 tmp
= (GPR (OP
[1]) << 16) | GPR (OP
[1] + 1);
1201 tmp
= ~((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
1208 SET_GPR (OP
[0], (i
- 1));
1209 trace_output_16 (i
- 1);
1214 SET_GPR (OP
[0], 16);
1215 trace_output_16 (16);
1225 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1226 tmp
= SEXT40(ACC (OP
[1]));
1228 tmp
= ~tmp
& MASK40
;
1230 foo
= 0x4000000000LL
;
1235 SET_GPR (OP
[0], i
- 9);
1236 trace_output_16 (i
- 9);
1241 SET_GPR (OP
[0], 16);
1242 trace_output_16 (16);
1249 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1250 SET_GPR (13, PC
+ 1);
1252 trace_output_void ();
1259 trace_input ("jmp", OP_REG
,
1260 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1261 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1264 trace_output_void ();
1272 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1273 tmp
= RW (OP
[1] + GPR (OP
[2]));
1274 SET_GPR (OP
[0], tmp
);
1275 trace_output_16 (tmp
);
1283 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1284 tmp
= RW (GPR (OP
[1]));
1285 SET_GPR (OP
[0], tmp
);
1287 INC_ADDR (OP
[1], -2);
1288 trace_output_16 (tmp
);
1296 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1297 tmp
= RW (GPR (OP
[1]));
1298 SET_GPR (OP
[0], tmp
);
1300 INC_ADDR (OP
[1], 2);
1301 trace_output_16 (tmp
);
1309 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1310 tmp
= RW (GPR (OP
[1]));
1311 SET_GPR (OP
[0], tmp
);
1312 trace_output_16 (tmp
);
1320 uint16 addr
= GPR (OP
[2]);
1321 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1322 tmp
= RLW (OP
[1] + addr
);
1323 SET_GPR32 (OP
[0], tmp
);
1324 trace_output_32 (tmp
);
1331 uint16 addr
= GPR (OP
[1]);
1333 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1335 SET_GPR32 (OP
[0], tmp
);
1336 INC_ADDR (OP
[1], -4);
1337 trace_output_32 (tmp
);
1345 uint16 addr
= GPR (OP
[1]);
1346 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1348 SET_GPR32 (OP
[0], tmp
);
1349 INC_ADDR (OP
[1], 4);
1350 trace_output_32 (tmp
);
1357 uint16 addr
= GPR (OP
[1]);
1359 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1360 tmp
= RLW (addr
+ 0);
1361 SET_GPR32 (OP
[0], tmp
);
1362 trace_output_32 (tmp
);
1370 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1371 tmp
= SEXT8 (RB (OP
[1] + GPR (OP
[2])));
1372 SET_GPR (OP
[0], tmp
);
1373 trace_output_16 (tmp
);
1381 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1382 tmp
= SEXT8 (RB (GPR (OP
[1])));
1383 SET_GPR (OP
[0], tmp
);
1384 trace_output_16 (tmp
);
1392 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1393 tmp
= SEXT4 (OP
[1]);
1394 SET_GPR (OP
[0], tmp
);
1395 trace_output_16 (tmp
);
1403 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1405 SET_GPR (OP
[0], tmp
);
1406 trace_output_16 (tmp
);
1414 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1415 tmp
= RB (OP
[1] + GPR (OP
[2]));
1416 SET_GPR (OP
[0], tmp
);
1417 trace_output_16 (tmp
);
1425 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1426 tmp
= RB (GPR (OP
[1]));
1427 SET_GPR (OP
[0], tmp
);
1428 trace_output_16 (tmp
);
1437 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1438 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1441 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1443 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1446 tmp
+= SEXT40 (ACC (OP
[0]));
1449 if (tmp
> SEXT40(MAX32
))
1451 else if (tmp
< SEXT40(MIN32
))
1454 tmp
= (tmp
& MASK40
);
1457 tmp
= (tmp
& MASK40
);
1458 SET_ACC (OP
[0], tmp
);
1459 trace_output_40 (tmp
);
1468 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1469 tmp
= SEXT40 ((int16
) GPR (OP
[1]) * GPR (OP
[2]));
1471 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1472 tmp
= ((SEXT40 (ACC (OP
[0])) + tmp
) & MASK40
);
1473 SET_ACC (OP
[0], tmp
);
1474 trace_output_40 (tmp
);
1485 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1486 src1
= (uint16
) GPR (OP
[1]);
1487 src2
= (uint16
) GPR (OP
[2]);
1491 tmp
= ((ACC (OP
[0]) + tmp
) & MASK40
);
1492 SET_ACC (OP
[0], tmp
);
1493 trace_output_40 (tmp
);
1501 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1502 SET_PSW_F1 (PSW_F0
);
1503 if ((int16
) GPR (OP
[1]) > (int16
)GPR (OP
[0]))
1513 SET_GPR (OP
[0], tmp
);
1514 trace_output_16 (tmp
);
1523 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1524 SET_PSW_F1 (PSW_F0
);
1525 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1526 if (tmp
> SEXT40 (ACC (OP
[0])))
1528 tmp
= (tmp
& MASK40
);
1536 SET_ACC (OP
[0], tmp
);
1537 trace_output_40 (tmp
);
1545 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1546 SET_PSW_F1 (PSW_F0
);
1547 if (SEXT40 (ACC (OP
[1])) > SEXT40 (ACC (OP
[0])))
1557 SET_ACC (OP
[0], tmp
);
1558 trace_output_40 (tmp
);
1567 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1568 SET_PSW_F1 (PSW_F0
);
1569 if ((int16
)GPR (OP
[1]) < (int16
)GPR (OP
[0]))
1579 SET_GPR (OP
[0], tmp
);
1580 trace_output_16 (tmp
);
1589 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1590 SET_PSW_F1 (PSW_F0
);
1591 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1592 if (tmp
< SEXT40(ACC (OP
[0])))
1594 tmp
= (tmp
& MASK40
);
1602 SET_ACC (OP
[0], tmp
);
1603 trace_output_40 (tmp
);
1611 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1612 SET_PSW_F1 (PSW_F0
);
1613 if (SEXT40(ACC (OP
[1])) < SEXT40(ACC (OP
[0])))
1623 SET_ACC (OP
[0], tmp
);
1624 trace_output_40 (tmp
);
1633 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1634 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1637 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1639 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1642 tmp
= SEXT40(ACC (OP
[0])) - tmp
;
1645 if (tmp
> SEXT40(MAX32
))
1647 else if (tmp
< SEXT40(MIN32
))
1650 tmp
= (tmp
& MASK40
);
1654 tmp
= (tmp
& MASK40
);
1656 SET_ACC (OP
[0], tmp
);
1657 trace_output_40 (tmp
);
1666 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1667 tmp
= SEXT40 ((int16
)GPR (OP
[1]) * GPR (OP
[2]));
1669 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1670 tmp
= ((SEXT40 (ACC (OP
[0])) - tmp
) & MASK40
);
1671 SET_ACC (OP
[0], tmp
);
1672 trace_output_40 (tmp
);
1683 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1684 src1
= (uint16
) GPR (OP
[1]);
1685 src2
= (uint16
) GPR (OP
[2]);
1689 tmp
= ((ACC (OP
[0]) - tmp
) & MASK40
);
1690 SET_ACC (OP
[0], tmp
);
1691 trace_output_40 (tmp
);
1699 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1700 tmp
= GPR (OP
[0]) * GPR (OP
[1]);
1701 SET_GPR (OP
[0], tmp
);
1702 trace_output_16 (tmp
);
1711 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1712 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1715 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1717 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1720 tmp
= (tmp
& MASK40
);
1721 SET_ACC (OP
[0], tmp
);
1722 trace_output_40 (tmp
);
1731 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1732 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * GPR (OP
[2]));
1736 tmp
= (tmp
& MASK40
);
1737 SET_ACC (OP
[0], tmp
);
1738 trace_output_40 (tmp
);
1749 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1750 src1
= (uint16
) GPR (OP
[1]);
1751 src2
= (uint16
) GPR (OP
[2]);
1755 tmp
= (tmp
& MASK40
);
1756 SET_ACC (OP
[0], tmp
);
1757 trace_output_40 (tmp
);
1765 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1767 SET_GPR (OP
[0], tmp
);
1768 trace_output_16 (tmp
);
1776 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1777 tmp
= GPR32 (OP
[1]);
1778 SET_GPR32 (OP
[0], tmp
);
1779 trace_output_32 (tmp
);
1787 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1789 SET_GPR32 (OP
[0], tmp
);
1790 trace_output_32 (tmp
);
1798 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1799 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1)) & MASK40
);
1800 SET_ACC (OP
[1], tmp
);
1801 trace_output_40 (tmp
);
1809 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1811 SET_ACC (OP
[0], tmp
);
1812 trace_output_40 (tmp
);
1820 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1821 tmp
= SEXT8 (GPR (OP
[1]) & 0xff);
1822 SET_GPR (OP
[0], tmp
);
1823 trace_output_16 (tmp
);
1831 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1835 SET_GPR (OP
[0], tmp
);
1839 trace_output_16 (tmp
);
1847 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1851 SET_GPR (OP
[0], tmp
);
1855 trace_output_16 (tmp
);
1863 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1864 tmp
= ((ACC (OP
[1]) >> 32) & 0xff);
1865 SET_GPR (OP
[0], tmp
);
1866 trace_output_16 (tmp
);
1874 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1875 tmp
= (ACC (OP
[1]) >> 16);
1876 SET_GPR (OP
[0], tmp
);
1877 trace_output_16 (tmp
);
1885 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1887 SET_GPR (OP
[0], tmp
);
1888 trace_output_16 (tmp
);
1896 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1898 SET_GPR (OP
[0], tmp
);
1899 trace_output_16 (tmp
);
1907 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1908 tmp
= ((ACC (OP
[1]) & MASK32
)
1909 | ((int64
)(GPR (OP
[0]) & 0xff) << 32));
1910 SET_ACC (OP
[1], tmp
);
1911 trace_output_40 (tmp
);
1919 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1920 tmp
= ACC (OP
[1]) & 0xffff;
1921 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | tmp
) & MASK40
);
1922 SET_ACC (OP
[1], tmp
);
1923 trace_output_40 (tmp
);
1931 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1932 tmp
= ((SEXT16 (GPR (OP
[0]))) & MASK40
);
1933 SET_ACC (OP
[1], tmp
);
1934 trace_output_40 (tmp
);
1942 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1944 tmp
= SET_CREG (OP
[1], tmp
);
1945 trace_output_16 (tmp
);
1953 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1954 tmp
= (GPR (OP
[1]) & 0xff);
1955 SET_GPR (OP
[0], tmp
);
1956 trace_output_16 (tmp
);
1964 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1965 tmp
= - GPR (OP
[0]);
1966 SET_GPR (OP
[0], tmp
);
1967 trace_output_16 (tmp
);
1976 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1977 tmp
= -SEXT40(ACC (OP
[0]));
1980 if (tmp
> SEXT40(MAX32
))
1982 else if (tmp
< SEXT40(MIN32
))
1985 tmp
= (tmp
& MASK40
);
1988 tmp
= (tmp
& MASK40
);
1989 SET_ACC (OP
[0], tmp
);
1990 trace_output_40 (tmp
);
1998 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
2000 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
2001 switch (State
.ins_type
)
2004 ins_type_counters
[ (int)INS_UNKNOWN
]++;
2007 case INS_LEFT_PARALLEL
:
2008 /* Don't count a parallel op that includes a NOP as a true parallel op */
2009 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
2010 ins_type_counters
[ (int)INS_RIGHT
]++;
2011 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2015 case INS_LEFT_COND_EXE
:
2016 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2019 case INS_RIGHT_PARALLEL
:
2020 /* Don't count a parallel op that includes a NOP as a true parallel op */
2021 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
2022 ins_type_counters
[ (int)INS_LEFT
]++;
2023 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2027 case INS_RIGHT_COND_EXE
:
2028 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2032 trace_output_void ();
2040 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
2042 SET_GPR (OP
[0], tmp
);
2043 trace_output_16 (tmp
);
2051 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
2052 tmp
= (GPR (OP
[0]) | GPR (OP
[1]));
2053 SET_GPR (OP
[0], tmp
);
2054 trace_output_16 (tmp
);
2062 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2063 tmp
= (GPR (OP
[1]) | OP
[2]);
2064 SET_GPR (OP
[0], tmp
);
2065 trace_output_16 (tmp
);
2073 int shift
= SEXT3 (OP
[2]);
2075 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2078 (*d10v_callback
->printf_filtered
) (d10v_callback
,
2079 "ERROR at PC 0x%x: instruction only valid for A0\n",
2081 State
.exception
= SIGILL
;
2084 SET_PSW_F1 (PSW_F0
);
2085 tmp
= SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2091 tmp
>>= 16; /* look at bits 0:43 */
2092 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2097 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2106 SET_GPR32 (OP
[0], tmp
);
2107 trace_output_32 (tmp
);
2115 int shift
= SEXT3 (OP
[2]);
2117 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2118 SET_PSW_F1 (PSW_F0
);
2120 tmp
= SEXT40 (ACC (OP
[1])) << shift
;
2122 tmp
= SEXT40 (ACC (OP
[1])) >> -shift
;
2125 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2130 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2140 SET_GPR (OP
[0], tmp
);
2141 trace_output_16 (tmp
);
2148 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2150 SET_RPT_E (PC
+ OP
[1]);
2151 SET_RPT_C (GPR (OP
[0]));
2153 if (GPR (OP
[0]) == 0)
2155 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
2156 State
.exception
= SIGILL
;
2160 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2161 State
.exception
= SIGILL
;
2163 trace_output_void ();
2170 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2172 SET_RPT_E (PC
+ OP
[1]);
2177 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2178 State
.exception
= SIGILL
;
2182 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2183 State
.exception
= SIGILL
;
2185 trace_output_void ();
2192 trace_input ("rtd", OP_VOID
, OP_VOID
, OP_VOID
);
2193 SET_CREG (PSW_CR
, DPSW
);
2195 trace_output_void ();
2202 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2203 SET_CREG (PSW_CR
, BPSW
);
2205 trace_output_void ();
2214 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2215 tmp
= SEXT40(ACC (OP
[0])) + (SEXT40(ACC (OP
[1])) >> 16);
2218 if (tmp
> SEXT40(MAX32
))
2220 else if (tmp
< SEXT40(MIN32
))
2223 tmp
= (tmp
& MASK40
);
2226 tmp
= (tmp
& MASK40
);
2227 SET_ACC (OP
[0], tmp
);
2228 trace_output_40 (tmp
);
2236 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2237 tmp
= ((PSW_F0
== 0) ? 1 : 0);
2238 SET_GPR (OP
[0], tmp
);
2239 trace_output_16 (tmp
);
2247 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2248 tmp
= ((PSW_F0
== 1) ? 1 : 0);
2249 SET_GPR (OP
[0], tmp
);
2250 trace_output_16 (tmp
);
2257 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2259 trace_output_void ();
2267 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2268 tmp
= (GPR (OP
[0]) << (GPR (OP
[1]) & 0xf));
2269 SET_GPR (OP
[0], tmp
);
2270 trace_output_16 (tmp
);
2278 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2279 if ((GPR (OP
[1]) & 31) <= 16)
2280 tmp
= SEXT40 (ACC (OP
[0])) << (GPR (OP
[1]) & 31);
2283 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2284 State
.exception
= SIGILL
;
2290 if (tmp
> SEXT40(MAX32
))
2292 else if (tmp
< SEXT40(MIN32
))
2295 tmp
= (tmp
& MASK40
);
2298 tmp
= (tmp
& MASK40
);
2299 SET_ACC (OP
[0], tmp
);
2300 trace_output_40 (tmp
);
2308 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2309 tmp
= (GPR (OP
[0]) << OP
[1]);
2310 SET_GPR (OP
[0], tmp
);
2311 trace_output_16 (tmp
);
2323 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2324 tmp
= SEXT40(ACC (OP
[0])) << OP
[1];
2328 if (tmp
> SEXT40(MAX32
))
2330 else if (tmp
< SEXT40(MIN32
))
2333 tmp
= (tmp
& MASK40
);
2336 tmp
= (tmp
& MASK40
);
2337 SET_ACC (OP
[0], tmp
);
2338 trace_output_40 (tmp
);
2346 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2347 tmp
= ((GPR (OP
[0]) << 1) | PSW_F0
);
2348 SET_GPR (OP
[0], tmp
);
2349 trace_output_16 (tmp
);
2357 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2358 tmp
= (((int16
)(GPR (OP
[0]))) >> (GPR (OP
[1]) & 0xf));
2359 SET_GPR (OP
[0], tmp
);
2360 trace_output_16 (tmp
);
2367 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2368 if ((GPR (OP
[1]) & 31) <= 16)
2370 int64 tmp
= ((SEXT40(ACC (OP
[0])) >> (GPR (OP
[1]) & 31)) & MASK40
);
2371 SET_ACC (OP
[0], tmp
);
2372 trace_output_40 (tmp
);
2376 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2377 State
.exception
= SIGILL
;
2387 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2388 tmp
= (((int16
)(GPR (OP
[0]))) >> OP
[1]);
2389 SET_GPR (OP
[0], tmp
);
2390 trace_output_16 (tmp
);
2401 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2402 tmp
= ((SEXT40(ACC (OP
[0])) >> OP
[1]) & MASK40
);
2403 SET_ACC (OP
[0], tmp
);
2404 trace_output_40 (tmp
);
2412 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2413 tmp
= (GPR (OP
[0]) >> (GPR (OP
[1]) & 0xf));
2414 SET_GPR (OP
[0], tmp
);
2415 trace_output_16 (tmp
);
2422 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2423 if ((GPR (OP
[1]) & 31) <= 16)
2425 int64 tmp
= ((uint64
)((ACC (OP
[0]) & MASK40
) >> (GPR (OP
[1]) & 31)));
2426 SET_ACC (OP
[0], tmp
);
2427 trace_output_40 (tmp
);
2431 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2432 State
.exception
= SIGILL
;
2443 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2444 tmp
= (GPR (OP
[0]) >> OP
[1]);
2445 SET_GPR (OP
[0], tmp
);
2446 trace_output_16 (tmp
);
2457 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2458 tmp
= ((uint64
)(ACC (OP
[0]) & MASK40
) >> OP
[1]);
2459 SET_ACC (OP
[0], tmp
);
2460 trace_output_40 (tmp
);
2468 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2470 tmp
= ((GPR (OP
[0]) >> 1) | tmp
);
2471 SET_GPR (OP
[0], tmp
);
2472 trace_output_16 (tmp
);
2479 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2480 SW (OP
[1] + GPR (OP
[2]), GPR (OP
[0]));
2481 trace_output_void ();
2488 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2489 SW (GPR (OP
[1]), GPR (OP
[0]));
2490 trace_output_void ();
2497 uint16 addr
= GPR (OP
[1]) - 2;
2498 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2501 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2502 State
.exception
= SIGILL
;
2505 SW (addr
, GPR (OP
[0]));
2506 SET_GPR (OP
[1], addr
);
2507 trace_output_void ();
2514 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2515 SW (GPR (OP
[1]), GPR (OP
[0]));
2516 INC_ADDR (OP
[1], 2);
2517 trace_output_void ();
2524 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2527 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2528 State
.exception
= SIGILL
;
2531 SW (GPR (OP
[1]), GPR (OP
[0]));
2532 INC_ADDR (OP
[1], -2);
2533 trace_output_void ();
2540 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2541 SW (GPR (OP
[2])+ OP
[1] + 0, GPR (OP
[0] + 0));
2542 SW (GPR (OP
[2])+ OP
[1] + 2, GPR (OP
[0] + 1));
2543 trace_output_void ();
2550 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2551 SW (GPR (OP
[1]) + 0, GPR (OP
[0] + 0));
2552 SW (GPR (OP
[1]) + 2, GPR (OP
[0] + 1));
2553 trace_output_void ();
2560 uint16 addr
= GPR (OP
[1]) - 4;
2561 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2564 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2565 State
.exception
= SIGILL
;
2568 SW (addr
+ 0, GPR (OP
[0] + 0));
2569 SW (addr
+ 2, GPR (OP
[0] + 1));
2570 SET_GPR (OP
[1], addr
);
2571 trace_output_void ();
2578 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2579 SW (GPR (OP
[1]) + 0, GPR (OP
[0] + 0));
2580 SW (GPR (OP
[1]) + 2, GPR (OP
[0] + 1));
2581 INC_ADDR (OP
[1], 4);
2582 trace_output_void ();
2589 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2592 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2593 State
.exception
= SIGILL
;
2596 SW (GPR (OP
[1]) + 0, GPR (OP
[0] + 0));
2597 SW (GPR (OP
[1]) + 2, GPR (OP
[0] + 1));
2598 INC_ADDR (OP
[1], -4);
2599 trace_output_void ();
2606 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2607 SB (GPR (OP
[2]) + OP
[1], GPR (OP
[0]));
2608 trace_output_void ();
2615 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2616 SB (GPR (OP
[1]), GPR (OP
[0]));
2617 trace_output_void ();
2624 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2625 State
.exception
= SIG_D10V_STOP
;
2626 trace_output_void ();
2633 uint16 a
= GPR (OP
[0]);
2634 uint16 b
= GPR (OP
[1]);
2635 uint16 tmp
= (a
- b
);
2636 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2637 /* see ../common/sim-alu.h for a more extensive discussion on how to
2638 compute the carry/overflow bits. */
2640 SET_GPR (OP
[0], tmp
);
2641 trace_output_16 (tmp
);
2650 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2651 tmp
= SEXT40(ACC (OP
[0])) - (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
2654 if (tmp
> SEXT40(MAX32
))
2656 else if (tmp
< SEXT40(MIN32
))
2659 tmp
= (tmp
& MASK40
);
2662 tmp
= (tmp
& MASK40
);
2663 SET_ACC (OP
[0], tmp
);
2665 trace_output_40 (tmp
);
2675 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2676 tmp
= SEXT40(ACC (OP
[0])) - SEXT40(ACC (OP
[1]));
2679 if (tmp
> SEXT40(MAX32
))
2681 else if (tmp
< SEXT40(MIN32
))
2684 tmp
= (tmp
& MASK40
);
2687 tmp
= (tmp
& MASK40
);
2688 SET_ACC (OP
[0], tmp
);
2690 trace_output_40 (tmp
);
2699 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2700 a
= (uint32
)((GPR (OP
[0]) << 16) | GPR (OP
[0] + 1));
2701 b
= (uint32
)((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
2702 /* see ../common/sim-alu.h for a more extensive discussion on how to
2703 compute the carry/overflow bits */
2706 SET_GPR32 (OP
[0], tmp
);
2707 trace_output_32 (tmp
);
2716 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2717 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40 (ACC (OP
[2]));
2718 SET_GPR32 (OP
[0], tmp
);
2719 trace_output_32 (tmp
);
2728 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2729 tmp
= SEXT40 (ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
2730 SET_GPR32 (OP
[0], tmp
);
2731 trace_output_32 (tmp
);
2740 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2741 SET_PSW_F1 (PSW_F0
);
2742 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40(ACC (OP
[2]));
2743 if (tmp
> SEXT40(MAX32
))
2748 else if (tmp
< SEXT40(MIN32
))
2757 SET_GPR32 (OP
[0], tmp
);
2758 trace_output_32 (tmp
);
2767 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2768 SET_PSW_F1 (PSW_F0
);
2769 tmp
= SEXT40(ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
2770 if (tmp
> SEXT40(MAX32
))
2775 else if (tmp
< SEXT40(MIN32
))
2784 SET_GPR32 (OP
[0], tmp
);
2785 trace_output_32 (tmp
);
2796 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2797 /* see ../common/sim-alu.h for a more extensive discussion on how to
2798 compute the carry/overflow bits. */
2799 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2800 tmp
= ((unsigned)(unsigned16
) GPR (OP
[0])
2801 + (unsigned)(unsigned16
) ( - OP
[1]));
2802 SET_PSW_C (tmp
>= (1 << 16));
2803 SET_GPR (OP
[0], tmp
);
2804 trace_output_16 (tmp
);
2811 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2812 trace_output_void ();
2817 #if (DEBUG & DEBUG_TRAP) == 0
2819 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
2822 SET_PSW (PSW
& PSW_SM_BIT
);
2826 #else /* if debugging use trap to print registers */
2829 static int first_time
= 1;
2834 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2835 for (i
= 0; i
< 16; i
++)
2836 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2837 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2840 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2842 for (i
= 0; i
< 16; i
++)
2843 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) GPR (i
));
2845 for (i
= 0; i
< 2; i
++)
2846 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2847 ((int)(ACC (i
) >> 32) & 0xff),
2848 ((unsigned long) ACC (i
)) & 0xffffffff);
2850 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2851 PSW_F0
!= 0, PSW_F1
!= 0, PSW_C
!= 0);
2852 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2856 case 15: /* new system call trap */
2857 /* Trap 15 is used for simulating low-level I/O */
2859 unsigned32 result
= 0;
2862 /* Registers passed to trap 0 */
2864 #define FUNC GPR (4) /* function number */
2865 #define PARM1 GPR (0) /* optional parm 1 */
2866 #define PARM2 GPR (1) /* optional parm 2 */
2867 #define PARM3 GPR (2) /* optional parm 3 */
2868 #define PARM4 GPR (3) /* optional parm 3 */
2870 /* Registers set by trap 0 */
2872 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
2873 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
2874 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
2876 /* Turn a pointer in a register into a pointer into real memory. */
2878 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2882 #if !defined(__GO32__) && !defined(_WIN32)
2883 case TARGET_SYS_fork
:
2884 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2886 trace_output_16 (result
);
2890 case TARGET_SYS_getpid
:
2891 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2893 trace_output_16 (result
);
2896 case TARGET_SYS_kill
:
2897 trace_input ("<kill>", OP_R0
, OP_R1
, OP_VOID
);
2898 if (PARM1
== getpid ())
2900 trace_output_void ();
2901 State
.exception
= PARM2
;
2909 case 1: os_sig
= SIGHUP
; break;
2912 case 2: os_sig
= SIGINT
; break;
2915 case 3: os_sig
= SIGQUIT
; break;
2918 case 4: os_sig
= SIGILL
; break;
2921 case 5: os_sig
= SIGTRAP
; break;
2924 case 6: os_sig
= SIGABRT
; break;
2925 #elif defined(SIGIOT)
2926 case 6: os_sig
= SIGIOT
; break;
2929 case 7: os_sig
= SIGEMT
; break;
2932 case 8: os_sig
= SIGFPE
; break;
2935 case 9: os_sig
= SIGKILL
; break;
2938 case 10: os_sig
= SIGBUS
; break;
2941 case 11: os_sig
= SIGSEGV
; break;
2944 case 12: os_sig
= SIGSYS
; break;
2947 case 13: os_sig
= SIGPIPE
; break;
2950 case 14: os_sig
= SIGALRM
; break;
2953 case 15: os_sig
= SIGTERM
; break;
2956 case 16: os_sig
= SIGURG
; break;
2959 case 17: os_sig
= SIGSTOP
; break;
2962 case 18: os_sig
= SIGTSTP
; break;
2965 case 19: os_sig
= SIGCONT
; break;
2968 case 20: os_sig
= SIGCHLD
; break;
2969 #elif defined(SIGCLD)
2970 case 20: os_sig
= SIGCLD
; break;
2973 case 21: os_sig
= SIGTTIN
; break;
2976 case 22: os_sig
= SIGTTOU
; break;
2979 case 23: os_sig
= SIGIO
; break;
2980 #elif defined (SIGPOLL)
2981 case 23: os_sig
= SIGPOLL
; break;
2984 case 24: os_sig
= SIGXCPU
; break;
2987 case 25: os_sig
= SIGXFSZ
; break;
2990 case 26: os_sig
= SIGVTALRM
; break;
2993 case 27: os_sig
= SIGPROF
; break;
2996 case 28: os_sig
= SIGWINCH
; break;
2999 case 29: os_sig
= SIGLOST
; break;
3002 case 30: os_sig
= SIGUSR1
; break;
3005 case 31: os_sig
= SIGUSR2
; break;
3011 trace_output_void ();
3012 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
3013 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3014 State
.exception
= SIGILL
;
3018 RETVAL (kill (PARM1
, PARM2
));
3019 trace_output_16 (result
);
3024 case TARGET_SYS_execve
:
3025 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
3026 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
3027 (char **)MEMPTR (PARM3
)));
3028 trace_output_16 (result
);
3031 #ifdef TARGET_SYS_execv
3032 case TARGET_SYS_execv
:
3033 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
3034 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
3035 trace_output_16 (result
);
3039 case TARGET_SYS_pipe
:
3044 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
3046 RETVAL (pipe (host_fd
));
3047 SW (buf
, host_fd
[0]);
3048 buf
+= sizeof(uint16
);
3049 SW (buf
, host_fd
[1]);
3050 trace_output_16 (result
);
3055 #ifdef TARGET_SYS_wait
3056 case TARGET_SYS_wait
:
3059 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
3060 RETVAL (wait (&status
));
3063 trace_output_16 (result
);
3069 case TARGET_SYS_getpid
:
3070 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3072 trace_output_16 (result
);
3075 case TARGET_SYS_kill
:
3076 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
3077 trace_output_void ();
3078 State
.exception
= PARM2
;
3082 case TARGET_SYS_read
:
3083 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
3084 RETVAL (d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
3086 trace_output_16 (result
);
3089 case TARGET_SYS_write
:
3090 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
3092 RETVAL ((int)d10v_callback
->write_stdout (d10v_callback
,
3093 MEMPTR (PARM2
), PARM3
));
3095 RETVAL ((int)d10v_callback
->write (d10v_callback
, PARM1
,
3096 MEMPTR (PARM2
), PARM3
));
3097 trace_output_16 (result
);
3100 case TARGET_SYS_lseek
:
3101 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
3102 RETVAL32 (d10v_callback
->lseek (d10v_callback
, PARM1
,
3103 ((((unsigned long) PARM2
) << 16)
3104 || (unsigned long) PARM3
),
3106 trace_output_32 (result
);
3109 case TARGET_SYS_close
:
3110 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
3111 RETVAL (d10v_callback
->close (d10v_callback
, PARM1
));
3112 trace_output_16 (result
);
3115 case TARGET_SYS_open
:
3116 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
3117 RETVAL (d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
));
3118 trace_output_16 (result
);
3121 case TARGET_SYS_exit
:
3122 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
3123 State
.exception
= SIG_D10V_EXIT
;
3124 trace_output_void ();
3127 case TARGET_SYS_stat
:
3128 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
3129 /* stat system call */
3131 struct stat host_stat
;
3134 RETVAL (stat (MEMPTR (PARM1
), &host_stat
));
3138 /* The hard-coded offsets and sizes were determined by using
3139 * the D10V compiler on a test program that used struct stat.
3141 SW (buf
, host_stat
.st_dev
);
3142 SW (buf
+2, host_stat
.st_ino
);
3143 SW (buf
+4, host_stat
.st_mode
);
3144 SW (buf
+6, host_stat
.st_nlink
);
3145 SW (buf
+8, host_stat
.st_uid
);
3146 SW (buf
+10, host_stat
.st_gid
);
3147 SW (buf
+12, host_stat
.st_rdev
);
3148 SLW (buf
+16, host_stat
.st_size
);
3149 SLW (buf
+20, host_stat
.st_atime
);
3150 SLW (buf
+28, host_stat
.st_mtime
);
3151 SLW (buf
+36, host_stat
.st_ctime
);
3153 trace_output_16 (result
);
3156 case TARGET_SYS_chown
:
3157 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3158 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
3159 trace_output_16 (result
);
3162 case TARGET_SYS_chmod
:
3163 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3164 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
3165 trace_output_16 (result
);
3169 #ifdef TARGET_SYS_utime
3170 case TARGET_SYS_utime
:
3171 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3172 /* Cast the second argument to void *, to avoid type mismatch
3173 if a prototype is present. */
3174 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
3175 trace_output_16 (result
);
3181 #ifdef TARGET_SYS_time
3182 case TARGET_SYS_time
:
3183 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3184 RETVAL32 (time (PARM1
? MEMPTR (PARM1
) : NULL
));
3185 trace_output_32 (result
);
3191 d10v_callback
->error (d10v_callback
, "Unknown syscall %d", FUNC
);
3193 if ((uint16
) result
== (uint16
) -1)
3194 RETERR (d10v_callback
->get_errno(d10v_callback
));
3206 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3207 SET_PSW_F1 (PSW_F0
);;
3208 SET_PSW_F0 ((GPR (OP
[0]) & OP
[1]) ? 1 : 0);
3209 trace_output_flag ();
3216 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3217 SET_PSW_F1 (PSW_F0
);
3218 SET_PSW_F0 ((~(GPR (OP
[0])) & OP
[1]) ? 1 : 0);
3219 trace_output_flag ();
3226 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3228 trace_output_void ();
3236 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3237 tmp
= (GPR (OP
[0]) ^ GPR (OP
[1]));
3238 SET_GPR (OP
[0], tmp
);
3239 trace_output_16 (tmp
);
3247 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3248 tmp
= (GPR (OP
[1]) ^ OP
[2]);
3249 SET_GPR (OP
[0], tmp
);
3250 trace_output_16 (tmp
);
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