9 #include "sys/syscall.h"
42 static void trace_input_func
PARAMS ((char *name
,
47 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
49 static void trace_output_func
PARAMS ((enum op_types result
));
51 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
53 static int init_text_p
= 0;
54 static asection
*text
;
55 static bfd_vma text_start
;
56 static bfd_vma text_end
;
59 #ifndef SIZE_INSTRUCTION
60 #define SIZE_INSTRUCTION 8
64 #define SIZE_OPERANDS 18
68 #define SIZE_VALUES 13
72 #define SIZE_LOCATION 20
79 #ifndef SIZE_LINE_NUMBER
80 #define SIZE_LINE_NUMBER 4
84 trace_input_func (name
, in1
, in2
, in3
)
99 const char *functionname
;
100 unsigned int linenumber
;
103 if ((d10v_debug
& DEBUG_TRACE
) == 0)
106 switch (State
.ins_type
)
109 case INS_UNKNOWN
: type
= " ?"; break;
110 case INS_LEFT
: type
= " L"; break;
111 case INS_RIGHT
: type
= " R"; break;
112 case INS_LEFT_PARALLEL
: type
= "*L"; break;
113 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
114 case INS_LONG
: type
= " B"; break;
117 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
118 (*d10v_callback
->printf_filtered
) (d10v_callback
,
120 SIZE_PC
, (unsigned)PC
,
122 SIZE_INSTRUCTION
, name
);
129 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
130 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
133 text_start
= bfd_get_section_vma (exec_bfd
, s
);
134 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
140 byte_pc
= (bfd_vma
)PC
<< 2;
141 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
143 filename
= (const char *)0;
144 functionname
= (const char *)0;
146 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
147 &filename
, &functionname
, &linenumber
))
152 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
157 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
158 p
+= SIZE_LINE_NUMBER
+2;
163 sprintf (p
, "%s ", functionname
);
168 char *q
= (char *) strrchr (filename
, '/');
169 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
178 (*d10v_callback
->printf_filtered
) (d10v_callback
,
179 "0x%.*x %s: %-*.*s %-*s ",
180 SIZE_PC
, (unsigned)PC
,
182 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
183 SIZE_INSTRUCTION
, name
);
191 for (i
= 0; i
< 3; i
++)
205 sprintf (p
, "%sr%d", comma
, OP
[i
]);
213 sprintf (p
, "%scr%d", comma
, OP
[i
]);
219 case OP_ACCUM_OUTPUT
:
220 case OP_ACCUM_REVERSE
:
221 sprintf (p
, "%sa%d", comma
, OP
[i
]);
227 sprintf (p
, "%s%d", comma
, OP
[i
]);
233 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
239 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
245 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
251 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
257 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
263 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
269 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
275 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
283 sprintf (p
, "%sf0", comma
);
286 sprintf (p
, "%sf1", comma
);
289 sprintf (p
, "%sc", comma
);
297 if ((d10v_debug
& DEBUG_VALUES
) == 0)
301 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
306 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
309 for (i
= 0; i
< 3; i
++)
315 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
321 case OP_ACCUM_OUTPUT
:
323 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
331 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
332 (uint16
)State
.regs
[OP
[i
]]);
336 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
337 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
342 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
343 (uint16
)State
.cregs
[OP
[i
]]);
347 case OP_ACCUM_REVERSE
:
348 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
349 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
350 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
354 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
359 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
360 (uint16
)SEXT4(OP
[i
]));
364 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
365 (uint16
)SEXT8(OP
[i
]));
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
370 (uint16
)SEXT3(OP
[i
]));
375 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
379 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
383 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
389 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
391 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
392 (uint16
)State
.regs
[OP
[++i
]]);
396 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
397 (uint16
)State
.regs
[2]);
401 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
402 (uint16
)State
.regs
[3]);
406 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
407 (uint16
)State
.regs
[4]);
415 trace_output_func (result
)
416 enum op_types result
;
418 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
431 (uint16
)State
.regs
[OP
[0]],
432 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
437 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
439 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
445 (uint16
)State
.cregs
[OP
[0]],
446 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
451 (uint16
)State
.cregs
[OP
[1]],
452 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
456 case OP_ACCUM_OUTPUT
:
457 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
458 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
459 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
460 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
463 case OP_ACCUM_REVERSE
:
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
465 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
466 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
467 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
472 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
473 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
478 (uint16
)State
.regs
[2],
479 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
483 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
484 (uint16
)State
.regs
[2], (uint16
)State
.regs
[3],
485 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
492 #define trace_input(NAME, IN1, IN2, IN3)
493 #define trace_output(RESULT)
500 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
502 if ((int16
)(State
.regs
[OP
[0]]) < 0)
504 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
509 trace_output (OP_REG
);
518 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
520 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
522 if (State
.a
[OP
[0]] < 0 )
524 tmp
= -State
.a
[OP
[0]];
528 State
.a
[OP
[0]] = MAX32
;
529 else if (tmp
< MIN32
)
530 State
.a
[OP
[0]] = MIN32
;
532 State
.a
[OP
[0]] = tmp
& MASK40
;
535 State
.a
[OP
[0]] = tmp
& MASK40
;
540 trace_output (OP_ACCUM
);
547 uint16 tmp
= State
.regs
[OP
[0]];
548 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
549 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
550 if ( tmp
> State
.regs
[OP
[0]])
554 trace_output (OP_REG
);
562 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
564 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
568 State
.a
[OP
[0]] = MAX32
;
569 else if ( tmp
< MIN32
)
570 State
.a
[OP
[0]] = MIN32
;
572 State
.a
[OP
[0]] = tmp
& MASK40
;
575 State
.a
[OP
[0]] = tmp
& MASK40
;
576 trace_output (OP_ACCUM
);
584 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
586 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
590 State
.a
[OP
[0]] = MAX32
;
591 else if ( tmp
< MIN32
)
592 State
.a
[OP
[0]] = MIN32
;
594 State
.a
[OP
[0]] = tmp
& MASK40
;
597 State
.a
[OP
[0]] = tmp
& MASK40
;
598 trace_output (OP_ACCUM
);
606 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
607 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
609 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
611 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
615 State
.regs
[OP
[0]] = tmp
>> 16;
616 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
617 trace_output (OP_DREG
);
624 uint16 tmp
= State
.regs
[OP
[0]];
625 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
627 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
628 if ( tmp
> State
.regs
[OP
[0]])
632 trace_output (OP_REG
);
640 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
642 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
643 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
644 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
645 trace_output (OP_DREG
);
653 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
655 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
656 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
657 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
658 trace_output (OP_DREG
);
668 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
669 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
672 State
.regs
[OP
[0]] = 0x7fff;
673 State
.regs
[OP
[0]+1] = 0xffff;
676 else if (tmp
< MIN32
)
678 State
.regs
[OP
[0]] = 0x8000;
679 State
.regs
[OP
[0]+1] = 0;
684 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
685 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
688 trace_output (OP_DREG
);
698 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
699 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
702 State
.regs
[OP
[0]] = 0x7fff;
703 State
.regs
[OP
[0]+1] = 0xffff;
706 else if (tmp
< MIN32
)
708 State
.regs
[OP
[0]] = 0x8000;
709 State
.regs
[OP
[0]+1] = 0;
714 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
715 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
718 trace_output (OP_DREG
);
725 uint tmp
= State
.regs
[OP
[0]];
728 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
729 State
.regs
[OP
[0]] += OP
[1];
730 if (tmp
> State
.regs
[OP
[0]])
734 trace_output (OP_REG
);
741 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
742 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
743 trace_output (OP_REG
);
750 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
751 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
752 trace_output (OP_REG
);
759 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
760 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
761 trace_output (OP_REG
);
768 trace_input ("bl.s", OP_CONSTANT8
, OP_R2
, OP_R3
);
769 State
.regs
[13] = PC
+1;
771 trace_output (OP_VOID
);
778 trace_input ("bl.l", OP_CONSTANT16
, OP_R2
, OP_R3
);
779 State
.regs
[13] = PC
+1;
781 trace_output (OP_VOID
);
788 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
789 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
790 trace_output (OP_REG
);
797 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
799 trace_output (OP_VOID
);
806 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
808 trace_output (OP_VOID
);
815 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
818 trace_output (OP_FLAG
);
825 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
828 trace_output (OP_FLAG
);
835 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
838 trace_output (OP_FLAG
);
845 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
848 trace_output (OP_FLAG
);
855 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
856 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
857 trace_output (OP_REG
);
864 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
866 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
867 trace_output (OP_FLAG
);
874 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
876 trace_output (OP_ACCUM
);
883 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
885 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
886 trace_output (OP_FLAG
);
893 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
895 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
896 trace_output (OP_FLAG
);
903 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
905 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
906 trace_output (OP_FLAG
);
913 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
915 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
916 trace_output (OP_FLAG
);
923 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
925 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
926 trace_output (OP_FLAG
);
933 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
935 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
936 trace_output (OP_FLAG
);
943 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
945 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
946 trace_output (OP_FLAG
);
953 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
955 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
956 trace_output (OP_FLAG
);
963 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
965 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
966 trace_output (OP_FLAG
);
973 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
975 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
976 trace_output (OP_FLAG
);
985 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
999 trace_output (OP_FLAG
);
1006 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1007 State
.exception
= SIGTRAP
;
1014 uint16 foo
, tmp
, tmpf
;
1016 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1017 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1018 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1019 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1020 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1021 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1022 trace_output (OP_DREG
);
1029 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1030 State
.exe
= (State
.F0
== 0);
1031 trace_output (OP_FLAG
);
1038 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1039 State
.exe
= (State
.F0
!= 0);
1040 trace_output (OP_FLAG
);
1047 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1048 State
.exe
= (State
.F1
== 0);
1049 trace_output (OP_FLAG
);
1056 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1057 State
.exe
= (State
.F1
!= 0);
1058 trace_output (OP_FLAG
);
1065 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1066 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1067 trace_output (OP_FLAG
);
1074 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1075 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1076 trace_output (OP_FLAG
);
1083 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1084 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1085 trace_output (OP_FLAG
);
1092 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1093 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1094 trace_output (OP_FLAG
);
1104 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1105 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1106 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1108 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1115 State
.regs
[OP
[0]] = i
-1;
1116 trace_output (OP_REG
);
1121 State
.regs
[OP
[0]] = 16;
1122 trace_output (OP_REG
);
1132 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1133 if (SEXT40(State
.a
[OP
[1]]) >= 0)
1134 tmp
= State
.a
[OP
[1]];
1136 tmp
= ~(State
.a
[OP
[1]]);
1138 foo
= 0x4000000000LL
;
1143 State
.regs
[OP
[0]] = i
-9;
1144 trace_output (OP_REG
);
1149 State
.regs
[OP
[0]] = 16;
1150 trace_output (OP_REG
);
1157 trace_input ("jl", OP_REG
, OP_R2
, OP_R3
);
1158 State
.regs
[13] = PC
+1;
1159 PC
= State
.regs
[OP
[0]];
1160 trace_output (OP_VOID
);
1167 trace_input ("jmp", OP_REG
,
1168 (OP
[0] == 13) ? OP_R2
: OP_VOID
,
1169 (OP
[0] == 13) ? OP_R3
: OP_VOID
);
1171 PC
= State
.regs
[OP
[0]];
1172 trace_output (OP_VOID
);
1179 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1180 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1181 trace_output (OP_REG
);
1188 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1189 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1190 INC_ADDR(State
.regs
[OP
[1]],-2);
1191 trace_output (OP_REG
);
1198 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1199 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1200 INC_ADDR(State
.regs
[OP
[1]],2);
1201 trace_output (OP_REG
);
1208 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1209 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1210 trace_output (OP_REG
);
1217 uint16 addr
= State
.regs
[OP
[2]];
1218 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1219 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1220 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1221 trace_output (OP_DREG
);
1228 uint16 addr
= State
.regs
[OP
[1]];
1229 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1230 State
.regs
[OP
[0]] = RW (addr
);
1231 State
.regs
[OP
[0]+1] = RW (addr
+2);
1232 INC_ADDR(State
.regs
[OP
[1]],-4);
1233 trace_output (OP_DREG
);
1240 uint16 addr
= State
.regs
[OP
[1]];
1241 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1242 State
.regs
[OP
[0]] = RW (addr
);
1243 State
.regs
[OP
[0]+1] = RW (addr
+2);
1244 INC_ADDR(State
.regs
[OP
[1]],4);
1245 trace_output (OP_DREG
);
1252 uint16 addr
= State
.regs
[OP
[1]];
1253 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1254 State
.regs
[OP
[0]] = RW (addr
);
1255 State
.regs
[OP
[0]+1] = RW (addr
+2);
1256 trace_output (OP_DREG
);
1263 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1264 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1265 SEXT8 (State
.regs
[OP
[0]]);
1266 trace_output (OP_REG
);
1273 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1274 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1275 SEXT8 (State
.regs
[OP
[0]]);
1276 trace_output (OP_REG
);
1283 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1284 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1285 trace_output (OP_REG
);
1292 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1293 State
.regs
[OP
[0]] = OP
[1];
1294 trace_output (OP_REG
);
1301 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1302 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1303 trace_output (OP_REG
);
1310 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1311 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1312 trace_output (OP_REG
);
1321 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1322 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1325 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1327 if (State
.ST
&& tmp
> MAX32
)
1330 tmp
+= SEXT40(State
.a
[OP
[0]]);
1334 State
.a
[OP
[0]] = MAX32
;
1335 else if (tmp
< MIN32
)
1336 State
.a
[OP
[0]] = MIN32
;
1338 State
.a
[OP
[0]] = tmp
& MASK40
;
1341 State
.a
[OP
[0]] = tmp
& MASK40
;
1342 trace_output (OP_ACCUM
);
1351 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1352 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1354 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1356 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1357 trace_output (OP_ACCUM
);
1366 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1367 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1369 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1370 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1371 trace_output (OP_ACCUM
);
1378 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1379 State
.F1
= State
.F0
;
1380 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1382 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1387 trace_output (OP_REG
);
1396 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1397 State
.F1
= State
.F0
;
1398 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1399 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1401 State
.a
[OP
[0]] = tmp
& MASK40
;
1406 trace_output (OP_ACCUM
);
1413 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1414 State
.F1
= State
.F0
;
1415 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1417 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1422 trace_output (OP_ACCUM
);
1430 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1431 State
.F1
= State
.F0
;
1432 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1434 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1439 trace_output (OP_REG
);
1448 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1449 State
.F1
= State
.F0
;
1450 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1451 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1453 State
.a
[OP
[0]] = tmp
& MASK40
;
1458 trace_output (OP_ACCUM
);
1465 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1466 State
.F1
= State
.F0
;
1467 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1469 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1474 trace_output (OP_ACCUM
);
1483 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1484 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1487 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1489 if (State
.ST
&& tmp
> MAX32
)
1492 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1496 State
.a
[OP
[0]] = MAX32
;
1497 else if (tmp
< MIN32
)
1498 State
.a
[OP
[0]] = MIN32
;
1500 State
.a
[OP
[0]] = tmp
& MASK40
;
1503 State
.a
[OP
[0]] = tmp
& MASK40
;
1504 trace_output (OP_ACCUM
);
1513 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1514 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1516 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1518 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1519 trace_output (OP_ACCUM
);
1528 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1529 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1531 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1533 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1534 trace_output (OP_ACCUM
);
1541 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1542 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1543 trace_output (OP_REG
);
1552 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1553 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1556 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1558 if (State
.ST
&& tmp
> MAX32
)
1559 State
.a
[OP
[0]] = MAX32
;
1561 State
.a
[OP
[0]] = tmp
& MASK40
;
1562 trace_output (OP_ACCUM
);
1571 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1572 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1577 State
.a
[OP
[0]] = tmp
& MASK40
;
1578 trace_output (OP_ACCUM
);
1587 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1588 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1593 State
.a
[OP
[0]] = tmp
& MASK40
;
1594 trace_output (OP_ACCUM
);
1601 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1602 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1603 trace_output (OP_REG
);
1610 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1611 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1612 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1613 trace_output (OP_DREG
);
1620 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1621 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1622 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1623 trace_output (OP_DREG
);
1630 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1631 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1632 trace_output (OP_ACCUM
);
1639 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1640 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1641 trace_output (OP_ACCUM
);
1648 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1649 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1650 trace_output (OP_REG
);
1657 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1659 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1660 trace_output (OP_REG
);
1667 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1669 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1670 trace_output (OP_REG
);
1677 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1678 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1679 trace_output (OP_ACCUM
);
1686 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1687 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1688 trace_output (OP_REG
);
1695 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1696 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1697 trace_output (OP_REG
);
1704 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1707 /* PSW is treated specially */
1709 if (State
.SM
) PSW
|= 0x8000;
1710 if (State
.EA
) PSW
|= 0x2000;
1711 if (State
.DB
) PSW
|= 0x1000;
1712 if (State
.IE
) PSW
|= 0x400;
1713 if (State
.RP
) PSW
|= 0x200;
1714 if (State
.MD
) PSW
|= 0x100;
1715 if (State
.FX
) PSW
|= 0x80;
1716 if (State
.ST
) PSW
|= 0x40;
1717 if (State
.F0
) PSW
|= 8;
1718 if (State
.F1
) PSW
|= 4;
1719 if (State
.C
) PSW
|= 1;
1721 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1722 trace_output (OP_REG
);
1729 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1730 State
.a
[OP
[1]] &= MASK32
;
1731 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1732 trace_output (OP_ACCUM_REVERSE
);
1741 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1742 tmp
= State
.a
[OP
[1]] & 0xffff;
1743 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1744 trace_output (OP_ACCUM_REVERSE
);
1751 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1752 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1753 trace_output (OP_ACCUM_REVERSE
);
1760 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1761 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1764 /* PSW is treated specially */
1765 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1766 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1767 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1768 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1769 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1770 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1771 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1772 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1773 State
.F0
= (PSW
& 8) ? 1 : 0;
1774 State
.F1
= (PSW
& 4) ? 1 : 0;
1776 if (State
.ST
&& !State
.FX
)
1778 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1779 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1781 State
.exception
= SIGILL
;
1784 trace_output (OP_CR_REVERSE
);
1791 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1792 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1793 trace_output (OP_REG
);
1800 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1801 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1802 trace_output (OP_REG
);
1811 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1812 tmp
= -SEXT40(State
.a
[OP
[0]]);
1816 State
.a
[OP
[0]] = MAX32
;
1817 else if (tmp
< MIN32
)
1818 State
.a
[OP
[0]] = MIN32
;
1820 State
.a
[OP
[0]] = tmp
& MASK40
;
1823 State
.a
[OP
[0]] = tmp
& MASK40
;
1824 trace_output (OP_ACCUM
);
1832 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1833 trace_output (OP_VOID
);
1835 if (State
.ins_type
== INS_LEFT
|| State
.ins_type
== INS_LEFT_PARALLEL
)
1845 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1846 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1847 trace_output (OP_REG
);
1854 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1855 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1856 trace_output (OP_REG
);
1863 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1864 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1865 trace_output (OP_REG
);
1873 int shift
= SEXT3 (OP
[2]);
1875 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1878 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1879 "ERROR at PC 0x%x: instruction only valid for A0\n",
1881 State
.exception
= SIGILL
;
1884 State
.F1
= State
.F0
;
1886 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1888 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1889 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1892 State
.regs
[OP
[0]] = 0x7fff;
1893 State
.regs
[OP
[0]+1] = 0xffff;
1896 else if (tmp
< MIN32
)
1898 State
.regs
[OP
[0]] = 0x8000;
1899 State
.regs
[OP
[0]+1] = 0;
1904 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1905 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1908 trace_output (OP_DREG
);
1916 int shift
= SEXT3 (OP
[2]);
1918 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1919 State
.F1
= State
.F0
;
1921 tmp
= SEXT44 (State
.a
[1]) << shift
;
1923 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1928 State
.regs
[OP
[0]] = 0x7fff;
1931 else if (tmp
< 0xfff80000000LL
)
1933 State
.regs
[OP
[0]] = 0x8000;
1938 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1941 trace_output (OP_REG
);
1948 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1951 RPT_C
= State
.regs
[OP
[0]];
1955 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1956 State
.exception
= SIGILL
;
1960 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1961 State
.exception
= SIGILL
;
1963 trace_output (OP_VOID
);
1970 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1977 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1978 State
.exception
= SIGILL
;
1982 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
1983 State
.exception
= SIGILL
;
1985 trace_output (OP_VOID
);
1992 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
1993 State
.exception
= SIGILL
;
2000 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2003 trace_output (OP_VOID
);
2012 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2013 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2017 State
.a
[OP
[0]] = MAX32
;
2018 else if (tmp
< MIN32
)
2019 State
.a
[OP
[0]] = MIN32
;
2021 State
.a
[OP
[0]] = tmp
& MASK40
;
2024 State
.a
[OP
[0]] = tmp
& MASK40
;
2025 trace_output (OP_ACCUM
);
2032 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2033 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2034 trace_output (OP_REG
);
2041 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2042 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2043 trace_output (OP_REG
);
2050 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2052 trace_output (OP_VOID
);
2059 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2060 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2061 trace_output (OP_REG
);
2069 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2070 if ((State
.regs
[OP
[1]] & 31) <= 16)
2071 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2074 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2075 State
.exception
= SIGILL
;
2082 State
.a
[OP
[0]] = MAX32
;
2083 else if (tmp
< 0xffffff80000000LL
)
2084 State
.a
[OP
[0]] = MIN32
;
2086 State
.a
[OP
[0]] = tmp
& MASK40
;
2089 State
.a
[OP
[0]] = tmp
& MASK40
;
2090 trace_output (OP_ACCUM
);
2097 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2098 State
.regs
[OP
[0]] <<= OP
[1];
2099 trace_output (OP_REG
);
2111 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2112 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2117 State
.a
[OP
[0]] = MAX32
;
2118 else if (tmp
< 0xffffff80000000LL
)
2119 State
.a
[OP
[0]] = MIN32
;
2121 State
.a
[OP
[0]] = tmp
& MASK40
;
2124 State
.a
[OP
[0]] = tmp
& MASK40
;
2125 trace_output (OP_ACCUM
);
2134 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2135 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2136 trace_output (OP_REG
);
2143 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2144 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2145 trace_output (OP_REG
);
2152 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2153 if ((State
.regs
[OP
[1]] & 31) <= 16)
2154 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2157 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2158 State
.exception
= SIGILL
;
2162 trace_output (OP_ACCUM
);
2169 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2170 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2171 trace_output (OP_REG
);
2181 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2182 State
.a
[OP
[0]] >>= OP
[1];
2183 trace_output (OP_ACCUM
);
2190 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2191 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2192 trace_output (OP_REG
);
2199 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2200 if ((State
.regs
[OP
[1]] & 31) <= 16)
2201 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2204 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2205 State
.exception
= SIGILL
;
2209 trace_output (OP_ACCUM
);
2216 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2217 State
.regs
[OP
[0]] >>= OP
[1];
2218 trace_output (OP_REG
);
2228 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2229 State
.a
[OP
[0]] >>= OP
[1];
2230 trace_output (OP_ACCUM
);
2239 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2240 tmp
= State
.F0
<< 15;
2241 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2242 trace_output (OP_REG
);
2249 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2250 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2251 trace_output (OP_VOID
);
2258 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2259 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2260 trace_output (OP_VOID
);
2267 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2270 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2271 State
.exception
= SIGILL
;
2274 State
.regs
[OP
[1]] -= 2;
2275 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2276 trace_output (OP_VOID
);
2283 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2284 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2285 INC_ADDR (State
.regs
[OP
[1]],2);
2286 trace_output (OP_VOID
);
2293 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2294 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2295 INC_ADDR (State
.regs
[OP
[1]],-2);
2296 trace_output (OP_VOID
);
2303 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2304 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2305 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2306 trace_output (OP_VOID
);
2313 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2314 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2315 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2316 trace_output (OP_VOID
);
2323 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2326 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2327 State
.exception
= SIGILL
;
2330 State
.regs
[OP
[1]] -= 4;
2331 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2332 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2333 trace_output (OP_VOID
);
2340 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2341 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2342 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2343 INC_ADDR (State
.regs
[OP
[1]],4);
2344 trace_output (OP_VOID
);
2351 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2352 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2353 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2354 INC_ADDR (State
.regs
[OP
[1]],-4);
2355 trace_output (OP_VOID
);
2362 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2363 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2364 trace_output (OP_VOID
);
2371 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2372 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2373 trace_output (OP_VOID
);
2380 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2381 State
.exception
= SIG_D10V_STOP
;
2382 trace_output (OP_VOID
);
2391 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2392 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2393 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2394 State
.regs
[OP
[0]] = tmp
& 0xffff;
2395 trace_output (OP_REG
);
2404 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2405 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2409 State
.a
[OP
[0]] = MAX32
;
2410 else if ( tmp
< MIN32
)
2411 State
.a
[OP
[0]] = MIN32
;
2413 State
.a
[OP
[0]] = tmp
& MASK40
;
2416 State
.a
[OP
[0]] = tmp
& MASK40
;
2418 trace_output (OP_ACCUM
);
2428 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2429 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2433 State
.a
[OP
[0]] = MAX32
;
2434 else if ( tmp
< MIN32
)
2435 State
.a
[OP
[0]] = MIN32
;
2437 State
.a
[OP
[0]] = tmp
& MASK40
;
2440 State
.a
[OP
[0]] = tmp
& MASK40
;
2442 trace_output (OP_ACCUM
);
2452 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2453 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2454 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2456 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2457 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2458 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2459 trace_output (OP_DREG
);
2468 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2469 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2470 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2471 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2472 trace_output (OP_DREG
);
2481 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2482 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2483 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2484 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2485 trace_output (OP_DREG
);
2494 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2495 State
.F1
= State
.F0
;
2496 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2499 State
.regs
[OP
[0]] = 0x7fff;
2500 State
.regs
[OP
[0]+1] = 0xffff;
2503 else if (tmp
< MIN32
)
2505 State
.regs
[OP
[0]] = 0x8000;
2506 State
.regs
[OP
[0]+1] = 0;
2511 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2512 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2515 trace_output (OP_DREG
);
2524 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2525 State
.F1
= State
.F0
;
2526 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2529 State
.regs
[OP
[0]] = 0x7fff;
2530 State
.regs
[OP
[0]+1] = 0xffff;
2533 else if (tmp
< MIN32
)
2535 State
.regs
[OP
[0]] = 0x8000;
2536 State
.regs
[OP
[0]+1] = 0;
2541 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2542 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2545 trace_output (OP_DREG
);
2556 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2557 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2558 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2559 State
.regs
[OP
[0]] = tmp
& 0xffff;
2560 trace_output (OP_REG
);
2567 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2568 trace_output (OP_VOID
);
2574 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2575 State
.exception
= SIGILL
;
2577 /* Use any other traps for batch debugging. */
2580 static int first_time
= 1;
2585 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2586 for (i
= 0; i
< 16; i
++)
2587 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2588 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2591 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2593 for (i
= 0; i
< 16; i
++)
2594 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2596 for (i
= 0; i
< 2; i
++)
2597 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2598 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
2599 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
2601 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2602 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2607 /* Trap 0 is used for simulating low-level I/O */
2609 int save_errno
= errno
;
2612 /* Registers passed to trap 0 */
2614 #define FUNC State.regs[6] /* function number */
2615 #define PARM1 State.regs[2] /* optional parm 1 */
2616 #define PARM2 State.regs[3] /* optional parm 2 */
2617 #define PARM3 State.regs[4] /* optional parm 3 */
2618 #define PARM4 State.regs[5] /* optional parm 3 */
2620 /* Registers set by trap 0 */
2622 #define RETVAL State.regs[2] /* return value */
2623 #define RETVAL_HIGH State.regs[2] /* return value */
2624 #define RETVAL_LOW State.regs[3] /* return value */
2625 #define RETERR State.regs[4] /* return error code */
2627 /* Turn a pointer in a register into a pointer into real memory. */
2629 #define MEMPTR(x) ((char *)((x) + State.imem))
2633 #if !defined(__GO32__) && !defined(_WIN32)
2636 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2637 trace_output (OP_R2
);
2641 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2643 trace_output (OP_R2
);
2647 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2648 if (PARM1
== getpid ())
2650 trace_output (OP_VOID
);
2651 State
.exception
= PARM2
;
2659 case 1: os_sig
= SIGHUP
; break;
2662 case 2: os_sig
= SIGINT
; break;
2665 case 3: os_sig
= SIGQUIT
; break;
2668 case 4: os_sig
= SIGILL
; break;
2671 case 5: os_sig
= SIGTRAP
; break;
2674 case 6: os_sig
= SIGABRT
; break;
2675 #elif defined(SIGIOT)
2676 case 6: os_sig
= SIGIOT
; break;
2679 case 7: os_sig
= SIGEMT
; break;
2682 case 8: os_sig
= SIGFPE
; break;
2685 case 9: os_sig
= SIGKILL
; break;
2688 case 10: os_sig
= SIGBUS
; break;
2691 case 11: os_sig
= SIGSEGV
; break;
2694 case 12: os_sig
= SIGSYS
; break;
2697 case 13: os_sig
= SIGPIPE
; break;
2700 case 14: os_sig
= SIGALRM
; break;
2703 case 15: os_sig
= SIGTERM
; break;
2706 case 16: os_sig
= SIGURG
; break;
2709 case 17: os_sig
= SIGSTOP
; break;
2712 case 18: os_sig
= SIGTSTP
; break;
2715 case 19: os_sig
= SIGCONT
; break;
2718 case 20: os_sig
= SIGCHLD
; break;
2719 #elif defined(SIGCLD)
2720 case 20: os_sig
= SIGCLD
; break;
2723 case 21: os_sig
= SIGTTIN
; break;
2726 case 22: os_sig
= SIGTTOU
; break;
2729 case 23: os_sig
= SIGIO
; break;
2730 #elif defined (SIGPOLL)
2731 case 23: os_sig
= SIGPOLL
; break;
2734 case 24: os_sig
= SIGXCPU
; break;
2737 case 25: os_sig
= SIGXFSZ
; break;
2740 case 26: os_sig
= SIGVTALRM
; break;
2743 case 27: os_sig
= SIGPROF
; break;
2746 case 28: os_sig
= SIGWINCH
; break;
2749 case 29: os_sig
= SIGLOST
; break;
2752 case 30: os_sig
= SIGUSR1
; break;
2755 case 31: os_sig
= SIGUSR2
; break;
2761 trace_output (OP_VOID
);
2762 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2763 State
.exception
= SIGILL
;
2767 RETVAL
= kill (PARM1
, PARM2
);
2768 trace_output (OP_R2
);
2774 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2775 (char **)MEMPTR (PARM3
));
2776 trace_input ("<execve>", OP_R2
, OP_R3
, OP_R4
);
2777 trace_output (OP_R2
);
2781 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2782 trace_input ("<execv>", OP_R2
, OP_R3
, OP_VOID
);
2783 trace_output (OP_R2
);
2792 RETVAL
= pipe (host_fd
);
2793 SW (buf
, host_fd
[0]);
2794 buf
+= sizeof(uint16
);
2795 SW (buf
, host_fd
[1]);
2796 trace_input ("<pipe>", OP_R2
, OP_VOID
, OP_VOID
);
2797 trace_output (OP_R2
);
2805 RETVAL
= wait (&status
);
2808 trace_input ("<wait>", OP_R2
, OP_VOID
, OP_VOID
);
2809 trace_output (OP_R2
);
2814 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2816 trace_output (OP_R2
);
2820 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2821 trace_output (OP_VOID
);
2822 State
.exception
= PARM2
;
2827 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2829 trace_input ("<read>", OP_R2
, OP_R3
, OP_R4
);
2830 trace_output (OP_R2
);
2835 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2836 MEMPTR (PARM2
), PARM3
);
2838 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2839 MEMPTR (PARM2
), PARM3
);
2840 trace_input ("<write>", OP_R2
, OP_R3
, OP_R4
);
2841 trace_output (OP_R2
);
2846 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2847 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2849 RETVAL_HIGH
= ret
>> 16;
2850 RETVAL_LOW
= ret
& 0xffff;
2852 trace_input ("<lseek>", OP_R2
, OP_R3
, OP_R4
);
2853 trace_output (OP_R2R3
);
2857 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2858 trace_input ("<close>", OP_R2
, OP_VOID
, OP_VOID
);
2859 trace_output (OP_R2
);
2863 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2864 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2865 trace_output (OP_R2
);
2866 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2867 trace_output (OP_R2
);
2871 State
.exception
= SIG_D10V_EXIT
;
2872 trace_input ("<exit>", OP_R2
, OP_VOID
, OP_VOID
);
2873 trace_output (OP_VOID
);
2877 /* stat system call */
2879 struct stat host_stat
;
2882 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2886 /* The hard-coded offsets and sizes were determined by using
2887 * the D10V compiler on a test program that used struct stat.
2889 SW (buf
, host_stat
.st_dev
);
2890 SW (buf
+2, host_stat
.st_ino
);
2891 SW (buf
+4, host_stat
.st_mode
);
2892 SW (buf
+6, host_stat
.st_nlink
);
2893 SW (buf
+8, host_stat
.st_uid
);
2894 SW (buf
+10, host_stat
.st_gid
);
2895 SW (buf
+12, host_stat
.st_rdev
);
2896 SLW (buf
+16, host_stat
.st_size
);
2897 SLW (buf
+20, host_stat
.st_atime
);
2898 SLW (buf
+28, host_stat
.st_mtime
);
2899 SLW (buf
+36, host_stat
.st_ctime
);
2901 trace_input ("<stat>", OP_R2
, OP_R3
, OP_VOID
);
2902 trace_output (OP_R2
);
2906 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2907 trace_input ("<chown>", OP_R2
, OP_R3
, OP_R4
);
2908 trace_output (OP_R2
);
2912 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2913 trace_input ("<chmod>", OP_R2
, OP_R3
, OP_R4
);
2914 trace_output (OP_R2
);
2918 /* Cast the second argument to void *, to avoid type mismatch
2919 if a prototype is present. */
2920 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2921 trace_input ("<utime>", OP_R2
, OP_R3
, OP_R4
);
2922 trace_output (OP_R2
);
2927 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
2928 RETVAL_HIGH
= ret
>> 16;
2929 RETVAL_LOW
= ret
& 0xffff;
2931 trace_input ("<time>", OP_R2
, OP_R3
, OP_R4
);
2932 trace_output (OP_R2R3
);
2938 RETERR
= d10v_callback
->get_errno(d10v_callback
);
2943 /* Trap 1 prints a string */
2945 char *fstr
= State
.regs
[2] + State
.imem
;
2946 fputs (fstr
, stdout
);
2951 /* Trap 2 calls printf */
2953 char *fstr
= State
.regs
[2] + State
.imem
;
2954 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2955 (int16
)State
.regs
[3],
2956 (int16
)State
.regs
[4],
2957 (int16
)State
.regs
[5]);
2962 /* Trap 3 writes a character */
2963 putchar (State
.regs
[2]);
2973 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2974 State
.F1
= State
.F0
;
2975 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2976 trace_output (OP_FLAG
);
2983 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2984 State
.F1
= State
.F0
;
2985 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2986 trace_output (OP_FLAG
);
2993 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
2995 trace_output (OP_VOID
);
3002 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3003 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3004 trace_output (OP_REG
);
3011 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3012 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3013 trace_output (OP_REG
);
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