16 #include "targ-vals.h"
49 PSW_MASK
= (PSW_SM_BIT
60 /* The following bits in the PSW _can't_ be set by instructions such
62 PSW_HW_MASK
= (PSW_MASK
| PSW_DM_BIT
)
66 move_to_cr (int cr
, reg_t mask
, reg_t val
, int psw_hw_p
)
68 /* A MASK bit is set when the corresponding bit in the CR should
70 /* This assumes that (VAL & MASK) == 0 */
78 if ((mask
& PSW_SM_BIT
) == 0)
80 int new_psw_sm
= (val
& PSW_SM_BIT
) != 0;
82 SET_HELD_SP (PSW_SM
, GPR (SP_IDX
));
83 if (PSW_SM
!= new_psw_sm
)
85 SET_GPR (SP_IDX
, HELD_SP (new_psw_sm
));
87 if ((mask
& (PSW_ST_BIT
| PSW_FX_BIT
)) == 0)
89 if (val
& PSW_ST_BIT
&& !(val
& PSW_FX_BIT
))
91 (*d10v_callback
->printf_filtered
)
93 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
95 State
.exception
= SIGILL
;
98 /* keep an up-to-date psw around for tracing */
99 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
103 /* Just like PSW, mask things like DM out. */
116 /* only issue an update if the register is being changed */
117 if ((State
.cregs
[cr
] & ~mask
) != val
)
118 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
123 static void trace_input_func (const char *name
,
128 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
130 #ifndef SIZE_INSTRUCTION
131 #define SIZE_INSTRUCTION 8
134 #ifndef SIZE_OPERANDS
135 #define SIZE_OPERANDS 18
139 #define SIZE_VALUES 13
142 #ifndef SIZE_LOCATION
143 #define SIZE_LOCATION 20
150 #ifndef SIZE_LINE_NUMBER
151 #define SIZE_LINE_NUMBER 4
155 trace_input_func (const char *name
, enum op_types in1
, enum op_types in2
, enum op_types in3
)
164 const char *filename
;
165 const char *functionname
;
166 unsigned int linenumber
;
169 if ((d10v_debug
& DEBUG_TRACE
) == 0)
172 switch (State
.ins_type
)
175 case INS_UNKNOWN
: type
= " ?"; break;
176 case INS_LEFT
: type
= " L"; break;
177 case INS_RIGHT
: type
= " R"; break;
178 case INS_LEFT_PARALLEL
: type
= "*L"; break;
179 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
180 case INS_LEFT_COND_TEST
: type
= "?L"; break;
181 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
182 case INS_LEFT_COND_EXE
: type
= "&L"; break;
183 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
184 case INS_LONG
: type
= " B"; break;
187 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
188 (*d10v_callback
->printf_filtered
) (d10v_callback
,
190 SIZE_PC
, (unsigned)PC
,
192 SIZE_INSTRUCTION
, name
);
197 byte_pc
= decode_pc ();
198 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
200 filename
= (const char *)0;
201 functionname
= (const char *)0;
203 if (bfd_find_nearest_line (prog_bfd
, text
, (struct bfd_symbol
**)0, byte_pc
- text_start
,
204 &filename
, &functionname
, &linenumber
))
209 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
214 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
215 p
+= SIZE_LINE_NUMBER
+2;
220 sprintf (p
, "%s ", functionname
);
225 char *q
= strrchr (filename
, '/');
226 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
235 (*d10v_callback
->printf_filtered
) (d10v_callback
,
236 "0x%.*x %s: %-*.*s %-*s ",
237 SIZE_PC
, (unsigned)PC
,
239 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
240 SIZE_INSTRUCTION
, name
);
248 for (i
= 0; i
< 3; i
++)
262 sprintf (p
, "%sr%d", comma
, OP
[i
]);
270 sprintf (p
, "%scr%d", comma
, OP
[i
]);
276 case OP_ACCUM_OUTPUT
:
277 case OP_ACCUM_REVERSE
:
278 sprintf (p
, "%sa%d", comma
, OP
[i
]);
284 sprintf (p
, "%s%d", comma
, OP
[i
]);
290 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
296 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
302 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
308 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
314 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
320 sprintf (p
, "%s@%d", comma
, OP
[i
]);
326 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
332 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
338 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
346 sprintf (p
, "%sf0", comma
);
349 sprintf (p
, "%sf1", comma
);
352 sprintf (p
, "%sc", comma
);
360 if ((d10v_debug
& DEBUG_VALUES
) == 0)
364 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
372 for (i
= 0; i
< 3; i
++)
378 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
384 case OP_ACCUM_OUTPUT
:
386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
394 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
395 (uint16
) GPR (OP
[i
]));
399 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "", (uint16
) OP
[i
]);
403 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
404 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
409 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
410 (uint16
) CREG (OP
[i
]));
414 case OP_ACCUM_REVERSE
:
415 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
416 ((int)(ACC (OP
[i
]) >> 32) & 0xff),
417 ((unsigned long) ACC (OP
[i
])) & 0xffffffff);
421 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
426 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
427 (uint16
)SEXT4(OP
[i
]));
431 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
432 (uint16
)SEXT8(OP
[i
]));
436 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
437 (uint16
)SEXT3(OP
[i
]));
442 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
446 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
456 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
458 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
459 (uint16
)GPR (OP
[i
+ 1]));
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
469 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
474 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
482 (*d10v_callback
->flush_stdout
) (d10v_callback
);
486 do_trace_output_flush (void)
488 (*d10v_callback
->flush_stdout
) (d10v_callback
);
492 do_trace_output_finish (void)
494 (*d10v_callback
->printf_filtered
) (d10v_callback
,
495 " F0=%d F1=%d C=%d\n",
496 (State
.trace
.psw
& PSW_F0_BIT
) != 0,
497 (State
.trace
.psw
& PSW_F1_BIT
) != 0,
498 (State
.trace
.psw
& PSW_C_BIT
) != 0);
499 (*d10v_callback
->flush_stdout
) (d10v_callback
);
503 trace_output_40 (uint64 val
)
505 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
507 (*d10v_callback
->printf_filtered
) (d10v_callback
,
508 " :: %*s0x%.2x%.8lx",
511 ((int)(val
>> 32) & 0xff),
512 ((unsigned long) val
) & 0xffffffff);
513 do_trace_output_finish ();
518 trace_output_32 (uint32 val
)
520 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
522 (*d10v_callback
->printf_filtered
) (d10v_callback
,
527 do_trace_output_finish ();
532 trace_output_16 (uint16 val
)
534 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
536 (*d10v_callback
->printf_filtered
) (d10v_callback
,
541 do_trace_output_finish ();
546 trace_output_void (void)
548 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
550 (*d10v_callback
->printf_filtered
) (d10v_callback
, "\n");
551 do_trace_output_flush ();
556 trace_output_flag (void)
558 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
560 (*d10v_callback
->printf_filtered
) (d10v_callback
,
564 do_trace_output_finish ();
572 #define trace_input(NAME, IN1, IN2, IN3)
573 #define trace_output(RESULT)
581 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
591 SET_GPR (OP
[0], tmp
);
592 trace_output_16 (tmp
);
600 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
603 tmp
= SEXT40 (ACC (OP
[0]));
609 if (tmp
> SEXT40(MAX32
))
611 else if (tmp
< SEXT40(MIN32
))
614 tmp
= (tmp
& MASK40
);
617 tmp
= (tmp
& MASK40
);
622 tmp
= (tmp
& MASK40
);
625 SET_ACC (OP
[0], tmp
);
626 trace_output_40 (tmp
);
633 uint16 a
= GPR (OP
[0]);
634 uint16 b
= GPR (OP
[1]);
635 uint16 tmp
= (a
+ b
);
636 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
638 SET_GPR (OP
[0], tmp
);
639 trace_output_16 (tmp
);
647 tmp
= SEXT40(ACC (OP
[0])) + (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
649 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
652 if (tmp
> SEXT40(MAX32
))
654 else if (tmp
< SEXT40(MIN32
))
657 tmp
= (tmp
& MASK40
);
660 tmp
= (tmp
& MASK40
);
661 SET_ACC (OP
[0], tmp
);
662 trace_output_40 (tmp
);
670 tmp
= SEXT40(ACC (OP
[0])) + SEXT40(ACC (OP
[1]));
672 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
675 if (tmp
> SEXT40(MAX32
))
677 else if (tmp
< SEXT40(MIN32
))
680 tmp
= (tmp
& MASK40
);
683 tmp
= (tmp
& MASK40
);
684 SET_ACC (OP
[0], tmp
);
685 trace_output_40 (tmp
);
693 uint32 a
= (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1);
694 uint32 b
= (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
695 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
698 SET_GPR (OP
[0] + 0, (tmp
>> 16));
699 SET_GPR (OP
[0] + 1, (tmp
& 0xFFFF));
700 trace_output_32 (tmp
);
707 uint16 a
= GPR (OP
[1]);
709 uint16 tmp
= (a
+ b
);
710 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
712 SET_GPR (OP
[0], tmp
);
713 trace_output_16 (tmp
);
721 tmp
= SEXT40(ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
723 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
724 SET_GPR (OP
[0] + 0, ((tmp
>> 16) & 0xffff));
725 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
726 trace_output_32 (tmp
);
734 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
736 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
737 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
738 SET_GPR (OP
[0] + 1, tmp
& 0xffff);
739 trace_output_32 (tmp
);
749 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
750 tmp
= SEXT40 (ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
751 if (tmp
> SEXT40(MAX32
))
756 else if (tmp
< SEXT40(MIN32
))
765 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
766 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
767 trace_output_32 (tmp
);
777 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
778 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
779 if (tmp
> SEXT40(MAX32
))
784 else if (tmp
< SEXT40(MIN32
))
793 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
794 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
795 trace_output_32 (tmp
);
802 uint16 a
= GPR (OP
[0]);
809 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
811 SET_GPR (OP
[0], tmp
);
812 trace_output_16 (tmp
);
819 uint16 tmp
= GPR (OP
[0]) & GPR (OP
[1]);
820 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
821 SET_GPR (OP
[0], tmp
);
822 trace_output_16 (tmp
);
829 uint16 tmp
= GPR (OP
[1]) & OP
[2];
830 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
831 SET_GPR (OP
[0], tmp
);
832 trace_output_16 (tmp
);
840 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
841 tmp
= (GPR (OP
[0]) &~(0x8000 >> OP
[1]));
842 SET_GPR (OP
[0], tmp
);
843 trace_output_16 (tmp
);
850 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
851 SET_GPR (13, PC
+ 1);
852 JMP( PC
+ SEXT8 (OP
[0]));
853 trace_output_void ();
860 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
861 SET_GPR (13, (PC
+ 1));
863 trace_output_void ();
871 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
872 tmp
= (GPR (OP
[0]) ^ (0x8000 >> OP
[1]));
873 SET_GPR (OP
[0], tmp
);
874 trace_output_16 (tmp
);
881 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
882 JMP (PC
+ SEXT8 (OP
[0]));
883 trace_output_void ();
890 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
892 trace_output_void ();
899 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
901 JMP (PC
+ SEXT8 (OP
[0]));
902 trace_output_flag ();
909 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
912 trace_output_flag ();
919 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
921 JMP (PC
+ SEXT8 (OP
[0]));
922 trace_output_flag ();
929 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
932 trace_output_flag ();
940 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
941 tmp
= (GPR (OP
[0]) | (0x8000 >> OP
[1]));
942 SET_GPR (OP
[0], tmp
);
943 trace_output_16 (tmp
);
950 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
952 SET_PSW_F0 ((GPR (OP
[0]) & (0x8000 >> OP
[1])) ? 1 : 0);
953 trace_output_flag ();
960 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
969 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
971 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(GPR (OP
[1]))) ? 1 : 0);
972 trace_output_flag ();
979 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
981 SET_PSW_F0 ((SEXT40(ACC (OP
[0])) < SEXT40(ACC (OP
[1]))) ? 1 : 0);
982 trace_output_flag ();
989 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
991 SET_PSW_F0 ((GPR (OP
[0]) == GPR (OP
[1])) ? 1 : 0);
992 trace_output_flag ();
999 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1000 SET_PSW_F1 (PSW_F0
);
1001 SET_PSW_F0 (((ACC (OP
[0]) & MASK40
) == (ACC (OP
[1]) & MASK40
)) ? 1 : 0);
1002 trace_output_flag ();
1009 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1010 SET_PSW_F1 (PSW_F0
);
1011 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
) SEXT4 (OP
[1])) ? 1 : 0);
1012 trace_output_flag ();
1019 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1020 SET_PSW_F1 (PSW_F0
);
1021 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
)OP
[1]) ? 1 : 0);
1022 trace_output_flag ();
1029 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1030 SET_PSW_F1 (PSW_F0
);
1031 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)SEXT4(OP
[1])) ? 1 : 0);
1032 trace_output_flag ();
1039 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1040 SET_PSW_F1 (PSW_F0
);
1041 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(OP
[1])) ? 1 : 0);
1042 trace_output_flag ();
1049 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1050 SET_PSW_F1 (PSW_F0
);
1051 SET_PSW_F0 ((GPR (OP
[0]) < GPR (OP
[1])) ? 1 : 0);
1052 trace_output_flag ();
1059 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1060 SET_PSW_F1 (PSW_F0
);
1061 SET_PSW_F0 ((GPR (OP
[0]) < (reg_t
)OP
[1]) ? 1 : 0);
1062 trace_output_flag ();
1071 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1075 else if (OP
[1] == 1)
1084 trace_output_flag ();
1093 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1097 else if (OP
[1] == 1)
1106 trace_output_flag ();
1113 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1115 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1116 The conditional below is for either of the instruction pairs
1117 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1118 where the dbt instruction should be interpreted.
1120 The module `sim-break' provides a more effective mechanism for
1121 detecting GDB planted breakpoints. The code below may,
1122 eventually, be changed to use that mechanism. */
1124 if (State
.ins_type
== INS_LEFT
1125 || State
.ins_type
== INS_RIGHT
)
1127 trace_input ("dbt", OP_VOID
, OP_VOID
, OP_VOID
);
1130 SET_HW_PSW (PSW_DM_BIT
| (PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1131 JMP (DBT_VECTOR_START
);
1132 trace_output_void ();
1136 State
.exception
= SIGTRAP
;
1144 uint16 foo
, tmp
, tmpf
;
1148 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1149 foo
= (GPR (OP
[0]) << 1) | (GPR (OP
[0] + 1) >> 15);
1150 tmp
= (int16
)foo
- (int16
)(GPR (OP
[1]));
1151 tmpf
= (foo
>= GPR (OP
[1])) ? 1 : 0;
1152 hi
= ((tmpf
== 1) ? tmp
: foo
);
1153 lo
= ((GPR (OP
[0] + 1) << 1) | tmpf
);
1154 SET_GPR (OP
[0] + 0, hi
);
1155 SET_GPR (OP
[0] + 1, lo
);
1156 trace_output_32 (((uint32
) hi
<< 16) | lo
);
1163 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1164 State
.exe
= (PSW_F0
== 0);
1165 trace_output_flag ();
1172 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1173 State
.exe
= (PSW_F0
!= 0);
1174 trace_output_flag ();
1181 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1182 State
.exe
= (PSW_F1
== 0);
1183 trace_output_flag ();
1190 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1191 State
.exe
= (PSW_F1
!= 0);
1192 trace_output_flag ();
1199 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1200 State
.exe
= (PSW_F0
== 0) & (PSW_F1
== 0);
1201 trace_output_flag ();
1208 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1209 State
.exe
= (PSW_F0
== 0) & (PSW_F1
!= 0);
1210 trace_output_flag ();
1217 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1218 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
== 0);
1219 trace_output_flag ();
1226 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1227 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
!= 0);
1228 trace_output_flag ();
1238 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1239 if (((int16
)GPR (OP
[1])) >= 0)
1240 tmp
= (GPR (OP
[1]) << 16) | GPR (OP
[1] + 1);
1242 tmp
= ~((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
1249 SET_GPR (OP
[0], (i
- 1));
1250 trace_output_16 (i
- 1);
1255 SET_GPR (OP
[0], 16);
1256 trace_output_16 (16);
1266 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1267 tmp
= SEXT40(ACC (OP
[1]));
1269 tmp
= ~tmp
& MASK40
;
1271 foo
= 0x4000000000LL
;
1276 SET_GPR (OP
[0], i
- 9);
1277 trace_output_16 (i
- 9);
1282 SET_GPR (OP
[0], 16);
1283 trace_output_16 (16);
1290 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1291 SET_GPR (13, PC
+ 1);
1293 trace_output_void ();
1300 trace_input ("jmp", OP_REG
,
1301 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1302 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1305 trace_output_void ();
1313 uint16 addr
= OP
[1] + GPR (OP
[2]);
1314 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1317 State
.exception
= SIG_D10V_BUS
;
1318 State
.pc_changed
= 1; /* Don't increment the PC. */
1319 trace_output_void ();
1323 SET_GPR (OP
[0], tmp
);
1324 trace_output_16 (tmp
);
1332 uint16 addr
= GPR (OP
[1]);
1333 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1336 State
.exception
= SIG_D10V_BUS
;
1337 State
.pc_changed
= 1; /* Don't increment the PC. */
1338 trace_output_void ();
1342 SET_GPR (OP
[0], tmp
);
1344 INC_ADDR (OP
[1], -2);
1345 trace_output_16 (tmp
);
1353 uint16 addr
= GPR (OP
[1]);
1354 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1357 State
.exception
= SIG_D10V_BUS
;
1358 State
.pc_changed
= 1; /* Don't increment the PC. */
1359 trace_output_void ();
1363 SET_GPR (OP
[0], tmp
);
1365 INC_ADDR (OP
[1], 2);
1366 trace_output_16 (tmp
);
1374 uint16 addr
= GPR (OP
[1]);
1375 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1378 State
.exception
= SIG_D10V_BUS
;
1379 State
.pc_changed
= 1; /* Don't increment the PC. */
1380 trace_output_void ();
1384 SET_GPR (OP
[0], tmp
);
1385 trace_output_16 (tmp
);
1393 uint16 addr
= OP
[1];
1394 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1397 State
.exception
= SIG_D10V_BUS
;
1398 State
.pc_changed
= 1; /* Don't increment the PC. */
1399 trace_output_void ();
1403 SET_GPR (OP
[0], tmp
);
1404 trace_output_16 (tmp
);
1412 uint16 addr
= OP
[1] + GPR (OP
[2]);
1413 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1416 State
.exception
= SIG_D10V_BUS
;
1417 State
.pc_changed
= 1; /* Don't increment the PC. */
1418 trace_output_void ();
1422 SET_GPR32 (OP
[0], tmp
);
1423 trace_output_32 (tmp
);
1430 uint16 addr
= GPR (OP
[1]);
1432 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1435 State
.exception
= SIG_D10V_BUS
;
1436 State
.pc_changed
= 1; /* Don't increment the PC. */
1437 trace_output_void ();
1441 SET_GPR32 (OP
[0], tmp
);
1442 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1443 INC_ADDR (OP
[1], -4);
1444 trace_output_32 (tmp
);
1452 uint16 addr
= GPR (OP
[1]);
1453 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1456 State
.exception
= SIG_D10V_BUS
;
1457 State
.pc_changed
= 1; /* Don't increment the PC. */
1458 trace_output_void ();
1462 SET_GPR32 (OP
[0], tmp
);
1463 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1464 INC_ADDR (OP
[1], 4);
1465 trace_output_32 (tmp
);
1472 uint16 addr
= GPR (OP
[1]);
1474 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1477 State
.exception
= SIG_D10V_BUS
;
1478 State
.pc_changed
= 1; /* Don't increment the PC. */
1479 trace_output_void ();
1483 SET_GPR32 (OP
[0], tmp
);
1484 trace_output_32 (tmp
);
1492 uint16 addr
= OP
[1];
1493 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1496 State
.exception
= SIG_D10V_BUS
;
1497 State
.pc_changed
= 1; /* Don't increment the PC. */
1498 trace_output_void ();
1502 SET_GPR32 (OP
[0], tmp
);
1503 trace_output_32 (tmp
);
1511 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1512 tmp
= SEXT8 (RB (OP
[1] + GPR (OP
[2])));
1513 SET_GPR (OP
[0], tmp
);
1514 trace_output_16 (tmp
);
1522 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1523 tmp
= SEXT8 (RB (GPR (OP
[1])));
1524 SET_GPR (OP
[0], tmp
);
1525 trace_output_16 (tmp
);
1533 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1534 tmp
= SEXT4 (OP
[1]);
1535 SET_GPR (OP
[0], tmp
);
1536 trace_output_16 (tmp
);
1544 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1546 SET_GPR (OP
[0], tmp
);
1547 trace_output_16 (tmp
);
1555 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1556 tmp
= RB (OP
[1] + GPR (OP
[2]));
1557 SET_GPR (OP
[0], tmp
);
1558 trace_output_16 (tmp
);
1566 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1567 tmp
= RB (GPR (OP
[1]));
1568 SET_GPR (OP
[0], tmp
);
1569 trace_output_16 (tmp
);
1578 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1579 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1582 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1584 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1587 tmp
+= SEXT40 (ACC (OP
[0]));
1590 if (tmp
> SEXT40(MAX32
))
1592 else if (tmp
< SEXT40(MIN32
))
1595 tmp
= (tmp
& MASK40
);
1598 tmp
= (tmp
& MASK40
);
1599 SET_ACC (OP
[0], tmp
);
1600 trace_output_40 (tmp
);
1609 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1610 tmp
= SEXT40 ((int16
) GPR (OP
[1]) * GPR (OP
[2]));
1612 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1613 tmp
= ((SEXT40 (ACC (OP
[0])) + tmp
) & MASK40
);
1614 SET_ACC (OP
[0], tmp
);
1615 trace_output_40 (tmp
);
1626 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1627 src1
= (uint16
) GPR (OP
[1]);
1628 src2
= (uint16
) GPR (OP
[2]);
1632 tmp
= ((ACC (OP
[0]) + tmp
) & MASK40
);
1633 SET_ACC (OP
[0], tmp
);
1634 trace_output_40 (tmp
);
1642 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1643 SET_PSW_F1 (PSW_F0
);
1644 if ((int16
) GPR (OP
[1]) > (int16
)GPR (OP
[0]))
1654 SET_GPR (OP
[0], tmp
);
1655 trace_output_16 (tmp
);
1664 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1665 SET_PSW_F1 (PSW_F0
);
1666 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1667 if (tmp
> SEXT40 (ACC (OP
[0])))
1669 tmp
= (tmp
& MASK40
);
1677 SET_ACC (OP
[0], tmp
);
1678 trace_output_40 (tmp
);
1686 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1687 SET_PSW_F1 (PSW_F0
);
1688 if (SEXT40 (ACC (OP
[1])) > SEXT40 (ACC (OP
[0])))
1698 SET_ACC (OP
[0], tmp
);
1699 trace_output_40 (tmp
);
1708 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1709 SET_PSW_F1 (PSW_F0
);
1710 if ((int16
)GPR (OP
[1]) < (int16
)GPR (OP
[0]))
1720 SET_GPR (OP
[0], tmp
);
1721 trace_output_16 (tmp
);
1730 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1731 SET_PSW_F1 (PSW_F0
);
1732 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1733 if (tmp
< SEXT40(ACC (OP
[0])))
1735 tmp
= (tmp
& MASK40
);
1743 SET_ACC (OP
[0], tmp
);
1744 trace_output_40 (tmp
);
1752 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1753 SET_PSW_F1 (PSW_F0
);
1754 if (SEXT40(ACC (OP
[1])) < SEXT40(ACC (OP
[0])))
1764 SET_ACC (OP
[0], tmp
);
1765 trace_output_40 (tmp
);
1774 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1775 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1778 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1780 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1783 tmp
= SEXT40(ACC (OP
[0])) - tmp
;
1786 if (tmp
> SEXT40(MAX32
))
1788 else if (tmp
< SEXT40(MIN32
))
1791 tmp
= (tmp
& MASK40
);
1795 tmp
= (tmp
& MASK40
);
1797 SET_ACC (OP
[0], tmp
);
1798 trace_output_40 (tmp
);
1807 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1808 tmp
= SEXT40 ((int16
)GPR (OP
[1]) * GPR (OP
[2]));
1810 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1811 tmp
= ((SEXT40 (ACC (OP
[0])) - tmp
) & MASK40
);
1812 SET_ACC (OP
[0], tmp
);
1813 trace_output_40 (tmp
);
1824 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1825 src1
= (uint16
) GPR (OP
[1]);
1826 src2
= (uint16
) GPR (OP
[2]);
1830 tmp
= ((ACC (OP
[0]) - tmp
) & MASK40
);
1831 SET_ACC (OP
[0], tmp
);
1832 trace_output_40 (tmp
);
1840 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1841 tmp
= GPR (OP
[0]) * GPR (OP
[1]);
1842 SET_GPR (OP
[0], tmp
);
1843 trace_output_16 (tmp
);
1852 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1853 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1856 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1858 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1861 tmp
= (tmp
& MASK40
);
1862 SET_ACC (OP
[0], tmp
);
1863 trace_output_40 (tmp
);
1872 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1873 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * GPR (OP
[2]));
1877 tmp
= (tmp
& MASK40
);
1878 SET_ACC (OP
[0], tmp
);
1879 trace_output_40 (tmp
);
1890 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1891 src1
= (uint16
) GPR (OP
[1]);
1892 src2
= (uint16
) GPR (OP
[2]);
1896 tmp
= (tmp
& MASK40
);
1897 SET_ACC (OP
[0], tmp
);
1898 trace_output_40 (tmp
);
1906 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1908 SET_GPR (OP
[0], tmp
);
1909 trace_output_16 (tmp
);
1917 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1918 tmp
= GPR32 (OP
[1]);
1919 SET_GPR32 (OP
[0], tmp
);
1920 trace_output_32 (tmp
);
1928 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1930 SET_GPR32 (OP
[0], tmp
);
1931 trace_output_32 (tmp
);
1939 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1940 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1)) & MASK40
);
1941 SET_ACC (OP
[1], tmp
);
1942 trace_output_40 (tmp
);
1950 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1952 SET_ACC (OP
[0], tmp
);
1953 trace_output_40 (tmp
);
1961 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1962 tmp
= SEXT8 (GPR (OP
[1]) & 0xff);
1963 SET_GPR (OP
[0], tmp
);
1964 trace_output_16 (tmp
);
1972 trace_input ("mvf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1976 SET_GPR (OP
[0], tmp
);
1980 trace_output_16 (tmp
);
1988 trace_input ("mvf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1992 SET_GPR (OP
[0], tmp
);
1996 trace_output_16 (tmp
);
2004 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2005 tmp
= ((ACC (OP
[1]) >> 32) & 0xff);
2006 SET_GPR (OP
[0], tmp
);
2007 trace_output_16 (tmp
);
2015 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2016 tmp
= (ACC (OP
[1]) >> 16);
2017 SET_GPR (OP
[0], tmp
);
2018 trace_output_16 (tmp
);
2026 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2028 SET_GPR (OP
[0], tmp
);
2029 trace_output_16 (tmp
);
2037 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
2039 SET_GPR (OP
[0], tmp
);
2040 trace_output_16 (tmp
);
2048 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
2049 tmp
= ((ACC (OP
[1]) & MASK32
)
2050 | ((int64
)(GPR (OP
[0]) & 0xff) << 32));
2051 SET_ACC (OP
[1], tmp
);
2052 trace_output_40 (tmp
);
2060 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
2061 tmp
= ACC (OP
[1]) & 0xffff;
2062 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | tmp
) & MASK40
);
2063 SET_ACC (OP
[1], tmp
);
2064 trace_output_40 (tmp
);
2072 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
2073 tmp
= ((SEXT16 (GPR (OP
[0]))) & MASK40
);
2074 SET_ACC (OP
[1], tmp
);
2075 trace_output_40 (tmp
);
2083 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
2085 tmp
= SET_CREG (OP
[1], tmp
);
2086 trace_output_16 (tmp
);
2094 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
2095 tmp
= (GPR (OP
[1]) & 0xff);
2096 SET_GPR (OP
[0], tmp
);
2097 trace_output_16 (tmp
);
2105 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
2106 tmp
= - GPR (OP
[0]);
2107 SET_GPR (OP
[0], tmp
);
2108 trace_output_16 (tmp
);
2117 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
2118 tmp
= -SEXT40(ACC (OP
[0]));
2121 if (tmp
> SEXT40(MAX32
))
2123 else if (tmp
< SEXT40(MIN32
))
2126 tmp
= (tmp
& MASK40
);
2129 tmp
= (tmp
& MASK40
);
2130 SET_ACC (OP
[0], tmp
);
2131 trace_output_40 (tmp
);
2139 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
2141 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
2142 switch (State
.ins_type
)
2145 ins_type_counters
[ (int)INS_UNKNOWN
]++;
2148 case INS_LEFT_PARALLEL
:
2149 /* Don't count a parallel op that includes a NOP as a true parallel op */
2150 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
2151 ins_type_counters
[ (int)INS_RIGHT
]++;
2152 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2156 case INS_LEFT_COND_EXE
:
2157 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2160 case INS_RIGHT_PARALLEL
:
2161 /* Don't count a parallel op that includes a NOP as a true parallel op */
2162 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
2163 ins_type_counters
[ (int)INS_LEFT
]++;
2164 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2168 case INS_RIGHT_COND_EXE
:
2169 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2173 trace_output_void ();
2181 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
2183 SET_GPR (OP
[0], tmp
);
2184 trace_output_16 (tmp
);
2192 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
2193 tmp
= (GPR (OP
[0]) | GPR (OP
[1]));
2194 SET_GPR (OP
[0], tmp
);
2195 trace_output_16 (tmp
);
2203 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2204 tmp
= (GPR (OP
[1]) | OP
[2]);
2205 SET_GPR (OP
[0], tmp
);
2206 trace_output_16 (tmp
);
2214 int shift
= SEXT3 (OP
[2]);
2216 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2219 (*d10v_callback
->printf_filtered
) (d10v_callback
,
2220 "ERROR at PC 0x%x: instruction only valid for A0\n",
2222 State
.exception
= SIGILL
;
2225 SET_PSW_F1 (PSW_F0
);
2226 tmp
= SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2232 tmp
>>= 16; /* look at bits 0:43 */
2233 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2238 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2247 SET_GPR32 (OP
[0], tmp
);
2248 trace_output_32 (tmp
);
2256 int shift
= SEXT3 (OP
[2]);
2258 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2259 SET_PSW_F1 (PSW_F0
);
2261 tmp
= SEXT40 (ACC (OP
[1])) << shift
;
2263 tmp
= SEXT40 (ACC (OP
[1])) >> -shift
;
2266 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2271 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2281 SET_GPR (OP
[0], tmp
);
2282 trace_output_16 (tmp
);
2289 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2291 SET_RPT_E (PC
+ OP
[1]);
2292 SET_RPT_C (GPR (OP
[0]));
2294 if (GPR (OP
[0]) == 0)
2296 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
2297 State
.exception
= SIGILL
;
2301 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2302 State
.exception
= SIGILL
;
2304 trace_output_void ();
2311 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2313 SET_RPT_E (PC
+ OP
[1]);
2318 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2319 State
.exception
= SIGILL
;
2323 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2324 State
.exception
= SIGILL
;
2326 trace_output_void ();
2333 trace_input ("rtd", OP_VOID
, OP_VOID
, OP_VOID
);
2334 SET_CREG (PSW_CR
, DPSW
);
2336 trace_output_void ();
2343 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2344 SET_CREG (PSW_CR
, BPSW
);
2346 trace_output_void ();
2354 trace_input ("sac", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2356 tmp
= SEXT40(ACC (OP
[1]));
2358 SET_PSW_F1 (PSW_F0
);
2360 if (tmp
> SEXT40(MAX32
))
2365 else if (tmp
< SEXT40(MIN32
))
2372 tmp
= (tmp
& MASK32
);
2376 SET_GPR32 (OP
[0], tmp
);
2378 trace_output_40 (tmp
);
2387 trace_input ("sachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2389 tmp
= SEXT40(ACC (OP
[1]));
2391 SET_PSW_F1 (PSW_F0
);
2393 if (tmp
> SEXT40(MAX32
))
2398 else if (tmp
< SEXT40(MIN32
))
2409 SET_GPR (OP
[0], tmp
);
2411 trace_output_16 (OP
[0]);
2420 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2421 tmp
= SEXT40(ACC (OP
[0])) + (SEXT40(ACC (OP
[1])) >> 16);
2424 if (tmp
> SEXT40(MAX32
))
2426 else if (tmp
< SEXT40(MIN32
))
2429 tmp
= (tmp
& MASK40
);
2432 tmp
= (tmp
& MASK40
);
2433 SET_ACC (OP
[0], tmp
);
2434 trace_output_40 (tmp
);
2442 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2443 tmp
= ((PSW_F0
== 0) ? 1 : 0);
2444 SET_GPR (OP
[0], tmp
);
2445 trace_output_16 (tmp
);
2453 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2454 tmp
= ((PSW_F0
== 1) ? 1 : 0);
2455 SET_GPR (OP
[0], tmp
);
2456 trace_output_16 (tmp
);
2466 trace_input ("slae", OP_ACCUM
, OP_REG
, OP_VOID
);
2468 reg
= SEXT16 (GPR (OP
[1]));
2470 if (reg
>= 17 || reg
<= -17)
2472 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", reg
);
2473 State
.exception
= SIGILL
;
2477 tmp
= SEXT40 (ACC (OP
[0]));
2479 if (PSW_ST
&& (tmp
< SEXT40 (MIN32
) || tmp
> SEXT40 (MAX32
)))
2481 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp
>> 32) & 0xff), ((unsigned long) tmp
) & 0xffffffff);
2482 State
.exception
= SIGILL
;
2486 if (reg
>= 0 && reg
<= 16)
2488 tmp
= SEXT56 ((SEXT56 (tmp
)) << (GPR (OP
[1])));
2491 if (tmp
> SEXT40(MAX32
))
2493 else if (tmp
< SEXT40(MIN32
))
2496 tmp
= (tmp
& MASK40
);
2499 tmp
= (tmp
& MASK40
);
2503 tmp
= (SEXT40 (ACC (OP
[0]))) >> (-GPR (OP
[1]));
2506 SET_ACC(OP
[0], tmp
);
2508 trace_output_40(tmp
);
2515 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2517 trace_output_void ();
2525 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2526 tmp
= (GPR (OP
[0]) << (GPR (OP
[1]) & 0xf));
2527 SET_GPR (OP
[0], tmp
);
2528 trace_output_16 (tmp
);
2536 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2537 if ((GPR (OP
[1]) & 31) <= 16)
2538 tmp
= SEXT40 (ACC (OP
[0])) << (GPR (OP
[1]) & 31);
2541 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2542 State
.exception
= SIGILL
;
2548 if (tmp
> SEXT40(MAX32
))
2550 else if (tmp
< SEXT40(MIN32
))
2553 tmp
= (tmp
& MASK40
);
2556 tmp
= (tmp
& MASK40
);
2557 SET_ACC (OP
[0], tmp
);
2558 trace_output_40 (tmp
);
2566 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2567 tmp
= (GPR (OP
[0]) << OP
[1]);
2568 SET_GPR (OP
[0], tmp
);
2569 trace_output_16 (tmp
);
2581 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2582 tmp
= SEXT40(ACC (OP
[0])) << OP
[1];
2586 if (tmp
> SEXT40(MAX32
))
2588 else if (tmp
< SEXT40(MIN32
))
2591 tmp
= (tmp
& MASK40
);
2594 tmp
= (tmp
& MASK40
);
2595 SET_ACC (OP
[0], tmp
);
2596 trace_output_40 (tmp
);
2604 trace_input ("slx", OP_REG
, OP_VOID
, OP_VOID
);
2605 tmp
= ((GPR (OP
[0]) << 1) | PSW_F0
);
2606 SET_GPR (OP
[0], tmp
);
2607 trace_output_16 (tmp
);
2615 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2616 tmp
= (((int16
)(GPR (OP
[0]))) >> (GPR (OP
[1]) & 0xf));
2617 SET_GPR (OP
[0], tmp
);
2618 trace_output_16 (tmp
);
2625 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2626 if ((GPR (OP
[1]) & 31) <= 16)
2628 int64 tmp
= ((SEXT40(ACC (OP
[0])) >> (GPR (OP
[1]) & 31)) & MASK40
);
2629 SET_ACC (OP
[0], tmp
);
2630 trace_output_40 (tmp
);
2634 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2635 State
.exception
= SIGILL
;
2645 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2646 tmp
= (((int16
)(GPR (OP
[0]))) >> OP
[1]);
2647 SET_GPR (OP
[0], tmp
);
2648 trace_output_16 (tmp
);
2659 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2660 tmp
= ((SEXT40(ACC (OP
[0])) >> OP
[1]) & MASK40
);
2661 SET_ACC (OP
[0], tmp
);
2662 trace_output_40 (tmp
);
2670 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2671 tmp
= (GPR (OP
[0]) >> (GPR (OP
[1]) & 0xf));
2672 SET_GPR (OP
[0], tmp
);
2673 trace_output_16 (tmp
);
2680 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2681 if ((GPR (OP
[1]) & 31) <= 16)
2683 int64 tmp
= ((uint64
)((ACC (OP
[0]) & MASK40
) >> (GPR (OP
[1]) & 31)));
2684 SET_ACC (OP
[0], tmp
);
2685 trace_output_40 (tmp
);
2689 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2690 State
.exception
= SIGILL
;
2701 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2702 tmp
= (GPR (OP
[0]) >> OP
[1]);
2703 SET_GPR (OP
[0], tmp
);
2704 trace_output_16 (tmp
);
2715 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2716 tmp
= ((uint64
)(ACC (OP
[0]) & MASK40
) >> OP
[1]);
2717 SET_ACC (OP
[0], tmp
);
2718 trace_output_40 (tmp
);
2726 trace_input ("srx", OP_REG
, OP_VOID
, OP_VOID
);
2728 tmp
= ((GPR (OP
[0]) >> 1) | tmp
);
2729 SET_GPR (OP
[0], tmp
);
2730 trace_output_16 (tmp
);
2737 uint16 addr
= OP
[1] + GPR (OP
[2]);
2738 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2741 State
.exception
= SIG_D10V_BUS
;
2742 State
.pc_changed
= 1; /* Don't increment the PC. */
2743 trace_output_void ();
2746 SW (addr
, GPR (OP
[0]));
2747 trace_output_void ();
2754 uint16 addr
= GPR (OP
[1]);
2755 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2758 State
.exception
= SIG_D10V_BUS
;
2759 State
.pc_changed
= 1; /* Don't increment the PC. */
2760 trace_output_void ();
2763 SW (addr
, GPR (OP
[0]));
2764 trace_output_void ();
2772 uint16 addr
= GPR (OP
[1]) - 2;
2773 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2776 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2777 State
.exception
= SIGILL
;
2782 State
.exception
= SIG_D10V_BUS
;
2783 State
.pc_changed
= 1; /* Don't increment the PC. */
2784 trace_output_void ();
2787 SW (addr
, GPR (OP
[0]));
2788 SET_GPR (OP
[1], addr
);
2789 trace_output_void ();
2796 uint16 addr
= GPR (OP
[1]);
2797 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2800 State
.exception
= SIG_D10V_BUS
;
2801 State
.pc_changed
= 1; /* Don't increment the PC. */
2802 trace_output_void ();
2805 SW (addr
, GPR (OP
[0]));
2806 INC_ADDR (OP
[1], 2);
2807 trace_output_void ();
2814 uint16 addr
= GPR (OP
[1]);
2815 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2818 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2819 State
.exception
= SIGILL
;
2824 State
.exception
= SIG_D10V_BUS
;
2825 State
.pc_changed
= 1; /* Don't increment the PC. */
2826 trace_output_void ();
2829 SW (addr
, GPR (OP
[0]));
2830 INC_ADDR (OP
[1], -2);
2831 trace_output_void ();
2838 uint16 addr
= OP
[1];
2839 trace_input ("st", OP_REG
, OP_MEMREF3
, OP_VOID
);
2842 State
.exception
= SIG_D10V_BUS
;
2843 State
.pc_changed
= 1; /* Don't increment the PC. */
2844 trace_output_void ();
2847 SW (addr
, GPR (OP
[0]));
2848 trace_output_void ();
2855 uint16 addr
= GPR (OP
[2])+ OP
[1];
2856 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2859 State
.exception
= SIG_D10V_BUS
;
2860 State
.pc_changed
= 1; /* Don't increment the PC. */
2861 trace_output_void ();
2864 SW (addr
+ 0, GPR (OP
[0] + 0));
2865 SW (addr
+ 2, GPR (OP
[0] + 1));
2866 trace_output_void ();
2873 uint16 addr
= GPR (OP
[1]);
2874 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2877 State
.exception
= SIG_D10V_BUS
;
2878 State
.pc_changed
= 1; /* Don't increment the PC. */
2879 trace_output_void ();
2882 SW (addr
+ 0, GPR (OP
[0] + 0));
2883 SW (addr
+ 2, GPR (OP
[0] + 1));
2884 trace_output_void ();
2891 uint16 addr
= GPR (OP
[1]) - 4;
2892 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2895 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2896 State
.exception
= SIGILL
;
2901 State
.exception
= SIG_D10V_BUS
;
2902 State
.pc_changed
= 1; /* Don't increment the PC. */
2903 trace_output_void ();
2906 SW (addr
+ 0, GPR (OP
[0] + 0));
2907 SW (addr
+ 2, GPR (OP
[0] + 1));
2908 SET_GPR (OP
[1], addr
);
2909 trace_output_void ();
2916 uint16 addr
= GPR (OP
[1]);
2917 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2920 State
.exception
= SIG_D10V_BUS
;
2921 State
.pc_changed
= 1; /* Don't increment the PC. */
2922 trace_output_void ();
2925 SW (addr
+ 0, GPR (OP
[0] + 0));
2926 SW (addr
+ 2, GPR (OP
[0] + 1));
2927 INC_ADDR (OP
[1], 4);
2928 trace_output_void ();
2935 uint16 addr
= GPR (OP
[1]);
2936 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2939 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2940 State
.exception
= SIGILL
;
2945 State
.exception
= SIG_D10V_BUS
;
2946 State
.pc_changed
= 1; /* Don't increment the PC. */
2947 trace_output_void ();
2950 SW (addr
+ 0, GPR (OP
[0] + 0));
2951 SW (addr
+ 2, GPR (OP
[0] + 1));
2952 INC_ADDR (OP
[1], -4);
2953 trace_output_void ();
2960 uint16 addr
= OP
[1];
2961 trace_input ("st2w", OP_DREG
, OP_MEMREF3
, OP_VOID
);
2964 State
.exception
= SIG_D10V_BUS
;
2965 State
.pc_changed
= 1; /* Don't increment the PC. */
2966 trace_output_void ();
2969 SW (addr
+ 0, GPR (OP
[0] + 0));
2970 SW (addr
+ 2, GPR (OP
[0] + 1));
2971 trace_output_void ();
2978 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2979 SB (GPR (OP
[2]) + OP
[1], GPR (OP
[0]));
2980 trace_output_void ();
2987 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2988 SB (GPR (OP
[1]), GPR (OP
[0]));
2989 trace_output_void ();
2996 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2997 State
.exception
= SIG_D10V_STOP
;
2998 trace_output_void ();
3005 uint16 a
= GPR (OP
[0]);
3006 uint16 b
= GPR (OP
[1]);
3007 uint16 tmp
= (a
- b
);
3008 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
3009 /* see ../common/sim-alu.h for a more extensive discussion on how to
3010 compute the carry/overflow bits. */
3012 SET_GPR (OP
[0], tmp
);
3013 trace_output_16 (tmp
);
3022 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
3023 tmp
= SEXT40(ACC (OP
[0])) - (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
3026 if (tmp
> SEXT40(MAX32
))
3028 else if (tmp
< SEXT40(MIN32
))
3031 tmp
= (tmp
& MASK40
);
3034 tmp
= (tmp
& MASK40
);
3035 SET_ACC (OP
[0], tmp
);
3037 trace_output_40 (tmp
);
3047 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
3048 tmp
= SEXT40(ACC (OP
[0])) - SEXT40(ACC (OP
[1]));
3051 if (tmp
> SEXT40(MAX32
))
3053 else if (tmp
< SEXT40(MIN32
))
3056 tmp
= (tmp
& MASK40
);
3059 tmp
= (tmp
& MASK40
);
3060 SET_ACC (OP
[0], tmp
);
3062 trace_output_40 (tmp
);
3071 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
3072 a
= (uint32
)((GPR (OP
[0]) << 16) | GPR (OP
[0] + 1));
3073 b
= (uint32
)((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
3074 /* see ../common/sim-alu.h for a more extensive discussion on how to
3075 compute the carry/overflow bits */
3078 SET_GPR32 (OP
[0], tmp
);
3079 trace_output_32 (tmp
);
3088 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3089 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40 (ACC (OP
[2]));
3090 SET_GPR32 (OP
[0], tmp
);
3091 trace_output_32 (tmp
);
3100 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3101 tmp
= SEXT40 (ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3102 SET_GPR32 (OP
[0], tmp
);
3103 trace_output_32 (tmp
);
3112 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3113 SET_PSW_F1 (PSW_F0
);
3114 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40(ACC (OP
[2]));
3115 if (tmp
> SEXT40(MAX32
))
3120 else if (tmp
< SEXT40(MIN32
))
3129 SET_GPR32 (OP
[0], tmp
);
3130 trace_output_32 (tmp
);
3139 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3140 SET_PSW_F1 (PSW_F0
);
3141 tmp
= SEXT40(ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3142 if (tmp
> SEXT40(MAX32
))
3147 else if (tmp
< SEXT40(MIN32
))
3156 SET_GPR32 (OP
[0], tmp
);
3157 trace_output_32 (tmp
);
3168 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3169 /* see ../common/sim-alu.h for a more extensive discussion on how to
3170 compute the carry/overflow bits. */
3171 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3172 tmp
= ((unsigned)(unsigned16
) GPR (OP
[0])
3173 + (unsigned)(unsigned16
) ( - OP
[1]));
3174 SET_PSW_C (tmp
>= (1 << 16));
3175 SET_GPR (OP
[0], tmp
);
3176 trace_output_16 (tmp
);
3183 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
3184 trace_output_void ();
3189 #if (DEBUG & DEBUG_TRAP) == 0
3191 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
3194 SET_PSW (PSW
& PSW_SM_BIT
);
3198 #else /* if debugging use trap to print registers */
3201 static int first_time
= 1;
3206 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
3207 for (i
= 0; i
< 16; i
++)
3208 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
3209 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
3212 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
3214 for (i
= 0; i
< 16; i
++)
3215 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) GPR (i
));
3217 for (i
= 0; i
< 2; i
++)
3218 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
3219 ((int)(ACC (i
) >> 32) & 0xff),
3220 ((unsigned long) ACC (i
)) & 0xffffffff);
3222 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
3223 PSW_F0
!= 0, PSW_F1
!= 0, PSW_C
!= 0);
3224 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3228 case 15: /* new system call trap */
3229 /* Trap 15 is used for simulating low-level I/O */
3231 unsigned32 result
= 0;
3234 /* Registers passed to trap 0 */
3236 #define FUNC GPR (4) /* function number */
3237 #define PARM1 GPR (0) /* optional parm 1 */
3238 #define PARM2 GPR (1) /* optional parm 2 */
3239 #define PARM3 GPR (2) /* optional parm 3 */
3240 #define PARM4 GPR (3) /* optional parm 3 */
3242 /* Registers set by trap 0 */
3244 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3245 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3246 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3248 /* Turn a pointer in a register into a pointer into real memory. */
3250 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3254 #if !defined(__GO32__) && !defined(_WIN32)
3255 case TARGET_SYS_fork
:
3256 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
3258 trace_output_16 (result
);
3262 case TARGET_SYS_getpid
:
3263 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3265 trace_output_16 (result
);
3268 case TARGET_SYS_kill
:
3269 trace_input ("<kill>", OP_R0
, OP_R1
, OP_VOID
);
3270 if (PARM1
== getpid ())
3272 trace_output_void ();
3273 State
.exception
= PARM2
;
3281 case 1: os_sig
= SIGHUP
; break;
3284 case 2: os_sig
= SIGINT
; break;
3287 case 3: os_sig
= SIGQUIT
; break;
3290 case 4: os_sig
= SIGILL
; break;
3293 case 5: os_sig
= SIGTRAP
; break;
3296 case 6: os_sig
= SIGABRT
; break;
3297 #elif defined(SIGIOT)
3298 case 6: os_sig
= SIGIOT
; break;
3301 case 7: os_sig
= SIGEMT
; break;
3304 case 8: os_sig
= SIGFPE
; break;
3307 case 9: os_sig
= SIGKILL
; break;
3310 case 10: os_sig
= SIGBUS
; break;
3313 case 11: os_sig
= SIGSEGV
; break;
3316 case 12: os_sig
= SIGSYS
; break;
3319 case 13: os_sig
= SIGPIPE
; break;
3322 case 14: os_sig
= SIGALRM
; break;
3325 case 15: os_sig
= SIGTERM
; break;
3328 case 16: os_sig
= SIGURG
; break;
3331 case 17: os_sig
= SIGSTOP
; break;
3334 case 18: os_sig
= SIGTSTP
; break;
3337 case 19: os_sig
= SIGCONT
; break;
3340 case 20: os_sig
= SIGCHLD
; break;
3341 #elif defined(SIGCLD)
3342 case 20: os_sig
= SIGCLD
; break;
3345 case 21: os_sig
= SIGTTIN
; break;
3348 case 22: os_sig
= SIGTTOU
; break;
3351 case 23: os_sig
= SIGIO
; break;
3352 #elif defined (SIGPOLL)
3353 case 23: os_sig
= SIGPOLL
; break;
3356 case 24: os_sig
= SIGXCPU
; break;
3359 case 25: os_sig
= SIGXFSZ
; break;
3362 case 26: os_sig
= SIGVTALRM
; break;
3365 case 27: os_sig
= SIGPROF
; break;
3368 case 28: os_sig
= SIGWINCH
; break;
3371 case 29: os_sig
= SIGLOST
; break;
3374 case 30: os_sig
= SIGUSR1
; break;
3377 case 31: os_sig
= SIGUSR2
; break;
3383 trace_output_void ();
3384 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
3385 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3386 State
.exception
= SIGILL
;
3390 RETVAL (kill (PARM1
, PARM2
));
3391 trace_output_16 (result
);
3396 case TARGET_SYS_execve
:
3397 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
3398 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
3399 (char **)MEMPTR (PARM3
)));
3400 trace_output_16 (result
);
3403 #ifdef TARGET_SYS_execv
3404 case TARGET_SYS_execv
:
3405 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
3406 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
3407 trace_output_16 (result
);
3411 case TARGET_SYS_pipe
:
3416 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
3418 RETVAL (pipe (host_fd
));
3419 SW (buf
, host_fd
[0]);
3420 buf
+= sizeof(uint16
);
3421 SW (buf
, host_fd
[1]);
3422 trace_output_16 (result
);
3427 #ifdef TARGET_SYS_wait
3428 case TARGET_SYS_wait
:
3431 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
3432 RETVAL (wait (&status
));
3435 trace_output_16 (result
);
3441 case TARGET_SYS_getpid
:
3442 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3444 trace_output_16 (result
);
3447 case TARGET_SYS_kill
:
3448 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
3449 trace_output_void ();
3450 State
.exception
= PARM2
;
3454 case TARGET_SYS_read
:
3455 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
3456 RETVAL (d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
3458 trace_output_16 (result
);
3461 case TARGET_SYS_write
:
3462 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
3464 RETVAL ((int)d10v_callback
->write_stdout (d10v_callback
,
3465 MEMPTR (PARM2
), PARM3
));
3467 RETVAL ((int)d10v_callback
->write (d10v_callback
, PARM1
,
3468 MEMPTR (PARM2
), PARM3
));
3469 trace_output_16 (result
);
3472 case TARGET_SYS_lseek
:
3473 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
3474 RETVAL32 (d10v_callback
->lseek (d10v_callback
, PARM1
,
3475 ((((unsigned long) PARM2
) << 16)
3476 || (unsigned long) PARM3
),
3478 trace_output_32 (result
);
3481 case TARGET_SYS_close
:
3482 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
3483 RETVAL (d10v_callback
->close (d10v_callback
, PARM1
));
3484 trace_output_16 (result
);
3487 case TARGET_SYS_open
:
3488 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
3489 RETVAL (d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
));
3490 trace_output_16 (result
);
3493 case TARGET_SYS_exit
:
3494 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
3495 State
.exception
= SIG_D10V_EXIT
;
3496 trace_output_void ();
3499 #ifdef TARGET_SYS_stat
3500 case TARGET_SYS_stat
:
3501 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
3502 /* stat system call */
3504 struct stat host_stat
;
3507 RETVAL (stat (MEMPTR (PARM1
), &host_stat
));
3511 /* The hard-coded offsets and sizes were determined by using
3512 * the D10V compiler on a test program that used struct stat.
3514 SW (buf
, host_stat
.st_dev
);
3515 SW (buf
+2, host_stat
.st_ino
);
3516 SW (buf
+4, host_stat
.st_mode
);
3517 SW (buf
+6, host_stat
.st_nlink
);
3518 SW (buf
+8, host_stat
.st_uid
);
3519 SW (buf
+10, host_stat
.st_gid
);
3520 SW (buf
+12, host_stat
.st_rdev
);
3521 SLW (buf
+16, host_stat
.st_size
);
3522 SLW (buf
+20, host_stat
.st_atime
);
3523 SLW (buf
+28, host_stat
.st_mtime
);
3524 SLW (buf
+36, host_stat
.st_ctime
);
3526 trace_output_16 (result
);
3530 case TARGET_SYS_chown
:
3531 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3532 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
3533 trace_output_16 (result
);
3536 case TARGET_SYS_chmod
:
3537 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3538 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
3539 trace_output_16 (result
);
3543 #ifdef TARGET_SYS_utime
3544 case TARGET_SYS_utime
:
3545 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3546 /* Cast the second argument to void *, to avoid type mismatch
3547 if a prototype is present. */
3548 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
3549 trace_output_16 (result
);
3555 #ifdef TARGET_SYS_time
3556 case TARGET_SYS_time
:
3557 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3558 RETVAL32 (time (PARM1
? MEMPTR (PARM1
) : NULL
));
3559 trace_output_32 (result
);
3565 d10v_callback
->error (d10v_callback
, "Unknown syscall %d", FUNC
);
3567 if ((uint16
) result
== (uint16
) -1)
3568 RETERR (d10v_callback
->get_errno(d10v_callback
));
3580 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3581 SET_PSW_F1 (PSW_F0
);;
3582 SET_PSW_F0 ((GPR (OP
[0]) & OP
[1]) ? 1 : 0);
3583 trace_output_flag ();
3590 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3591 SET_PSW_F1 (PSW_F0
);
3592 SET_PSW_F0 ((~(GPR (OP
[0])) & OP
[1]) ? 1 : 0);
3593 trace_output_flag ();
3600 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3602 trace_output_void ();
3610 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3611 tmp
= (GPR (OP
[0]) ^ GPR (OP
[1]));
3612 SET_GPR (OP
[0], tmp
);
3613 trace_output_16 (tmp
);
3621 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3622 tmp
= (GPR (OP
[1]) ^ OP
[2]);
3623 SET_GPR (OP
[0], tmp
);
3624 trace_output_16 (tmp
);
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