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[deliverable/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "targ-vals.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R0,
41 OP_R1,
42 OP_R2,
43 };
44
45
46 enum {
47 PSW_MASK = (PSW_SM_BIT
48 | PSW_EA_BIT
49 | PSW_DB_BIT
50 | PSW_DM_BIT
51 | PSW_IE_BIT
52 | PSW_RP_BIT
53 | PSW_MD_BIT
54 | PSW_FX_BIT
55 | PSW_ST_BIT
56 | PSW_F0_BIT
57 | PSW_F1_BIT
58 | PSW_C_BIT),
59 };
60
61 reg_t
62 move_to_cr (int cr, reg_t mask, reg_t val)
63 {
64 /* A MASK bit is set when the corresponding bit in the CR should
65 be left alone */
66 /* This assumes that (VAL & MASK) == 0 */
67 switch (cr)
68 {
69 case PSW_CR:
70 val &= PSW_MASK;
71 if ((mask & PSW_SM_BIT) == 0)
72 {
73 int new_sm = (val & PSW_SM_BIT) != 0;
74 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
75 if (PSW_SM != new_sm)
76 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
77 }
78 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
79 {
80 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
81 {
82 (*d10v_callback->printf_filtered)
83 (d10v_callback,
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
85 PC<<2);
86 State.exception = SIGILL;
87 }
88 }
89 /* keep an up-to-date psw around for tracing */
90 State.trace.psw = (State.trace.psw & mask) | val;
91 break;
92 case BPSW_CR:
93 case DPSW_CR:
94 val &= PSW_MASK;
95 break;
96 case MOD_S_CR:
97 case MOD_E_CR:
98 val &= ~1;
99 break;
100 default:
101 break;
102 }
103 /* only issue an update if the register is being changed */
104 if ((State.cregs[cr] & ~mask) != val)
105 SLOT_PEND_MASK (State.cregs[cr], mask, val);
106 return val;
107 }
108
109 #ifdef DEBUG
110 static void trace_input_func PARAMS ((char *name,
111 enum op_types in1,
112 enum op_types in2,
113 enum op_types in3));
114
115 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
116
117 #ifndef SIZE_INSTRUCTION
118 #define SIZE_INSTRUCTION 8
119 #endif
120
121 #ifndef SIZE_OPERANDS
122 #define SIZE_OPERANDS 18
123 #endif
124
125 #ifndef SIZE_VALUES
126 #define SIZE_VALUES 13
127 #endif
128
129 #ifndef SIZE_LOCATION
130 #define SIZE_LOCATION 20
131 #endif
132
133 #ifndef SIZE_PC
134 #define SIZE_PC 6
135 #endif
136
137 #ifndef SIZE_LINE_NUMBER
138 #define SIZE_LINE_NUMBER 4
139 #endif
140
141 static void
142 trace_input_func (name, in1, in2, in3)
143 char *name;
144 enum op_types in1;
145 enum op_types in2;
146 enum op_types in3;
147 {
148 char *comma;
149 enum op_types in[3];
150 int i;
151 char buf[1024];
152 char *p;
153 long tmp;
154 char *type;
155 const char *filename;
156 const char *functionname;
157 unsigned int linenumber;
158 bfd_vma byte_pc;
159
160 if ((d10v_debug & DEBUG_TRACE) == 0)
161 return;
162
163 switch (State.ins_type)
164 {
165 default:
166 case INS_UNKNOWN: type = " ?"; break;
167 case INS_LEFT: type = " L"; break;
168 case INS_RIGHT: type = " R"; break;
169 case INS_LEFT_PARALLEL: type = "*L"; break;
170 case INS_RIGHT_PARALLEL: type = "*R"; break;
171 case INS_LEFT_COND_TEST: type = "?L"; break;
172 case INS_RIGHT_COND_TEST: type = "?R"; break;
173 case INS_LEFT_COND_EXE: type = "&L"; break;
174 case INS_RIGHT_COND_EXE: type = "&R"; break;
175 case INS_LONG: type = " B"; break;
176 }
177
178 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
179 (*d10v_callback->printf_filtered) (d10v_callback,
180 "0x%.*x %s: %-*s ",
181 SIZE_PC, (unsigned)PC,
182 type,
183 SIZE_INSTRUCTION, name);
184
185 else
186 {
187 buf[0] = '\0';
188 byte_pc = decode_pc ();
189 if (text && byte_pc >= text_start && byte_pc < text_end)
190 {
191 filename = (const char *)0;
192 functionname = (const char *)0;
193 linenumber = 0;
194 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
195 &filename, &functionname, &linenumber))
196 {
197 p = buf;
198 if (linenumber)
199 {
200 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
201 p += strlen (p);
202 }
203 else
204 {
205 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
206 p += SIZE_LINE_NUMBER+2;
207 }
208
209 if (functionname)
210 {
211 sprintf (p, "%s ", functionname);
212 p += strlen (p);
213 }
214 else if (filename)
215 {
216 char *q = strrchr (filename, '/');
217 sprintf (p, "%s ", (q) ? q+1 : filename);
218 p += strlen (p);
219 }
220
221 if (*p == ' ')
222 *p = '\0';
223 }
224 }
225
226 (*d10v_callback->printf_filtered) (d10v_callback,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC, (unsigned)PC,
229 type,
230 SIZE_LOCATION, SIZE_LOCATION, buf,
231 SIZE_INSTRUCTION, name);
232 }
233
234 in[0] = in1;
235 in[1] = in2;
236 in[2] = in3;
237 comma = "";
238 p = buf;
239 for (i = 0; i < 3; i++)
240 {
241 switch (in[i])
242 {
243 case OP_VOID:
244 case OP_R0:
245 case OP_R1:
246 case OP_R2:
247 break;
248
249 case OP_REG:
250 case OP_REG_OUTPUT:
251 case OP_DREG:
252 case OP_DREG_OUTPUT:
253 sprintf (p, "%sr%d", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_CR:
259 case OP_CR_OUTPUT:
260 case OP_CR_REVERSE:
261 sprintf (p, "%scr%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_ACCUM:
267 case OP_ACCUM_OUTPUT:
268 case OP_ACCUM_REVERSE:
269 sprintf (p, "%sa%d", comma, OP[i]);
270 p += strlen (p);
271 comma = ",";
272 break;
273
274 case OP_CONSTANT16:
275 sprintf (p, "%s%d", comma, OP[i]);
276 p += strlen (p);
277 comma = ",";
278 break;
279
280 case OP_CONSTANT8:
281 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
282 p += strlen (p);
283 comma = ",";
284 break;
285
286 case OP_CONSTANT4:
287 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
288 p += strlen (p);
289 comma = ",";
290 break;
291
292 case OP_CONSTANT3:
293 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
294 p += strlen (p);
295 comma = ",";
296 break;
297
298 case OP_MEMREF:
299 sprintf (p, "%s@r%d", comma, OP[i]);
300 p += strlen (p);
301 comma = ",";
302 break;
303
304 case OP_MEMREF2:
305 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
306 p += strlen (p);
307 comma = ",";
308 break;
309
310 case OP_POSTINC:
311 sprintf (p, "%s@r%d+", comma, OP[i]);
312 p += strlen (p);
313 comma = ",";
314 break;
315
316 case OP_POSTDEC:
317 sprintf (p, "%s@r%d-", comma, OP[i]);
318 p += strlen (p);
319 comma = ",";
320 break;
321
322 case OP_PREDEC:
323 sprintf (p, "%s@-r%d", comma, OP[i]);
324 p += strlen (p);
325 comma = ",";
326 break;
327
328 case OP_FLAG:
329 case OP_FLAG_OUTPUT:
330 if (OP[i] == 0)
331 sprintf (p, "%sf0", comma);
332
333 else if (OP[i] == 1)
334 sprintf (p, "%sf1", comma);
335
336 else
337 sprintf (p, "%sc", comma);
338
339 p += strlen (p);
340 comma = ",";
341 break;
342 }
343 }
344
345 if ((d10v_debug & DEBUG_VALUES) == 0)
346 {
347 *p++ = '\n';
348 *p = '\0';
349 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
350 }
351 else
352 {
353 *p = '\0';
354 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
355
356 p = buf;
357 for (i = 0; i < 3; i++)
358 {
359 buf[0] = '\0';
360 switch (in[i])
361 {
362 case OP_VOID:
363 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
364 break;
365
366 case OP_REG_OUTPUT:
367 case OP_DREG_OUTPUT:
368 case OP_CR_OUTPUT:
369 case OP_ACCUM_OUTPUT:
370 case OP_FLAG_OUTPUT:
371 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
372 break;
373
374 case OP_REG:
375 case OP_MEMREF:
376 case OP_POSTDEC:
377 case OP_POSTINC:
378 case OP_PREDEC:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16) GPR (OP[i]));
381 break;
382
383 case OP_DREG:
384 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
386 break;
387
388 case OP_CR:
389 case OP_CR_REVERSE:
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
391 (uint16) CREG (OP[i]));
392 break;
393
394 case OP_ACCUM:
395 case OP_ACCUM_REVERSE:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
397 ((int)(ACC (OP[i]) >> 32) & 0xff),
398 ((unsigned long) ACC (OP[i])) & 0xffffffff);
399 break;
400
401 case OP_CONSTANT16:
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
403 (uint16)OP[i]);
404 break;
405
406 case OP_CONSTANT4:
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
408 (uint16)SEXT4(OP[i]));
409 break;
410
411 case OP_CONSTANT8:
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16)SEXT8(OP[i]));
414 break;
415
416 case OP_CONSTANT3:
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT3(OP[i]));
419 break;
420
421 case OP_FLAG:
422 if (OP[i] == 0)
423 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
424 PSW_F0 != 0);
425
426 else if (OP[i] == 1)
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
428 PSW_F1 != 0);
429
430 else
431 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
432 PSW_C != 0);
433
434 break;
435
436 case OP_MEMREF2:
437 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
438 (uint16)OP[i]);
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)GPR (OP[i + 1]));
441 i++;
442 break;
443
444 case OP_R0:
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
446 (uint16) GPR (0));
447 break;
448
449 case OP_R1:
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
451 (uint16) GPR (1));
452 break;
453
454 case OP_R2:
455 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
456 (uint16) GPR (2));
457 break;
458
459 }
460 }
461 }
462
463 (*d10v_callback->flush_stdout) (d10v_callback);
464 }
465
466 static void
467 do_trace_output_flush (void)
468 {
469 (*d10v_callback->flush_stdout) (d10v_callback);
470 }
471
472 static void
473 do_trace_output_finish (void)
474 {
475 (*d10v_callback->printf_filtered) (d10v_callback,
476 " F0=%d F1=%d C=%d\n",
477 (State.trace.psw & PSW_F0_BIT) != 0,
478 (State.trace.psw & PSW_F1_BIT) != 0,
479 (State.trace.psw & PSW_C_BIT) != 0);
480 (*d10v_callback->flush_stdout) (d10v_callback);
481 }
482
483 static void
484 trace_output_40 (uint64 val)
485 {
486 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
487 {
488 (*d10v_callback->printf_filtered) (d10v_callback,
489 " :: %*s0x%.2x%.8lx",
490 SIZE_VALUES - 12,
491 "",
492 ((int)(val >> 32) & 0xff),
493 ((unsigned long) val) & 0xffffffff);
494 do_trace_output_finish ();
495 }
496 }
497
498 static void
499 trace_output_32 (uint32 val)
500 {
501 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
502 {
503 (*d10v_callback->printf_filtered) (d10v_callback,
504 " :: %*s0x%.8x",
505 SIZE_VALUES - 10,
506 "",
507 (int) val);
508 do_trace_output_finish ();
509 }
510 }
511
512 static void
513 trace_output_16 (uint16 val)
514 {
515 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
516 {
517 (*d10v_callback->printf_filtered) (d10v_callback,
518 " :: %*s0x%.4x",
519 SIZE_VALUES - 6,
520 "",
521 (int) val);
522 do_trace_output_finish ();
523 }
524 }
525
526 static void
527 trace_output_void ()
528 {
529 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
530 {
531 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
532 do_trace_output_flush ();
533 }
534 }
535
536 static void
537 trace_output_flag ()
538 {
539 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
540 {
541 (*d10v_callback->printf_filtered) (d10v_callback,
542 " :: %*s",
543 SIZE_VALUES,
544 "");
545 do_trace_output_finish ();
546 }
547 }
548
549
550
551
552 #else
553 #define trace_input(NAME, IN1, IN2, IN3)
554 #define trace_output(RESULT)
555 #endif
556
557 /* abs */
558 void
559 OP_4607 ()
560 {
561 int16 tmp;
562 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
563 SET_PSW_F1 (PSW_F0);
564 tmp = GPR(OP[0]);
565 if (tmp < 0)
566 {
567 tmp = - tmp;
568 SET_PSW_F0 (1);
569 }
570 else
571 SET_PSW_F0 (0);
572 SET_GPR (OP[0], tmp);
573 trace_output_16 (tmp);
574 }
575
576 /* abs */
577 void
578 OP_5607 ()
579 {
580 int64 tmp;
581 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
582 SET_PSW_F1 (PSW_F0);
583
584 tmp = SEXT40 (ACC (OP[0]));
585 if (tmp < 0 )
586 {
587 tmp = - tmp;
588 if (PSW_ST)
589 {
590 if (tmp > SEXT40(MAX32))
591 tmp = (MAX32);
592 else if (tmp < SEXT40(MIN32))
593 tmp = (MIN32);
594 else
595 tmp = (tmp & MASK40);
596 }
597 else
598 tmp = (tmp & MASK40);
599 SET_PSW_F0 (1);
600 }
601 else
602 {
603 tmp = (tmp & MASK40);
604 SET_PSW_F0 (0);
605 }
606 SET_ACC (OP[0], tmp);
607 trace_output_40 (tmp);
608 }
609
610 /* add */
611 void
612 OP_200 ()
613 {
614 uint16 a = GPR (OP[0]);
615 uint16 b = GPR (OP[1]);
616 uint16 tmp = (a + b);
617 trace_input ("add", OP_REG, OP_REG, OP_VOID);
618 SET_PSW_C (a > tmp);
619 SET_GPR (OP[0], tmp);
620 trace_output_16 (tmp);
621 }
622
623 /* add */
624 void
625 OP_1201 ()
626 {
627 int64 tmp;
628 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
629
630 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
631 if (PSW_ST)
632 {
633 if (tmp > SEXT40(MAX32))
634 tmp = (MAX32);
635 else if (tmp < SEXT40(MIN32))
636 tmp = (MIN32);
637 else
638 tmp = (tmp & MASK40);
639 }
640 else
641 tmp = (tmp & MASK40);
642 SET_ACC (OP[0], tmp);
643 trace_output_40 (tmp);
644 }
645
646 /* add */
647 void
648 OP_1203 ()
649 {
650 int64 tmp;
651 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
652
653 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
654 if (PSW_ST)
655 {
656 if (tmp > SEXT40(MAX32))
657 tmp = (MAX32);
658 else if (tmp < SEXT40(MIN32))
659 tmp = (MIN32);
660 else
661 tmp = (tmp & MASK40);
662 }
663 else
664 tmp = (tmp & MASK40);
665 SET_ACC (OP[0], tmp);
666 trace_output_40 (tmp);
667 }
668
669 /* add2w */
670 void
671 OP_1200 ()
672 {
673 uint32 tmp;
674 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
675 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
676 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
677 tmp = a + b;
678 SET_PSW_C (tmp < a);
679 SET_GPR (OP[0] + 0, (tmp >> 16));
680 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
681 trace_output_32 (tmp);
682 }
683
684 /* add3 */
685 void
686 OP_1000000 ()
687 {
688 uint16 a = GPR (OP[1]);
689 uint16 b = OP[2];
690 uint16 tmp = (a + b);
691 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
692 SET_PSW_C (tmp < a);
693 SET_GPR (OP[0], tmp);
694 trace_output_16 (tmp);
695 }
696
697 /* addac3 */
698 void
699 OP_17000200 ()
700 {
701 int64 tmp;
702 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
703
704 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
705 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
706 SET_GPR (OP[0] + 1, (tmp & 0xffff));
707 trace_output_32 (tmp);
708 }
709
710 /* addac3 */
711 void
712 OP_17000202 ()
713 {
714 int64 tmp;
715 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
716
717 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
718 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
719 SET_GPR (OP[0] + 1, tmp & 0xffff);
720 trace_output_32 (tmp);
721 }
722
723 /* addac3s */
724 void
725 OP_17001200 ()
726 {
727 int64 tmp;
728 SET_PSW_F1 (PSW_F0);
729
730 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
731 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
732 if (tmp > SEXT40(MAX32))
733 {
734 tmp = (MAX32);
735 SET_PSW_F0 (1);
736 }
737 else if (tmp < SEXT40(MIN32))
738 {
739 tmp = (MIN32);
740 SET_PSW_F0 (1);
741 }
742 else
743 {
744 SET_PSW_F0 (0);
745 }
746 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
747 SET_GPR (OP[0] + 1, (tmp & 0xffff));
748 trace_output_32 (tmp);
749 }
750
751 /* addac3s */
752 void
753 OP_17001202 ()
754 {
755 int64 tmp;
756 SET_PSW_F1 (PSW_F0);
757
758 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
759 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
760 if (tmp > SEXT40(MAX32))
761 {
762 tmp = (MAX32);
763 SET_PSW_F0 (1);
764 }
765 else if (tmp < SEXT40(MIN32))
766 {
767 tmp = (MIN32);
768 SET_PSW_F0 (1);
769 }
770 else
771 {
772 SET_PSW_F0 (0);
773 }
774 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
775 SET_GPR (OP[0] + 1, (tmp & 0xffff));
776 trace_output_32 (tmp);
777 }
778
779 /* addi */
780 void
781 OP_201 ()
782 {
783 uint16 a = GPR (OP[0]);
784 uint16 b;
785 uint16 tmp;
786 if (OP[1] == 0)
787 OP[1] = 16;
788 b = OP[1];
789 tmp = (a + b);
790 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
791 SET_PSW_C (tmp < a);
792 SET_GPR (OP[0], tmp);
793 trace_output_16 (tmp);
794 }
795
796 /* and */
797 void
798 OP_C00 ()
799 {
800 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
801 trace_input ("and", OP_REG, OP_REG, OP_VOID);
802 SET_GPR (OP[0], tmp);
803 trace_output_16 (tmp);
804 }
805
806 /* and3 */
807 void
808 OP_6000000 ()
809 {
810 uint16 tmp = GPR (OP[1]) & OP[2];
811 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
812 SET_GPR (OP[0], tmp);
813 trace_output_16 (tmp);
814 }
815
816 /* bclri */
817 void
818 OP_C01 ()
819 {
820 int16 tmp;
821 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
822 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
823 SET_GPR (OP[0], tmp);
824 trace_output_16 (tmp);
825 }
826
827 /* bl.s */
828 void
829 OP_4900 ()
830 {
831 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
832 SET_GPR (13, PC + 1);
833 JMP( PC + SEXT8 (OP[0]));
834 trace_output_void ();
835 }
836
837 /* bl.l */
838 void
839 OP_24800000 ()
840 {
841 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
842 SET_GPR (13, (PC + 1));
843 JMP (PC + OP[0]);
844 trace_output_void ();
845 }
846
847 /* bnoti */
848 void
849 OP_A01 ()
850 {
851 int16 tmp;
852 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
853 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
854 SET_GPR (OP[0], tmp);
855 trace_output_16 (tmp);
856 }
857
858 /* bra.s */
859 void
860 OP_4800 ()
861 {
862 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
863 JMP (PC + SEXT8 (OP[0]));
864 trace_output_void ();
865 }
866
867 /* bra.l */
868 void
869 OP_24000000 ()
870 {
871 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
872 JMP (PC + OP[0]);
873 trace_output_void ();
874 }
875
876 /* brf0f.s */
877 void
878 OP_4A00 ()
879 {
880 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
881 if (!PSW_F0)
882 JMP (PC + SEXT8 (OP[0]));
883 trace_output_flag ();
884 }
885
886 /* brf0f.l */
887 void
888 OP_25000000 ()
889 {
890 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
891 if (!PSW_F0)
892 JMP (PC + OP[0]);
893 trace_output_flag ();
894 }
895
896 /* brf0t.s */
897 void
898 OP_4B00 ()
899 {
900 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
901 if (PSW_F0)
902 JMP (PC + SEXT8 (OP[0]));
903 trace_output_flag ();
904 }
905
906 /* brf0t.l */
907 void
908 OP_25800000 ()
909 {
910 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
911 if (PSW_F0)
912 JMP (PC + OP[0]);
913 trace_output_flag ();
914 }
915
916 /* bseti */
917 void
918 OP_801 ()
919 {
920 int16 tmp;
921 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
922 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
923 SET_GPR (OP[0], tmp);
924 trace_output_16 (tmp);
925 }
926
927 /* btsti */
928 void
929 OP_E01 ()
930 {
931 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
932 SET_PSW_F1 (PSW_F0);
933 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
934 trace_output_flag ();
935 }
936
937 /* clrac */
938 void
939 OP_5601 ()
940 {
941 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
942 SET_ACC (OP[0], 0);
943 trace_output_40 (0);
944 }
945
946 /* cmp */
947 void
948 OP_600 ()
949 {
950 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
951 SET_PSW_F1 (PSW_F0);
952 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
953 trace_output_flag ();
954 }
955
956 /* cmp */
957 void
958 OP_1603 ()
959 {
960 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
961 SET_PSW_F1 (PSW_F0);
962 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
963 trace_output_flag ();
964 }
965
966 /* cmpeq */
967 void
968 OP_400 ()
969 {
970 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
971 SET_PSW_F1 (PSW_F0);
972 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
973 trace_output_flag ();
974 }
975
976 /* cmpeq */
977 void
978 OP_1403 ()
979 {
980 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
981 SET_PSW_F1 (PSW_F0);
982 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
983 trace_output_flag ();
984 }
985
986 /* cmpeqi.s */
987 void
988 OP_401 ()
989 {
990 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
991 SET_PSW_F1 (PSW_F0);
992 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
993 trace_output_flag ();
994 }
995
996 /* cmpeqi.l */
997 void
998 OP_2000000 ()
999 {
1000 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1001 SET_PSW_F1 (PSW_F0);
1002 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1003 trace_output_flag ();
1004 }
1005
1006 /* cmpi.s */
1007 void
1008 OP_601 ()
1009 {
1010 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1011 SET_PSW_F1 (PSW_F0);
1012 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1013 trace_output_flag ();
1014 }
1015
1016 /* cmpi.l */
1017 void
1018 OP_3000000 ()
1019 {
1020 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1021 SET_PSW_F1 (PSW_F0);
1022 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1023 trace_output_flag ();
1024 }
1025
1026 /* cmpu */
1027 void
1028 OP_4600 ()
1029 {
1030 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1031 SET_PSW_F1 (PSW_F0);
1032 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1033 trace_output_flag ();
1034 }
1035
1036 /* cmpui */
1037 void
1038 OP_23000000 ()
1039 {
1040 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1041 SET_PSW_F1 (PSW_F0);
1042 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1043 trace_output_flag ();
1044 }
1045
1046 /* cpfg */
1047 void
1048 OP_4E09 ()
1049 {
1050 uint8 val;
1051
1052 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1053
1054 if (OP[1] == 0)
1055 val = PSW_F0;
1056 else if (OP[1] == 1)
1057 val = PSW_F1;
1058 else
1059 val = PSW_C;
1060 if (OP[0] == 0)
1061 SET_PSW_F0 (val);
1062 else
1063 SET_PSW_F1 (val);
1064
1065 trace_output_flag ();
1066 }
1067
1068 /* dbt */
1069 void
1070 OP_5F20 ()
1071 {
1072 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1073
1074 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1075 The conditional below is for either of the instruction pairs
1076 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1077 where the dbt instruction should be interpreted.
1078
1079 The module `sim-break' provides a more effective mechanism for
1080 detecting GDB planted breakpoints. The code below may,
1081 eventually, be changed to use that mechanism. */
1082
1083 if (State.ins_type == INS_LEFT
1084 || State.ins_type == INS_RIGHT)
1085 {
1086 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1087 SET_DPC (PC + 1);
1088 SET_DPSW (PSW);
1089 SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1090 JMP (DBT_VECTOR_START);
1091 trace_output_void ();
1092 }
1093 else
1094 {
1095 State.exception = SIGTRAP;
1096 }
1097 }
1098
1099 /* divs */
1100 void
1101 OP_14002800 ()
1102 {
1103 uint16 foo, tmp, tmpf;
1104 uint16 hi;
1105 uint16 lo;
1106
1107 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1108 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1109 tmp = (int16)foo - (int16)(GPR (OP[1]));
1110 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1111 hi = ((tmpf == 1) ? tmp : foo);
1112 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1113 SET_GPR (OP[0] + 0, hi);
1114 SET_GPR (OP[0] + 1, lo);
1115 trace_output_32 (((uint32) hi << 16) | lo);
1116 }
1117
1118 /* exef0f */
1119 void
1120 OP_4E04 ()
1121 {
1122 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1123 State.exe = (PSW_F0 == 0);
1124 trace_output_flag ();
1125 }
1126
1127 /* exef0t */
1128 void
1129 OP_4E24 ()
1130 {
1131 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1132 State.exe = (PSW_F0 != 0);
1133 trace_output_flag ();
1134 }
1135
1136 /* exef1f */
1137 void
1138 OP_4E40 ()
1139 {
1140 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1141 State.exe = (PSW_F1 == 0);
1142 trace_output_flag ();
1143 }
1144
1145 /* exef1t */
1146 void
1147 OP_4E42 ()
1148 {
1149 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1150 State.exe = (PSW_F1 != 0);
1151 trace_output_flag ();
1152 }
1153
1154 /* exefaf */
1155 void
1156 OP_4E00 ()
1157 {
1158 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1159 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1160 trace_output_flag ();
1161 }
1162
1163 /* exefat */
1164 void
1165 OP_4E02 ()
1166 {
1167 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1168 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1169 trace_output_flag ();
1170 }
1171
1172 /* exetaf */
1173 void
1174 OP_4E20 ()
1175 {
1176 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1177 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1178 trace_output_flag ();
1179 }
1180
1181 /* exetat */
1182 void
1183 OP_4E22 ()
1184 {
1185 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1186 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1187 trace_output_flag ();
1188 }
1189
1190 /* exp */
1191 void
1192 OP_15002A00 ()
1193 {
1194 uint32 tmp, foo;
1195 int i;
1196
1197 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1198 if (((int16)GPR (OP[1])) >= 0)
1199 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1200 else
1201 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1202
1203 foo = 0x40000000;
1204 for (i=1;i<17;i++)
1205 {
1206 if (tmp & foo)
1207 {
1208 SET_GPR (OP[0], (i - 1));
1209 trace_output_16 (i - 1);
1210 return;
1211 }
1212 foo >>= 1;
1213 }
1214 SET_GPR (OP[0], 16);
1215 trace_output_16 (16);
1216 }
1217
1218 /* exp */
1219 void
1220 OP_15002A02 ()
1221 {
1222 int64 tmp, foo;
1223 int i;
1224
1225 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1226 tmp = SEXT40(ACC (OP[1]));
1227 if (tmp < 0)
1228 tmp = ~tmp & MASK40;
1229
1230 foo = 0x4000000000LL;
1231 for (i=1;i<25;i++)
1232 {
1233 if (tmp & foo)
1234 {
1235 SET_GPR (OP[0], i - 9);
1236 trace_output_16 (i - 9);
1237 return;
1238 }
1239 foo >>= 1;
1240 }
1241 SET_GPR (OP[0], 16);
1242 trace_output_16 (16);
1243 }
1244
1245 /* jl */
1246 void
1247 OP_4D00 ()
1248 {
1249 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1250 SET_GPR (13, PC + 1);
1251 JMP (GPR (OP[0]));
1252 trace_output_void ();
1253 }
1254
1255 /* jmp */
1256 void
1257 OP_4C00 ()
1258 {
1259 trace_input ("jmp", OP_REG,
1260 (OP[0] == 13) ? OP_R0 : OP_VOID,
1261 (OP[0] == 13) ? OP_R1 : OP_VOID);
1262
1263 JMP (GPR (OP[0]));
1264 trace_output_void ();
1265 }
1266
1267 /* ld */
1268 void
1269 OP_30000000 ()
1270 {
1271 uint16 tmp;
1272 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1273 tmp = RW (OP[1] + GPR (OP[2]));
1274 SET_GPR (OP[0], tmp);
1275 trace_output_16 (tmp);
1276 }
1277
1278 /* ld */
1279 void
1280 OP_6401 ()
1281 {
1282 uint16 tmp;
1283 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1284 tmp = RW (GPR (OP[1]));
1285 SET_GPR (OP[0], tmp);
1286 if (OP[0] != OP[1])
1287 INC_ADDR (OP[1], -2);
1288 trace_output_16 (tmp);
1289 }
1290
1291 /* ld */
1292 void
1293 OP_6001 ()
1294 {
1295 uint16 tmp;
1296 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1297 tmp = RW (GPR (OP[1]));
1298 SET_GPR (OP[0], tmp);
1299 if (OP[0] != OP[1])
1300 INC_ADDR (OP[1], 2);
1301 trace_output_16 (tmp);
1302 }
1303
1304 /* ld */
1305 void
1306 OP_6000 ()
1307 {
1308 uint16 tmp;
1309 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1310 tmp = RW (GPR (OP[1]));
1311 SET_GPR (OP[0], tmp);
1312 trace_output_16 (tmp);
1313 }
1314
1315 /* ld2w */
1316 void
1317 OP_31000000 ()
1318 {
1319 int32 tmp;
1320 uint16 addr = GPR (OP[2]);
1321 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1322 tmp = RLW (OP[1] + addr);
1323 SET_GPR32 (OP[0], tmp);
1324 trace_output_32 (tmp);
1325 }
1326
1327 /* ld2w */
1328 void
1329 OP_6601 ()
1330 {
1331 uint16 addr = GPR (OP[1]);
1332 int32 tmp;
1333 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1334 tmp = RLW (addr);
1335 SET_GPR32 (OP[0], tmp);
1336 INC_ADDR (OP[1], -4);
1337 trace_output_32 (tmp);
1338 }
1339
1340 /* ld2w */
1341 void
1342 OP_6201 ()
1343 {
1344 int32 tmp;
1345 uint16 addr = GPR (OP[1]);
1346 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1347 tmp = RLW (addr);
1348 SET_GPR32 (OP[0], tmp);
1349 INC_ADDR (OP[1], 4);
1350 trace_output_32 (tmp);
1351 }
1352
1353 /* ld2w */
1354 void
1355 OP_6200 ()
1356 {
1357 uint16 addr = GPR (OP[1]);
1358 int32 tmp;
1359 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1360 tmp = RLW (addr + 0);
1361 SET_GPR32 (OP[0], tmp);
1362 trace_output_32 (tmp);
1363 }
1364
1365 /* ldb */
1366 void
1367 OP_38000000 ()
1368 {
1369 int16 tmp;
1370 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1371 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1372 SET_GPR (OP[0], tmp);
1373 trace_output_16 (tmp);
1374 }
1375
1376 /* ldb */
1377 void
1378 OP_7000 ()
1379 {
1380 int16 tmp;
1381 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1382 tmp = SEXT8 (RB (GPR (OP[1])));
1383 SET_GPR (OP[0], tmp);
1384 trace_output_16 (tmp);
1385 }
1386
1387 /* ldi.s */
1388 void
1389 OP_4001 ()
1390 {
1391 int16 tmp;
1392 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1393 tmp = SEXT4 (OP[1]);
1394 SET_GPR (OP[0], tmp);
1395 trace_output_16 (tmp);
1396 }
1397
1398 /* ldi.l */
1399 void
1400 OP_20000000 ()
1401 {
1402 int16 tmp;
1403 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1404 tmp = OP[1];
1405 SET_GPR (OP[0], tmp);
1406 trace_output_16 (tmp);
1407 }
1408
1409 /* ldub */
1410 void
1411 OP_39000000 ()
1412 {
1413 int16 tmp;
1414 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1415 tmp = RB (OP[1] + GPR (OP[2]));
1416 SET_GPR (OP[0], tmp);
1417 trace_output_16 (tmp);
1418 }
1419
1420 /* ldub */
1421 void
1422 OP_7200 ()
1423 {
1424 int16 tmp;
1425 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1426 tmp = RB (GPR (OP[1]));
1427 SET_GPR (OP[0], tmp);
1428 trace_output_16 (tmp);
1429 }
1430
1431 /* mac */
1432 void
1433 OP_2A00 ()
1434 {
1435 int64 tmp;
1436
1437 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1438 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1439
1440 if (PSW_FX)
1441 tmp = SEXT40( (tmp << 1) & MASK40);
1442
1443 if (PSW_ST && tmp > SEXT40(MAX32))
1444 tmp = (MAX32);
1445
1446 tmp += SEXT40 (ACC (OP[0]));
1447 if (PSW_ST)
1448 {
1449 if (tmp > SEXT40(MAX32))
1450 tmp = (MAX32);
1451 else if (tmp < SEXT40(MIN32))
1452 tmp = (MIN32);
1453 else
1454 tmp = (tmp & MASK40);
1455 }
1456 else
1457 tmp = (tmp & MASK40);
1458 SET_ACC (OP[0], tmp);
1459 trace_output_40 (tmp);
1460 }
1461
1462 /* macsu */
1463 void
1464 OP_1A00 ()
1465 {
1466 int64 tmp;
1467
1468 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1469 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1470 if (PSW_FX)
1471 tmp = SEXT40 ((tmp << 1) & MASK40);
1472 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1473 SET_ACC (OP[0], tmp);
1474 trace_output_40 (tmp);
1475 }
1476
1477 /* macu */
1478 void
1479 OP_3A00 ()
1480 {
1481 uint64 tmp;
1482 uint32 src1;
1483 uint32 src2;
1484
1485 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1486 src1 = (uint16) GPR (OP[1]);
1487 src2 = (uint16) GPR (OP[2]);
1488 tmp = src1 * src2;
1489 if (PSW_FX)
1490 tmp = (tmp << 1);
1491 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1492 SET_ACC (OP[0], tmp);
1493 trace_output_40 (tmp);
1494 }
1495
1496 /* max */
1497 void
1498 OP_2600 ()
1499 {
1500 int16 tmp;
1501 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1502 SET_PSW_F1 (PSW_F0);
1503 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1504 {
1505 tmp = GPR (OP[1]);
1506 SET_PSW_F0 (1);
1507 }
1508 else
1509 {
1510 tmp = GPR (OP[0]);
1511 SET_PSW_F0 (0);
1512 }
1513 SET_GPR (OP[0], tmp);
1514 trace_output_16 (tmp);
1515 }
1516
1517 /* max */
1518 void
1519 OP_3600 ()
1520 {
1521 int64 tmp;
1522
1523 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1524 SET_PSW_F1 (PSW_F0);
1525 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1526 if (tmp > SEXT40 (ACC (OP[0])))
1527 {
1528 tmp = (tmp & MASK40);
1529 SET_PSW_F0 (1);
1530 }
1531 else
1532 {
1533 tmp = ACC (OP[0]);
1534 SET_PSW_F0 (0);
1535 }
1536 SET_ACC (OP[0], tmp);
1537 trace_output_40 (tmp);
1538 }
1539
1540 /* max */
1541 void
1542 OP_3602 ()
1543 {
1544 int64 tmp;
1545 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1546 SET_PSW_F1 (PSW_F0);
1547 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1548 {
1549 tmp = ACC (OP[1]);
1550 SET_PSW_F0 (1);
1551 }
1552 else
1553 {
1554 tmp = ACC (OP[0]);
1555 SET_PSW_F0 (0);
1556 }
1557 SET_ACC (OP[0], tmp);
1558 trace_output_40 (tmp);
1559 }
1560
1561
1562 /* min */
1563 void
1564 OP_2601 ()
1565 {
1566 int16 tmp;
1567 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1568 SET_PSW_F1 (PSW_F0);
1569 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1570 {
1571 tmp = GPR (OP[1]);
1572 SET_PSW_F0 (1);
1573 }
1574 else
1575 {
1576 tmp = GPR (OP[0]);
1577 SET_PSW_F0 (0);
1578 }
1579 SET_GPR (OP[0], tmp);
1580 trace_output_16 (tmp);
1581 }
1582
1583 /* min */
1584 void
1585 OP_3601 ()
1586 {
1587 int64 tmp;
1588
1589 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1590 SET_PSW_F1 (PSW_F0);
1591 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1592 if (tmp < SEXT40(ACC (OP[0])))
1593 {
1594 tmp = (tmp & MASK40);
1595 SET_PSW_F0 (1);
1596 }
1597 else
1598 {
1599 tmp = ACC (OP[0]);
1600 SET_PSW_F0 (0);
1601 }
1602 SET_ACC (OP[0], tmp);
1603 trace_output_40 (tmp);
1604 }
1605
1606 /* min */
1607 void
1608 OP_3603 ()
1609 {
1610 int64 tmp;
1611 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1612 SET_PSW_F1 (PSW_F0);
1613 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1614 {
1615 tmp = ACC (OP[1]);
1616 SET_PSW_F0 (1);
1617 }
1618 else
1619 {
1620 tmp = ACC (OP[0]);
1621 SET_PSW_F0 (0);
1622 }
1623 SET_ACC (OP[0], tmp);
1624 trace_output_40 (tmp);
1625 }
1626
1627 /* msb */
1628 void
1629 OP_2800 ()
1630 {
1631 int64 tmp;
1632
1633 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1634 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1635
1636 if (PSW_FX)
1637 tmp = SEXT40 ((tmp << 1) & MASK40);
1638
1639 if (PSW_ST && tmp > SEXT40(MAX32))
1640 tmp = (MAX32);
1641
1642 tmp = SEXT40(ACC (OP[0])) - tmp;
1643 if (PSW_ST)
1644 {
1645 if (tmp > SEXT40(MAX32))
1646 tmp = (MAX32);
1647 else if (tmp < SEXT40(MIN32))
1648 tmp = (MIN32);
1649 else
1650 tmp = (tmp & MASK40);
1651 }
1652 else
1653 {
1654 tmp = (tmp & MASK40);
1655 }
1656 SET_ACC (OP[0], tmp);
1657 trace_output_40 (tmp);
1658 }
1659
1660 /* msbsu */
1661 void
1662 OP_1800 ()
1663 {
1664 int64 tmp;
1665
1666 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1667 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1668 if (PSW_FX)
1669 tmp = SEXT40( (tmp << 1) & MASK40);
1670 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1671 SET_ACC (OP[0], tmp);
1672 trace_output_40 (tmp);
1673 }
1674
1675 /* msbu */
1676 void
1677 OP_3800 ()
1678 {
1679 uint64 tmp;
1680 uint32 src1;
1681 uint32 src2;
1682
1683 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1684 src1 = (uint16) GPR (OP[1]);
1685 src2 = (uint16) GPR (OP[2]);
1686 tmp = src1 * src2;
1687 if (PSW_FX)
1688 tmp = (tmp << 1);
1689 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1690 SET_ACC (OP[0], tmp);
1691 trace_output_40 (tmp);
1692 }
1693
1694 /* mul */
1695 void
1696 OP_2E00 ()
1697 {
1698 int16 tmp;
1699 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1700 tmp = GPR (OP[0]) * GPR (OP[1]);
1701 SET_GPR (OP[0], tmp);
1702 trace_output_16 (tmp);
1703 }
1704
1705 /* mulx */
1706 void
1707 OP_2C00 ()
1708 {
1709 int64 tmp;
1710
1711 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1712 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1713
1714 if (PSW_FX)
1715 tmp = SEXT40 ((tmp << 1) & MASK40);
1716
1717 if (PSW_ST && tmp > SEXT40(MAX32))
1718 tmp = (MAX32);
1719 else
1720 tmp = (tmp & MASK40);
1721 SET_ACC (OP[0], tmp);
1722 trace_output_40 (tmp);
1723 }
1724
1725 /* mulxsu */
1726 void
1727 OP_1C00 ()
1728 {
1729 int64 tmp;
1730
1731 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1732 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1733
1734 if (PSW_FX)
1735 tmp <<= 1;
1736 tmp = (tmp & MASK40);
1737 SET_ACC (OP[0], tmp);
1738 trace_output_40 (tmp);
1739 }
1740
1741 /* mulxu */
1742 void
1743 OP_3C00 ()
1744 {
1745 uint64 tmp;
1746 uint32 src1;
1747 uint32 src2;
1748
1749 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1750 src1 = (uint16) GPR (OP[1]);
1751 src2 = (uint16) GPR (OP[2]);
1752 tmp = src1 * src2;
1753 if (PSW_FX)
1754 tmp <<= 1;
1755 tmp = (tmp & MASK40);
1756 SET_ACC (OP[0], tmp);
1757 trace_output_40 (tmp);
1758 }
1759
1760 /* mv */
1761 void
1762 OP_4000 ()
1763 {
1764 int16 tmp;
1765 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1766 tmp = GPR (OP[1]);
1767 SET_GPR (OP[0], tmp);
1768 trace_output_16 (tmp);
1769 }
1770
1771 /* mv2w */
1772 void
1773 OP_5000 ()
1774 {
1775 int32 tmp;
1776 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1777 tmp = GPR32 (OP[1]);
1778 SET_GPR32 (OP[0], tmp);
1779 trace_output_32 (tmp);
1780 }
1781
1782 /* mv2wfac */
1783 void
1784 OP_3E00 ()
1785 {
1786 int32 tmp;
1787 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1788 tmp = ACC (OP[1]);
1789 SET_GPR32 (OP[0], tmp);
1790 trace_output_32 (tmp);
1791 }
1792
1793 /* mv2wtac */
1794 void
1795 OP_3E01 ()
1796 {
1797 int64 tmp;
1798 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1799 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1800 SET_ACC (OP[1], tmp);
1801 trace_output_40 (tmp);
1802 }
1803
1804 /* mvac */
1805 void
1806 OP_3E03 ()
1807 {
1808 int64 tmp;
1809 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1810 tmp = ACC (OP[1]);
1811 SET_ACC (OP[0], tmp);
1812 trace_output_40 (tmp);
1813 }
1814
1815 /* mvb */
1816 void
1817 OP_5400 ()
1818 {
1819 int16 tmp;
1820 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1821 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1822 SET_GPR (OP[0], tmp);
1823 trace_output_16 (tmp);
1824 }
1825
1826 /* mvf0f */
1827 void
1828 OP_4400 ()
1829 {
1830 int16 tmp;
1831 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1832 if (PSW_F0 == 0)
1833 {
1834 tmp = GPR (OP[1]);
1835 SET_GPR (OP[0], tmp);
1836 }
1837 else
1838 tmp = GPR (OP[0]);
1839 trace_output_16 (tmp);
1840 }
1841
1842 /* mvf0t */
1843 void
1844 OP_4401 ()
1845 {
1846 int16 tmp;
1847 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1848 if (PSW_F0)
1849 {
1850 tmp = GPR (OP[1]);
1851 SET_GPR (OP[0], tmp);
1852 }
1853 else
1854 tmp = GPR (OP[0]);
1855 trace_output_16 (tmp);
1856 }
1857
1858 /* mvfacg */
1859 void
1860 OP_1E04 ()
1861 {
1862 int16 tmp;
1863 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1864 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1865 SET_GPR (OP[0], tmp);
1866 trace_output_16 (tmp);
1867 }
1868
1869 /* mvfachi */
1870 void
1871 OP_1E00 ()
1872 {
1873 int16 tmp;
1874 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1875 tmp = (ACC (OP[1]) >> 16);
1876 SET_GPR (OP[0], tmp);
1877 trace_output_16 (tmp);
1878 }
1879
1880 /* mvfaclo */
1881 void
1882 OP_1E02 ()
1883 {
1884 int16 tmp;
1885 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1886 tmp = ACC (OP[1]);
1887 SET_GPR (OP[0], tmp);
1888 trace_output_16 (tmp);
1889 }
1890
1891 /* mvfc */
1892 void
1893 OP_5200 ()
1894 {
1895 int16 tmp;
1896 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1897 tmp = CREG (OP[1]);
1898 SET_GPR (OP[0], tmp);
1899 trace_output_16 (tmp);
1900 }
1901
1902 /* mvtacg */
1903 void
1904 OP_1E41 ()
1905 {
1906 int64 tmp;
1907 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1908 tmp = ((ACC (OP[1]) & MASK32)
1909 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1910 SET_ACC (OP[1], tmp);
1911 trace_output_40 (tmp);
1912 }
1913
1914 /* mvtachi */
1915 void
1916 OP_1E01 ()
1917 {
1918 uint64 tmp;
1919 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1920 tmp = ACC (OP[1]) & 0xffff;
1921 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1922 SET_ACC (OP[1], tmp);
1923 trace_output_40 (tmp);
1924 }
1925
1926 /* mvtaclo */
1927 void
1928 OP_1E21 ()
1929 {
1930 int64 tmp;
1931 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1932 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1933 SET_ACC (OP[1], tmp);
1934 trace_output_40 (tmp);
1935 }
1936
1937 /* mvtc */
1938 void
1939 OP_5600 ()
1940 {
1941 int16 tmp;
1942 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1943 tmp = GPR (OP[0]);
1944 tmp = SET_CREG (OP[1], tmp);
1945 trace_output_16 (tmp);
1946 }
1947
1948 /* mvub */
1949 void
1950 OP_5401 ()
1951 {
1952 int16 tmp;
1953 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1954 tmp = (GPR (OP[1]) & 0xff);
1955 SET_GPR (OP[0], tmp);
1956 trace_output_16 (tmp);
1957 }
1958
1959 /* neg */
1960 void
1961 OP_4605 ()
1962 {
1963 int16 tmp;
1964 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1965 tmp = - GPR (OP[0]);
1966 SET_GPR (OP[0], tmp);
1967 trace_output_16 (tmp);
1968 }
1969
1970 /* neg */
1971 void
1972 OP_5605 ()
1973 {
1974 int64 tmp;
1975
1976 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1977 tmp = -SEXT40(ACC (OP[0]));
1978 if (PSW_ST)
1979 {
1980 if (tmp > SEXT40(MAX32))
1981 tmp = (MAX32);
1982 else if (tmp < SEXT40(MIN32))
1983 tmp = (MIN32);
1984 else
1985 tmp = (tmp & MASK40);
1986 }
1987 else
1988 tmp = (tmp & MASK40);
1989 SET_ACC (OP[0], tmp);
1990 trace_output_40 (tmp);
1991 }
1992
1993
1994 /* nop */
1995 void
1996 OP_5E00 ()
1997 {
1998 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1999
2000 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2001 switch (State.ins_type)
2002 {
2003 default:
2004 ins_type_counters[ (int)INS_UNKNOWN ]++;
2005 break;
2006
2007 case INS_LEFT_PARALLEL:
2008 /* Don't count a parallel op that includes a NOP as a true parallel op */
2009 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2010 ins_type_counters[ (int)INS_RIGHT ]++;
2011 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2012 break;
2013
2014 case INS_LEFT:
2015 case INS_LEFT_COND_EXE:
2016 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2017 break;
2018
2019 case INS_RIGHT_PARALLEL:
2020 /* Don't count a parallel op that includes a NOP as a true parallel op */
2021 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2022 ins_type_counters[ (int)INS_LEFT ]++;
2023 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2024 break;
2025
2026 case INS_RIGHT:
2027 case INS_RIGHT_COND_EXE:
2028 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2029 break;
2030 }
2031
2032 trace_output_void ();
2033 }
2034
2035 /* not */
2036 void
2037 OP_4603 ()
2038 {
2039 int16 tmp;
2040 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2041 tmp = ~GPR (OP[0]);
2042 SET_GPR (OP[0], tmp);
2043 trace_output_16 (tmp);
2044 }
2045
2046 /* or */
2047 void
2048 OP_800 ()
2049 {
2050 int16 tmp;
2051 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2052 tmp = (GPR (OP[0]) | GPR (OP[1]));
2053 SET_GPR (OP[0], tmp);
2054 trace_output_16 (tmp);
2055 }
2056
2057 /* or3 */
2058 void
2059 OP_4000000 ()
2060 {
2061 int16 tmp;
2062 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2063 tmp = (GPR (OP[1]) | OP[2]);
2064 SET_GPR (OP[0], tmp);
2065 trace_output_16 (tmp);
2066 }
2067
2068 /* rac */
2069 void
2070 OP_5201 ()
2071 {
2072 int64 tmp;
2073 int shift = SEXT3 (OP[2]);
2074
2075 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2076 if (OP[1] != 0)
2077 {
2078 (*d10v_callback->printf_filtered) (d10v_callback,
2079 "ERROR at PC 0x%x: instruction only valid for A0\n",
2080 PC<<2);
2081 State.exception = SIGILL;
2082 }
2083
2084 SET_PSW_F1 (PSW_F0);
2085 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2086 if (shift >=0)
2087 tmp <<= shift;
2088 else
2089 tmp >>= -shift;
2090 tmp += 0x8000;
2091 tmp >>= 16; /* look at bits 0:43 */
2092 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2093 {
2094 tmp = 0x7fffffff;
2095 SET_PSW_F0 (1);
2096 }
2097 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2098 {
2099 tmp = 0x80000000;
2100 SET_PSW_F0 (1);
2101 }
2102 else
2103 {
2104 SET_PSW_F0 (0);
2105 }
2106 SET_GPR32 (OP[0], tmp);
2107 trace_output_32 (tmp);
2108 }
2109
2110 /* rachi */
2111 void
2112 OP_4201 ()
2113 {
2114 signed64 tmp;
2115 int shift = SEXT3 (OP[2]);
2116
2117 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2118 SET_PSW_F1 (PSW_F0);
2119 if (shift >=0)
2120 tmp = SEXT40 (ACC (OP[1])) << shift;
2121 else
2122 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2123 tmp += 0x8000;
2124
2125 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2126 {
2127 tmp = 0x7fff;
2128 SET_PSW_F0 (1);
2129 }
2130 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2131 {
2132 tmp = 0x8000;
2133 SET_PSW_F0 (1);
2134 }
2135 else
2136 {
2137 tmp = (tmp >> 16);
2138 SET_PSW_F0 (0);
2139 }
2140 SET_GPR (OP[0], tmp);
2141 trace_output_16 (tmp);
2142 }
2143
2144 /* rep */
2145 void
2146 OP_27000000 ()
2147 {
2148 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2149 SET_RPT_S (PC + 1);
2150 SET_RPT_E (PC + OP[1]);
2151 SET_RPT_C (GPR (OP[0]));
2152 SET_PSW_RP (1);
2153 if (GPR (OP[0]) == 0)
2154 {
2155 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2156 State.exception = SIGILL;
2157 }
2158 if (OP[1] < 4)
2159 {
2160 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2161 State.exception = SIGILL;
2162 }
2163 trace_output_void ();
2164 }
2165
2166 /* repi */
2167 void
2168 OP_2F000000 ()
2169 {
2170 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2171 SET_RPT_S (PC + 1);
2172 SET_RPT_E (PC + OP[1]);
2173 SET_RPT_C (OP[0]);
2174 SET_PSW_RP (1);
2175 if (OP[0] == 0)
2176 {
2177 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2178 State.exception = SIGILL;
2179 }
2180 if (OP[1] < 4)
2181 {
2182 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2183 State.exception = SIGILL;
2184 }
2185 trace_output_void ();
2186 }
2187
2188 /* rtd */
2189 void
2190 OP_5F60 ()
2191 {
2192 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2193 SET_CREG (PSW_CR, DPSW);
2194 JMP(DPC);
2195 trace_output_void ();
2196 }
2197
2198 /* rte */
2199 void
2200 OP_5F40 ()
2201 {
2202 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2203 SET_CREG (PSW_CR, BPSW);
2204 JMP(BPC);
2205 trace_output_void ();
2206 }
2207
2208 /* sadd */
2209 void
2210 OP_1223 ()
2211 {
2212 int64 tmp;
2213
2214 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2215 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2216 if (PSW_ST)
2217 {
2218 if (tmp > SEXT40(MAX32))
2219 tmp = (MAX32);
2220 else if (tmp < SEXT40(MIN32))
2221 tmp = (MIN32);
2222 else
2223 tmp = (tmp & MASK40);
2224 }
2225 else
2226 tmp = (tmp & MASK40);
2227 SET_ACC (OP[0], tmp);
2228 trace_output_40 (tmp);
2229 }
2230
2231 /* setf0f */
2232 void
2233 OP_4611 ()
2234 {
2235 int16 tmp;
2236 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2237 tmp = ((PSW_F0 == 0) ? 1 : 0);
2238 SET_GPR (OP[0], tmp);
2239 trace_output_16 (tmp);
2240 }
2241
2242 /* setf0t */
2243 void
2244 OP_4613 ()
2245 {
2246 int16 tmp;
2247 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2248 tmp = ((PSW_F0 == 1) ? 1 : 0);
2249 SET_GPR (OP[0], tmp);
2250 trace_output_16 (tmp);
2251 }
2252
2253 /* sleep */
2254 void
2255 OP_5FC0 ()
2256 {
2257 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2258 SET_PSW_IE (1);
2259 trace_output_void ();
2260 }
2261
2262 /* sll */
2263 void
2264 OP_2200 ()
2265 {
2266 int16 tmp;
2267 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2268 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2269 SET_GPR (OP[0], tmp);
2270 trace_output_16 (tmp);
2271 }
2272
2273 /* sll */
2274 void
2275 OP_3200 ()
2276 {
2277 int64 tmp;
2278 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2279 if ((GPR (OP[1]) & 31) <= 16)
2280 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2281 else
2282 {
2283 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2284 State.exception = SIGILL;
2285 return;
2286 }
2287
2288 if (PSW_ST)
2289 {
2290 if (tmp > SEXT40(MAX32))
2291 tmp = (MAX32);
2292 else if (tmp < SEXT40(MIN32))
2293 tmp = (MIN32);
2294 else
2295 tmp = (tmp & MASK40);
2296 }
2297 else
2298 tmp = (tmp & MASK40);
2299 SET_ACC (OP[0], tmp);
2300 trace_output_40 (tmp);
2301 }
2302
2303 /* slli */
2304 void
2305 OP_2201 ()
2306 {
2307 int16 tmp;
2308 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2309 tmp = (GPR (OP[0]) << OP[1]);
2310 SET_GPR (OP[0], tmp);
2311 trace_output_16 (tmp);
2312 }
2313
2314 /* slli */
2315 void
2316 OP_3201 ()
2317 {
2318 int64 tmp;
2319
2320 if (OP[1] == 0)
2321 OP[1] = 16;
2322
2323 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2324 tmp = SEXT40(ACC (OP[0])) << OP[1];
2325
2326 if (PSW_ST)
2327 {
2328 if (tmp > SEXT40(MAX32))
2329 tmp = (MAX32);
2330 else if (tmp < SEXT40(MIN32))
2331 tmp = (MIN32);
2332 else
2333 tmp = (tmp & MASK40);
2334 }
2335 else
2336 tmp = (tmp & MASK40);
2337 SET_ACC (OP[0], tmp);
2338 trace_output_40 (tmp);
2339 }
2340
2341 /* slx */
2342 void
2343 OP_460B ()
2344 {
2345 int16 tmp;
2346 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2347 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2348 SET_GPR (OP[0], tmp);
2349 trace_output_16 (tmp);
2350 }
2351
2352 /* sra */
2353 void
2354 OP_2400 ()
2355 {
2356 int16 tmp;
2357 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2358 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2359 SET_GPR (OP[0], tmp);
2360 trace_output_16 (tmp);
2361 }
2362
2363 /* sra */
2364 void
2365 OP_3400 ()
2366 {
2367 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2368 if ((GPR (OP[1]) & 31) <= 16)
2369 {
2370 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2371 SET_ACC (OP[0], tmp);
2372 trace_output_40 (tmp);
2373 }
2374 else
2375 {
2376 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2377 State.exception = SIGILL;
2378 return;
2379 }
2380 }
2381
2382 /* srai */
2383 void
2384 OP_2401 ()
2385 {
2386 int16 tmp;
2387 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2388 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2389 SET_GPR (OP[0], tmp);
2390 trace_output_16 (tmp);
2391 }
2392
2393 /* srai */
2394 void
2395 OP_3401 ()
2396 {
2397 int64 tmp;
2398 if (OP[1] == 0)
2399 OP[1] = 16;
2400
2401 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2402 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2403 SET_ACC (OP[0], tmp);
2404 trace_output_40 (tmp);
2405 }
2406
2407 /* srl */
2408 void
2409 OP_2000 ()
2410 {
2411 int16 tmp;
2412 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2413 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2414 SET_GPR (OP[0], tmp);
2415 trace_output_16 (tmp);
2416 }
2417
2418 /* srl */
2419 void
2420 OP_3000 ()
2421 {
2422 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2423 if ((GPR (OP[1]) & 31) <= 16)
2424 {
2425 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2426 SET_ACC (OP[0], tmp);
2427 trace_output_40 (tmp);
2428 }
2429 else
2430 {
2431 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2432 State.exception = SIGILL;
2433 return;
2434 }
2435
2436 }
2437
2438 /* srli */
2439 void
2440 OP_2001 ()
2441 {
2442 int16 tmp;
2443 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2444 tmp = (GPR (OP[0]) >> OP[1]);
2445 SET_GPR (OP[0], tmp);
2446 trace_output_16 (tmp);
2447 }
2448
2449 /* srli */
2450 void
2451 OP_3001 ()
2452 {
2453 int64 tmp;
2454 if (OP[1] == 0)
2455 OP[1] = 16;
2456
2457 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2458 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2459 SET_ACC (OP[0], tmp);
2460 trace_output_40 (tmp);
2461 }
2462
2463 /* srx */
2464 void
2465 OP_4609 ()
2466 {
2467 uint16 tmp;
2468 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2469 tmp = PSW_F0 << 15;
2470 tmp = ((GPR (OP[0]) >> 1) | tmp);
2471 SET_GPR (OP[0], tmp);
2472 trace_output_16 (tmp);
2473 }
2474
2475 /* st */
2476 void
2477 OP_34000000 ()
2478 {
2479 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2480 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2481 trace_output_void ();
2482 }
2483
2484 /* st */
2485 void
2486 OP_6800 ()
2487 {
2488 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2489 SW (GPR (OP[1]), GPR (OP[0]));
2490 trace_output_void ();
2491 }
2492
2493 /* st */
2494 void
2495 OP_6C1F ()
2496 {
2497 uint16 addr = GPR (OP[1]) - 2;
2498 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2499 if (OP[1] != 15)
2500 {
2501 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2502 State.exception = SIGILL;
2503 return;
2504 }
2505 SW (addr, GPR (OP[0]));
2506 SET_GPR (OP[1], addr);
2507 trace_output_void ();
2508 }
2509
2510 /* st */
2511 void
2512 OP_6801 ()
2513 {
2514 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2515 SW (GPR (OP[1]), GPR (OP[0]));
2516 INC_ADDR (OP[1], 2);
2517 trace_output_void ();
2518 }
2519
2520 /* st */
2521 void
2522 OP_6C01 ()
2523 {
2524 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2525 if ( OP[1] == 15 )
2526 {
2527 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2528 State.exception = SIGILL;
2529 return;
2530 }
2531 SW (GPR (OP[1]), GPR (OP[0]));
2532 INC_ADDR (OP[1], -2);
2533 trace_output_void ();
2534 }
2535
2536 /* st2w */
2537 void
2538 OP_35000000 ()
2539 {
2540 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2541 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2542 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2543 trace_output_void ();
2544 }
2545
2546 /* st2w */
2547 void
2548 OP_6A00 ()
2549 {
2550 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2551 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2552 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2553 trace_output_void ();
2554 }
2555
2556 /* st2w */
2557 void
2558 OP_6E1F ()
2559 {
2560 uint16 addr = GPR (OP[1]) - 4;
2561 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2562 if ( OP[1] != 15 )
2563 {
2564 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2565 State.exception = SIGILL;
2566 return;
2567 }
2568 SW (addr + 0, GPR (OP[0] + 0));
2569 SW (addr + 2, GPR (OP[0] + 1));
2570 SET_GPR (OP[1], addr);
2571 trace_output_void ();
2572 }
2573
2574 /* st2w */
2575 void
2576 OP_6A01 ()
2577 {
2578 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2579 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2580 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2581 INC_ADDR (OP[1], 4);
2582 trace_output_void ();
2583 }
2584
2585 /* st2w */
2586 void
2587 OP_6E01 ()
2588 {
2589 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2590 if ( OP[1] == 15 )
2591 {
2592 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2593 State.exception = SIGILL;
2594 return;
2595 }
2596 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2597 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2598 INC_ADDR (OP[1], -4);
2599 trace_output_void ();
2600 }
2601
2602 /* stb */
2603 void
2604 OP_3C000000 ()
2605 {
2606 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2607 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2608 trace_output_void ();
2609 }
2610
2611 /* stb */
2612 void
2613 OP_7800 ()
2614 {
2615 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2616 SB (GPR (OP[1]), GPR (OP[0]));
2617 trace_output_void ();
2618 }
2619
2620 /* stop */
2621 void
2622 OP_5FE0 ()
2623 {
2624 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2625 State.exception = SIG_D10V_STOP;
2626 trace_output_void ();
2627 }
2628
2629 /* sub */
2630 void
2631 OP_0 ()
2632 {
2633 uint16 a = GPR (OP[0]);
2634 uint16 b = GPR (OP[1]);
2635 uint16 tmp = (a - b);
2636 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2637 /* see ../common/sim-alu.h for a more extensive discussion on how to
2638 compute the carry/overflow bits. */
2639 SET_PSW_C (a >= b);
2640 SET_GPR (OP[0], tmp);
2641 trace_output_16 (tmp);
2642 }
2643
2644 /* sub */
2645 void
2646 OP_1001 ()
2647 {
2648 int64 tmp;
2649
2650 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2651 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2652 if (PSW_ST)
2653 {
2654 if (tmp > SEXT40(MAX32))
2655 tmp = (MAX32);
2656 else if (tmp < SEXT40(MIN32))
2657 tmp = (MIN32);
2658 else
2659 tmp = (tmp & MASK40);
2660 }
2661 else
2662 tmp = (tmp & MASK40);
2663 SET_ACC (OP[0], tmp);
2664
2665 trace_output_40 (tmp);
2666 }
2667
2668 /* sub */
2669
2670 void
2671 OP_1003 ()
2672 {
2673 int64 tmp;
2674
2675 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2676 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2677 if (PSW_ST)
2678 {
2679 if (tmp > SEXT40(MAX32))
2680 tmp = (MAX32);
2681 else if (tmp < SEXT40(MIN32))
2682 tmp = (MIN32);
2683 else
2684 tmp = (tmp & MASK40);
2685 }
2686 else
2687 tmp = (tmp & MASK40);
2688 SET_ACC (OP[0], tmp);
2689
2690 trace_output_40 (tmp);
2691 }
2692
2693 /* sub2w */
2694 void
2695 OP_1000 ()
2696 {
2697 uint32 tmp, a, b;
2698
2699 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2700 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2701 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2702 /* see ../common/sim-alu.h for a more extensive discussion on how to
2703 compute the carry/overflow bits */
2704 tmp = a - b;
2705 SET_PSW_C (a >= b);
2706 SET_GPR32 (OP[0], tmp);
2707 trace_output_32 (tmp);
2708 }
2709
2710 /* subac3 */
2711 void
2712 OP_17000000 ()
2713 {
2714 int64 tmp;
2715
2716 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2717 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2718 SET_GPR32 (OP[0], tmp);
2719 trace_output_32 (tmp);
2720 }
2721
2722 /* subac3 */
2723 void
2724 OP_17000002 ()
2725 {
2726 int64 tmp;
2727
2728 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2729 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2730 SET_GPR32 (OP[0], tmp);
2731 trace_output_32 (tmp);
2732 }
2733
2734 /* subac3s */
2735 void
2736 OP_17001000 ()
2737 {
2738 int64 tmp;
2739
2740 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2741 SET_PSW_F1 (PSW_F0);
2742 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2743 if (tmp > SEXT40(MAX32))
2744 {
2745 tmp = (MAX32);
2746 SET_PSW_F0 (1);
2747 }
2748 else if (tmp < SEXT40(MIN32))
2749 {
2750 tmp = (MIN32);
2751 SET_PSW_F0 (1);
2752 }
2753 else
2754 {
2755 SET_PSW_F0 (0);
2756 }
2757 SET_GPR32 (OP[0], tmp);
2758 trace_output_32 (tmp);
2759 }
2760
2761 /* subac3s */
2762 void
2763 OP_17001002 ()
2764 {
2765 int64 tmp;
2766
2767 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2768 SET_PSW_F1 (PSW_F0);
2769 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2770 if (tmp > SEXT40(MAX32))
2771 {
2772 tmp = (MAX32);
2773 SET_PSW_F0 (1);
2774 }
2775 else if (tmp < SEXT40(MIN32))
2776 {
2777 tmp = (MIN32);
2778 SET_PSW_F0 (1);
2779 }
2780 else
2781 {
2782 SET_PSW_F0 (0);
2783 }
2784 SET_GPR32 (OP[0], tmp);
2785 trace_output_32 (tmp);
2786 }
2787
2788 /* subi */
2789 void
2790 OP_1 ()
2791 {
2792 unsigned tmp;
2793 if (OP[1] == 0)
2794 OP[1] = 16;
2795
2796 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2797 /* see ../common/sim-alu.h for a more extensive discussion on how to
2798 compute the carry/overflow bits. */
2799 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2800 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2801 + (unsigned)(unsigned16) ( - OP[1]));
2802 SET_PSW_C (tmp >= (1 << 16));
2803 SET_GPR (OP[0], tmp);
2804 trace_output_16 (tmp);
2805 }
2806
2807 /* trap */
2808 void
2809 OP_5F00 ()
2810 {
2811 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2812 trace_output_void ();
2813
2814 switch (OP[0])
2815 {
2816 default:
2817 #if (DEBUG & DEBUG_TRAP) == 0
2818 {
2819 uint16 vec = OP[0] + TRAP_VECTOR_START;
2820 SET_BPC (PC + 1);
2821 SET_BPSW (PSW);
2822 SET_PSW (PSW & PSW_SM_BIT);
2823 JMP (vec);
2824 break;
2825 }
2826 #else /* if debugging use trap to print registers */
2827 {
2828 int i;
2829 static int first_time = 1;
2830
2831 if (first_time)
2832 {
2833 first_time = 0;
2834 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2835 for (i = 0; i < 16; i++)
2836 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2837 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2838 }
2839
2840 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2841
2842 for (i = 0; i < 16; i++)
2843 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
2844
2845 for (i = 0; i < 2; i++)
2846 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2847 ((int)(ACC (i) >> 32) & 0xff),
2848 ((unsigned long) ACC (i)) & 0xffffffff);
2849
2850 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2851 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
2852 (*d10v_callback->flush_stdout) (d10v_callback);
2853 break;
2854 }
2855 #endif
2856 case 15: /* new system call trap */
2857 /* Trap 15 is used for simulating low-level I/O */
2858 {
2859 unsigned32 result = 0;
2860 errno = 0;
2861
2862 /* Registers passed to trap 0 */
2863
2864 #define FUNC GPR (4) /* function number */
2865 #define PARM1 GPR (0) /* optional parm 1 */
2866 #define PARM2 GPR (1) /* optional parm 2 */
2867 #define PARM3 GPR (2) /* optional parm 3 */
2868 #define PARM4 GPR (3) /* optional parm 3 */
2869
2870 /* Registers set by trap 0 */
2871
2872 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
2873 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
2874 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
2875
2876 /* Turn a pointer in a register into a pointer into real memory. */
2877
2878 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2879
2880 switch (FUNC)
2881 {
2882 #if !defined(__GO32__) && !defined(_WIN32)
2883 case TARGET_SYS_fork:
2884 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2885 RETVAL (fork ());
2886 trace_output_16 (result);
2887 break;
2888
2889 #define getpid() 47
2890 case TARGET_SYS_getpid:
2891 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2892 RETVAL (getpid ());
2893 trace_output_16 (result);
2894 break;
2895
2896 case TARGET_SYS_kill:
2897 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
2898 if (PARM1 == getpid ())
2899 {
2900 trace_output_void ();
2901 State.exception = PARM2;
2902 }
2903 else
2904 {
2905 int os_sig = -1;
2906 switch (PARM2)
2907 {
2908 #ifdef SIGHUP
2909 case 1: os_sig = SIGHUP; break;
2910 #endif
2911 #ifdef SIGINT
2912 case 2: os_sig = SIGINT; break;
2913 #endif
2914 #ifdef SIGQUIT
2915 case 3: os_sig = SIGQUIT; break;
2916 #endif
2917 #ifdef SIGILL
2918 case 4: os_sig = SIGILL; break;
2919 #endif
2920 #ifdef SIGTRAP
2921 case 5: os_sig = SIGTRAP; break;
2922 #endif
2923 #ifdef SIGABRT
2924 case 6: os_sig = SIGABRT; break;
2925 #elif defined(SIGIOT)
2926 case 6: os_sig = SIGIOT; break;
2927 #endif
2928 #ifdef SIGEMT
2929 case 7: os_sig = SIGEMT; break;
2930 #endif
2931 #ifdef SIGFPE
2932 case 8: os_sig = SIGFPE; break;
2933 #endif
2934 #ifdef SIGKILL
2935 case 9: os_sig = SIGKILL; break;
2936 #endif
2937 #ifdef SIGBUS
2938 case 10: os_sig = SIGBUS; break;
2939 #endif
2940 #ifdef SIGSEGV
2941 case 11: os_sig = SIGSEGV; break;
2942 #endif
2943 #ifdef SIGSYS
2944 case 12: os_sig = SIGSYS; break;
2945 #endif
2946 #ifdef SIGPIPE
2947 case 13: os_sig = SIGPIPE; break;
2948 #endif
2949 #ifdef SIGALRM
2950 case 14: os_sig = SIGALRM; break;
2951 #endif
2952 #ifdef SIGTERM
2953 case 15: os_sig = SIGTERM; break;
2954 #endif
2955 #ifdef SIGURG
2956 case 16: os_sig = SIGURG; break;
2957 #endif
2958 #ifdef SIGSTOP
2959 case 17: os_sig = SIGSTOP; break;
2960 #endif
2961 #ifdef SIGTSTP
2962 case 18: os_sig = SIGTSTP; break;
2963 #endif
2964 #ifdef SIGCONT
2965 case 19: os_sig = SIGCONT; break;
2966 #endif
2967 #ifdef SIGCHLD
2968 case 20: os_sig = SIGCHLD; break;
2969 #elif defined(SIGCLD)
2970 case 20: os_sig = SIGCLD; break;
2971 #endif
2972 #ifdef SIGTTIN
2973 case 21: os_sig = SIGTTIN; break;
2974 #endif
2975 #ifdef SIGTTOU
2976 case 22: os_sig = SIGTTOU; break;
2977 #endif
2978 #ifdef SIGIO
2979 case 23: os_sig = SIGIO; break;
2980 #elif defined (SIGPOLL)
2981 case 23: os_sig = SIGPOLL; break;
2982 #endif
2983 #ifdef SIGXCPU
2984 case 24: os_sig = SIGXCPU; break;
2985 #endif
2986 #ifdef SIGXFSZ
2987 case 25: os_sig = SIGXFSZ; break;
2988 #endif
2989 #ifdef SIGVTALRM
2990 case 26: os_sig = SIGVTALRM; break;
2991 #endif
2992 #ifdef SIGPROF
2993 case 27: os_sig = SIGPROF; break;
2994 #endif
2995 #ifdef SIGWINCH
2996 case 28: os_sig = SIGWINCH; break;
2997 #endif
2998 #ifdef SIGLOST
2999 case 29: os_sig = SIGLOST; break;
3000 #endif
3001 #ifdef SIGUSR1
3002 case 30: os_sig = SIGUSR1; break;
3003 #endif
3004 #ifdef SIGUSR2
3005 case 31: os_sig = SIGUSR2; break;
3006 #endif
3007 }
3008
3009 if (os_sig == -1)
3010 {
3011 trace_output_void ();
3012 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3013 (*d10v_callback->flush_stdout) (d10v_callback);
3014 State.exception = SIGILL;
3015 }
3016 else
3017 {
3018 RETVAL (kill (PARM1, PARM2));
3019 trace_output_16 (result);
3020 }
3021 }
3022 break;
3023
3024 case TARGET_SYS_execve:
3025 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3026 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3027 (char **)MEMPTR (PARM3)));
3028 trace_output_16 (result);
3029 break;
3030
3031 #ifdef TARGET_SYS_execv
3032 case TARGET_SYS_execv:
3033 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3034 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3035 trace_output_16 (result);
3036 break;
3037 #endif
3038
3039 case TARGET_SYS_pipe:
3040 {
3041 reg_t buf;
3042 int host_fd[2];
3043
3044 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3045 buf = PARM1;
3046 RETVAL (pipe (host_fd));
3047 SW (buf, host_fd[0]);
3048 buf += sizeof(uint16);
3049 SW (buf, host_fd[1]);
3050 trace_output_16 (result);
3051 }
3052 break;
3053
3054 #if 0
3055 #ifdef TARGET_SYS_wait
3056 case TARGET_SYS_wait:
3057 {
3058 int status;
3059 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3060 RETVAL (wait (&status));
3061 if (PARM1)
3062 SW (PARM1, status);
3063 trace_output_16 (result);
3064 }
3065 break;
3066 #endif
3067 #endif
3068 #else
3069 case TARGET_SYS_getpid:
3070 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3071 RETVAL (1);
3072 trace_output_16 (result);
3073 break;
3074
3075 case TARGET_SYS_kill:
3076 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3077 trace_output_void ();
3078 State.exception = PARM2;
3079 break;
3080 #endif
3081
3082 case TARGET_SYS_read:
3083 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3084 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3085 PARM3));
3086 trace_output_16 (result);
3087 break;
3088
3089 case TARGET_SYS_write:
3090 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3091 if (PARM1 == 1)
3092 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3093 MEMPTR (PARM2), PARM3));
3094 else
3095 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3096 MEMPTR (PARM2), PARM3));
3097 trace_output_16 (result);
3098 break;
3099
3100 case TARGET_SYS_lseek:
3101 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3102 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3103 ((((unsigned long) PARM2) << 16)
3104 || (unsigned long) PARM3),
3105 PARM4));
3106 trace_output_32 (result);
3107 break;
3108
3109 case TARGET_SYS_close:
3110 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3111 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3112 trace_output_16 (result);
3113 break;
3114
3115 case TARGET_SYS_open:
3116 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3117 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3118 trace_output_16 (result);
3119 break;
3120
3121 case TARGET_SYS_exit:
3122 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3123 State.exception = SIG_D10V_EXIT;
3124 trace_output_void ();
3125 break;
3126
3127 case TARGET_SYS_stat:
3128 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3129 /* stat system call */
3130 {
3131 struct stat host_stat;
3132 reg_t buf;
3133
3134 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3135
3136 buf = PARM2;
3137
3138 /* The hard-coded offsets and sizes were determined by using
3139 * the D10V compiler on a test program that used struct stat.
3140 */
3141 SW (buf, host_stat.st_dev);
3142 SW (buf+2, host_stat.st_ino);
3143 SW (buf+4, host_stat.st_mode);
3144 SW (buf+6, host_stat.st_nlink);
3145 SW (buf+8, host_stat.st_uid);
3146 SW (buf+10, host_stat.st_gid);
3147 SW (buf+12, host_stat.st_rdev);
3148 SLW (buf+16, host_stat.st_size);
3149 SLW (buf+20, host_stat.st_atime);
3150 SLW (buf+28, host_stat.st_mtime);
3151 SLW (buf+36, host_stat.st_ctime);
3152 }
3153 trace_output_16 (result);
3154 break;
3155
3156 case TARGET_SYS_chown:
3157 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3158 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3159 trace_output_16 (result);
3160 break;
3161
3162 case TARGET_SYS_chmod:
3163 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3164 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3165 trace_output_16 (result);
3166 break;
3167
3168 #if 0
3169 #ifdef TARGET_SYS_utime
3170 case TARGET_SYS_utime:
3171 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3172 /* Cast the second argument to void *, to avoid type mismatch
3173 if a prototype is present. */
3174 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3175 trace_output_16 (result);
3176 break;
3177 #endif
3178 #endif
3179
3180 #if 0
3181 #ifdef TARGET_SYS_time
3182 case TARGET_SYS_time:
3183 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3184 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3185 trace_output_32 (result);
3186 break;
3187 #endif
3188 #endif
3189
3190 default:
3191 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3192 }
3193 if ((uint16) result == (uint16) -1)
3194 RETERR (d10v_callback->get_errno(d10v_callback));
3195 else
3196 RETERR (0);
3197 break;
3198 }
3199 }
3200 }
3201
3202 /* tst0i */
3203 void
3204 OP_7000000 ()
3205 {
3206 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3207 SET_PSW_F1 (PSW_F0);;
3208 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3209 trace_output_flag ();
3210 }
3211
3212 /* tst1i */
3213 void
3214 OP_F000000 ()
3215 {
3216 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3217 SET_PSW_F1 (PSW_F0);
3218 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3219 trace_output_flag ();
3220 }
3221
3222 /* wait */
3223 void
3224 OP_5F80 ()
3225 {
3226 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3227 SET_PSW_IE (1);
3228 trace_output_void ();
3229 }
3230
3231 /* xor */
3232 void
3233 OP_A00 ()
3234 {
3235 int16 tmp;
3236 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3237 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3238 SET_GPR (OP[0], tmp);
3239 trace_output_16 (tmp);
3240 }
3241
3242 /* xor3 */
3243 void
3244 OP_5000000 ()
3245 {
3246 int16 tmp;
3247 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3248 tmp = (GPR (OP[1]) ^ OP[2]);
3249 SET_GPR (OP[0], tmp);
3250 trace_output_16 (tmp);
3251 }
3252
GDB Binutils - Deliverables
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