sim/d10v/simops.c

   1 #include <signal.h>
   2 #include "d10v_sim.h"
   3 #include "simops.h"
   4
   5 /* #define DEBUG 1 */
   6
   7 /* abs */
   8 void
   9 OP_4607 ()
  10 {
  11 #ifdef DEBUG
  12   printf("   abs\tr%d\n",OP[0]);
  13 #endif
  14   State.F1 = State.F0;
  15   if ((int16)(State.regs[OP[0]]) < 0)
  16     {
  17       State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
  18       State.F0 = 1;
  19     }
  20   else
  21     State.F0 = 0;
  22 }
  23
  24 /* abs */
  25 void
  26 OP_5607 ()
  27 {
  28   int64 tmp;
  29
  30 #ifdef DEBUG
  31   printf("   abs\ta%d\n",OP[0]);
  32 #endif
  33   State.F1 = State.F0;
  34   State.a[OP[0]] = SEXT40(State.a[OP[0]]);
  35
  36   if (State.a[OP[0]] < 0 )
  37     {
  38       tmp = -State.a[OP[0]];
  39       if (State.ST)
  40         {
  41           if (tmp > MAX32)
  42             State.a[OP[0]] = MAX32;
  43           else if (tmp < MIN32)
  44             State.a[OP[0]] = MIN32;
  45           else
  46             State.a[OP[0]] = tmp & MASK40;
  47         }
  48       else
  49         State.a[OP[0]] = tmp & MASK40;
  50       State.F0 = 1;
  51     }
  52   else
  53     State.F0 = 0;
  54 }
  55
  56 /* add */
  57 void
  58 OP_200 ()
  59 {
  60   uint16 tmp = State.regs[OP[0]];
  61 #ifdef DEBUG
  62   printf("   add\tr%d,r%d\n",OP[0],OP[1]);
  63 #endif
  64   State.regs[OP[0]] += State.regs[OP[1]];
  65   if ( tmp > State.regs[OP[0]])
  66     State.C = 1;
  67   else
  68     State.C = 0;
  69 }
  70
  71 /* add */
  72 void
  73 OP_1201 ()
  74 {
  75   int64 tmp;
  76 #ifdef DEBUG
  77   printf("   add\ta%d,r%d\n",OP[0],OP[1]);
  78 #endif
  79   tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
  80   if (State.ST)
  81     {
  82       if ( tmp > MAX32)
  83         State.a[OP[0]] = MAX32;
  84       else if ( tmp < MIN32)
  85         State.a[OP[0]] = MIN32;
  86       else
  87         State.a[OP[0]] = tmp & MASK40;
  88     }
  89   else
  90     State.a[OP[0]] = tmp & MASK40;
  91 }
  92
  93 /* add */
  94 void
  95 OP_1203 ()
  96 {
  97   int64 tmp;
  98 #ifdef DEBUG
  99   printf("   add\ta%d,a%d\n",OP[0],OP[1]);
 100 #endif
 101   tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
 102   if (State.ST)
 103     {
 104       if (tmp > MAX32)
 105         State.a[OP[0]] = MAX32;
 106       else if ( tmp < MIN32)
 107         State.a[OP[0]] = MIN32;
 108       else
 109         State.a[OP[0]] = tmp & MASK40;
 110     }
 111   else
 112     State.a[OP[0]] = tmp & MASK40;
 113 }
 114
 115 /* add2w */
 116 void
 117 OP_1200 ()
 118 {
 119   uint32 tmp;
 120   uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
 121   uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
 122 #ifdef DEBUG
 123   printf("   add2w\tr%d,r%d\n",OP[0],OP[1]);
 124 #endif
 125   tmp = tmp1 + tmp2;
 126   if ( (tmp < tmp1) || (tmp < tmp2) )
 127     State.C = 1;
 128   else
 129     State.C = 0;
 130   State.regs[OP[0]] = tmp >> 16;
 131   State.regs[OP[0]+1] = tmp & 0xFFFF;
 132 }
 133
 134 /* add3 */
 135 void
 136 OP_1000000 ()
 137 {
 138   uint16 tmp = State.regs[OP[0]];
 139 #ifdef DEBUG
 140   printf("   add3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
 141 #endif
 142   State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
 143   if ( tmp > State.regs[OP[0]])
 144     State.C = 1;
 145   else
 146     State.C = 0;
 147 }
 148
 149 /* addac3 */
 150 void
 151 OP_17000200 ()
 152 {
 153   int64 tmp;
 154 #ifdef DEBUG
 155   printf("   addac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
 156 #endif
 157   tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
 158   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
 159   State.regs[OP[0]+1] = tmp & 0xffff;
 160 }
 161
 162 /* addac3 */
 163 void
 164 OP_17000202 ()
 165 {
 166   int64 tmp;
 167 #ifdef DEBUG
 168   printf("   addac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
 169 #endif
 170   tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
 171   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
 172   State.regs[OP[0]+1] = tmp & 0xffff;
 173 }
 174
 175 /* addac3s */
 176 void
 177 OP_17001200 ()
 178 {
 179   int64 tmp;
 180 #ifdef DEBUG
 181   printf("   addac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
 182 #endif
 183   State.F1 = State.F0;
 184   tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
 185   if ( tmp > MAX32)
 186     {
 187       State.regs[OP[0]] = 0x7fff;
 188       State.regs[OP[0]+1] = 0xffff;
 189       State.F0 = 1;
 190     }
 191   else if (tmp < MIN32)
 192     {
 193       State.regs[OP[0]] = 0x8000;
 194       State.regs[OP[0]+1] = 0;
 195       State.F0 = 1;
 196     }
 197   else
 198     {
 199       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
 200       State.regs[OP[0]+1] = tmp & 0xffff;
 201       State.F0 = 0;
 202     }
 203 }
 204
 205 /* addac3s */
 206 void
 207 OP_17001202 ()
 208 {
 209   int64 tmp;
 210 #ifdef DEBUG
 211   printf("   addac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
 212 #endif
 213   State.F1 = State.F0;
 214   tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
 215   if ( tmp > MAX32)
 216     {
 217       State.regs[OP[0]] = 0x7fff;
 218       State.regs[OP[0]+1] = 0xffff;
 219       State.F0 = 1;
 220     }
 221   else if (tmp < MIN32)
 222     {
 223       State.regs[OP[0]] = 0x8000;
 224       State.regs[OP[0]+1] = 0;
 225       State.F0 = 1;
 226     }
 227   else
 228     {
 229       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
 230       State.regs[OP[0]+1] = tmp & 0xffff;
 231       State.F0 = 0;
 232     }
 233 }
 234
 235 /* addi */
 236 void
 237 OP_201 ()
 238 {
 239   if (OP[1] == 0)
 240     OP[1] = 16;
 241 #ifdef DEBUG
 242   printf("   addi\tr%d,0x%x\n",OP[0],OP[1]);
 243 #endif
 244   State.regs[OP[0]] += OP[1];
 245 }
 246
 247 /* and */
 248 void
 249 OP_C00 ()
 250 {
 251 #ifdef DEBUG
 252   printf("   and\tr%d,r%d\n",OP[0],OP[1]);
 253 #endif
 254   State.regs[OP[0]] &= State.regs[OP[1]];
 255 }
 256
 257 /* and3 */
 258 void
 259 OP_6000000 ()
 260 {
 261 #ifdef DEBUG
 262   printf("   and3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
 263 #endif
 264   State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
 265 }
 266
 267 /* bclri */
 268 void
 269 OP_C01 ()
 270 {
 271 #ifdef DEBUG
 272   printf("   bclri\tr%d,%d\n",OP[0],OP[1]);
 273 #endif
 274   State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
 275 }
 276
 277 /* bl.s */
 278 void
 279 OP_4900 ()
 280 {
 281 #ifdef DEBUG
 282   printf("   bl.s\t0x%x\n",OP[0]);
 283 #endif
 284   State.regs[13] = PC+1;
 285   PC += SEXT8 (OP[0]);
 286 }
 287
 288 /* bl.l */
 289 void
 290 OP_24800000 ()
 291 {
 292 #ifdef DEBUG
 293   printf("   bl.l\t0x%x\n",OP[0]);
 294 #endif
 295   State.regs[13] = PC+1;
 296   PC += OP[0];
 297 }
 298
 299 /* bnoti */
 300 void
 301 OP_A01 ()
 302 {
 303 #ifdef DEBUG
 304   printf("   bnoti\tr%d,%d\n",OP[0],OP[1]);
 305 #endif
 306   State.regs[OP[0]] ^= 0x8000 >> OP[1];
 307 }
 308
 309 /* bra.s */
 310 void
 311 OP_4800 ()
 312 {
 313 #ifdef DEBUG
 314   printf("   bra.s\t0x%x\n",OP[0]);
 315 #endif
 316   PC += SEXT8 (OP[0]);
 317 }
 318
 319 /* bra.l */
 320 void
 321 OP_24000000 ()
 322 {
 323 #ifdef DEBUG
 324   printf("   bra.l\t0x%x\n",OP[0]);
 325 #endif
 326   PC += OP[0];
 327 }
 328
 329 /* brf0f.s */
 330 void
 331 OP_4A00 ()
 332 {
 333 #ifdef DEBUG
 334   printf("   brf0f.s\t0x%x\n",OP[0]);
 335 #endif
 336   if (State.F0 == 0)
 337     PC += SEXT8 (OP[0]);
 338 }
 339
 340 /* brf0f.l */
 341 void
 342 OP_25000000 ()
 343 {
 344 #ifdef DEBUG
 345   printf("   brf0f.l\t0x%x\n",OP[0]);
 346 #endif
 347   if (State.F0 == 0)
 348     PC += OP[0];
 349 }
 350
 351 /* brf0t.s */
 352 void
 353 OP_4B00 ()
 354 {
 355 #ifdef DEBUG
 356   printf("   brf0t.s\t0x%x\n",OP[0]);
 357 #endif
 358   if (State.F0)
 359     PC += SEXT8 (OP[0]);
 360 }
 361
 362 /* brf0t.l */
 363 void
 364 OP_25800000 ()
 365 {
 366 #ifdef DEBUG
 367   printf("   brf0t.l\t0x%x\n",OP[0]);
 368 #endif
 369   if (State.F0)
 370     PC += OP[0];
 371 }
 372
 373 /* bseti */
 374 void
 375 OP_801 ()
 376 {
 377 #ifdef DEBUG
 378   printf("   bseti\tr%d,%d\n",OP[0],OP[1]);
 379 #endif
 380   State.regs[OP[0]] |= 0x8000 >> OP[1];
 381 }
 382
 383 /* btsti */
 384 void
 385 OP_E01 ()
 386 {
 387 #ifdef DEBUG
 388   printf("   btsti\tr%d,%d\n",OP[0],OP[1]);
 389 #endif
 390   State.F1 = State.F0;
 391   State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
 392 }
 393
 394 /* clrac */
 395 void
 396 OP_5601 ()
 397 {
 398 #ifdef DEBUG
 399   printf("   clrac\ta%d\n",OP[0]);
 400 #endif
 401   State.a[OP[0]] = 0;
 402 }
 403
 404 /* cmp */
 405 void
 406 OP_600 ()
 407 {
 408 #ifdef DEBUG
 409   printf("   cmp\tr%d,r%d\n",OP[0],OP[1]);
 410 #endif
 411   State.F1 = State.F0;
 412   State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
 413 }
 414
 415 /* cmp */
 416 void
 417 OP_1603 ()
 418 {
 419 #ifdef DEBUG
 420   printf("   cmp\ta%d,a%d\n",OP[0],OP[1]);
 421 #endif
 422   State.F1 = State.F0;
 423   State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
 424 }
 425
 426 /* cmpeq */
 427 void
 428 OP_400 ()
 429 {
 430 #ifdef DEBUG
 431   printf("   cmpeq\tr%d,r%d\n",OP[0],OP[1]);
 432 #endif
 433   State.F1 = State.F0;
 434   State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
 435 }
 436
 437 /* cmpeq */
 438 void
 439 OP_1403 ()
 440 {
 441 #ifdef DEBUG
 442   printf("   cmpeq\ta%d,a%d\n",OP[0],OP[1]);
 443 #endif
 444   State.F1 = State.F0;
 445   State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
 446 }
 447
 448 /* cmpeqi.s */
 449 void
 450 OP_401 ()
 451 {
 452 #ifdef DEBUG
 453   printf("   cmpeqi.s\tr%d,0x%x\n",OP[0],OP[1]);
 454 #endif
 455   State.F1 = State.F0;
 456   State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
 457 }
 458
 459 /* cmpeqi.l */
 460 void
 461 OP_2000000 ()
 462 {
 463 #ifdef DEBUG
 464   printf("   cmpeqi.l\tr%d,0x%x\n",OP[0],OP[1]);
 465 #endif
 466   State.F1 = State.F0;
 467   State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
 468 }
 469
 470 /* cmpi.s */
 471 void
 472 OP_601 ()
 473 {
 474 #ifdef DEBUG
 475   printf("   cmpi.s\tr%d,0x%x\n",OP[0],OP[1]);
 476 #endif
 477   State.F1 = State.F0;
 478   State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
 479 }
 480
 481 /* cmpi.l */
 482 void
 483 OP_3000000 ()
 484 {
 485 #ifdef DEBUG
 486   printf("   cmpi.l\tr%d,0x%x\n",OP[0],OP[1]);
 487 #endif
 488   State.F1 = State.F0;
 489   State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
 490 }
 491
 492 /* cmpu */
 493 void
 494 OP_4600 ()
 495 {
 496 #ifdef DEBUG
 497   printf("   cmpu\tr%d,r%d\n",OP[0],OP[1]);
 498 #endif
 499   State.F1 = State.F0;
 500   State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
 501 }
 502
 503 /* cmpui */
 504 void
 505 OP_23000000 ()
 506 {
 507 #ifdef DEBUG
 508   printf("   cmpui\tr%d,0x%x\n",OP[0],OP[1]);
 509 #endif
 510   State.F1 = State.F0;
 511   State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
 512 }
 513
 514 /* cpfg */
 515 void
 516 OP_4E09 ()
 517 {
 518   uint8 *src, *dst;
 519 #ifdef DEBUG
 520   printf("   cpfg\t%x,%x\n",OP[0],OP[1]);
 521 #endif
 522
 523   if (OP[0] == 0)
 524     dst = &State.F0;
 525   else
 526     dst = &State.F1;
 527
 528   if (OP[1] == 0)
 529     src = &State.F0;
 530   else if (OP[1] == 1)
 531     src = &State.F1;
 532   else
 533     src = &State.C;
 534
 535   *dst = *src;
 536 }
 537
 538 /* dbt */
 539 void
 540 OP_5F20 ()
 541 {
 542   printf("***** DBT *****  PC=%x\n",PC);
 543   State.exception = SIGTRAP;
 544 }
 545
 546 /* divs */
 547 void
 548 OP_14002800 ()
 549 {
 550   uint16 foo, tmp, tmpf;
 551 #ifdef DEBUG
 552   printf("   divs\tr%d,r%d\n",OP[0],OP[1]);
 553 #endif
 554   foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
 555   tmp = (int16)foo - (int16)(State.regs[OP[1]]);
 556   tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
 557   State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
 558   State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
 559 }
 560
 561 /* exef0f */
 562 void
 563 OP_4E04 ()
 564 {
 565 #ifdef DEBUG
 566   printf("   exef0f\n");
 567 #endif
 568   State.exe = (State.F0) ? 0 : 1;
 569 }
 570
 571 /* exef0t */
 572 void
 573 OP_4E24 ()
 574 {
 575 #ifdef DEBUG
 576   printf("   exef0t\n");
 577 #endif
 578   State.exe = State.F0;
 579 }
 580
 581 /* exef1f */
 582 void
 583 OP_4E40 ()
 584 {
 585 #ifdef DEBUG
 586   printf("   exef1f\n");
 587 #endif
 588   State.exe = (State.F1) ? 0 : 1;
 589 }
 590
 591 /* exef1t */
 592 void
 593 OP_4E42 ()
 594 {
 595 #ifdef DEBUG
 596   printf("   exef1t\n");
 597 #endif
 598   State.exe = State.F1;
 599 }
 600
 601 /* exefaf */
 602 void
 603 OP_4E00 ()
 604 {
 605 #ifdef DEBUG
 606   printf("   exefaf\n");
 607 #endif
 608   State.exe = (State.F0 | State.F1) ? 0 : 1;
 609 }
 610
 611 /* exefat */
 612 void
 613 OP_4E02 ()
 614 {
 615 #ifdef DEBUG
 616   printf("   exefat\n");
 617 #endif
 618   State.exe = (State.F0) ? 0 : (State.F1);
 619 }
 620
 621 /* exetaf */
 622 void
 623 OP_4E20 ()
 624 {
 625 #ifdef DEBUG
 626   printf("   exetaf\n");
 627 #endif
 628   State.exe = (State.F1) ? 0 : (State.F0);
 629 }
 630
 631 /* exetat */
 632 void
 633 OP_4E22 ()
 634 {
 635 #ifdef DEBUG
 636   printf("   exetat\n");
 637 #endif
 638   State.exe = (State.F0) ? (State.F1) : 0;
 639 }
 640
 641 /* exp */
 642 void
 643 OP_15002A00 ()
 644 {
 645   uint32 tmp, foo;
 646   int i;
 647
 648 #ifdef DEBUG
 649   printf("   exp\tr%d,r%d\n",OP[0],OP[1]);
 650 #endif
 651   if (((int16)State.regs[OP[1]]) >= 0)
 652     tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
 653   else
 654     tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
 655
 656   foo = 0x40000000;
 657   for (i=1;i<17;i++)
 658     {
 659       if (tmp & foo)
 660         {
 661           State.regs[OP[0]] = i-1;
 662           return;
 663         }
 664       foo >>= 1;
 665     }
 666   State.regs[OP[0]] = 16;
 667 }
 668
 669 /* exp */
 670 void
 671 OP_15002A02 ()
 672 {
 673   int64 tmp, foo;
 674   int i;
 675 #ifdef DEBUG
 676   printf("   exp\tr%d,a%d\n",OP[0],OP[1]);
 677 #endif
 678   if (SEXT40(State.a[OP[1]]) >= 0)
 679     tmp = State.a[OP[1]];
 680   else
 681     tmp = ~(State.a[OP[1]]);
 682
 683   foo = 0x4000000000LL;
 684   for (i=1;i<25;i++)
 685     {
 686       if (tmp & foo)
 687         {
 688           State.regs[OP[0]] = i-9;
 689           return;
 690         }
 691       foo >>= 1;
 692     }
 693   State.regs[OP[0]] = 16;
 694 }
 695
 696 /* jl */
 697 void
 698 OP_4D00 ()
 699 {
 700 #ifdef DEBUG
 701   printf("   jl\t%x\n",OP[0]);
 702 #endif
 703   State.regs[13] = PC+1;
 704   PC = State.regs[OP[0]];
 705 }
 706
 707 /* jmp */
 708 void
 709 OP_4C00 ()
 710 {
 711 #ifdef DEBUG
 712   printf("   jmp\tr%d\n",OP[0]);
 713 #endif
 714   PC = State.regs[OP[0]];
 715 }
 716
 717 /* ld */
 718 void
 719 OP_30000000 ()
 720 {
 721 #ifdef DEBUG
 722   printf("   ld\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
 723 #endif
 724   State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
 725 }
 726
 727 /* ld */
 728 void
 729 OP_6401 ()
 730 {
 731 #ifdef DEBUG
 732   printf("   ld\tr%d,@r%d-\n",OP[0],OP[1]);
 733 #endif
 734   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 735   INC_ADDR(State.regs[OP[1]],-2);
 736 }
 737
 738 /* ld */
 739 void
 740 OP_6001 ()
 741 {
 742 #ifdef DEBUG
 743   printf("   ld\tr%d,@r%d+\n",OP[0],OP[1]);
 744 #endif
 745   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 746   INC_ADDR(State.regs[OP[1]],2);
 747 }
 748
 749 /* ld */
 750 void
 751 OP_6000 ()
 752 {
 753 #ifdef DEBUG
 754   printf("   ld\tr%d,@r%d\n",OP[0],OP[1]);
 755 #endif
 756   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 757 }
 758
 759 /* ld2w */
 760 void
 761 OP_31000000 ()
 762 {
 763 #ifdef DEBUG
 764   printf("   ld2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
 765 #endif
 766   State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
 767   State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
 768 }
 769
 770 /* ld2w */
 771 void
 772 OP_6601 ()
 773 {
 774 #ifdef DEBUG
 775   printf("   ld2w\tr%d,@r%d-\n",OP[0],OP[1]);
 776 #endif
 777   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 778   State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
 779   INC_ADDR(State.regs[OP[1]],-4);
 780 }
 781
 782 /* ld2w */
 783 void
 784 OP_6201 ()
 785 {
 786 #ifdef DEBUG
 787   printf("   ld2w\tr%d,@r%d+\n",OP[0],OP[1]);
 788 #endif
 789   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 790   State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
 791   INC_ADDR(State.regs[OP[1]],4);
 792 }
 793
 794 /* ld2w */
 795 void
 796 OP_6200 ()
 797 {
 798 #ifdef DEBUG
 799   printf("   ld2w\tr%d,@r%d\n",OP[0],OP[1]);
 800 #endif
 801   State.regs[OP[0]] = RW (State.regs[OP[1]]);
 802   State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
 803 }
 804
 805 /* ldb */
 806 void
 807 OP_38000000 ()
 808 {
 809 #ifdef DEBUG
 810   printf("   ldb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
 811 #endif
 812   State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
 813   SEXT8 (State.regs[OP[0]]);
 814 }
 815
 816 /* ldb */
 817 void
 818 OP_7000 ()
 819 {
 820 #ifdef DEBUG
 821   printf("   ldb\tr%d,@r%d\n",OP[0],OP[1]);
 822 #endif
 823   State.regs[OP[0]] = RB (State.regs[OP[1]]);
 824   SEXT8 (State.regs[OP[0]]);
 825 }
 826
 827 /* ldi.s */
 828 void
 829 OP_4001 ()
 830 {
 831 #ifdef DEBUG
 832   printf("   ldi.s\tr%d,%x\n",OP[0],SEXT4(OP[1]));
 833 #endif
 834   State.regs[OP[0]] = SEXT4(OP[1]);
 835 }
 836
 837 /* ldi.l */
 838 void
 839 OP_20000000 ()
 840 {
 841 #ifdef DEBUG
 842   printf("   ldi.l\tr%d,%d\t;0x%x\n",OP[0],OP[1],OP[1]);
 843 #endif
 844   State.regs[OP[0]] = OP[1];
 845 }
 846
 847 /* ldub */
 848 void
 849 OP_39000000 ()
 850 {
 851 #ifdef DEBUG
 852   printf("   ldub\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
 853 #endif
 854   State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
 855 }
 856
 857 /* ldub */
 858 void
 859 OP_7200 ()
 860 {
 861 #ifdef DEBUG
 862   printf("   ldub\tr%d,@r%d\n",OP[0],OP[1]);
 863 #endif
 864   State.regs[OP[0]] = RB (State.regs[OP[1]]);
 865 }
 866
 867 /* mac */
 868 void
 869 OP_2A00 ()
 870 {
 871   int64 tmp;
 872 #ifdef DEBUG
 873   printf("   mac\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
 874 #endif
 875   tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
 876
 877   if (State.FX)
 878     tmp = SEXT40( (tmp << 1) & MASK40);
 879
 880   if (State.ST && tmp > MAX32)
 881     tmp = MAX32;
 882
 883   tmp += SEXT40(State.a[OP[0]]);
 884   if (State.ST)
 885     {
 886       if (tmp > MAX32)
 887         State.a[OP[0]] = MAX32;
 888       else if (tmp < MIN32)
 889         State.a[OP[0]] = MIN32;
 890       else
 891         State.a[OP[0]] = tmp & MASK40;
 892     }
 893   else
 894     State.a[OP[0]] = tmp & MASK40;
 895 }
 896
 897 /* macsu */
 898 void
 899 OP_1A00 ()
 900 {
 901   int64 tmp;
 902 #ifdef DEBUG
 903   printf("   macsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
 904 #endif
 905   tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
 906   if (State.FX)
 907     tmp = SEXT40( (tmp << 1) & MASK40);
 908
 909   State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
 910 }
 911
 912 /* macu */
 913 void
 914 OP_3A00 ()
 915 {
 916   int64 tmp;
 917 #ifdef DEBUG
 918   printf("   macu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
 919 #endif
 920   tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
 921   if (State.FX)
 922     tmp = SEXT40( (tmp << 1) & MASK40);
 923   State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
 924 }
 925
 926 /* max */
 927 void
 928 OP_2600 ()
 929 {
 930 #ifdef DEBUG
 931   printf("   max\tr%d,r%d\n",OP[0],OP[1]);
 932 #endif
 933   State.F1 = State.F0;
 934   if (State.regs[OP[1]] > State.regs[OP[0]])
 935     {
 936       State.regs[OP[0]] = State.regs[OP[1]];
 937       State.F0 = 1;
 938     }
 939   else
 940     State.F0 = 0;
 941 }
 942
 943 /* max */
 944 void
 945 OP_3600 ()
 946 {
 947   int64 tmp;
 948 #ifdef DEBUG
 949   printf("   max\ta%d,r%d\n",OP[0],OP[1]);
 950 #endif
 951   State.F1 = State.F0;
 952   tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
 953   if (tmp > SEXT40(State.a[OP[0]]))
 954     {
 955       State.a[OP[0]] = tmp & MASK40;
 956       State.F0 = 1;
 957     }
 958   else
 959     State.F0 = 0;
 960 }
 961
 962 /* max */
 963 void
 964 OP_3602 ()
 965 {
 966 #ifdef DEBUG
 967   printf("   max\ta%d,a%d\n",OP[0],OP[1]);
 968 #endif
 969   State.F1 = State.F0;
 970   if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
 971     {
 972       State.a[OP[0]] = State.a[OP[1]];
 973       State.F0 = 1;
 974     }
 975   else
 976     State.F0 = 0;
 977 }
 978
 979
 980 /* min */
 981 void
 982 OP_2601 ()
 983 {
 984 #ifdef DEBUG
 985   printf("   min\tr%d,r%d\n",OP[0],OP[1]);
 986 #endif
 987   State.F1 = State.F0;
 988   if (State.regs[OP[1]] < State.regs[OP[0]])
 989     {
 990       State.regs[OP[0]] = State.regs[OP[1]];
 991       State.F0 = 1;
 992     }
 993   else
 994     State.F0 = 0;
 995 }
 996
 997 /* min */
 998 void
 999 OP_3601 ()
1000 {
1001   int64 tmp;
1002 #ifdef DEBUG
1003   printf("   min\ta%d,r%d\n",OP[0],OP[1]);
1004 #endif
1005   State.F1 = State.F0;
1006   tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1007   if (tmp < SEXT40(State.a[OP[0]]))
1008     {
1009       State.a[OP[0]] = tmp & MASK40;
1010       State.F0 = 1;
1011     }
1012   else
1013     State.F0 = 0;
1014 }
1015
1016 /* min */
1017 void
1018 OP_3603 ()
1019 {
1020 #ifdef DEBUG
1021   printf("   min\ta%d,a%d\n",OP[0],OP[1]);
1022 #endif
1023   State.F1 = State.F0;
1024   if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1025     {
1026       State.a[OP[0]] = State.a[OP[1]];
1027       State.F0 = 1;
1028     }
1029   else
1030     State.F0 = 0;
1031 }
1032
1033 /* msb */
1034 void
1035 OP_2800 ()
1036 {
1037   int64 tmp;
1038 #ifdef DEBUG
1039   printf("   msb\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1040 #endif
1041   tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1042
1043   if (State.FX)
1044     tmp = SEXT40 ((tmp << 1) & MASK40);
1045
1046   if (State.ST && tmp > MAX32)
1047     tmp = MAX32;
1048
1049   tmp = SEXT40(State.a[OP[0]]) - tmp;
1050   if (State.ST)
1051     {
1052       if (tmp > MAX32)
1053         State.a[OP[0]] = MAX32;
1054       else if (tmp < MIN32)
1055         State.a[OP[0]] = MIN32;
1056       else
1057         State.a[OP[0]] = tmp & MASK40;
1058     }
1059   else
1060     State.a[OP[0]] = tmp & MASK40;
1061 }
1062
1063 /* msbsu */
1064 void
1065 OP_1800 ()
1066 {
1067   int64 tmp;
1068 #ifdef DEBUG
1069   printf("   msbsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1070 #endif
1071   tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1072   if (State.FX)
1073     tmp = SEXT40( (tmp << 1) & MASK40);
1074
1075   State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1076 }
1077
1078 /* msbu */
1079 void
1080 OP_3800 ()
1081 {
1082   int64 tmp;
1083 #ifdef DEBUG
1084   printf("   msbu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1085 #endif
1086   tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1087   if (State.FX)
1088     tmp = SEXT40( (tmp << 1) & MASK40);
1089
1090   State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1091 }
1092
1093 /* mul */
1094 void
1095 OP_2E00 ()
1096 {
1097 #ifdef DEBUG
1098   printf("   mul\tr%d,r%d\n",OP[0],OP[1]);
1099 #endif
1100   State.regs[OP[0]] *= State.regs[OP[1]];
1101 }
1102
1103 /* mulx */
1104 void
1105 OP_2C00 ()
1106 {
1107   int64 tmp;
1108 #ifdef DEBUG
1109   printf("   mulx\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1110 #endif
1111   tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1112
1113   if (State.FX)
1114     tmp = SEXT40 ((tmp << 1) & MASK40);
1115
1116   if (State.ST && tmp > MAX32)
1117     State.a[OP[0]] = MAX32;
1118   else
1119     State.a[OP[0]] = tmp & MASK40;
1120 }
1121
1122 /* mulxsu */
1123 void
1124 OP_1C00 ()
1125 {
1126   int64 tmp;
1127 #ifdef DEBUG
1128   printf("   mulxsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1129 #endif
1130   tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1131
1132   if (State.FX)
1133     tmp <<= 1;
1134
1135   State.a[OP[0]] = tmp & MASK40;
1136 }
1137
1138 /* mulxu */
1139 void
1140 OP_3C00 ()
1141 {
1142   int64 tmp;
1143 #ifdef DEBUG
1144   printf("   mulxu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1145 #endif
1146   tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1147
1148   if (State.FX)
1149     tmp <<= 1;
1150
1151   State.a[OP[0]] = tmp & MASK40;
1152 }
1153
1154 /* mv */
1155 void
1156 OP_4000 ()
1157 {
1158 #ifdef DEBUG
1159   printf("   mv\tr%d,r%d\n",OP[0],OP[1]);
1160 #endif
1161   State.regs[OP[0]] = State.regs[OP[1]];
1162 }
1163
1164 /* mv2w */
1165 void
1166 OP_5000 ()
1167 {
1168 #ifdef DEBUG
1169   printf("   mv2w\tr%d,r%d\n",OP[0],OP[1]);
1170 #endif
1171   State.regs[OP[0]] = State.regs[OP[1]];
1172   State.regs[OP[0]+1] = State.regs[OP[1]+1];
1173 }
1174
1175 /* mv2wfac */
1176 void
1177 OP_3E00 ()
1178 {
1179 #ifdef DEBUG
1180   printf("   mv2wfac\tr%d,a%d\n",OP[0],OP[1]);
1181 #endif
1182   State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1183   State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1184 }
1185
1186 /* mv2wtac */
1187 void
1188 OP_3E01 ()
1189 {
1190 #ifdef DEBUG
1191   printf("   mv2wtac\tr%d,a%d\n",OP[0],OP[1]);
1192 #endif
1193   State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1194 }
1195
1196 /* mvac */
1197 void
1198 OP_3E03 ()
1199 {
1200 #ifdef DEBUG
1201   printf("   mvac\ta%d,a%d\n",OP[0],OP[1]);
1202 #endif
1203   State.a[OP[0]] = State.a[OP[1]];
1204 }
1205
1206 /* mvb */
1207 void
1208 OP_5400 ()
1209 {
1210 #ifdef DEBUG
1211   printf("   mvb\tr%d,r%d\n",OP[0],OP[1]);
1212 #endif
1213   State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1214 }
1215
1216 /* mvf0f */
1217 void
1218 OP_4400 ()
1219 {
1220 #ifdef DEBUG
1221   printf("   mvf0f\tr%d,r%d\n",OP[0],OP[1]);
1222 #endif
1223   if (State.F0 == 0)
1224     State.regs[OP[0]] = State.regs[OP[1]];
1225 }
1226
1227 /* mvf0t */
1228 void
1229 OP_4401 ()
1230 {
1231 #ifdef DEBUG
1232   printf("   mvf0t\tr%d,r%d\n",OP[0],OP[1]);
1233 #endif
1234   if (State.F0)
1235     State.regs[OP[0]] = State.regs[OP[1]];
1236 }
1237
1238 /* mvfacg */
1239 void
1240 OP_1E04 ()
1241 {
1242 #ifdef DEBUG
1243   printf("   mvfacg\tr%d,a%d\n",OP[0],OP[1]);
1244 #endif
1245   State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1246 }
1247
1248 /* mvfachi */
1249 void
1250 OP_1E00 ()
1251 {
1252 #ifdef DEBUG
1253   printf("   mvfachi\tr%d,a%d\n",OP[0],OP[1]);
1254 #endif
1255   State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1256 }
1257
1258 /* mvfaclo */
1259 void
1260 OP_1E02 ()
1261 {
1262 #ifdef DEBUG
1263   printf("   mvfaclo\tr%d,a%d\n",OP[0],OP[1]);
1264 #endif
1265   State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1266 }
1267
1268 /* mvfc */
1269 void
1270 OP_5200 ()
1271 {
1272 #ifdef DEBUG
1273   printf("   mvfc\tr%d,cr%d\n",OP[0],OP[1]);
1274 #endif
1275   if (OP[1] == 0)
1276     {
1277       /* PSW is treated specially */
1278       PSW = 0;
1279       if (State.SM) PSW |= 0x8000;
1280       if (State.EA) PSW |= 0x2000;
1281       if (State.DB) PSW |= 0x1000;
1282       if (State.IE) PSW |= 0x400;
1283       if (State.RP) PSW |= 0x200;
1284       if (State.MD) PSW |= 0x100;
1285       if (State.FX) PSW |= 0x80;
1286       if (State.ST) PSW |= 0x40;
1287       if (State.F0) PSW |= 8;
1288       if (State.F1) PSW |= 4;
1289       if (State.C) PSW |= 1;
1290     }
1291   State.regs[OP[0]] = State.cregs[OP[1]];
1292 }
1293
1294 /* mvtacg */
1295 void
1296 OP_1E41 ()
1297 {
1298 #ifdef DEBUG
1299   printf("   mvtacg\tr%d,a%d\n",OP[0],OP[1]);
1300 #endif
1301   State.a[OP[1]] &= MASK32;
1302   State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1303 }
1304
1305 /* mvtachi */
1306 void
1307 OP_1E01 ()
1308 {
1309   uint16 tmp;
1310 #ifdef DEBUG
1311   printf("   mvtachi\tr%d,a%d\n",OP[0],OP[1]);
1312 #endif
1313   tmp = State.a[OP[1]] & 0xffff;
1314   State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1315 }
1316
1317 /* mvtaclo */
1318 void
1319 OP_1E21 ()
1320 {
1321 #ifdef DEBUG
1322   printf("   mvtaclo\tr%d,a%d\n",OP[0],OP[1]);
1323 #endif
1324   State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1325 }
1326
1327 /* mvtc */
1328 void
1329 OP_5600 ()
1330 {
1331 #ifdef DEBUG
1332   printf("   mvtc\tr%d,cr%d\n",OP[0],OP[1]);
1333 #endif
1334   State.cregs[OP[1]] =  State.regs[OP[0]];
1335   if (OP[1] == 0)
1336     {
1337       /* PSW is treated specially */
1338       State.SM = (PSW & 0x8000) ? 1 : 0;
1339       State.EA = (PSW & 0x2000) ? 1 : 0;
1340       State.DB = (PSW & 0x1000) ? 1 : 0;
1341       State.IE = (PSW & 0x400) ? 1 : 0;
1342       State.RP = (PSW & 0x200) ? 1 : 0;
1343       State.MD = (PSW & 0x100) ? 1 : 0;
1344       State.FX = (PSW & 0x80) ? 1 : 0;
1345       State.ST = (PSW & 0x40) ? 1 : 0;
1346       State.F0 = (PSW & 8) ? 1 : 0;
1347       State.F1 = (PSW & 4) ? 1 : 0;
1348       State.C = PSW & 1;
1349       if (State.ST && !State.FX)
1350         {
1351           fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
1352           State.exception = SIGILL;
1353         }
1354     }
1355 }
1356
1357 /* mvub */
1358 void
1359 OP_5401 ()
1360 {
1361 #ifdef DEBUG
1362   printf("   mvub\tr%d,r%d\n",OP[0],OP[1]);
1363 #endif
1364   State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1365 }
1366
1367 /* neg */
1368 void
1369 OP_4605 ()
1370 {
1371 #ifdef DEBUG
1372   printf("   neg\tr%d\n",OP[0]);
1373 #endif
1374   State.regs[OP[0]] = 0 - State.regs[OP[0]];
1375 }
1376
1377 /* neg */
1378 void
1379 OP_5605 ()
1380 {
1381   int64 tmp;
1382 #ifdef DEBUG
1383   printf("   neg\ta%d\n",OP[0]);
1384 #endif
1385   tmp = -SEXT40(State.a[OP[0]]);
1386   if (State.ST)
1387     {
1388       if ( tmp > MAX32)
1389         State.a[OP[0]] = MAX32;
1390       else if (tmp < MIN32)
1391         State.a[OP[0]] = MIN32;
1392       else
1393         State.a[OP[0]] = tmp & MASK40;
1394     }
1395   else
1396     State.a[OP[0]] = tmp & MASK40;
1397 }
1398
1399
1400 /* nop */
1401 void
1402 OP_5E00 ()
1403 {
1404 }
1405
1406 /* not */
1407 void
1408 OP_4603 ()
1409 {
1410 #ifdef DEBUG
1411   printf("   not\tr%d\n",OP[0]);
1412 #endif
1413   State.regs[OP[0]] = ~(State.regs[OP[0]]);
1414 }
1415
1416 /* or */
1417 void
1418 OP_800 ()
1419 {
1420 #ifdef DEBUG
1421   printf("   or\tr%d,r%d\n",OP[0],OP[1]);
1422 #endif
1423   State.regs[OP[0]] |= State.regs[OP[1]];
1424 }
1425
1426 /* or3 */
1427 void
1428 OP_4000000 ()
1429 {
1430 #ifdef DEBUG
1431   printf("   or3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
1432 #endif
1433   State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1434 }
1435
1436 /* rac */
1437 void
1438 OP_5201 ()
1439 {
1440   int64 tmp;
1441   int shift = SEXT3 (OP[2]);
1442 #ifdef DEBUG
1443   printf("   rac\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1444 #endif
1445   State.F1 = State.F0;
1446   if (shift >=0)
1447     tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1448   else
1449     tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1450   tmp = (tmp + 0x8000) >> 16;
1451
1452   if (tmp > MAX32)
1453     {
1454       State.regs[OP[0]] = 0x7fff;
1455       State.regs[OP[0]+1] = 0xffff;
1456       State.F0 = 1;
1457     }
1458   else if (tmp < MIN32)
1459     {
1460       State.regs[OP[0]] = 0x8000;
1461       State.regs[OP[0]+1] = 0;
1462       State.F0 = 1;
1463     }
1464   else
1465     {
1466       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1467       State.regs[OP[0]+1] = tmp & 0xffff;
1468       State.F0 = 0;
1469     }
1470 }
1471
1472 /* rachi */
1473 void
1474 OP_4201 ()
1475 {
1476   int64 tmp;
1477   int shift = SEXT3 (OP[2]);
1478 #ifdef DEBUG
1479   printf("   rachi\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1480 #endif
1481   State.F1 = State.F0;
1482   if (shift >=0)
1483     tmp = SEXT40 (State.a[1]) << shift;
1484   else
1485     tmp = SEXT40 (State.a[1]) >> -shift;
1486   tmp += 0x8000;
1487   if (tmp > MAX32)
1488     {
1489       State.regs[OP[0]] = 0x7fff;
1490       State.F0 = 1;
1491     }
1492   else if (tmp < 0xfff80000000LL)
1493     {
1494       State.regs[OP[0]] = 0x8000;
1495       State.F0 = 1;
1496     }
1497   else
1498     {
1499       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1500       State.F0 = 0;
1501     }
1502 }
1503
1504 /* rep */
1505 void
1506 OP_27000000 ()
1507 {
1508 #ifdef DEBUG
1509   printf("   rep\tr%d,0x%x\n",OP[0],OP[1]);
1510 #endif
1511   RPT_S = PC + 1;
1512   RPT_E = PC + OP[1];
1513   RPT_C = State.regs[OP[0]];
1514   State.RP = 1;
1515   if (RPT_C == 0)
1516     {
1517       fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
1518       State.exception = SIGILL;
1519     }
1520   if (OP[1] < 4)
1521     {
1522       fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
1523       State.exception = SIGILL;
1524     }
1525 }
1526
1527 /* repi */
1528 void
1529 OP_2F000000 ()
1530 {
1531 #ifdef DEBUG
1532   printf("   repi\t%d,0x%x\n",OP[0],OP[1]);
1533 #endif
1534   RPT_S = PC + 1;
1535   RPT_E = PC + OP[1];
1536   RPT_C = OP[0];
1537   State.RP = 1;
1538   if (RPT_C == 0)
1539     {
1540       fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
1541       State.exception = SIGILL;
1542     }
1543   if (OP[1] < 4)
1544     {
1545       fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
1546       State.exception = SIGILL;
1547     }
1548 }
1549
1550 /* rtd */
1551 void
1552 OP_5F60 ()
1553 {
1554   printf("   rtd - NOT IMPLEMENTED\n");
1555 }
1556
1557 /* rte */
1558 void
1559 OP_5F40 ()
1560 {
1561 #ifdef DEBUG
1562   printf("   rte\n");
1563 #endif
1564   PC = BPC;
1565   PSW = BPSW;
1566 }
1567
1568 /* sadd */
1569 void
1570 OP_1223 ()
1571 {
1572   int64 tmp;
1573 #ifdef DEBUG
1574   printf("   sadd\ta%d,a%d\n",OP[0],OP[1]);
1575 #endif
1576   tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1577   if (State.ST)
1578     {
1579       if (tmp > MAX32)
1580         State.a[OP[0]] = MAX32;
1581       else if (tmp < MIN32)
1582         State.a[OP[0]] = MIN32;
1583       else
1584         State.a[OP[0]] = tmp & MASK40;
1585     }
1586   else
1587     State.a[OP[0]] = tmp & MASK40;
1588 }
1589
1590 /* setf0f */
1591 void
1592 OP_4611 ()
1593 {
1594 #ifdef DEBUG
1595   printf("   setf0f\tr%d\n",OP[0]);
1596 #endif
1597   State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1598 }
1599
1600 /* setf0t */
1601 void
1602 OP_4613 ()
1603 {
1604 #ifdef DEBUG
1605   printf("   setf0t\tr%d\n",OP[0]);
1606 #endif
1607   State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1608 }
1609
1610 /* sleep */
1611 void
1612 OP_5FC0 ()
1613 {
1614 #ifdef DEBUG
1615   printf("   sleep\n");
1616 #endif
1617   State.IE = 1;
1618 }
1619
1620 /* sll */
1621 void
1622 OP_2200 ()
1623 {
1624 #ifdef DEBUG
1625   printf("   sll\tr%d,r%d\n",OP[0],OP[1]);
1626 #endif
1627   State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1628 }
1629
1630 /* sll */
1631 void
1632 OP_3200 ()
1633 {
1634   int64 tmp;
1635 #ifdef DEBUG
1636   printf("   sll\ta%d,r%d\n",OP[0],OP[1]);
1637 #endif
1638   if (State.regs[OP[1]] & 31 <= 16)
1639     tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1640
1641   if (State.ST)
1642     {
1643       if (tmp > MAX32)
1644         State.a[OP[0]] = MAX32;
1645       else if (tmp < 0xffffff80000000LL)
1646         State.a[OP[0]] = MIN32;
1647       else
1648         State.a[OP[0]] = tmp & MASK40;
1649     }
1650   else
1651     State.a[OP[0]] = tmp & MASK40;
1652 }
1653
1654 /* slli */
1655 void
1656 OP_2201 ()
1657 {
1658 #ifdef DEBUG
1659   printf("   slli\tr%d,%d\n",OP[0],OP[1]);
1660 #endif
1661   State.regs[OP[0]] <<= OP[1];
1662 }
1663
1664 /* slli */
1665 void
1666 OP_3201 ()
1667 {
1668   int64 tmp;
1669
1670   if (OP[1] == 0)
1671     OP[1] = 16;
1672 #ifdef DEBUG
1673   printf("   slli\ta%d,%d\n",OP[0],OP[1]);
1674 #endif
1675
1676   tmp = SEXT40(State.a[OP[0]]) << OP[1];
1677
1678   if (State.ST)
1679     {
1680       if (tmp > MAX32)
1681         State.a[OP[0]] = MAX32;
1682       else if (tmp < 0xffffff80000000LL)
1683         State.a[OP[0]] = MIN32;
1684       else
1685         State.a[OP[0]] = tmp & MASK40;
1686     }
1687   else
1688     State.a[OP[0]] = tmp & MASK40;
1689 }
1690
1691 /* slx */
1692 void
1693 OP_460B ()
1694 {
1695   uint16 tmp;
1696 #ifdef DEBUG
1697   printf("   slx\tr%d\n",OP[0]);
1698 #endif
1699   State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1700 }
1701
1702 /* sra */
1703 void
1704 OP_2400 ()
1705 {
1706 #ifdef DEBUG
1707   printf("   sra\tr%d,r%d\n",OP[0],OP[1]);
1708 #endif
1709   State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1710 }
1711
1712 /* sra */
1713 void
1714 OP_3400 ()
1715 {
1716 #ifdef DEBUG
1717   printf("   sra\ta%d,r%d\n",OP[0],OP[1]);
1718 #endif
1719   if (State.regs[OP[1]] & 31 <= 16)
1720     State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
1721 }
1722
1723 /* srai */
1724 void
1725 OP_2401 ()
1726 {
1727 #ifdef DEBUG
1728   printf("   srai\tr%d,%d\n",OP[0],OP[1]);
1729 #endif
1730   State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1731 }
1732
1733 /* srai */
1734 void
1735 OP_3401 ()
1736 {
1737   if (OP[1] == 0)
1738     OP[1] = 16;
1739 #ifdef DEBUG
1740   printf("   srai\ta%d,%d\n",OP[0],OP[1]);
1741 #endif
1742     State.a[OP[0]] >>= OP[1];
1743 }
1744
1745 /* srl */
1746 void
1747 OP_2000 ()
1748 {
1749 #ifdef DEBUG
1750   printf("   srl\tr%d,r%d\n",OP[0],OP[1]);
1751 #endif
1752   State.regs[OP[0]] >>=  (State.regs[OP[1]] & 0xf);
1753 }
1754
1755 /* srl */
1756 void
1757 OP_3000 ()
1758 {
1759 #ifdef DEBUG
1760   printf("   srl\ta%d,r%d\n",OP[0],OP[1]);
1761 #endif
1762   if (State.regs[OP[1]] & 31 <= 16)
1763     State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
1764 }
1765
1766 /* srli */
1767 void
1768 OP_2001 ()
1769 {
1770 #ifdef DEBUG
1771 printf("   srli\tr%d,%d\n",OP[0],OP[1]);
1772 #endif
1773   State.regs[OP[0]] >>= OP[1];
1774 }
1775
1776 /* srli */
1777 void
1778 OP_3001 ()
1779 {
1780   if (OP[1] == 0)
1781     OP[1] = 16;
1782 #ifdef DEBUG
1783   printf("   srli\ta%d,%d\n",OP[0],OP[1]);
1784 #endif
1785     State.a[OP[0]] >>= OP[1];
1786 }
1787
1788 /* srx */
1789 void
1790 OP_4609 ()
1791 {
1792   uint16 tmp;
1793 #ifdef DEBUG
1794   printf("   srx\tr%d\n",OP[0]);
1795 #endif
1796   tmp = State.F0 << 15;
1797   State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
1798 }
1799
1800 /* st */
1801 void
1802 OP_34000000 ()
1803 {
1804 #ifdef DEBUG
1805   printf("   st\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1806 #endif
1807   SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
1808 }
1809
1810 /* st */
1811 void
1812 OP_6800 ()
1813 {
1814 #ifdef DEBUG
1815   printf("   st\tr%d,@r%d\n",OP[0],OP[1]);
1816 #endif
1817   SW (State.regs[OP[1]], State.regs[OP[0]]);
1818 }
1819
1820 /* st */
1821 void
1822 OP_6C1F ()
1823 {
1824 #ifdef DEBUG
1825   printf("   st\tr%d,@-r%d\n",OP[0],OP[1]);
1826 #endif
1827   if ( OP[1] != 15 )
1828     {
1829       fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1830       State.exception = SIGILL;
1831       return;
1832     }
1833   State.regs[OP[1]] -= 2;
1834   SW (State.regs[OP[1]], State.regs[OP[0]]);
1835 }
1836
1837 /* st */
1838 void
1839 OP_6801 ()
1840 {
1841 #ifdef DEBUG
1842   printf("   st\tr%d,@r%d+\n",OP[0],OP[1]);
1843 #endif
1844   SW (State.regs[OP[1]], State.regs[OP[0]]);
1845   INC_ADDR (State.regs[OP[1]],2);
1846 }
1847
1848 /* st */
1849 void
1850 OP_6C01 ()
1851 {
1852 #ifdef DEBUG
1853   printf("   st\tr%d,@r%d-\n",OP[0],OP[1]);
1854 #endif
1855   SW (State.regs[OP[1]], State.regs[OP[0]]);
1856   INC_ADDR (State.regs[OP[1]],-2);
1857 }
1858
1859 /* st2w */
1860 void
1861 OP_35000000 ()
1862 {
1863 #ifdef DEBUG
1864   printf("   st2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1865 #endif
1866   SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1867   SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
1868 }
1869
1870 /* st2w */
1871 void
1872 OP_6A00 ()
1873 {
1874 #ifdef DEBUG
1875   printf("   st2w\tr%d,@r%d\n",OP[0],OP[1]);
1876 #endif
1877   SW (State.regs[OP[1]],   State.regs[OP[0]]);
1878   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1879 }
1880
1881 /* st2w */
1882 void
1883 OP_6E1F ()
1884 {
1885 #ifdef DEBUG
1886   printf("   st2w\tr%d,@-r%d\n",OP[0],OP[1]);
1887 #endif
1888   if ( OP[1] != 15 )
1889     {
1890       fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1891       State.exception = SIGILL;
1892       return;
1893     }
1894   State.regs[OP[1]] -= 4;
1895   SW (State.regs[OP[1]],   State.regs[OP[0]]);
1896   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1897 }
1898
1899 /* st2w */
1900 void
1901 OP_6A01 ()
1902 {
1903 #ifdef DEBUG
1904   printf("   st2w\tr%d,r%d+\n",OP[0],OP[1]);
1905 #endif
1906   SW (State.regs[OP[1]],   State.regs[OP[0]]);
1907   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1908   INC_ADDR (State.regs[OP[1]],4);
1909 }
1910
1911 /* st2w */
1912 void
1913 OP_6E01 ()
1914 {
1915 #ifdef DEBUG
1916   printf("   st2w\tr%d,r%d-\n",OP[0],OP[1]);
1917 #endif
1918   SW (State.regs[OP[1]],   State.regs[OP[0]]);
1919   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1920   INC_ADDR (State.regs[OP[1]],-4);
1921 }
1922
1923 /* stb */
1924 void
1925 OP_3C000000 ()
1926 {
1927 #ifdef DEBUG
1928   printf("   stb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1929 #endif
1930   SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1931 }
1932
1933 /* stb */
1934 void
1935 OP_7800 ()
1936 {
1937 #ifdef DEBUG
1938   printf("   stb\tr%d,@r%d\n",OP[0],OP[1]);
1939 #endif
1940   SB (State.regs[OP[1]], State.regs[OP[0]]);
1941 }
1942
1943 /* stop */
1944 void
1945 OP_5FE0 ()
1946 {
1947 #ifdef DEBUG
1948   printf("   stop\n");
1949 #endif
1950   State.exception = SIGQUIT;
1951 }
1952
1953 /* sub */
1954 void
1955 OP_0 ()
1956 {
1957   int32 tmp;
1958 #ifdef DEBUG
1959   printf("   sub\tr%d,r%d\n",OP[0],OP[1]);
1960 #endif
1961   tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
1962   State.C = (tmp & 0xffff0000) ? 1 : 0;
1963   State.regs[OP[0]] = tmp & 0xffff;
1964 }
1965
1966 /* sub */
1967 void
1968 OP_1001 ()
1969 {
1970   int64 tmp;
1971 #ifdef DEBUG
1972   printf("   sub\ta%d,r%d\n",OP[0],OP[1]);
1973 #endif
1974   tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
1975   if (State.ST)
1976     {
1977       if ( tmp > MAX32)
1978         State.a[OP[0]] = MAX32;
1979       else if ( tmp < MIN32)
1980         State.a[OP[0]] = MIN32;
1981       else
1982         State.a[OP[0]] = tmp & MASK40;
1983     }
1984   else
1985     State.a[OP[0]] = tmp & MASK40;
1986 }
1987
1988 /* sub */
1989
1990 void
1991 OP_1003 ()
1992 {
1993   int64 tmp;
1994 #ifdef DEBUG
1995   printf("   sub\ta%d,a%d\n",OP[0],OP[1]);
1996 #endif
1997   tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
1998   if (State.ST)
1999     {
2000       if (tmp > MAX32)
2001         State.a[OP[0]] = MAX32;
2002       else if ( tmp < MIN32)
2003         State.a[OP[0]] = MIN32;
2004       else
2005         State.a[OP[0]] = tmp & MASK40;
2006     }
2007   else
2008     State.a[OP[0]] = tmp & MASK40;
2009 }
2010
2011 /* sub2w */
2012 void
2013 OP_1000 ()
2014 {
2015   int64 tmp;
2016   int32 a,b;
2017 #ifdef DEBUG
2018   printf("   sub2w\tr%d,r%d\n",OP[0],OP[1]);
2019 #endif
2020
2021   a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2022   b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2023   tmp = a-b;
2024   State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2025   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2026   State.regs[OP[0]+1] = tmp & 0xffff;
2027 }
2028
2029 /* subac3 */
2030 void
2031 OP_17000000 ()
2032 {
2033   int64 tmp;
2034 #ifdef DEBUG
2035   printf("   subac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2036 #endif
2037   tmp =  SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2038   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2039   State.regs[OP[0]+1] = tmp & 0xffff;
2040 }
2041
2042 /* subac3 */
2043 void
2044 OP_17000002 ()
2045 {
2046   int64 tmp;
2047 #ifdef DEBUG
2048   printf("   subac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2049 #endif
2050   tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2051   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2052   State.regs[OP[0]+1] = tmp & 0xffff;
2053 }
2054
2055 /* subac3s */
2056 void
2057 OP_17001000 ()
2058 {
2059   int64 tmp;
2060 #ifdef DEBUG
2061   printf("   subac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2062 #endif
2063   State.F1 = State.F0;
2064   tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2065   if ( tmp > MAX32)
2066     {
2067       State.regs[OP[0]] = 0x7fff;
2068       State.regs[OP[0]+1] = 0xffff;
2069       State.F0 = 1;
2070     }
2071   else if (tmp < MIN32)
2072     {
2073       State.regs[OP[0]] = 0x8000;
2074       State.regs[OP[0]+1] = 0;
2075       State.F0 = 1;
2076     }
2077   else
2078     {
2079       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2080       State.regs[OP[0]+1] = tmp & 0xffff;
2081       State.F0 = 0;
2082     }
2083 }
2084
2085 /* subac3s */
2086 void
2087 OP_17001002 ()
2088 {
2089   int64 tmp;
2090 #ifdef DEBUG
2091   printf("   subac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2092 #endif
2093   State.F1 = State.F0;
2094   tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2095   if ( tmp > MAX32)
2096     {
2097       State.regs[OP[0]] = 0x7fff;
2098       State.regs[OP[0]+1] = 0xffff;
2099       State.F0 = 1;
2100     }
2101   else if (tmp < MIN32)
2102     {
2103       State.regs[OP[0]] = 0x8000;
2104       State.regs[OP[0]+1] = 0;
2105       State.F0 = 1;
2106     }
2107   else
2108     {
2109       State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2110       State.regs[OP[0]+1] = tmp & 0xffff;
2111       State.F0 = 0;
2112     }
2113 }
2114
2115 /* subi */
2116 void
2117 OP_1 ()
2118 {
2119   int32 tmp;
2120   if (OP[1] == 0)
2121     OP[1] = 16;
2122 #ifdef DEBUG
2123   printf("   subi\tr%d,%d\n",OP[0],OP[1]);
2124 #endif
2125   tmp = (int16)State.regs[OP[0]] - OP[1];
2126   State.C = (tmp & 0xffff0000) ? 1 : 0;
2127   State.regs[OP[0]] = tmp & 0xffff;
2128 }
2129
2130 /* trap */
2131 void
2132 OP_5F00 ()
2133 {
2134 #ifdef DEBUG
2135   printf("   trap\t%d\n",OP[0]);
2136 #endif
2137
2138   /* for now, trap  is used for simulating IO */
2139
2140   if (OP[0] == 0)
2141     {
2142       char *fstr = State.regs[2] + State.imem;
2143       printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
2144     }
2145   else if (OP[0] == 1 )
2146     {
2147       char *fstr = State.regs[2] + State.imem;
2148       puts (fstr);
2149     }
2150 }
2151
2152 /* tst0i */
2153 void
2154 OP_7000000 ()
2155 {
2156 #ifdef DEBUG
2157   printf("   tst0i\tr%d,0x%x\n",OP[0],OP[1]);
2158 #endif
2159   State.F1 = State.F0;
2160   State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2161 }
2162
2163 /* tst1i */
2164 void
2165 OP_F000000 ()
2166 {
2167 #ifdef DEBUG
2168   printf("   tst1i\tr%d,0x%x\n",OP[0],OP[1]);
2169 #endif
2170   State.F1 = State.F0;
2171   State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2172 }
2173
2174 /* wait */
2175 void
2176 OP_5F80 ()
2177 {
2178 #ifdef DEBUG
2179   printf("   wait\n");
2180 #endif
2181   State.IE = 1;
2182 }
2183
2184 /* xor */
2185 void
2186 OP_A00 ()
2187 {
2188 #ifdef DEBUG
2189   printf("   xor\tr%d,r%d\n",OP[0],OP[1]);
2190 #endif
2191   State.regs[OP[0]] ^= State.regs[OP[1]];
2192 }
2193
2194 /* xor3 */
2195 void
2196 OP_5000000 ()
2197 {
2198 #ifdef DEBUG
2199   printf("   xor3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
2200 #endif
2201   State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2202 }
2203