projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Fix tracing for st2w
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11
12 enum op_types {
13 OP_VOID,
14 OP_REG,
15 OP_REG_OUTPUT,
16 OP_DREG,
17 OP_DREG_OUTPUT,
18 OP_ACCUM,
19 OP_ACCUM_OUTPUT,
20 OP_ACCUM_REVERSE,
21 OP_CR,
22 OP_CR_OUTPUT,
23 OP_CR_REVERSE,
24 OP_FLAG,
25 OP_FLAG_OUTPUT,
26 OP_CONSTANT16,
27 OP_CONSTANT8,
28 OP_CONSTANT3,
29 OP_CONSTANT4,
30 OP_MEMREF,
31 OP_MEMREF2,
32 OP_POSTDEC,
33 OP_POSTINC,
34 OP_PREDEC,
35 OP_R2,
36 OP_R3
37 };
38
39 #ifdef DEBUG
40 static void trace_input_func PARAMS ((char *name,
41 enum op_types in1,
42 enum op_types in2,
43 enum op_types in3));
44
45 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
46
47 static void trace_output_func PARAMS ((enum op_types result));
48
49 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
50
51 static int init_text_p = 0;
52 static asection *text;
53 static bfd_vma text_start;
54 static bfd_vma text_end;
55 extern bfd *exec_bfd;
56
57 #ifndef SIZE_INSTRUCTION
58 #define SIZE_INSTRUCTION 8
59 #endif
60
61 #ifndef SIZE_OPERANDS
62 #define SIZE_OPERANDS 18
63 #endif
64
65 #ifndef SIZE_VALUES
66 #define SIZE_VALUES 13
67 #endif
68
69 #ifndef SIZE_LOCATION
70 #define SIZE_LOCATION 20
71 #endif
72
73 #ifndef SIZE_PC
74 #define SIZE_PC 6
75 #endif
76
77 #ifndef SIZE_LINE_NUMBER
78 #define SIZE_LINE_NUMBER 4
79 #endif
80
81 static void
82 trace_input_func (name, in1, in2, in3)
83 char *name;
84 enum op_types in1;
85 enum op_types in2;
86 enum op_types in3;
87 {
88 char *comma;
89 enum op_types in[3];
90 int i;
91 char buf[1024];
92 char *p;
93 long tmp;
94 char *type;
95 asection *s;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
100
101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LONG: type = " B"; break;
113 }
114
115 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
116 (*d10v_callback->printf_filtered) (d10v_callback,
117 "0x%.*x %s: %-*s ",
118 SIZE_PC, (unsigned)PC,
119 type,
120 SIZE_INSTRUCTION, name);
121
122 else
123 {
124 if (!init_text_p)
125 {
126 init_text_p = 1;
127 for (s = exec_bfd->sections; s; s = s->next)
128 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
129 {
130 text = s;
131 text_start = bfd_get_section_vma (exec_bfd, s);
132 text_end = text_start + bfd_section_size (exec_bfd, s);
133 break;
134 }
135 }
136
137 buf[0] = '\0';
138 byte_pc = (bfd_vma)PC << 2;
139 if (text && byte_pc >= text_start && byte_pc < text_end)
140 {
141 filename = (const char *)0;
142 functionname = (const char *)0;
143 linenumber = 0;
144 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
145 &filename, &functionname, &linenumber))
146 {
147 p = buf;
148 if (linenumber)
149 {
150 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
151 p += strlen (p);
152 }
153 else
154 {
155 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
156 p += SIZE_LINE_NUMBER+2;
157 }
158
159 if (functionname)
160 {
161 sprintf (p, "%s ", functionname);
162 p += strlen (p);
163 }
164 else if (filename)
165 {
166 char *q = (char *) strrchr (filename, '/');
167 sprintf (p, "%s ", (q) ? q+1 : filename);
168 p += strlen (p);
169 }
170
171 if (*p == ' ')
172 *p = '\0';
173 }
174 }
175
176 (*d10v_callback->printf_filtered) (d10v_callback,
177 "0x%.*x %s: %-*.*s %-*s ",
178 SIZE_PC, (unsigned)PC,
179 type,
180 SIZE_LOCATION, SIZE_LOCATION, buf,
181 SIZE_INSTRUCTION, name);
182 }
183
184 in[0] = in1;
185 in[1] = in2;
186 in[2] = in3;
187 comma = "";
188 p = buf;
189 for (i = 0; i < 3; i++)
190 {
191 switch (in[i])
192 {
193 case OP_VOID:
194 case OP_R2:
195 case OP_R3:
196 break;
197
198 case OP_REG:
199 case OP_REG_OUTPUT:
200 case OP_DREG:
201 case OP_DREG_OUTPUT:
202 sprintf (p, "%sr%d", comma, OP[i]);
203 p += strlen (p);
204 comma = ",";
205 break;
206
207 case OP_CR:
208 case OP_CR_OUTPUT:
209 case OP_CR_REVERSE:
210 sprintf (p, "%scr%d", comma, OP[i]);
211 p += strlen (p);
212 comma = ",";
213 break;
214
215 case OP_ACCUM:
216 case OP_ACCUM_OUTPUT:
217 case OP_ACCUM_REVERSE:
218 sprintf (p, "%sa%d", comma, OP[i]);
219 p += strlen (p);
220 comma = ",";
221 break;
222
223 case OP_CONSTANT16:
224 sprintf (p, "%s%d", comma, OP[i]);
225 p += strlen (p);
226 comma = ",";
227 break;
228
229 case OP_CONSTANT8:
230 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
231 p += strlen (p);
232 comma = ",";
233 break;
234
235 case OP_CONSTANT4:
236 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
237 p += strlen (p);
238 comma = ",";
239 break;
240
241 case OP_CONSTANT3:
242 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
243 p += strlen (p);
244 comma = ",";
245 break;
246
247 case OP_MEMREF:
248 sprintf (p, "%s@r%d", comma, OP[i]);
249 p += strlen (p);
250 comma = ",";
251 break;
252
253 case OP_MEMREF2:
254 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
255 p += strlen (p);
256 comma = ",";
257 break;
258
259 case OP_POSTINC:
260 sprintf (p, "%s@r%d+", comma, OP[i]);
261 p += strlen (p);
262 comma = ",";
263 break;
264
265 case OP_POSTDEC:
266 sprintf (p, "%s@r%d-", comma, OP[i]);
267 p += strlen (p);
268 comma = ",";
269 break;
270
271 case OP_PREDEC:
272 sprintf (p, "%s@-r%d", comma, OP[i]);
273 p += strlen (p);
274 comma = ",";
275 break;
276
277 case OP_FLAG:
278 case OP_FLAG_OUTPUT:
279 if (OP[i] == 0)
280 sprintf (p, "%sf0", comma);
281
282 else if (OP[i] == 1)
283 sprintf (p, "%sf1", comma);
284
285 else
286 sprintf (p, "%sc", comma);
287
288 p += strlen (p);
289 comma = ",";
290 break;
291 }
292 }
293
294 if ((d10v_debug & DEBUG_VALUES) == 0)
295 {
296 *p++ = '\n';
297 *p = '\0';
298 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
299 }
300 else
301 {
302 *p = '\0';
303 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
304
305 p = buf;
306 for (i = 0; i < 3; i++)
307 {
308 buf[0] = '\0';
309 switch (in[i])
310 {
311 case OP_VOID:
312 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
313 break;
314
315 case OP_REG_OUTPUT:
316 case OP_DREG_OUTPUT:
317 case OP_CR_OUTPUT:
318 case OP_ACCUM_OUTPUT:
319 case OP_FLAG_OUTPUT:
320 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
321 break;
322
323 case OP_REG:
324 case OP_MEMREF:
325 case OP_POSTDEC:
326 case OP_POSTINC:
327 case OP_PREDEC:
328 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
329 (uint16)State.regs[OP[i]]);
330 break;
331
332 case OP_DREG:
333 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
334 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
335 break;
336
337 case OP_CR:
338 case OP_CR_REVERSE:
339 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
340 (uint16)State.cregs[OP[i]]);
341 break;
342
343 case OP_ACCUM:
344 case OP_ACCUM_REVERSE:
345 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
346 ((int)(State.a[OP[i]] >> 32) & 0xff),
347 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
348 break;
349
350 case OP_CONSTANT16:
351 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
352 (uint16)OP[i]);
353 break;
354
355 case OP_CONSTANT4:
356 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
357 (uint16)SEXT4(OP[i]));
358 break;
359
360 case OP_CONSTANT8:
361 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
362 (uint16)SEXT8(OP[i]));
363 break;
364
365 case OP_CONSTANT3:
366 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
367 (uint16)SEXT3(OP[i]));
368 break;
369
370 case OP_FLAG:
371 if (OP[i] == 0)
372 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
373 State.F0 != 0);
374
375 else if (OP[i] == 1)
376 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
377 State.F1 != 0);
378
379 else
380 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
381 State.C != 0);
382
383 break;
384
385 case OP_MEMREF2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)OP[i]);
388 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
389 (uint16)State.regs[OP[++i]]);
390 break;
391
392 case OP_R2:
393 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
394 (uint16)State.regs[2]);
395 break;
396
397 case OP_R3:
398 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
399 (uint16)State.regs[3]);
400 break;
401 }
402 }
403 }
404 }
405
406 static void
407 trace_output_func (result)
408 enum op_types result;
409 {
410 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
411 {
412 long tmp;
413
414 switch (result)
415 {
416 default:
417 putchar ('\n');
418 break;
419
420 case OP_REG:
421 case OP_REG_OUTPUT:
422 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
423 (uint16)State.regs[OP[0]],
424 State.F0 != 0, State.F1 != 0, State.C != 0);
425 break;
426
427 case OP_DREG:
428 case OP_DREG_OUTPUT:
429 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
431 State.F0 != 0, State.F1 != 0, State.C != 0);
432 break;
433
434 case OP_CR:
435 case OP_CR_OUTPUT:
436 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
437 (uint16)State.cregs[OP[0]],
438 State.F0 != 0, State.F1 != 0, State.C != 0);
439 break;
440
441 case OP_CR_REVERSE:
442 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
443 (uint16)State.cregs[OP[1]],
444 State.F0 != 0, State.F1 != 0, State.C != 0);
445 break;
446
447 case OP_ACCUM:
448 case OP_ACCUM_OUTPUT:
449 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
450 ((int)(State.a[OP[0]] >> 32) & 0xff),
451 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
452 State.F0 != 0, State.F1 != 0, State.C != 0);
453 break;
454
455 case OP_ACCUM_REVERSE:
456 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
457 ((int)(State.a[OP[1]] >> 32) & 0xff),
458 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
459 State.F0 != 0, State.F1 != 0, State.C != 0);
460 break;
461
462 case OP_FLAG:
463 case OP_FLAG_OUTPUT:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
465 State.F0 != 0, State.F1 != 0, State.C != 0);
466 break;
467 }
468 }
469 }
470
471 #else
472 #define trace_input(NAME, IN1, IN2, IN3)
473 #define trace_output(RESULT)
474 #endif
475
476 /* abs */
477 void
478 OP_4607 ()
479 {
480 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
481 State.F1 = State.F0;
482 if ((int16)(State.regs[OP[0]]) < 0)
483 {
484 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
485 State.F0 = 1;
486 }
487 else
488 State.F0 = 0;
489 trace_output (OP_REG);
490 }
491
492 /* abs */
493 void
494 OP_5607 ()
495 {
496 int64 tmp;
497
498 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
499 State.F1 = State.F0;
500 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
501
502 if (State.a[OP[0]] < 0 )
503 {
504 tmp = -State.a[OP[0]];
505 if (State.ST)
506 {
507 if (tmp > MAX32)
508 State.a[OP[0]] = MAX32;
509 else if (tmp < MIN32)
510 State.a[OP[0]] = MIN32;
511 else
512 State.a[OP[0]] = tmp & MASK40;
513 }
514 else
515 State.a[OP[0]] = tmp & MASK40;
516 State.F0 = 1;
517 }
518 else
519 State.F0 = 0;
520 trace_output (OP_ACCUM);
521 }
522
523 /* add */
524 void
525 OP_200 ()
526 {
527 uint16 tmp = State.regs[OP[0]];
528 trace_input ("add", OP_REG, OP_REG, OP_VOID);
529 State.regs[OP[0]] += State.regs[OP[1]];
530 if ( tmp > State.regs[OP[0]])
531 State.C = 1;
532 else
533 State.C = 0;
534 trace_output (OP_REG);
535 }
536
537 /* add */
538 void
539 OP_1201 ()
540 {
541 int64 tmp;
542 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
543
544 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
545 if (State.ST)
546 {
547 if ( tmp > MAX32)
548 State.a[OP[0]] = MAX32;
549 else if ( tmp < MIN32)
550 State.a[OP[0]] = MIN32;
551 else
552 State.a[OP[0]] = tmp & MASK40;
553 }
554 else
555 State.a[OP[0]] = tmp & MASK40;
556 trace_output (OP_ACCUM);
557 }
558
559 /* add */
560 void
561 OP_1203 ()
562 {
563 int64 tmp;
564 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
565
566 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
567 if (State.ST)
568 {
569 if (tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
574 State.a[OP[0]] = tmp & MASK40;
575 }
576 else
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
579 }
580
581 /* add2w */
582 void
583 OP_1200 ()
584 {
585 uint32 tmp;
586 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
587 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
588
589 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
590 tmp = tmp1 + tmp2;
591 if ( (tmp < tmp1) || (tmp < tmp2) )
592 State.C = 1;
593 else
594 State.C = 0;
595 State.regs[OP[0]] = tmp >> 16;
596 State.regs[OP[0]+1] = tmp & 0xFFFF;
597 trace_output (OP_DREG);
598 }
599
600 /* add3 */
601 void
602 OP_1000000 ()
603 {
604 uint16 tmp = State.regs[OP[0]];
605 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
606
607 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
608 if ( tmp > State.regs[OP[0]])
609 State.C = 1;
610 else
611 State.C = 0;
612 trace_output (OP_REG);
613 }
614
615 /* addac3 */
616 void
617 OP_17000200 ()
618 {
619 int64 tmp;
620 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
621
622 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
623 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
624 State.regs[OP[0]+1] = tmp & 0xffff;
625 trace_output (OP_DREG);
626 }
627
628 /* addac3 */
629 void
630 OP_17000202 ()
631 {
632 int64 tmp;
633 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
634
635 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
636 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
637 State.regs[OP[0]+1] = tmp & 0xffff;
638 trace_output (OP_DREG);
639 }
640
641 /* addac3s */
642 void
643 OP_17001200 ()
644 {
645 int64 tmp;
646 State.F1 = State.F0;
647
648 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
649 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
650 if ( tmp > MAX32)
651 {
652 State.regs[OP[0]] = 0x7fff;
653 State.regs[OP[0]+1] = 0xffff;
654 State.F0 = 1;
655 }
656 else if (tmp < MIN32)
657 {
658 State.regs[OP[0]] = 0x8000;
659 State.regs[OP[0]+1] = 0;
660 State.F0 = 1;
661 }
662 else
663 {
664 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
665 State.regs[OP[0]+1] = tmp & 0xffff;
666 State.F0 = 0;
667 }
668 trace_output (OP_DREG);
669 }
670
671 /* addac3s */
672 void
673 OP_17001202 ()
674 {
675 int64 tmp;
676 State.F1 = State.F0;
677
678 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
679 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
680 if ( tmp > MAX32)
681 {
682 State.regs[OP[0]] = 0x7fff;
683 State.regs[OP[0]+1] = 0xffff;
684 State.F0 = 1;
685 }
686 else if (tmp < MIN32)
687 {
688 State.regs[OP[0]] = 0x8000;
689 State.regs[OP[0]+1] = 0;
690 State.F0 = 1;
691 }
692 else
693 {
694 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
695 State.regs[OP[0]+1] = tmp & 0xffff;
696 State.F0 = 0;
697 }
698 trace_output (OP_DREG);
699 }
700
701 /* addi */
702 void
703 OP_201 ()
704 {
705 uint tmp = State.regs[OP[0]];
706 if (OP[1] == 0)
707 OP[1] = 16;
708 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
709 State.regs[OP[0]] += OP[1];
710 if (tmp > State.regs[OP[0]])
711 State.C = 1;
712 else
713 State.C = 0;
714 trace_output (OP_REG);
715 }
716
717 /* and */
718 void
719 OP_C00 ()
720 {
721 trace_input ("and", OP_REG, OP_REG, OP_VOID);
722 State.regs[OP[0]] &= State.regs[OP[1]];
723 trace_output (OP_REG);
724 }
725
726 /* and3 */
727 void
728 OP_6000000 ()
729 {
730 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
731 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
732 trace_output (OP_REG);
733 }
734
735 /* bclri */
736 void
737 OP_C01 ()
738 {
739 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
740 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
741 trace_output (OP_REG);
742 }
743
744 /* bl.s */
745 void
746 OP_4900 ()
747 {
748 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
749 State.regs[13] = PC+1;
750 PC += SEXT8 (OP[0]);
751 trace_output (OP_VOID);
752 }
753
754 /* bl.l */
755 void
756 OP_24800000 ()
757 {
758 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
759 State.regs[13] = PC+1;
760 PC += OP[0];
761 trace_output (OP_VOID);
762 }
763
764 /* bnoti */
765 void
766 OP_A01 ()
767 {
768 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
769 State.regs[OP[0]] ^= 0x8000 >> OP[1];
770 trace_output (OP_REG);
771 }
772
773 /* bra.s */
774 void
775 OP_4800 ()
776 {
777 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
778 PC += SEXT8 (OP[0]);
779 trace_output (OP_VOID);
780 }
781
782 /* bra.l */
783 void
784 OP_24000000 ()
785 {
786 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
787 PC += OP[0];
788 trace_output (OP_VOID);
789 }
790
791 /* brf0f.s */
792 void
793 OP_4A00 ()
794 {
795 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
796 if (State.F0 == 0)
797 PC += SEXT8 (OP[0]);
798 trace_output (OP_FLAG);
799 }
800
801 /* brf0f.l */
802 void
803 OP_25000000 ()
804 {
805 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
806 if (State.F0 == 0)
807 PC += OP[0];
808 trace_output (OP_FLAG);
809 }
810
811 /* brf0t.s */
812 void
813 OP_4B00 ()
814 {
815 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
816 if (State.F0)
817 PC += SEXT8 (OP[0]);
818 trace_output (OP_FLAG);
819 }
820
821 /* brf0t.l */
822 void
823 OP_25800000 ()
824 {
825 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
826 if (State.F0)
827 PC += OP[0];
828 trace_output (OP_FLAG);
829 }
830
831 /* bseti */
832 void
833 OP_801 ()
834 {
835 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
836 State.regs[OP[0]] |= 0x8000 >> OP[1];
837 trace_output (OP_REG);
838 }
839
840 /* btsti */
841 void
842 OP_E01 ()
843 {
844 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
845 State.F1 = State.F0;
846 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
847 trace_output (OP_FLAG);
848 }
849
850 /* clrac */
851 void
852 OP_5601 ()
853 {
854 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
855 State.a[OP[0]] = 0;
856 trace_output (OP_ACCUM);
857 }
858
859 /* cmp */
860 void
861 OP_600 ()
862 {
863 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
864 State.F1 = State.F0;
865 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
866 trace_output (OP_FLAG);
867 }
868
869 /* cmp */
870 void
871 OP_1603 ()
872 {
873 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
874 State.F1 = State.F0;
875 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
876 trace_output (OP_FLAG);
877 }
878
879 /* cmpeq */
880 void
881 OP_400 ()
882 {
883 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
884 State.F1 = State.F0;
885 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
886 trace_output (OP_FLAG);
887 }
888
889 /* cmpeq */
890 void
891 OP_1403 ()
892 {
893 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
894 State.F1 = State.F0;
895 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
896 trace_output (OP_FLAG);
897 }
898
899 /* cmpeqi.s */
900 void
901 OP_401 ()
902 {
903 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
904 State.F1 = State.F0;
905 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
906 trace_output (OP_FLAG);
907 }
908
909 /* cmpeqi.l */
910 void
911 OP_2000000 ()
912 {
913 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
914 State.F1 = State.F0;
915 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
916 trace_output (OP_FLAG);
917 }
918
919 /* cmpi.s */
920 void
921 OP_601 ()
922 {
923 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
924 State.F1 = State.F0;
925 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
926 trace_output (OP_FLAG);
927 }
928
929 /* cmpi.l */
930 void
931 OP_3000000 ()
932 {
933 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
934 State.F1 = State.F0;
935 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
936 trace_output (OP_FLAG);
937 }
938
939 /* cmpu */
940 void
941 OP_4600 ()
942 {
943 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
944 State.F1 = State.F0;
945 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
946 trace_output (OP_FLAG);
947 }
948
949 /* cmpui */
950 void
951 OP_23000000 ()
952 {
953 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
954 State.F1 = State.F0;
955 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
956 trace_output (OP_FLAG);
957 }
958
959 /* cpfg */
960 void
961 OP_4E09 ()
962 {
963 uint8 *src, *dst;
964
965 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
966 if (OP[0] == 0)
967 dst = &State.F0;
968 else
969 dst = &State.F1;
970
971 if (OP[1] == 0)
972 src = &State.F0;
973 else if (OP[1] == 1)
974 src = &State.F1;
975 else
976 src = &State.C;
977
978 *dst = *src;
979 trace_output (OP_FLAG);
980 }
981
982 /* dbt */
983 void
984 OP_5F20 ()
985 {
986 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
987 State.exception = SIGTRAP;
988 }
989
990 /* divs */
991 void
992 OP_14002800 ()
993 {
994 uint16 foo, tmp, tmpf;
995
996 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
997 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
998 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
999 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1000 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1001 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1002 trace_output (OP_DREG);
1003 }
1004
1005 /* exef0f */
1006 void
1007 OP_4E04 ()
1008 {
1009 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1010 State.exe = (State.F0 == 0);
1011 trace_output (OP_FLAG);
1012 }
1013
1014 /* exef0t */
1015 void
1016 OP_4E24 ()
1017 {
1018 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1019 State.exe = (State.F0 != 0);
1020 trace_output (OP_FLAG);
1021 }
1022
1023 /* exef1f */
1024 void
1025 OP_4E40 ()
1026 {
1027 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1028 State.exe = (State.F1 == 0);
1029 trace_output (OP_FLAG);
1030 }
1031
1032 /* exef1t */
1033 void
1034 OP_4E42 ()
1035 {
1036 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1037 State.exe = (State.F1 != 0);
1038 trace_output (OP_FLAG);
1039 }
1040
1041 /* exefaf */
1042 void
1043 OP_4E00 ()
1044 {
1045 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1046 State.exe = (State.F0 == 0) & (State.F1 == 0);
1047 trace_output (OP_FLAG);
1048 }
1049
1050 /* exefat */
1051 void
1052 OP_4E02 ()
1053 {
1054 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1055 State.exe = (State.F0 == 0) & (State.F1 != 0);
1056 trace_output (OP_FLAG);
1057 }
1058
1059 /* exetaf */
1060 void
1061 OP_4E20 ()
1062 {
1063 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1064 State.exe = (State.F0 != 0) & (State.F1 == 0);
1065 trace_output (OP_FLAG);
1066 }
1067
1068 /* exetat */
1069 void
1070 OP_4E22 ()
1071 {
1072 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1073 State.exe = (State.F0 != 0) & (State.F1 != 0);
1074 trace_output (OP_FLAG);
1075 }
1076
1077 /* exp */
1078 void
1079 OP_15002A00 ()
1080 {
1081 uint32 tmp, foo;
1082 int i;
1083
1084 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1085 if (((int16)State.regs[OP[1]]) >= 0)
1086 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1087 else
1088 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1089
1090 foo = 0x40000000;
1091 for (i=1;i<17;i++)
1092 {
1093 if (tmp & foo)
1094 {
1095 State.regs[OP[0]] = i-1;
1096 trace_output (OP_REG);
1097 return;
1098 }
1099 foo >>= 1;
1100 }
1101 State.regs[OP[0]] = 16;
1102 trace_output (OP_REG);
1103 }
1104
1105 /* exp */
1106 void
1107 OP_15002A02 ()
1108 {
1109 int64 tmp, foo;
1110 int i;
1111
1112 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1113 if (SEXT40(State.a[OP[1]]) >= 0)
1114 tmp = State.a[OP[1]];
1115 else
1116 tmp = ~(State.a[OP[1]]);
1117
1118 foo = 0x4000000000LL;
1119 for (i=1;i<25;i++)
1120 {
1121 if (tmp & foo)
1122 {
1123 State.regs[OP[0]] = i-9;
1124 trace_output (OP_REG);
1125 return;
1126 }
1127 foo >>= 1;
1128 }
1129 State.regs[OP[0]] = 16;
1130 trace_output (OP_REG);
1131 }
1132
1133 /* jl */
1134 void
1135 OP_4D00 ()
1136 {
1137 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1138 State.regs[13] = PC+1;
1139 PC = State.regs[OP[0]];
1140 trace_output (OP_VOID);
1141 }
1142
1143 /* jmp */
1144 void
1145 OP_4C00 ()
1146 {
1147 trace_input ("jmp", OP_REG,
1148 (OP[0] == 13) ? OP_R2 : OP_VOID,
1149 (OP[0] == 13) ? OP_R3 : OP_VOID);
1150
1151 PC = State.regs[OP[0]];
1152 trace_output (OP_VOID);
1153 }
1154
1155 /* ld */
1156 void
1157 OP_30000000 ()
1158 {
1159 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1160 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1161 trace_output (OP_REG);
1162 }
1163
1164 /* ld */
1165 void
1166 OP_6401 ()
1167 {
1168 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1169 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1170 INC_ADDR(State.regs[OP[1]],-2);
1171 trace_output (OP_REG);
1172 }
1173
1174 /* ld */
1175 void
1176 OP_6001 ()
1177 {
1178 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1179 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1180 INC_ADDR(State.regs[OP[1]],2);
1181 trace_output (OP_REG);
1182 }
1183
1184 /* ld */
1185 void
1186 OP_6000 ()
1187 {
1188 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1189 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1190 trace_output (OP_REG);
1191 }
1192
1193 /* ld2w */
1194 void
1195 OP_31000000 ()
1196 {
1197 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1198 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1199 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1200 trace_output (OP_DREG);
1201 }
1202
1203 /* ld2w */
1204 void
1205 OP_6601 ()
1206 {
1207 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1208 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1209 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1210 INC_ADDR(State.regs[OP[1]],-4);
1211 trace_output (OP_DREG);
1212 }
1213
1214 /* ld2w */
1215 void
1216 OP_6201 ()
1217 {
1218 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1219 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1220 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1221 INC_ADDR(State.regs[OP[1]],4);
1222 trace_output (OP_REG);
1223 }
1224
1225 /* ld2w */
1226 void
1227 OP_6200 ()
1228 {
1229 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1230 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1231 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1232 trace_output (OP_REG);
1233 }
1234
1235 /* ldb */
1236 void
1237 OP_38000000 ()
1238 {
1239 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1240 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1241 SEXT8 (State.regs[OP[0]]);
1242 trace_output (OP_REG);
1243 }
1244
1245 /* ldb */
1246 void
1247 OP_7000 ()
1248 {
1249 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1250 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1251 SEXT8 (State.regs[OP[0]]);
1252 trace_output (OP_REG);
1253 }
1254
1255 /* ldi.s */
1256 void
1257 OP_4001 ()
1258 {
1259 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1260 State.regs[OP[0]] = SEXT4(OP[1]);
1261 trace_output (OP_REG);
1262 }
1263
1264 /* ldi.l */
1265 void
1266 OP_20000000 ()
1267 {
1268 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1269 State.regs[OP[0]] = OP[1];
1270 trace_output (OP_REG);
1271 }
1272
1273 /* ldub */
1274 void
1275 OP_39000000 ()
1276 {
1277 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1278 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1279 trace_output (OP_REG);
1280 }
1281
1282 /* ldub */
1283 void
1284 OP_7200 ()
1285 {
1286 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1287 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1288 trace_output (OP_REG);
1289 }
1290
1291 /* mac */
1292 void
1293 OP_2A00 ()
1294 {
1295 int64 tmp;
1296
1297 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1298 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1299
1300 if (State.FX)
1301 tmp = SEXT40( (tmp << 1) & MASK40);
1302
1303 if (State.ST && tmp > MAX32)
1304 tmp = MAX32;
1305
1306 tmp += SEXT40(State.a[OP[0]]);
1307 if (State.ST)
1308 {
1309 if (tmp > MAX32)
1310 State.a[OP[0]] = MAX32;
1311 else if (tmp < MIN32)
1312 State.a[OP[0]] = MIN32;
1313 else
1314 State.a[OP[0]] = tmp & MASK40;
1315 }
1316 else
1317 State.a[OP[0]] = tmp & MASK40;
1318 trace_output (OP_ACCUM);
1319 }
1320
1321 /* macsu */
1322 void
1323 OP_1A00 ()
1324 {
1325 int64 tmp;
1326
1327 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1328 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1329 if (State.FX)
1330 tmp = SEXT40( (tmp << 1) & MASK40);
1331
1332 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1333 trace_output (OP_ACCUM);
1334 }
1335
1336 /* macu */
1337 void
1338 OP_3A00 ()
1339 {
1340 int64 tmp;
1341
1342 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1343 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1347 trace_output (OP_ACCUM);
1348 }
1349
1350 /* max */
1351 void
1352 OP_2600 ()
1353 {
1354 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1355 State.F1 = State.F0;
1356 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1357 {
1358 State.regs[OP[0]] = State.regs[OP[1]];
1359 State.F0 = 1;
1360 }
1361 else
1362 State.F0 = 0;
1363 trace_output (OP_REG);
1364 }
1365
1366 /* max */
1367 void
1368 OP_3600 ()
1369 {
1370 int64 tmp;
1371
1372 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1373 State.F1 = State.F0;
1374 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1375 if (tmp > SEXT40(State.a[OP[0]]))
1376 {
1377 State.a[OP[0]] = tmp & MASK40;
1378 State.F0 = 1;
1379 }
1380 else
1381 State.F0 = 0;
1382 trace_output (OP_ACCUM);
1383 }
1384
1385 /* max */
1386 void
1387 OP_3602 ()
1388 {
1389 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1390 State.F1 = State.F0;
1391 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1392 {
1393 State.a[OP[0]] = State.a[OP[1]];
1394 State.F0 = 1;
1395 }
1396 else
1397 State.F0 = 0;
1398 trace_output (OP_ACCUM);
1399 }
1400
1401
1402 /* min */
1403 void
1404 OP_2601 ()
1405 {
1406 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1407 State.F1 = State.F0;
1408 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1409 {
1410 State.regs[OP[0]] = State.regs[OP[1]];
1411 State.F0 = 1;
1412 }
1413 else
1414 State.F0 = 0;
1415 trace_output (OP_REG);
1416 }
1417
1418 /* min */
1419 void
1420 OP_3601 ()
1421 {
1422 int64 tmp;
1423
1424 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1425 State.F1 = State.F0;
1426 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1427 if (tmp < SEXT40(State.a[OP[0]]))
1428 {
1429 State.a[OP[0]] = tmp & MASK40;
1430 State.F0 = 1;
1431 }
1432 else
1433 State.F0 = 0;
1434 trace_output (OP_ACCUM);
1435 }
1436
1437 /* min */
1438 void
1439 OP_3603 ()
1440 {
1441 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1442 State.F1 = State.F0;
1443 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1444 {
1445 State.a[OP[0]] = State.a[OP[1]];
1446 State.F0 = 1;
1447 }
1448 else
1449 State.F0 = 0;
1450 trace_output (OP_ACCUM);
1451 }
1452
1453 /* msb */
1454 void
1455 OP_2800 ()
1456 {
1457 int64 tmp;
1458
1459 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1460 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1461
1462 if (State.FX)
1463 tmp = SEXT40 ((tmp << 1) & MASK40);
1464
1465 if (State.ST && tmp > MAX32)
1466 tmp = MAX32;
1467
1468 tmp = SEXT40(State.a[OP[0]]) - tmp;
1469 if (State.ST)
1470 {
1471 if (tmp > MAX32)
1472 State.a[OP[0]] = MAX32;
1473 else if (tmp < MIN32)
1474 State.a[OP[0]] = MIN32;
1475 else
1476 State.a[OP[0]] = tmp & MASK40;
1477 }
1478 else
1479 State.a[OP[0]] = tmp & MASK40;
1480 trace_output (OP_ACCUM);
1481 }
1482
1483 /* msbsu */
1484 void
1485 OP_1800 ()
1486 {
1487 int64 tmp;
1488
1489 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1490 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1491 if (State.FX)
1492 tmp = SEXT40( (tmp << 1) & MASK40);
1493
1494 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1495 trace_output (OP_ACCUM);
1496 }
1497
1498 /* msbu */
1499 void
1500 OP_3800 ()
1501 {
1502 int64 tmp;
1503
1504 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1505 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1506 if (State.FX)
1507 tmp = SEXT40( (tmp << 1) & MASK40);
1508
1509 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1510 trace_output (OP_ACCUM);
1511 }
1512
1513 /* mul */
1514 void
1515 OP_2E00 ()
1516 {
1517 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1518 State.regs[OP[0]] *= State.regs[OP[1]];
1519 trace_output (OP_REG);
1520 }
1521
1522 /* mulx */
1523 void
1524 OP_2C00 ()
1525 {
1526 int64 tmp;
1527
1528 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1529 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1530
1531 if (State.FX)
1532 tmp = SEXT40 ((tmp << 1) & MASK40);
1533
1534 if (State.ST && tmp > MAX32)
1535 State.a[OP[0]] = MAX32;
1536 else
1537 State.a[OP[0]] = tmp & MASK40;
1538 trace_output (OP_ACCUM);
1539 }
1540
1541 /* mulxsu */
1542 void
1543 OP_1C00 ()
1544 {
1545 int64 tmp;
1546
1547 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1548 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1549
1550 if (State.FX)
1551 tmp <<= 1;
1552
1553 State.a[OP[0]] = tmp & MASK40;
1554 trace_output (OP_ACCUM);
1555 }
1556
1557 /* mulxu */
1558 void
1559 OP_3C00 ()
1560 {
1561 int64 tmp;
1562
1563 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1564 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1565
1566 if (State.FX)
1567 tmp <<= 1;
1568
1569 State.a[OP[0]] = tmp & MASK40;
1570 trace_output (OP_ACCUM);
1571 }
1572
1573 /* mv */
1574 void
1575 OP_4000 ()
1576 {
1577 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1578 State.regs[OP[0]] = State.regs[OP[1]];
1579 trace_output (OP_REG);
1580 }
1581
1582 /* mv2w */
1583 void
1584 OP_5000 ()
1585 {
1586 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1587 State.regs[OP[0]] = State.regs[OP[1]];
1588 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1589 trace_output (OP_DREG);
1590 }
1591
1592 /* mv2wfac */
1593 void
1594 OP_3E00 ()
1595 {
1596 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1597 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1598 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1599 trace_output (OP_DREG);
1600 }
1601
1602 /* mv2wtac */
1603 void
1604 OP_3E01 ()
1605 {
1606 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1607 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1608 trace_output (OP_ACCUM);
1609 }
1610
1611 /* mvac */
1612 void
1613 OP_3E03 ()
1614 {
1615 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1616 State.a[OP[0]] = State.a[OP[1]];
1617 trace_output (OP_ACCUM);
1618 }
1619
1620 /* mvb */
1621 void
1622 OP_5400 ()
1623 {
1624 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1625 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1626 trace_output (OP_REG);
1627 }
1628
1629 /* mvf0f */
1630 void
1631 OP_4400 ()
1632 {
1633 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1634 if (State.F0 == 0)
1635 State.regs[OP[0]] = State.regs[OP[1]];
1636 trace_output (OP_REG);
1637 }
1638
1639 /* mvf0t */
1640 void
1641 OP_4401 ()
1642 {
1643 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1644 if (State.F0)
1645 State.regs[OP[0]] = State.regs[OP[1]];
1646 trace_output (OP_REG);
1647 }
1648
1649 /* mvfacg */
1650 void
1651 OP_1E04 ()
1652 {
1653 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1654 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1655 trace_output (OP_ACCUM);
1656 }
1657
1658 /* mvfachi */
1659 void
1660 OP_1E00 ()
1661 {
1662 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1663 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1664 trace_output (OP_REG);
1665 }
1666
1667 /* mvfaclo */
1668 void
1669 OP_1E02 ()
1670 {
1671 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1672 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1673 trace_output (OP_REG);
1674 }
1675
1676 /* mvfc */
1677 void
1678 OP_5200 ()
1679 {
1680 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1681 if (OP[1] == 0)
1682 {
1683 /* PSW is treated specially */
1684 PSW = 0;
1685 if (State.SM) PSW |= 0x8000;
1686 if (State.EA) PSW |= 0x2000;
1687 if (State.DB) PSW |= 0x1000;
1688 if (State.IE) PSW |= 0x400;
1689 if (State.RP) PSW |= 0x200;
1690 if (State.MD) PSW |= 0x100;
1691 if (State.FX) PSW |= 0x80;
1692 if (State.ST) PSW |= 0x40;
1693 if (State.F0) PSW |= 8;
1694 if (State.F1) PSW |= 4;
1695 if (State.C) PSW |= 1;
1696 }
1697 State.regs[OP[0]] = State.cregs[OP[1]];
1698 trace_output (OP_REG);
1699 }
1700
1701 /* mvtacg */
1702 void
1703 OP_1E41 ()
1704 {
1705 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1706 State.a[OP[1]] &= MASK32;
1707 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1708 trace_output (OP_ACCUM_REVERSE);
1709 }
1710
1711 /* mvtachi */
1712 void
1713 OP_1E01 ()
1714 {
1715 uint16 tmp;
1716
1717 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1718 tmp = State.a[OP[1]] & 0xffff;
1719 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1720 trace_output (OP_ACCUM_REVERSE);
1721 }
1722
1723 /* mvtaclo */
1724 void
1725 OP_1E21 ()
1726 {
1727 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1728 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1729 trace_output (OP_ACCUM_REVERSE);
1730 }
1731
1732 /* mvtc */
1733 void
1734 OP_5600 ()
1735 {
1736 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1737 State.cregs[OP[1]] = State.regs[OP[0]];
1738 if (OP[1] == 0)
1739 {
1740 /* PSW is treated specially */
1741 State.SM = (PSW & 0x8000) ? 1 : 0;
1742 State.EA = (PSW & 0x2000) ? 1 : 0;
1743 State.DB = (PSW & 0x1000) ? 1 : 0;
1744 State.IE = (PSW & 0x400) ? 1 : 0;
1745 State.RP = (PSW & 0x200) ? 1 : 0;
1746 State.MD = (PSW & 0x100) ? 1 : 0;
1747 State.FX = (PSW & 0x80) ? 1 : 0;
1748 State.ST = (PSW & 0x40) ? 1 : 0;
1749 State.F0 = (PSW & 8) ? 1 : 0;
1750 State.F1 = (PSW & 4) ? 1 : 0;
1751 State.C = PSW & 1;
1752 if (State.ST && !State.FX)
1753 {
1754 (*d10v_callback->printf_filtered) (d10v_callback,
1755 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1756 PC<<2);
1757 State.exception = SIGILL;
1758 }
1759 }
1760 trace_output (OP_CR_REVERSE);
1761 }
1762
1763 /* mvub */
1764 void
1765 OP_5401 ()
1766 {
1767 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1768 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1769 trace_output (OP_REG);
1770 }
1771
1772 /* neg */
1773 void
1774 OP_4605 ()
1775 {
1776 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1777 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1778 trace_output (OP_REG);
1779 }
1780
1781 /* neg */
1782 void
1783 OP_5605 ()
1784 {
1785 int64 tmp;
1786
1787 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1788 tmp = -SEXT40(State.a[OP[0]]);
1789 if (State.ST)
1790 {
1791 if ( tmp > MAX32)
1792 State.a[OP[0]] = MAX32;
1793 else if (tmp < MIN32)
1794 State.a[OP[0]] = MIN32;
1795 else
1796 State.a[OP[0]] = tmp & MASK40;
1797 }
1798 else
1799 State.a[OP[0]] = tmp & MASK40;
1800 trace_output (OP_ACCUM);
1801 }
1802
1803
1804 /* nop */
1805 void
1806 OP_5E00 ()
1807 {
1808 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1809 trace_output (OP_VOID);
1810
1811 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1812 left_nops++;
1813 else
1814 right_nops++;
1815 }
1816
1817 /* not */
1818 void
1819 OP_4603 ()
1820 {
1821 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1822 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1823 trace_output (OP_REG);
1824 }
1825
1826 /* or */
1827 void
1828 OP_800 ()
1829 {
1830 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1831 State.regs[OP[0]] |= State.regs[OP[1]];
1832 trace_output (OP_REG);
1833 }
1834
1835 /* or3 */
1836 void
1837 OP_4000000 ()
1838 {
1839 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1840 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1841 trace_output (OP_REG);
1842 }
1843
1844 /* rac */
1845 void
1846 OP_5201 ()
1847 {
1848 int64 tmp;
1849 int shift = SEXT3 (OP[2]);
1850
1851 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1852 if (OP[1] != 0)
1853 {
1854 (*d10v_callback->printf_filtered) (d10v_callback,
1855 "ERROR at PC 0x%x: instruction only valid for A0\n",
1856 PC<<2);
1857 State.exception = SIGILL;
1858 }
1859
1860 State.F1 = State.F0;
1861 if (shift >=0)
1862 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1863 else
1864 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1865 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1866 if (tmp > MAX32)
1867 {
1868 State.regs[OP[0]] = 0x7fff;
1869 State.regs[OP[0]+1] = 0xffff;
1870 State.F0 = 1;
1871 }
1872 else if (tmp < MIN32)
1873 {
1874 State.regs[OP[0]] = 0x8000;
1875 State.regs[OP[0]+1] = 0;
1876 State.F0 = 1;
1877 }
1878 else
1879 {
1880 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1881 State.regs[OP[0]+1] = tmp & 0xffff;
1882 State.F0 = 0;
1883 }
1884 trace_output (OP_DREG);
1885 }
1886
1887 /* rachi */
1888 void
1889 OP_4201 ()
1890 {
1891 int64 tmp;
1892 int shift = SEXT3 (OP[2]);
1893
1894 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1895 State.F1 = State.F0;
1896 if (shift >=0)
1897 tmp = SEXT44 (State.a[1]) << shift;
1898 else
1899 tmp = SEXT44 (State.a[1]) >> -shift;
1900 tmp += 0x8000;
1901
1902 if (tmp > MAX32)
1903 {
1904 State.regs[OP[0]] = 0x7fff;
1905 State.F0 = 1;
1906 }
1907 else if (tmp < 0xfff80000000LL)
1908 {
1909 State.regs[OP[0]] = 0x8000;
1910 State.F0 = 1;
1911 }
1912 else
1913 {
1914 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1915 State.F0 = 0;
1916 }
1917 trace_output (OP_REG);
1918 }
1919
1920 /* rep */
1921 void
1922 OP_27000000 ()
1923 {
1924 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1925 RPT_S = PC + 1;
1926 RPT_E = PC + OP[1];
1927 RPT_C = State.regs[OP[0]];
1928 State.RP = 1;
1929 if (RPT_C == 0)
1930 {
1931 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1932 State.exception = SIGILL;
1933 }
1934 if (OP[1] < 4)
1935 {
1936 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1937 State.exception = SIGILL;
1938 }
1939 trace_output (OP_VOID);
1940 }
1941
1942 /* repi */
1943 void
1944 OP_2F000000 ()
1945 {
1946 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1947 RPT_S = PC + 1;
1948 RPT_E = PC + OP[1];
1949 RPT_C = OP[0];
1950 State.RP = 1;
1951 if (RPT_C == 0)
1952 {
1953 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1954 State.exception = SIGILL;
1955 }
1956 if (OP[1] < 4)
1957 {
1958 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1959 State.exception = SIGILL;
1960 }
1961 trace_output (OP_VOID);
1962 }
1963
1964 /* rtd */
1965 void
1966 OP_5F60 ()
1967 {
1968 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1969 State.exception = SIGILL;
1970 }
1971
1972 /* rte */
1973 void
1974 OP_5F40 ()
1975 {
1976 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1977 PC = BPC;
1978 PSW = BPSW;
1979 trace_output (OP_VOID);
1980 }
1981
1982 /* sadd */
1983 void
1984 OP_1223 ()
1985 {
1986 int64 tmp;
1987
1988 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1989 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1990 if (State.ST)
1991 {
1992 if (tmp > MAX32)
1993 State.a[OP[0]] = MAX32;
1994 else if (tmp < MIN32)
1995 State.a[OP[0]] = MIN32;
1996 else
1997 State.a[OP[0]] = tmp & MASK40;
1998 }
1999 else
2000 State.a[OP[0]] = tmp & MASK40;
2001 trace_output (OP_ACCUM);
2002 }
2003
2004 /* setf0f */
2005 void
2006 OP_4611 ()
2007 {
2008 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2009 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2010 trace_output (OP_REG);
2011 }
2012
2013 /* setf0t */
2014 void
2015 OP_4613 ()
2016 {
2017 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2018 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2019 trace_output (OP_REG);
2020 }
2021
2022 /* sleep */
2023 void
2024 OP_5FC0 ()
2025 {
2026 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2027 State.IE = 1;
2028 trace_output (OP_VOID);
2029 }
2030
2031 /* sll */
2032 void
2033 OP_2200 ()
2034 {
2035 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2036 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2037 trace_output (OP_REG);
2038 }
2039
2040 /* sll */
2041 void
2042 OP_3200 ()
2043 {
2044 int64 tmp;
2045 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2046 if ((State.regs[OP[1]] & 31) <= 16)
2047 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2048 else
2049 {
2050 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2051 State.exception = SIGILL;
2052 return;
2053 }
2054
2055 if (State.ST)
2056 {
2057 if (tmp > MAX32)
2058 State.a[OP[0]] = MAX32;
2059 else if (tmp < 0xffffff80000000LL)
2060 State.a[OP[0]] = MIN32;
2061 else
2062 State.a[OP[0]] = tmp & MASK40;
2063 }
2064 else
2065 State.a[OP[0]] = tmp & MASK40;
2066 trace_output (OP_ACCUM);
2067 }
2068
2069 /* slli */
2070 void
2071 OP_2201 ()
2072 {
2073 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2074 State.regs[OP[0]] <<= OP[1];
2075 trace_output (OP_REG);
2076 }
2077
2078 /* slli */
2079 void
2080 OP_3201 ()
2081 {
2082 int64 tmp;
2083
2084 if (OP[1] == 0)
2085 OP[1] = 16;
2086
2087 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2088 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2089
2090 if (State.ST)
2091 {
2092 if (tmp > MAX32)
2093 State.a[OP[0]] = MAX32;
2094 else if (tmp < 0xffffff80000000LL)
2095 State.a[OP[0]] = MIN32;
2096 else
2097 State.a[OP[0]] = tmp & MASK40;
2098 }
2099 else
2100 State.a[OP[0]] = tmp & MASK40;
2101 trace_output (OP_ACCUM);
2102 }
2103
2104 /* slx */
2105 void
2106 OP_460B ()
2107 {
2108 uint16 tmp;
2109
2110 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2111 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2112 trace_output (OP_REG);
2113 }
2114
2115 /* sra */
2116 void
2117 OP_2400 ()
2118 {
2119 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2120 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2121 trace_output (OP_REG);
2122 }
2123
2124 /* sra */
2125 void
2126 OP_3400 ()
2127 {
2128 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2129 if ((State.regs[OP[1]] & 31) <= 16)
2130 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2131 else
2132 {
2133 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2134 State.exception = SIGILL;
2135 return;
2136 }
2137
2138 trace_output (OP_ACCUM);
2139 }
2140
2141 /* srai */
2142 void
2143 OP_2401 ()
2144 {
2145 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2146 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2147 trace_output (OP_REG);
2148 }
2149
2150 /* srai */
2151 void
2152 OP_3401 ()
2153 {
2154 if (OP[1] == 0)
2155 OP[1] = 16;
2156
2157 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2158 State.a[OP[0]] >>= OP[1];
2159 trace_output (OP_ACCUM);
2160 }
2161
2162 /* srl */
2163 void
2164 OP_2000 ()
2165 {
2166 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2167 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2168 trace_output (OP_REG);
2169 }
2170
2171 /* srl */
2172 void
2173 OP_3000 ()
2174 {
2175 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2176 if ((State.regs[OP[1]] & 31) <= 16)
2177 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2178 else
2179 {
2180 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2181 State.exception = SIGILL;
2182 return;
2183 }
2184
2185 trace_output (OP_ACCUM);
2186 }
2187
2188 /* srli */
2189 void
2190 OP_2001 ()
2191 {
2192 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2193 State.regs[OP[0]] >>= OP[1];
2194 trace_output (OP_REG);
2195 }
2196
2197 /* srli */
2198 void
2199 OP_3001 ()
2200 {
2201 if (OP[1] == 0)
2202 OP[1] = 16;
2203
2204 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2205 State.a[OP[0]] >>= OP[1];
2206 trace_output (OP_ACCUM);
2207 }
2208
2209 /* srx */
2210 void
2211 OP_4609 ()
2212 {
2213 uint16 tmp;
2214
2215 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2216 tmp = State.F0 << 15;
2217 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2218 trace_output (OP_REG);
2219 }
2220
2221 /* st */
2222 void
2223 OP_34000000 ()
2224 {
2225 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2226 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2227 trace_output (OP_VOID);
2228 }
2229
2230 /* st */
2231 void
2232 OP_6800 ()
2233 {
2234 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2235 SW (State.regs[OP[1]], State.regs[OP[0]]);
2236 trace_output (OP_VOID);
2237 }
2238
2239 /* st */
2240 void
2241 OP_6C1F ()
2242 {
2243 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2244 if ( OP[1] != 15 )
2245 {
2246 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2247 State.exception = SIGILL;
2248 return;
2249 }
2250 State.regs[OP[1]] -= 2;
2251 SW (State.regs[OP[1]], State.regs[OP[0]]);
2252 trace_output (OP_VOID);
2253 }
2254
2255 /* st */
2256 void
2257 OP_6801 ()
2258 {
2259 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2260 SW (State.regs[OP[1]], State.regs[OP[0]]);
2261 INC_ADDR (State.regs[OP[1]],2);
2262 trace_output (OP_VOID);
2263 }
2264
2265 /* st */
2266 void
2267 OP_6C01 ()
2268 {
2269 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2270 SW (State.regs[OP[1]], State.regs[OP[0]]);
2271 INC_ADDR (State.regs[OP[1]],-2);
2272 trace_output (OP_VOID);
2273 }
2274
2275 /* st2w */
2276 void
2277 OP_35000000 ()
2278 {
2279 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2280 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2281 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2282 trace_output (OP_VOID);
2283 }
2284
2285 /* st2w */
2286 void
2287 OP_6A00 ()
2288 {
2289 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2290 SW (State.regs[OP[1]], State.regs[OP[0]]);
2291 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2292 trace_output (OP_VOID);
2293 }
2294
2295 /* st2w */
2296 void
2297 OP_6E1F ()
2298 {
2299 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2300 if ( OP[1] != 15 )
2301 {
2302 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2303 State.exception = SIGILL;
2304 return;
2305 }
2306 State.regs[OP[1]] -= 4;
2307 SW (State.regs[OP[1]], State.regs[OP[0]]);
2308 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2309 trace_output (OP_VOID);
2310 }
2311
2312 /* st2w */
2313 void
2314 OP_6A01 ()
2315 {
2316 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2317 SW (State.regs[OP[1]], State.regs[OP[0]]);
2318 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2319 INC_ADDR (State.regs[OP[1]],4);
2320 trace_output (OP_VOID);
2321 }
2322
2323 /* st2w */
2324 void
2325 OP_6E01 ()
2326 {
2327 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2328 SW (State.regs[OP[1]], State.regs[OP[0]]);
2329 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2330 INC_ADDR (State.regs[OP[1]],-4);
2331 trace_output (OP_VOID);
2332 }
2333
2334 /* stb */
2335 void
2336 OP_3C000000 ()
2337 {
2338 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2339 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2340 trace_output (OP_VOID);
2341 }
2342
2343 /* stb */
2344 void
2345 OP_7800 ()
2346 {
2347 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2348 SB (State.regs[OP[1]], State.regs[OP[0]]);
2349 trace_output (OP_VOID);
2350 }
2351
2352 /* stop */
2353 void
2354 OP_5FE0 ()
2355 {
2356 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2357 State.exception = SIG_D10V_STOP;
2358 trace_output (OP_VOID);
2359 }
2360
2361 /* sub */
2362 void
2363 OP_0 ()
2364 {
2365 int32 tmp;
2366
2367 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2368 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2369 State.C = (tmp & 0xffff0000) ? 1 : 0;
2370 State.regs[OP[0]] = tmp & 0xffff;
2371 trace_output (OP_REG);
2372 }
2373
2374 /* sub */
2375 void
2376 OP_1001 ()
2377 {
2378 int64 tmp;
2379
2380 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2381 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2382 if (State.ST)
2383 {
2384 if ( tmp > MAX32)
2385 State.a[OP[0]] = MAX32;
2386 else if ( tmp < MIN32)
2387 State.a[OP[0]] = MIN32;
2388 else
2389 State.a[OP[0]] = tmp & MASK40;
2390 }
2391 else
2392 State.a[OP[0]] = tmp & MASK40;
2393
2394 trace_output (OP_ACCUM);
2395 }
2396
2397 /* sub */
2398
2399 void
2400 OP_1003 ()
2401 {
2402 int64 tmp;
2403
2404 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2405 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2406 if (State.ST)
2407 {
2408 if (tmp > MAX32)
2409 State.a[OP[0]] = MAX32;
2410 else if ( tmp < MIN32)
2411 State.a[OP[0]] = MIN32;
2412 else
2413 State.a[OP[0]] = tmp & MASK40;
2414 }
2415 else
2416 State.a[OP[0]] = tmp & MASK40;
2417
2418 trace_output (OP_ACCUM);
2419 }
2420
2421 /* sub2w */
2422 void
2423 OP_1000 ()
2424 {
2425 int64 tmp;
2426 int32 a,b;
2427
2428 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2429 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2430 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2431 tmp = a-b;
2432 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2433 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2434 State.regs[OP[0]+1] = tmp & 0xffff;
2435 trace_output (OP_DREG);
2436 }
2437
2438 /* subac3 */
2439 void
2440 OP_17000000 ()
2441 {
2442 int64 tmp;
2443
2444 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2445 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2446 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2447 State.regs[OP[0]+1] = tmp & 0xffff;
2448 trace_output (OP_DREG);
2449 }
2450
2451 /* subac3 */
2452 void
2453 OP_17000002 ()
2454 {
2455 int64 tmp;
2456
2457 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2458 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2459 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2460 State.regs[OP[0]+1] = tmp & 0xffff;
2461 trace_output (OP_DREG);
2462 }
2463
2464 /* subac3s */
2465 void
2466 OP_17001000 ()
2467 {
2468 int64 tmp;
2469
2470 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2471 State.F1 = State.F0;
2472 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2473 if ( tmp > MAX32)
2474 {
2475 State.regs[OP[0]] = 0x7fff;
2476 State.regs[OP[0]+1] = 0xffff;
2477 State.F0 = 1;
2478 }
2479 else if (tmp < MIN32)
2480 {
2481 State.regs[OP[0]] = 0x8000;
2482 State.regs[OP[0]+1] = 0;
2483 State.F0 = 1;
2484 }
2485 else
2486 {
2487 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2488 State.regs[OP[0]+1] = tmp & 0xffff;
2489 State.F0 = 0;
2490 }
2491 trace_output (OP_DREG);
2492 }
2493
2494 /* subac3s */
2495 void
2496 OP_17001002 ()
2497 {
2498 int64 tmp;
2499
2500 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2501 State.F1 = State.F0;
2502 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2503 if ( tmp > MAX32)
2504 {
2505 State.regs[OP[0]] = 0x7fff;
2506 State.regs[OP[0]+1] = 0xffff;
2507 State.F0 = 1;
2508 }
2509 else if (tmp < MIN32)
2510 {
2511 State.regs[OP[0]] = 0x8000;
2512 State.regs[OP[0]+1] = 0;
2513 State.F0 = 1;
2514 }
2515 else
2516 {
2517 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2518 State.regs[OP[0]+1] = tmp & 0xffff;
2519 State.F0 = 0;
2520 }
2521 trace_output (OP_DREG);
2522 }
2523
2524 /* subi */
2525 void
2526 OP_1 ()
2527 {
2528 int32 tmp;
2529 if (OP[1] == 0)
2530 OP[1] = 16;
2531
2532 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2533 tmp = (int16)State.regs[OP[0]] - OP[1];
2534 State.C = (tmp & 0xffff0000) ? 1 : 0;
2535 State.regs[OP[0]] = tmp & 0xffff;
2536 trace_output (OP_REG);
2537 }
2538
2539 /* trap */
2540 void
2541 OP_5F00 ()
2542 {
2543 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2544 trace_output (OP_VOID);
2545
2546 switch (OP[0])
2547 {
2548 default:
2549 #if 0
2550 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2551 State.exception = SIGILL;
2552 #else
2553 /* Use any other traps for batch debugging. */
2554 {
2555 int i;
2556 static int first_time = 1;
2557
2558 if (first_time)
2559 {
2560 first_time = 0;
2561 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2562 for (i = 0; i < 16; i++)
2563 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2564 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2565 }
2566
2567 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2568
2569 for (i = 0; i < 16; i++)
2570 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2571
2572 for (i = 0; i < 2; i++)
2573 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2574 ((int)(State.a[OP[i]] >> 32) & 0xff),
2575 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
2576
2577 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2578 State.F0 != 0, State.F1 != 0, State.C != 0);
2579 break;
2580 #endif
2581
2582 case 0:
2583 /* Trap 0 is used for simulating low-level I/O */
2584 {
2585 int save_errno = errno;
2586 errno = 0;
2587
2588 /* Registers passed to trap 0 */
2589
2590 #define FUNC State.regs[6] /* function number */
2591 #define PARM1 State.regs[2] /* optional parm 1 */
2592 #define PARM2 State.regs[3] /* optional parm 2 */
2593 #define PARM3 State.regs[4] /* optional parm 3 */
2594 #define PARM4 State.regs[5] /* optional parm 3 */
2595
2596 /* Registers set by trap 0 */
2597
2598 #define RETVAL State.regs[2] /* return value */
2599 #define RETVAL_HIGH State.regs[2] /* return value */
2600 #define RETVAL_LOW State.regs[3] /* return value */
2601 #define RETERR State.regs[4] /* return error code */
2602
2603 /* Turn a pointer in a register into a pointer into real memory. */
2604
2605 #define MEMPTR(x) ((char *)((x) + State.imem))
2606
2607 switch (FUNC)
2608 {
2609 #if !defined(__GO32__) && !defined(_WIN32)
2610 case SYS_fork:
2611 RETVAL = fork ();
2612 break;
2613 case SYS_execve:
2614 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2615 (char **)MEMPTR (PARM3));
2616 break;
2617 case SYS_execv:
2618 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2619 break;
2620 case SYS_pipe:
2621 {
2622 reg_t buf;
2623 int host_fd[2];
2624
2625 buf = PARM1;
2626 RETVAL = pipe (host_fd);
2627 SW (buf, host_fd[0]);
2628 buf += sizeof(uint16);
2629 SW (buf, host_fd[1]);
2630 }
2631 break;
2632 case SYS_wait:
2633 {
2634 int status;
2635
2636 RETVAL = wait (&status);
2637 SW (PARM1, status);
2638 }
2639 break;
2640 #endif
2641 case SYS_read:
2642 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2643 PARM3);
2644 break;
2645 case SYS_write:
2646 if (PARM1 == 1)
2647 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2648 MEMPTR (PARM2), PARM3);
2649 else
2650 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2651 MEMPTR (PARM2), PARM3);
2652 break;
2653 case SYS_lseek:
2654 {
2655 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2656 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2657 PARM4);
2658 RETVAL_HIGH = ret >> 16;
2659 RETVAL_LOW = ret & 0xffff;
2660 }
2661 break;
2662 case SYS_close:
2663 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2664 break;
2665 case SYS_open:
2666 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2667 break;
2668 case SYS_exit:
2669 State.exception = SIG_D10V_EXIT;
2670 break;
2671
2672 case SYS_stat:
2673 /* stat system call */
2674 {
2675 struct stat host_stat;
2676 reg_t buf;
2677
2678 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2679
2680 buf = PARM2;
2681
2682 /* The hard-coded offsets and sizes were determined by using
2683 * the D10V compiler on a test program that used struct stat.
2684 */
2685 SW (buf, host_stat.st_dev);
2686 SW (buf+2, host_stat.st_ino);
2687 SW (buf+4, host_stat.st_mode);
2688 SW (buf+6, host_stat.st_nlink);
2689 SW (buf+8, host_stat.st_uid);
2690 SW (buf+10, host_stat.st_gid);
2691 SW (buf+12, host_stat.st_rdev);
2692 SLW (buf+16, host_stat.st_size);
2693 SLW (buf+20, host_stat.st_atime);
2694 SLW (buf+28, host_stat.st_mtime);
2695 SLW (buf+36, host_stat.st_ctime);
2696 }
2697 break;
2698
2699 case SYS_chown:
2700 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2701 break;
2702 case SYS_chmod:
2703 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2704 break;
2705 case SYS_utime:
2706 /* Cast the second argument to void *, to avoid type mismatch
2707 if a prototype is present. */
2708 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2709 break;
2710 default:
2711 abort ();
2712 }
2713 RETERR = d10v_callback->get_errno(d10v_callback);
2714 break;
2715 }
2716
2717 case 1:
2718 /* Trap 1 prints a string */
2719 {
2720 char *fstr = State.regs[2] + State.imem;
2721 fputs (fstr, stdout);
2722 break;
2723 }
2724
2725 case 2:
2726 /* Trap 2 calls printf */
2727 {
2728 char *fstr = State.regs[2] + State.imem;
2729 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2730 (int16)State.regs[3],
2731 (int16)State.regs[4],
2732 (int16)State.regs[5]);
2733 break;
2734 }
2735
2736 case 3:
2737 /* Trap 3 writes a character */
2738 putchar (State.regs[2]);
2739 break;
2740 }
2741 }
2742 }
2743
2744 /* tst0i */
2745 void
2746 OP_7000000 ()
2747 {
2748 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2749 State.F1 = State.F0;
2750 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2751 trace_output (OP_FLAG);
2752 }
2753
2754 /* tst1i */
2755 void
2756 OP_F000000 ()
2757 {
2758 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2759 State.F1 = State.F0;
2760 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2761 trace_output (OP_FLAG);
2762 }
2763
2764 /* wait */
2765 void
2766 OP_5F80 ()
2767 {
2768 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2769 State.IE = 1;
2770 trace_output (OP_VOID);
2771 }
2772
2773 /* xor */
2774 void
2775 OP_A00 ()
2776 {
2777 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2778 State.regs[OP[0]] ^= State.regs[OP[1]];
2779 trace_output (OP_REG);
2780 }
2781
2782 /* xor3 */
2783 void
2784 OP_5000000 ()
2785 {
2786 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2787 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2788 trace_output (OP_REG);
2789 }
2790
GDB Binutils - Deliverables
This page took 0.083456 seconds and 5 git commands to generate.