13 #include "sys/syscall.h"
15 extern char *strrchr ();
48 move_to_cr (int cr
, reg_t val
)
53 State
.SM
= (val
& PSW_SM_BIT
) != 0;
54 State
.EA
= (val
& PSW_EA_BIT
) != 0;
55 State
.DB
= (val
& PSW_DB_BIT
) != 0;
56 State
.DM
= (val
& PSW_DM_BIT
) != 0;
57 State
.IE
= (val
& PSW_IE_BIT
) != 0;
58 State
.RP
= (val
& PSW_RP_BIT
) != 0;
59 State
.MD
= (val
& PSW_MD_BIT
) != 0;
60 State
.FX
= (val
& PSW_FX_BIT
) != 0;
61 State
.ST
= (val
& PSW_ST_BIT
) != 0;
62 State
.F0
= (val
& PSW_F0_BIT
) != 0;
63 State
.F1
= (val
& PSW_F1_BIT
) != 0;
64 State
.C
= (val
& PSW_C_BIT
) != 0;
65 if (State
.ST
&& !State
.FX
)
67 (*d10v_callback
->printf_filtered
)
69 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
71 State
.exception
= SIGILL
;
73 State
.cregs
[cr
] = (val
& ~0x4032);
77 State
.cregs
[cr
] = (val
& ~0x4032);
81 State
.cregs
[cr
] = (val
& ~0x1);
84 State
.cregs
[cr
] = val
;
96 if (State
.SM
) val
|= PSW_SM_BIT
;
97 if (State
.EA
) val
|= PSW_EA_BIT
;
98 if (State
.DB
) val
|= PSW_DB_BIT
;
99 if (State
.DM
) val
|= PSW_DM_BIT
;
100 if (State
.IE
) val
|= PSW_IE_BIT
;
101 if (State
.RP
) val
|= PSW_RP_BIT
;
102 if (State
.MD
) val
|= PSW_MD_BIT
;
103 if (State
.FX
) val
|= PSW_FX_BIT
;
104 if (State
.ST
) val
|= PSW_ST_BIT
;
105 if (State
.F0
) val
|= PSW_F0_BIT
;
106 if (State
.F1
) val
|= PSW_F1_BIT
;
107 if (State
.C
) val
|= PSW_C_BIT
;
110 val
= State
.cregs
[cr
];
118 static void trace_input_func
PARAMS ((char *name
,
123 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
125 static void trace_output_func
PARAMS ((enum op_types result
));
127 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
129 #ifndef SIZE_INSTRUCTION
130 #define SIZE_INSTRUCTION 8
133 #ifndef SIZE_OPERANDS
134 #define SIZE_OPERANDS 18
138 #define SIZE_VALUES 13
141 #ifndef SIZE_LOCATION
142 #define SIZE_LOCATION 20
149 #ifndef SIZE_LINE_NUMBER
150 #define SIZE_LINE_NUMBER 4
154 trace_input_func (name
, in1
, in2
, in3
)
167 const char *filename
;
168 const char *functionname
;
169 unsigned int linenumber
;
172 if ((d10v_debug
& DEBUG_TRACE
) == 0)
175 switch (State
.ins_type
)
178 case INS_UNKNOWN
: type
= " ?"; break;
179 case INS_LEFT
: type
= " L"; break;
180 case INS_RIGHT
: type
= " R"; break;
181 case INS_LEFT_PARALLEL
: type
= "*L"; break;
182 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
183 case INS_LEFT_COND_TEST
: type
= "?L"; break;
184 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
185 case INS_LEFT_COND_EXE
: type
= "&L"; break;
186 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
187 case INS_LONG
: type
= " B"; break;
190 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
191 (*d10v_callback
->printf_filtered
) (d10v_callback
,
193 SIZE_PC
, (unsigned)PC
,
195 SIZE_INSTRUCTION
, name
);
200 byte_pc
= decode_pc ();
201 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
203 filename
= (const char *)0;
204 functionname
= (const char *)0;
206 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
207 &filename
, &functionname
, &linenumber
))
212 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
217 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
218 p
+= SIZE_LINE_NUMBER
+2;
223 sprintf (p
, "%s ", functionname
);
228 char *q
= strrchr (filename
, '/');
229 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
238 (*d10v_callback
->printf_filtered
) (d10v_callback
,
239 "0x%.*x %s: %-*.*s %-*s ",
240 SIZE_PC
, (unsigned)PC
,
242 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
243 SIZE_INSTRUCTION
, name
);
251 for (i
= 0; i
< 3; i
++)
266 sprintf (p
, "%sr%d", comma
, OP
[i
]);
274 sprintf (p
, "%scr%d", comma
, OP
[i
]);
280 case OP_ACCUM_OUTPUT
:
281 case OP_ACCUM_REVERSE
:
282 sprintf (p
, "%sa%d", comma
, OP
[i
]);
288 sprintf (p
, "%s%d", comma
, OP
[i
]);
294 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
300 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
306 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
312 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
318 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
324 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
330 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
336 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
344 sprintf (p
, "%sf0", comma
);
347 sprintf (p
, "%sf1", comma
);
350 sprintf (p
, "%sc", comma
);
358 if ((d10v_debug
& DEBUG_VALUES
) == 0)
362 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
367 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
370 for (i
= 0; i
< 3; i
++)
376 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
382 case OP_ACCUM_OUTPUT
:
384 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
392 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
393 (uint16
)State
.regs
[OP
[i
]]);
397 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
398 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
403 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
404 (uint16
)State
.cregs
[OP
[i
]]);
408 case OP_ACCUM_REVERSE
:
409 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
410 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
411 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
415 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
420 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
421 (uint16
)SEXT4(OP
[i
]));
425 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
426 (uint16
)SEXT8(OP
[i
]));
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
431 (uint16
)SEXT3(OP
[i
]));
436 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
440 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
452 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
453 (uint16
)State
.regs
[OP
[++i
]]);
457 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
458 (uint16
)State
.regs
[0]);
462 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
463 (uint16
)State
.regs
[1]);
467 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
468 (uint16
)State
.regs
[2]);
472 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
473 (uint16
)State
.regs
[0]);
474 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
475 (uint16
)State
.regs
[1]);
482 (*d10v_callback
->flush_stdout
) (d10v_callback
);
486 trace_output_func (result
)
487 enum op_types result
;
489 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
501 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
502 (uint16
)State
.regs
[OP
[0]],
503 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
508 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
509 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
510 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
515 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
516 (uint16
)State
.cregs
[OP
[0]],
517 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
521 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
522 (uint16
)State
.cregs
[OP
[1]],
523 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
527 case OP_ACCUM_OUTPUT
:
528 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
529 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
530 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
531 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
534 case OP_ACCUM_REVERSE
:
535 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
536 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
537 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
538 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
543 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
544 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
548 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
549 (uint16
)State
.regs
[0],
550 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
554 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
555 (uint16
)State
.regs
[0], (uint16
)State
.regs
[1],
556 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
561 (*d10v_callback
->flush_stdout
) (d10v_callback
);
565 #define trace_input(NAME, IN1, IN2, IN3)
566 #define trace_output(RESULT)
573 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
575 if ((int16
)(State
.regs
[OP
[0]]) < 0)
577 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
582 trace_output (OP_REG
);
591 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
593 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
595 if (State
.a
[OP
[0]] < 0 )
597 tmp
= -State
.a
[OP
[0]];
601 State
.a
[OP
[0]] = MAX32
;
602 else if (tmp
< MIN32
)
603 State
.a
[OP
[0]] = MIN32
;
605 State
.a
[OP
[0]] = tmp
& MASK40
;
608 State
.a
[OP
[0]] = tmp
& MASK40
;
613 trace_output (OP_ACCUM
);
620 uint16 tmp
= State
.regs
[OP
[0]];
621 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
622 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
623 if ( tmp
> State
.regs
[OP
[0]])
627 trace_output (OP_REG
);
635 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
637 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
641 State
.a
[OP
[0]] = MAX32
;
642 else if ( tmp
< MIN32
)
643 State
.a
[OP
[0]] = MIN32
;
645 State
.a
[OP
[0]] = tmp
& MASK40
;
648 State
.a
[OP
[0]] = tmp
& MASK40
;
649 trace_output (OP_ACCUM
);
657 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
659 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
663 State
.a
[OP
[0]] = MAX32
;
664 else if ( tmp
< MIN32
)
665 State
.a
[OP
[0]] = MIN32
;
667 State
.a
[OP
[0]] = tmp
& MASK40
;
670 State
.a
[OP
[0]] = tmp
& MASK40
;
671 trace_output (OP_ACCUM
);
679 uint32 a
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
680 uint32 b
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
682 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
685 State
.regs
[OP
[0]] = tmp
>> 16;
686 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
687 trace_output (OP_DREG
);
694 uint16 tmp
= State
.regs
[OP
[1]];
695 State
.regs
[OP
[0]] = tmp
+ OP
[2];
697 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
698 State
.C
= (State
.regs
[OP
[0]] < tmp
);
699 trace_output (OP_REG
);
707 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
709 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
710 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
711 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
712 trace_output (OP_DREG
);
720 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
722 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
723 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
724 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
725 trace_output (OP_DREG
);
735 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
736 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
739 State
.regs
[OP
[0]] = 0x7fff;
740 State
.regs
[OP
[0]+1] = 0xffff;
743 else if (tmp
< MIN32
)
745 State
.regs
[OP
[0]] = 0x8000;
746 State
.regs
[OP
[0]+1] = 0;
751 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
752 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
755 trace_output (OP_DREG
);
765 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
766 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
769 State
.regs
[OP
[0]] = 0x7fff;
770 State
.regs
[OP
[0]+1] = 0xffff;
773 else if (tmp
< MIN32
)
775 State
.regs
[OP
[0]] = 0x8000;
776 State
.regs
[OP
[0]+1] = 0;
781 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
782 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
785 trace_output (OP_DREG
);
792 uint tmp
= State
.regs
[OP
[0]];
796 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
797 State
.regs
[OP
[0]] += OP
[1];
798 State
.C
= (State
.regs
[OP
[0]] < tmp
);
799 trace_output (OP_REG
);
806 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
807 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
808 trace_output (OP_REG
);
815 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
816 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
817 trace_output (OP_REG
);
824 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
825 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
826 trace_output (OP_REG
);
833 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
834 State
.regs
[13] = PC
+1;
835 JMP( PC
+ SEXT8 (OP
[0]));
836 trace_output (OP_VOID
);
843 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
844 State
.regs
[13] = PC
+1;
846 trace_output (OP_VOID
);
853 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
854 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
855 trace_output (OP_REG
);
862 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
863 JMP (PC
+ SEXT8 (OP
[0]));
864 trace_output (OP_VOID
);
871 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
873 trace_output (OP_VOID
);
880 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
882 JMP (PC
+ SEXT8 (OP
[0]));
883 trace_output (OP_FLAG
);
890 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
893 trace_output (OP_FLAG
);
900 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
902 JMP (PC
+ SEXT8 (OP
[0]));
903 trace_output (OP_FLAG
);
910 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
913 trace_output (OP_FLAG
);
920 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
921 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
922 trace_output (OP_REG
);
929 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
931 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
932 trace_output (OP_FLAG
);
939 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
941 trace_output (OP_ACCUM
);
948 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
950 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
951 trace_output (OP_FLAG
);
958 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
960 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
961 trace_output (OP_FLAG
);
968 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
970 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
971 trace_output (OP_FLAG
);
978 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
980 State
.F0
= ((State
.a
[OP
[0]] & MASK40
) == (State
.a
[OP
[1]] & MASK40
)) ? 1 : 0;
981 trace_output (OP_FLAG
);
988 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
990 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
991 trace_output (OP_FLAG
);
998 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1000 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
1001 trace_output (OP_FLAG
);
1008 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1009 State
.F1
= State
.F0
;
1010 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
1011 trace_output (OP_FLAG
);
1018 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1019 State
.F1
= State
.F0
;
1020 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
1021 trace_output (OP_FLAG
);
1028 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1029 State
.F1
= State
.F0
;
1030 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
1031 trace_output (OP_FLAG
);
1038 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1039 State
.F1
= State
.F0
;
1040 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
1041 trace_output (OP_FLAG
);
1050 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1058 else if (OP
[1] == 1)
1064 trace_output (OP_FLAG
);
1071 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1072 State
.exception
= SIGTRAP
;
1079 uint16 foo
, tmp
, tmpf
;
1081 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1082 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1083 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1084 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1085 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1086 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1087 trace_output (OP_DREG
);
1094 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1095 State
.exe
= (State
.F0
== 0);
1096 trace_output (OP_FLAG
);
1103 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1104 State
.exe
= (State
.F0
!= 0);
1105 trace_output (OP_FLAG
);
1112 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1113 State
.exe
= (State
.F1
== 0);
1114 trace_output (OP_FLAG
);
1121 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1122 State
.exe
= (State
.F1
!= 0);
1123 trace_output (OP_FLAG
);
1130 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1131 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1132 trace_output (OP_FLAG
);
1139 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1140 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1141 trace_output (OP_FLAG
);
1148 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1149 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1150 trace_output (OP_FLAG
);
1157 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1158 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1159 trace_output (OP_FLAG
);
1169 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1170 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1171 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1173 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1180 State
.regs
[OP
[0]] = i
-1;
1181 trace_output (OP_REG
);
1186 State
.regs
[OP
[0]] = 16;
1187 trace_output (OP_REG
);
1197 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1198 tmp
= SEXT40(State
.a
[OP
[1]]);
1200 tmp
= ~tmp
& MASK40
;
1202 foo
= 0x4000000000LL
;
1207 State
.regs
[OP
[0]] = i
-9;
1208 trace_output (OP_REG
);
1213 State
.regs
[OP
[0]] = 16;
1214 trace_output (OP_REG
);
1221 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1222 State
.regs
[13] = PC
+1;
1223 JMP (State
.regs
[OP
[0]]);
1224 trace_output (OP_VOID
);
1231 trace_input ("jmp", OP_REG
,
1232 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1233 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1235 JMP (State
.regs
[OP
[0]]);
1236 trace_output (OP_VOID
);
1243 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1244 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1245 trace_output (OP_REG
);
1252 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1253 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1254 INC_ADDR(State
.regs
[OP
[1]],-2);
1255 trace_output (OP_REG
);
1262 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1263 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1264 INC_ADDR(State
.regs
[OP
[1]],2);
1265 trace_output (OP_REG
);
1272 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1273 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1274 trace_output (OP_REG
);
1281 uint16 addr
= State
.regs
[OP
[2]];
1282 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1283 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1284 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1285 trace_output (OP_DREG
);
1292 uint16 addr
= State
.regs
[OP
[1]];
1293 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1294 State
.regs
[OP
[0]] = RW (addr
);
1295 State
.regs
[OP
[0]+1] = RW (addr
+2);
1296 INC_ADDR(State
.regs
[OP
[1]],-4);
1297 trace_output (OP_DREG
);
1304 uint16 addr
= State
.regs
[OP
[1]];
1305 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1306 State
.regs
[OP
[0]] = RW (addr
);
1307 State
.regs
[OP
[0]+1] = RW (addr
+2);
1308 INC_ADDR(State
.regs
[OP
[1]],4);
1309 trace_output (OP_DREG
);
1316 uint16 addr
= State
.regs
[OP
[1]];
1317 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1318 State
.regs
[OP
[0]] = RW (addr
);
1319 State
.regs
[OP
[0]+1] = RW (addr
+2);
1320 trace_output (OP_DREG
);
1327 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1328 State
.regs
[OP
[0]] = SEXT8 (RB (OP
[1] + State
.regs
[OP
[2]]));
1329 trace_output (OP_REG
);
1336 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1337 State
.regs
[OP
[0]] = SEXT8 (RB (State
.regs
[OP
[1]]));
1338 trace_output (OP_REG
);
1345 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1346 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1347 trace_output (OP_REG
);
1354 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1355 State
.regs
[OP
[0]] = OP
[1];
1356 trace_output (OP_REG
);
1363 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1364 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1365 trace_output (OP_REG
);
1372 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1373 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1374 trace_output (OP_REG
);
1383 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1384 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1387 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1389 if (State
.ST
&& tmp
> MAX32
)
1392 tmp
+= SEXT40(State
.a
[OP
[0]]);
1396 State
.a
[OP
[0]] = MAX32
;
1397 else if (tmp
< MIN32
)
1398 State
.a
[OP
[0]] = MIN32
;
1400 State
.a
[OP
[0]] = tmp
& MASK40
;
1403 State
.a
[OP
[0]] = tmp
& MASK40
;
1404 trace_output (OP_ACCUM
);
1413 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1414 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1416 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1418 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1419 trace_output (OP_ACCUM
);
1430 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1431 src1
= (uint16
) State
.regs
[OP
[1]];
1432 src2
= (uint16
) State
.regs
[OP
[2]];
1436 State
.a
[OP
[0]] = (State
.a
[OP
[0]] + tmp
) & MASK40
;
1437 trace_output (OP_ACCUM
);
1444 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1445 State
.F1
= State
.F0
;
1446 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1448 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1453 trace_output (OP_REG
);
1462 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1463 State
.F1
= State
.F0
;
1464 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1465 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1467 State
.a
[OP
[0]] = tmp
& MASK40
;
1472 trace_output (OP_ACCUM
);
1479 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1480 State
.F1
= State
.F0
;
1481 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1483 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1488 trace_output (OP_ACCUM
);
1496 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1497 State
.F1
= State
.F0
;
1498 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1500 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1505 trace_output (OP_REG
);
1514 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1515 State
.F1
= State
.F0
;
1516 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1517 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1519 State
.a
[OP
[0]] = tmp
& MASK40
;
1524 trace_output (OP_ACCUM
);
1531 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1532 State
.F1
= State
.F0
;
1533 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1535 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1540 trace_output (OP_ACCUM
);
1549 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1550 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1553 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1555 if (State
.ST
&& tmp
> MAX32
)
1558 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1562 State
.a
[OP
[0]] = MAX32
;
1563 else if (tmp
< MIN32
)
1564 State
.a
[OP
[0]] = MIN32
;
1566 State
.a
[OP
[0]] = tmp
& MASK40
;
1569 State
.a
[OP
[0]] = tmp
& MASK40
;
1570 trace_output (OP_ACCUM
);
1579 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1580 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1582 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1584 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1585 trace_output (OP_ACCUM
);
1596 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1597 src1
= (uint16
) State
.regs
[OP
[1]];
1598 src2
= (uint16
) State
.regs
[OP
[2]];
1603 State
.a
[OP
[0]] = (State
.a
[OP
[0]] - tmp
) & MASK40
;
1604 trace_output (OP_ACCUM
);
1611 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1612 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1613 trace_output (OP_REG
);
1622 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1623 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1626 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1628 if (State
.ST
&& tmp
> MAX32
)
1629 State
.a
[OP
[0]] = MAX32
;
1631 State
.a
[OP
[0]] = tmp
& MASK40
;
1632 trace_output (OP_ACCUM
);
1641 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1642 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1647 State
.a
[OP
[0]] = tmp
& MASK40
;
1648 trace_output (OP_ACCUM
);
1659 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1660 src1
= (uint16
) State
.regs
[OP
[1]];
1661 src2
= (uint16
) State
.regs
[OP
[2]];
1666 State
.a
[OP
[0]] = tmp
& MASK40
;
1667 trace_output (OP_ACCUM
);
1674 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1675 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1676 trace_output (OP_REG
);
1683 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1684 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1685 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1686 trace_output (OP_DREG
);
1693 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1694 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1695 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1696 trace_output (OP_DREG
);
1703 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1704 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1705 trace_output (OP_ACCUM_REVERSE
);
1712 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1713 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1714 trace_output (OP_ACCUM
);
1721 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1722 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1723 trace_output (OP_REG
);
1730 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1732 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1733 trace_output (OP_REG
);
1740 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1742 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1743 trace_output (OP_REG
);
1750 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1751 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1752 trace_output (OP_ACCUM
);
1759 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1760 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1761 trace_output (OP_REG
);
1768 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1769 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1770 trace_output (OP_REG
);
1777 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1778 State
.regs
[OP
[0]] = move_from_cr (OP
[1]);
1779 trace_output (OP_REG
);
1786 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1787 State
.a
[OP
[1]] &= MASK32
;
1788 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1789 trace_output (OP_ACCUM_REVERSE
);
1798 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1799 tmp
= State
.a
[OP
[1]] & 0xffff;
1800 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1801 trace_output (OP_ACCUM_REVERSE
);
1808 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1809 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1810 trace_output (OP_ACCUM_REVERSE
);
1817 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1818 move_to_cr (OP
[1], State
.regs
[OP
[0]]);
1819 trace_output (OP_CR_REVERSE
);
1826 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1827 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1828 trace_output (OP_REG
);
1835 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1836 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1837 trace_output (OP_REG
);
1846 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1847 tmp
= -SEXT40(State
.a
[OP
[0]]);
1851 State
.a
[OP
[0]] = MAX32
;
1852 else if (tmp
< MIN32
)
1853 State
.a
[OP
[0]] = MIN32
;
1855 State
.a
[OP
[0]] = tmp
& MASK40
;
1858 State
.a
[OP
[0]] = tmp
& MASK40
;
1859 trace_output (OP_ACCUM
);
1867 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1869 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
1870 switch (State
.ins_type
)
1873 ins_type_counters
[ (int)INS_UNKNOWN
]++;
1876 case INS_LEFT_PARALLEL
:
1877 /* Don't count a parallel op that includes a NOP as a true parallel op */
1878 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
1879 ins_type_counters
[ (int)INS_RIGHT
]++;
1880 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1884 case INS_LEFT_COND_EXE
:
1885 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1888 case INS_RIGHT_PARALLEL
:
1889 /* Don't count a parallel op that includes a NOP as a true parallel op */
1890 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
1891 ins_type_counters
[ (int)INS_LEFT
]++;
1892 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1896 case INS_RIGHT_COND_EXE
:
1897 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1901 trace_output (OP_VOID
);
1908 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1909 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1910 trace_output (OP_REG
);
1917 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1918 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1919 trace_output (OP_REG
);
1926 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1927 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1928 trace_output (OP_REG
);
1936 int shift
= SEXT3 (OP
[2]);
1938 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1941 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1942 "ERROR at PC 0x%x: instruction only valid for A0\n",
1944 State
.exception
= SIGILL
;
1947 State
.F1
= State
.F0
;
1948 tmp
= SEXT56 ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff));
1954 tmp
>>= 16; /* look at bits 0:43 */
1955 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
1957 State
.regs
[OP
[0]] = 0x7fff;
1958 State
.regs
[OP
[0]+1] = 0xffff;
1961 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
1963 State
.regs
[OP
[0]] = 0x8000;
1964 State
.regs
[OP
[0]+1] = 0;
1969 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1970 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1973 trace_output (OP_DREG
);
1981 int shift
= SEXT3 (OP
[2]);
1983 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1984 State
.F1
= State
.F0
;
1986 tmp
= SEXT40 (State
.a
[OP
[1]]) << shift
;
1988 tmp
= SEXT40 (State
.a
[OP
[1]]) >> -shift
;
1991 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
1993 State
.regs
[OP
[0]] = 0x7fff;
1996 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
1998 State
.regs
[OP
[0]] = 0x8000;
2003 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2006 trace_output (OP_REG
);
2013 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2016 RPT_C
= State
.regs
[OP
[0]];
2020 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
2021 State
.exception
= SIGILL
;
2025 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2026 State
.exception
= SIGILL
;
2028 trace_output (OP_VOID
);
2035 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2042 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2043 State
.exception
= SIGILL
;
2047 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2048 State
.exception
= SIGILL
;
2050 trace_output (OP_VOID
);
2057 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
2058 State
.exception
= SIGILL
;
2065 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2066 move_to_cr (PSW_CR
, BPSW
);
2068 trace_output (OP_VOID
);
2077 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2078 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2082 State
.a
[OP
[0]] = MAX32
;
2083 else if (tmp
< MIN32
)
2084 State
.a
[OP
[0]] = MIN32
;
2086 State
.a
[OP
[0]] = tmp
& MASK40
;
2089 State
.a
[OP
[0]] = tmp
& MASK40
;
2090 trace_output (OP_ACCUM
);
2097 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2098 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2099 trace_output (OP_REG
);
2106 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2107 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2108 trace_output (OP_REG
);
2115 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2117 trace_output (OP_VOID
);
2124 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2125 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2126 trace_output (OP_REG
);
2134 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2135 if ((State
.regs
[OP
[1]] & 31) <= 16)
2136 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2139 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2140 State
.exception
= SIGILL
;
2147 State
.a
[OP
[0]] = MAX32
;
2148 else if (tmp
< 0xffffff80000000LL
)
2149 State
.a
[OP
[0]] = MIN32
;
2151 State
.a
[OP
[0]] = tmp
& MASK40
;
2154 State
.a
[OP
[0]] = tmp
& MASK40
;
2155 trace_output (OP_ACCUM
);
2162 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2163 State
.regs
[OP
[0]] <<= OP
[1];
2164 trace_output (OP_REG
);
2176 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2177 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2182 State
.a
[OP
[0]] = MAX32
;
2183 else if (tmp
< 0xffffff80000000LL
)
2184 State
.a
[OP
[0]] = MIN32
;
2186 State
.a
[OP
[0]] = tmp
& MASK40
;
2189 State
.a
[OP
[0]] = tmp
& MASK40
;
2190 trace_output (OP_ACCUM
);
2197 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2198 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2199 trace_output (OP_REG
);
2206 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2207 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2208 trace_output (OP_REG
);
2215 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2216 if ((State
.regs
[OP
[1]] & 31) <= 16)
2217 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> (State
.regs
[OP
[1]] & 31)) & MASK40
;
2220 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2221 State
.exception
= SIGILL
;
2225 trace_output (OP_ACCUM
);
2232 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2233 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2234 trace_output (OP_REG
);
2244 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2245 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> OP
[1]) & MASK40
;
2246 trace_output (OP_ACCUM
);
2253 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2254 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2255 trace_output (OP_REG
);
2262 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2263 if ((State
.regs
[OP
[1]] & 31) <= 16)
2264 State
.a
[OP
[0]] = (uint64
)((State
.a
[OP
[0]] & MASK40
) >> (State
.regs
[OP
[1]] & 31));
2267 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2268 State
.exception
= SIGILL
;
2272 trace_output (OP_ACCUM
);
2279 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2280 State
.regs
[OP
[0]] >>= OP
[1];
2281 trace_output (OP_REG
);
2291 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2292 State
.a
[OP
[0]] = (uint64
)(State
.a
[OP
[0]] & MASK40
) >> OP
[1];
2293 trace_output (OP_ACCUM
);
2302 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2303 tmp
= State
.F0
<< 15;
2304 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2305 trace_output (OP_REG
);
2312 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2313 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2314 trace_output (OP_VOID
);
2321 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2322 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2323 trace_output (OP_VOID
);
2330 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2333 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2334 State
.exception
= SIGILL
;
2337 State
.regs
[OP
[1]] -= 2;
2338 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2339 trace_output (OP_VOID
);
2346 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2347 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2348 INC_ADDR (State
.regs
[OP
[1]],2);
2349 trace_output (OP_VOID
);
2356 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2359 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2360 State
.exception
= SIGILL
;
2363 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2364 INC_ADDR (State
.regs
[OP
[1]],-2);
2365 trace_output (OP_VOID
);
2372 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2373 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2374 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2375 trace_output (OP_VOID
);
2382 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2383 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2384 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2385 trace_output (OP_VOID
);
2392 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2395 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2396 State
.exception
= SIGILL
;
2399 State
.regs
[OP
[1]] -= 4;
2400 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2401 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2402 trace_output (OP_VOID
);
2409 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2410 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2411 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2412 INC_ADDR (State
.regs
[OP
[1]],4);
2413 trace_output (OP_VOID
);
2420 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2423 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2424 State
.exception
= SIGILL
;
2427 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2428 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2429 INC_ADDR (State
.regs
[OP
[1]],-4);
2430 trace_output (OP_VOID
);
2437 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2438 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2439 trace_output (OP_VOID
);
2446 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2447 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2448 trace_output (OP_VOID
);
2455 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2456 State
.exception
= SIG_D10V_STOP
;
2457 trace_output (OP_VOID
);
2466 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2467 /* see ../common/sim-alu.h for a more extensive discussion on how to
2468 compute the carry/overflow bits. */
2469 tmp
= State
.regs
[OP
[0]] - State
.regs
[OP
[1]];
2470 State
.C
= ((uint16
) State
.regs
[OP
[0]] >= (uint16
) State
.regs
[OP
[1]]);
2471 State
.regs
[OP
[0]] = tmp
;
2472 trace_output (OP_REG
);
2481 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2482 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2486 State
.a
[OP
[0]] = MAX32
;
2487 else if ( tmp
< MIN32
)
2488 State
.a
[OP
[0]] = MIN32
;
2490 State
.a
[OP
[0]] = tmp
& MASK40
;
2493 State
.a
[OP
[0]] = tmp
& MASK40
;
2495 trace_output (OP_ACCUM
);
2505 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2506 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2510 State
.a
[OP
[0]] = MAX32
;
2511 else if ( tmp
< MIN32
)
2512 State
.a
[OP
[0]] = MIN32
;
2514 State
.a
[OP
[0]] = tmp
& MASK40
;
2517 State
.a
[OP
[0]] = tmp
& MASK40
;
2519 trace_output (OP_ACCUM
);
2528 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2529 a
= (uint32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2530 b
= (uint32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2531 /* see ../common/sim-alu.h for a more extensive discussion on how to
2532 compute the carry/overflow bits */
2535 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2536 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2537 trace_output (OP_DREG
);
2546 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2547 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2548 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2549 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2550 trace_output (OP_DREG
);
2559 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2560 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2561 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2562 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2563 trace_output (OP_DREG
);
2572 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2573 State
.F1
= State
.F0
;
2574 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2577 State
.regs
[OP
[0]] = 0x7fff;
2578 State
.regs
[OP
[0]+1] = 0xffff;
2581 else if (tmp
< MIN32
)
2583 State
.regs
[OP
[0]] = 0x8000;
2584 State
.regs
[OP
[0]+1] = 0;
2589 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2590 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2593 trace_output (OP_DREG
);
2602 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2603 State
.F1
= State
.F0
;
2604 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2607 State
.regs
[OP
[0]] = 0x7fff;
2608 State
.regs
[OP
[0]+1] = 0xffff;
2611 else if (tmp
< MIN32
)
2613 State
.regs
[OP
[0]] = 0x8000;
2614 State
.regs
[OP
[0]+1] = 0;
2619 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2620 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2623 trace_output (OP_DREG
);
2634 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2635 /* see ../common/sim-alu.h for a more extensive discussion on how to
2636 compute the carry/overflow bits. */
2637 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2638 tmp
= ((unsigned)(unsigned16
) State
.regs
[OP
[0]]
2639 + (unsigned)(unsigned16
) ( - OP
[1]));
2640 State
.C
= (tmp
>= (1 << 16));
2641 State
.regs
[OP
[0]] = tmp
;
2642 trace_output (OP_REG
);
2649 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2650 trace_output (OP_VOID
);
2655 #if (DEBUG & DEBUG_TRAP) == 0
2657 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
2659 move_to_cr (BPSW_CR
, PSW
);
2660 move_to_cr (PSW_CR
, PSW
& PSW_SM_BIT
);
2664 #else /* if debugging use trap to print registers */
2667 static int first_time
= 1;
2672 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2673 for (i
= 0; i
< 16; i
++)
2674 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2675 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2678 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2680 for (i
= 0; i
< 16; i
++)
2681 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2683 for (i
= 0; i
< 2; i
++)
2684 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2685 ((int)(State
.a
[i
] >> 32) & 0xff),
2686 ((unsigned long)State
.a
[i
]) & 0xffffffff);
2688 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2689 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2690 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2694 case 15: /* new system call trap */
2695 /* Trap 15 is used for simulating low-level I/O */
2699 /* Registers passed to trap 0 */
2701 #define FUNC State.regs[4] /* function number */
2702 #define PARM1 State.regs[0] /* optional parm 1 */
2703 #define PARM2 State.regs[1] /* optional parm 2 */
2704 #define PARM3 State.regs[2] /* optional parm 3 */
2705 #define PARM4 State.regs[3] /* optional parm 3 */
2707 /* Registers set by trap 0 */
2709 #define RETVAL State.regs[0] /* return value */
2710 #define RETVAL_HIGH State.regs[0] /* return value */
2711 #define RETVAL_LOW State.regs[1] /* return value */
2712 #define RETERR State.regs[4] /* return error code */
2714 /* Turn a pointer in a register into a pointer into real memory. */
2716 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2720 #if !defined(__GO32__) && !defined(_WIN32)
2723 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2724 trace_output (OP_R0
);
2728 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2730 trace_output (OP_R0
);
2734 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2735 if (PARM1
== getpid ())
2737 trace_output (OP_VOID
);
2738 State
.exception
= PARM2
;
2746 case 1: os_sig
= SIGHUP
; break;
2749 case 2: os_sig
= SIGINT
; break;
2752 case 3: os_sig
= SIGQUIT
; break;
2755 case 4: os_sig
= SIGILL
; break;
2758 case 5: os_sig
= SIGTRAP
; break;
2761 case 6: os_sig
= SIGABRT
; break;
2762 #elif defined(SIGIOT)
2763 case 6: os_sig
= SIGIOT
; break;
2766 case 7: os_sig
= SIGEMT
; break;
2769 case 8: os_sig
= SIGFPE
; break;
2772 case 9: os_sig
= SIGKILL
; break;
2775 case 10: os_sig
= SIGBUS
; break;
2778 case 11: os_sig
= SIGSEGV
; break;
2781 case 12: os_sig
= SIGSYS
; break;
2784 case 13: os_sig
= SIGPIPE
; break;
2787 case 14: os_sig
= SIGALRM
; break;
2790 case 15: os_sig
= SIGTERM
; break;
2793 case 16: os_sig
= SIGURG
; break;
2796 case 17: os_sig
= SIGSTOP
; break;
2799 case 18: os_sig
= SIGTSTP
; break;
2802 case 19: os_sig
= SIGCONT
; break;
2805 case 20: os_sig
= SIGCHLD
; break;
2806 #elif defined(SIGCLD)
2807 case 20: os_sig
= SIGCLD
; break;
2810 case 21: os_sig
= SIGTTIN
; break;
2813 case 22: os_sig
= SIGTTOU
; break;
2816 case 23: os_sig
= SIGIO
; break;
2817 #elif defined (SIGPOLL)
2818 case 23: os_sig
= SIGPOLL
; break;
2821 case 24: os_sig
= SIGXCPU
; break;
2824 case 25: os_sig
= SIGXFSZ
; break;
2827 case 26: os_sig
= SIGVTALRM
; break;
2830 case 27: os_sig
= SIGPROF
; break;
2833 case 28: os_sig
= SIGWINCH
; break;
2836 case 29: os_sig
= SIGLOST
; break;
2839 case 30: os_sig
= SIGUSR1
; break;
2842 case 31: os_sig
= SIGUSR2
; break;
2848 trace_output (OP_VOID
);
2849 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2850 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2851 State
.exception
= SIGILL
;
2855 RETVAL
= kill (PARM1
, PARM2
);
2856 trace_output (OP_R0
);
2862 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2863 (char **)MEMPTR (PARM3
));
2864 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
2865 trace_output (OP_R0
);
2870 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2871 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
2872 trace_output (OP_R0
);
2882 RETVAL
= pipe (host_fd
);
2883 SW (buf
, host_fd
[0]);
2884 buf
+= sizeof(uint16
);
2885 SW (buf
, host_fd
[1]);
2886 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
2887 trace_output (OP_R0
);
2896 RETVAL
= wait (&status
);
2899 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
2900 trace_output (OP_R0
);
2906 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2908 trace_output (OP_R0
);
2912 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2913 trace_output (OP_VOID
);
2914 State
.exception
= PARM2
;
2919 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2921 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
2922 trace_output (OP_R0
);
2927 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2928 MEMPTR (PARM2
), PARM3
);
2930 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2931 MEMPTR (PARM2
), PARM3
);
2932 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
2933 trace_output (OP_R0
);
2938 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2939 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2941 RETVAL_HIGH
= ret
>> 16;
2942 RETVAL_LOW
= ret
& 0xffff;
2944 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
2945 trace_output (OP_R0R1
);
2949 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2950 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
2951 trace_output (OP_R0
);
2955 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2956 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
2957 trace_output (OP_R0
);
2958 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
2959 trace_output (OP_R0
);
2963 State
.exception
= SIG_D10V_EXIT
;
2964 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
2965 trace_output (OP_VOID
);
2969 /* stat system call */
2971 struct stat host_stat
;
2974 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2978 /* The hard-coded offsets and sizes were determined by using
2979 * the D10V compiler on a test program that used struct stat.
2981 SW (buf
, host_stat
.st_dev
);
2982 SW (buf
+2, host_stat
.st_ino
);
2983 SW (buf
+4, host_stat
.st_mode
);
2984 SW (buf
+6, host_stat
.st_nlink
);
2985 SW (buf
+8, host_stat
.st_uid
);
2986 SW (buf
+10, host_stat
.st_gid
);
2987 SW (buf
+12, host_stat
.st_rdev
);
2988 SLW (buf
+16, host_stat
.st_size
);
2989 SLW (buf
+20, host_stat
.st_atime
);
2990 SLW (buf
+28, host_stat
.st_mtime
);
2991 SLW (buf
+36, host_stat
.st_ctime
);
2993 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
2994 trace_output (OP_R0
);
2998 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2999 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3000 trace_output (OP_R0
);
3004 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
3005 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3006 trace_output (OP_R0
);
3011 /* Cast the second argument to void *, to avoid type mismatch
3012 if a prototype is present. */
3013 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
3014 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3015 trace_output (OP_R0
);
3022 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
3023 RETVAL_HIGH
= ret
>> 16;
3024 RETVAL_LOW
= ret
& 0xffff;
3026 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3027 trace_output (OP_R0R1
);
3032 d10v_callback
->error (d10v_callback
, "Unknown syscall %d", FUNC
);
3034 RETERR
= (RETVAL
== (uint16
) -1) ? d10v_callback
->get_errno(d10v_callback
) : 0;
3044 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3045 State
.F1
= State
.F0
;
3046 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
3047 trace_output (OP_FLAG
);
3054 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3055 State
.F1
= State
.F0
;
3056 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
3057 trace_output (OP_FLAG
);
3064 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3066 trace_output (OP_VOID
);
3073 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3074 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3075 trace_output (OP_REG
);
3082 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3083 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3084 trace_output (OP_REG
);
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