sim/d10v/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #include <errno.h>
   5 #include <sys/types.h>
   6 #include <sys/stat.h>
   7 #ifdef HAVE_UNISTD_H
   8 #include <unistd.h>
   9 #endif
  10
  11 #include "d10v_sim.h"
  12 #include "simops.h"
  13 #include "targ-vals.h"
  14
  15 extern char *strrchr ();
  16
  17 enum op_types {
  18   OP_VOID,
  19   OP_REG,
  20   OP_REG_OUTPUT,
  21   OP_DREG,
  22   OP_DREG_OUTPUT,
  23   OP_ACCUM,
  24   OP_ACCUM_OUTPUT,
  25   OP_ACCUM_REVERSE,
  26   OP_CR,
  27   OP_CR_OUTPUT,
  28   OP_CR_REVERSE,
  29   OP_FLAG,
  30   OP_FLAG_OUTPUT,
  31   OP_CONSTANT16,
  32   OP_CONSTANT8,
  33   OP_CONSTANT3,
  34   OP_CONSTANT4,
  35   OP_MEMREF,
  36   OP_MEMREF2,
  37   OP_MEMREF3,
  38   OP_POSTDEC,
  39   OP_POSTINC,
  40   OP_PREDEC,
  41   OP_R0,
  42   OP_R1,
  43   OP_R2,
  44 };
  45
  46
  47 enum {
  48   PSW_MASK = (PSW_SM_BIT
  49               | PSW_EA_BIT
  50               | PSW_DB_BIT
  51               | PSW_IE_BIT
  52               | PSW_RP_BIT
  53               | PSW_MD_BIT
  54               | PSW_FX_BIT
  55               | PSW_ST_BIT
  56               | PSW_F0_BIT
  57               | PSW_F1_BIT
  58               | PSW_C_BIT),
  59   /* The following bits in the PSW _can't_ be set by instructions such
  60      as mvtc. */
  61   PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
  62 };
  63
  64 reg_t
  65 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
  66 {
  67   /* A MASK bit is set when the corresponding bit in the CR should
  68      be left alone */
  69   /* This assumes that (VAL & MASK) == 0 */
  70   switch (cr)
  71     {
  72     case PSW_CR:
  73       if (psw_hw_p)
  74         val &= PSW_HW_MASK;
  75       else
  76         val &= PSW_MASK;
  77       if ((mask & PSW_SM_BIT) == 0)
  78         {
  79           int new_psw_sm = (val & PSW_SM_BIT) != 0;
  80           /* save old SP */
  81           SET_HELD_SP (PSW_SM, GPR (SP_IDX));
  82           if (PSW_SM != new_psw_sm)
  83             /* restore new SP */
  84             SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
  85         }
  86       if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
  87         {
  88           if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
  89             {
  90               (*d10v_callback->printf_filtered)
  91                 (d10v_callback,
  92                  "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
  93                  PC<<2);
  94               State.exception = SIGILL;
  95             }
  96         }
  97       /* keep an up-to-date psw around for tracing */
  98       State.trace.psw = (State.trace.psw & mask) | val;
  99       break;
 100     case BPSW_CR:
 101     case DPSW_CR:
 102       /* Just like PSW, mask things like DM out. */
 103       if (psw_hw_p)
 104         val &= PSW_HW_MASK;
 105       else
 106         val &= PSW_MASK;
 107       break;
 108     case MOD_S_CR:
 109     case MOD_E_CR:
 110       val &= ~1;
 111       break;
 112     default:
 113       break;
 114     }
 115   /* only issue an update if the register is being changed */
 116   if ((State.cregs[cr] & ~mask) != val)
 117     SLOT_PEND_MASK (State.cregs[cr], mask, val);
 118   return val;
 119 }
 120
 121 #ifdef DEBUG
 122 static void trace_input_func PARAMS ((char *name,
 123                                       enum op_types in1,
 124                                       enum op_types in2,
 125                                       enum op_types in3));
 126
 127 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
 128
 129 #ifndef SIZE_INSTRUCTION
 130 #define SIZE_INSTRUCTION 8
 131 #endif
 132
 133 #ifndef SIZE_OPERANDS
 134 #define SIZE_OPERANDS 18
 135 #endif
 136
 137 #ifndef SIZE_VALUES
 138 #define SIZE_VALUES 13
 139 #endif
 140
 141 #ifndef SIZE_LOCATION
 142 #define SIZE_LOCATION 20
 143 #endif
 144
 145 #ifndef SIZE_PC
 146 #define SIZE_PC 6
 147 #endif
 148
 149 #ifndef SIZE_LINE_NUMBER
 150 #define SIZE_LINE_NUMBER 4
 151 #endif
 152
 153 static void
 154 trace_input_func (name, in1, in2, in3)
 155      char *name;
 156      enum op_types in1;
 157      enum op_types in2;
 158      enum op_types in3;
 159 {
 160   char *comma;
 161   enum op_types in[3];
 162   int i;
 163   char buf[1024];
 164   char *p;
 165   long tmp;
 166   char *type;
 167   const char *filename;
 168   const char *functionname;
 169   unsigned int linenumber;
 170   bfd_vma byte_pc;
 171
 172   if ((d10v_debug & DEBUG_TRACE) == 0)
 173     return;
 174
 175   switch (State.ins_type)
 176     {
 177     default:
 178     case INS_UNKNOWN:           type = " ?"; break;
 179     case INS_LEFT:              type = " L"; break;
 180     case INS_RIGHT:             type = " R"; break;
 181     case INS_LEFT_PARALLEL:     type = "*L"; break;
 182     case INS_RIGHT_PARALLEL:    type = "*R"; break;
 183     case INS_LEFT_COND_TEST:    type = "?L"; break;
 184     case INS_RIGHT_COND_TEST:   type = "?R"; break;
 185     case INS_LEFT_COND_EXE:     type = "&L"; break;
 186     case INS_RIGHT_COND_EXE:    type = "&R"; break;
 187     case INS_LONG:              type = " B"; break;
 188     }
 189
 190   if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
 191     (*d10v_callback->printf_filtered) (d10v_callback,
 192                                        "0x%.*x %s: %-*s ",
 193                                        SIZE_PC, (unsigned)PC,
 194                                        type,
 195                                        SIZE_INSTRUCTION, name);
 196
 197   else
 198     {
 199       buf[0] = '\0';
 200       byte_pc = decode_pc ();
 201       if (text && byte_pc >= text_start && byte_pc < text_end)
 202         {
 203           filename = (const char *)0;
 204           functionname = (const char *)0;
 205           linenumber = 0;
 206           if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
 207                                      &filename, &functionname, &linenumber))
 208             {
 209               p = buf;
 210               if (linenumber)
 211                 {
 212                   sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
 213                   p += strlen (p);
 214                 }
 215               else
 216                 {
 217                   sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
 218                   p += SIZE_LINE_NUMBER+2;
 219                 }
 220
 221               if (functionname)
 222                 {
 223                   sprintf (p, "%s ", functionname);
 224                   p += strlen (p);
 225                 }
 226               else if (filename)
 227                 {
 228                   char *q = strrchr (filename, '/');
 229                   sprintf (p, "%s ", (q) ? q+1 : filename);
 230                   p += strlen (p);
 231                 }
 232
 233               if (*p == ' ')
 234                 *p = '\0';
 235             }
 236         }
 237
 238       (*d10v_callback->printf_filtered) (d10v_callback,
 239                                          "0x%.*x %s: %-*.*s %-*s ",
 240                                          SIZE_PC, (unsigned)PC,
 241                                          type,
 242                                          SIZE_LOCATION, SIZE_LOCATION, buf,
 243                                          SIZE_INSTRUCTION, name);
 244     }
 245
 246   in[0] = in1;
 247   in[1] = in2;
 248   in[2] = in3;
 249   comma = "";
 250   p = buf;
 251   for (i = 0; i < 3; i++)
 252     {
 253       switch (in[i])
 254         {
 255         case OP_VOID:
 256         case OP_R0:
 257         case OP_R1:
 258         case OP_R2:
 259           break;
 260
 261         case OP_REG:
 262         case OP_REG_OUTPUT:
 263         case OP_DREG:
 264         case OP_DREG_OUTPUT:
 265           sprintf (p, "%sr%d", comma, OP[i]);
 266           p += strlen (p);
 267           comma = ",";
 268           break;
 269
 270         case OP_CR:
 271         case OP_CR_OUTPUT:
 272         case OP_CR_REVERSE:
 273           sprintf (p, "%scr%d", comma, OP[i]);
 274           p += strlen (p);
 275           comma = ",";
 276           break;
 277
 278         case OP_ACCUM:
 279         case OP_ACCUM_OUTPUT:
 280         case OP_ACCUM_REVERSE:
 281           sprintf (p, "%sa%d", comma, OP[i]);
 282           p += strlen (p);
 283           comma = ",";
 284           break;
 285
 286         case OP_CONSTANT16:
 287           sprintf (p, "%s%d", comma, OP[i]);
 288           p += strlen (p);
 289           comma = ",";
 290           break;
 291
 292         case OP_CONSTANT8:
 293           sprintf (p, "%s%d", comma, SEXT8(OP[i]));
 294           p += strlen (p);
 295           comma = ",";
 296           break;
 297
 298         case OP_CONSTANT4:
 299           sprintf (p, "%s%d", comma, SEXT4(OP[i]));
 300           p += strlen (p);
 301           comma = ",";
 302           break;
 303
 304         case OP_CONSTANT3:
 305           sprintf (p, "%s%d", comma, SEXT3(OP[i]));
 306           p += strlen (p);
 307           comma = ",";
 308           break;
 309
 310         case OP_MEMREF:
 311           sprintf (p, "%s@r%d", comma, OP[i]);
 312           p += strlen (p);
 313           comma = ",";
 314           break;
 315
 316         case OP_MEMREF2:
 317           sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
 318           p += strlen (p);
 319           comma = ",";
 320           break;
 321
 322         case OP_MEMREF3:
 323           sprintf (p, "%s@%d", comma, OP[i]);
 324           p += strlen (p);
 325           comma = ",";
 326           break;
 327
 328         case OP_POSTINC:
 329           sprintf (p, "%s@r%d+", comma, OP[i]);
 330           p += strlen (p);
 331           comma = ",";
 332           break;
 333
 334         case OP_POSTDEC:
 335           sprintf (p, "%s@r%d-", comma, OP[i]);
 336           p += strlen (p);
 337           comma = ",";
 338           break;
 339
 340         case OP_PREDEC:
 341           sprintf (p, "%s@-r%d", comma, OP[i]);
 342           p += strlen (p);
 343           comma = ",";
 344           break;
 345
 346         case OP_FLAG:
 347         case OP_FLAG_OUTPUT:
 348           if (OP[i] == 0)
 349             sprintf (p, "%sf0", comma);
 350
 351           else if (OP[i] == 1)
 352             sprintf (p, "%sf1", comma);
 353
 354           else
 355             sprintf (p, "%sc", comma);
 356
 357           p += strlen (p);
 358           comma = ",";
 359           break;
 360         }
 361     }
 362
 363   if ((d10v_debug & DEBUG_VALUES) == 0)
 364     {
 365       *p++ = '\n';
 366       *p = '\0';
 367       (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
 368     }
 369   else
 370     {
 371       *p = '\0';
 372       (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
 373
 374       p = buf;
 375       for (i = 0; i < 3; i++)
 376         {
 377           buf[0] = '\0';
 378           switch (in[i])
 379             {
 380             case OP_VOID:
 381               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
 382               break;
 383
 384             case OP_REG_OUTPUT:
 385             case OP_DREG_OUTPUT:
 386             case OP_CR_OUTPUT:
 387             case OP_ACCUM_OUTPUT:
 388             case OP_FLAG_OUTPUT:
 389               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
 390               break;
 391
 392             case OP_REG:
 393             case OP_MEMREF:
 394             case OP_POSTDEC:
 395             case OP_POSTINC:
 396             case OP_PREDEC:
 397               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 398                                                  (uint16) GPR (OP[i]));
 399               break;
 400
 401             case OP_MEMREF3:
 402               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
 403               break;
 404
 405             case OP_DREG:
 406               tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
 407               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
 408               break;
 409
 410             case OP_CR:
 411             case OP_CR_REVERSE:
 412               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 413                                                  (uint16) CREG (OP[i]));
 414               break;
 415
 416             case OP_ACCUM:
 417             case OP_ACCUM_REVERSE:
 418               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
 419                                                  ((int)(ACC (OP[i]) >> 32) & 0xff),
 420                                                  ((unsigned long) ACC (OP[i])) & 0xffffffff);
 421               break;
 422
 423             case OP_CONSTANT16:
 424               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 425                                                  (uint16)OP[i]);
 426               break;
 427
 428             case OP_CONSTANT4:
 429               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 430                                                  (uint16)SEXT4(OP[i]));
 431               break;
 432
 433             case OP_CONSTANT8:
 434               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 435                                                  (uint16)SEXT8(OP[i]));
 436               break;
 437
 438             case OP_CONSTANT3:
 439               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 440                                                  (uint16)SEXT3(OP[i]));
 441               break;
 442
 443             case OP_FLAG:
 444               if (OP[i] == 0)
 445                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
 446                                                    PSW_F0 != 0);
 447
 448               else if (OP[i] == 1)
 449                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
 450                                                    PSW_F1 != 0);
 451
 452               else
 453                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
 454                                                    PSW_C != 0);
 455
 456               break;
 457
 458             case OP_MEMREF2:
 459               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 460                                                  (uint16)OP[i]);
 461               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 462                                                  (uint16)GPR (OP[i + 1]));
 463               i++;
 464               break;
 465
 466             case OP_R0:
 467               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 468                                                  (uint16) GPR (0));
 469               break;
 470
 471             case OP_R1:
 472               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 473                                                  (uint16) GPR (1));
 474               break;
 475
 476             case OP_R2:
 477               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 478                                                  (uint16) GPR (2));
 479               break;
 480
 481             }
 482         }
 483     }
 484
 485   (*d10v_callback->flush_stdout) (d10v_callback);
 486 }
 487
 488 static void
 489 do_trace_output_flush (void)
 490 {
 491   (*d10v_callback->flush_stdout) (d10v_callback);
 492 }
 493
 494 static void
 495 do_trace_output_finish (void)
 496 {
 497   (*d10v_callback->printf_filtered) (d10v_callback,
 498                                      " F0=%d F1=%d C=%d\n",
 499                                      (State.trace.psw & PSW_F0_BIT) != 0,
 500                                      (State.trace.psw & PSW_F1_BIT) != 0,
 501                                      (State.trace.psw & PSW_C_BIT) != 0);
 502   (*d10v_callback->flush_stdout) (d10v_callback);
 503 }
 504
 505 static void
 506 trace_output_40 (uint64 val)
 507 {
 508   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 509     {
 510       (*d10v_callback->printf_filtered) (d10v_callback,
 511                                          " :: %*s0x%.2x%.8lx",
 512                                          SIZE_VALUES - 12,
 513                                          "",
 514                                          ((int)(val >> 32) & 0xff),
 515                                          ((unsigned long) val) & 0xffffffff);
 516       do_trace_output_finish ();
 517     }
 518 }
 519
 520 static void
 521 trace_output_32 (uint32 val)
 522 {
 523   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 524     {
 525       (*d10v_callback->printf_filtered) (d10v_callback,
 526                                          " :: %*s0x%.8x",
 527                                          SIZE_VALUES - 10,
 528                                          "",
 529                                          (int) val);
 530       do_trace_output_finish ();
 531     }
 532 }
 533
 534 static void
 535 trace_output_16 (uint16 val)
 536 {
 537   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 538     {
 539       (*d10v_callback->printf_filtered) (d10v_callback,
 540                                          " :: %*s0x%.4x",
 541                                          SIZE_VALUES - 6,
 542                                          "",
 543                                          (int) val);
 544       do_trace_output_finish ();
 545     }
 546 }
 547
 548 static void
 549 trace_output_void ()
 550 {
 551   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 552     {
 553       (*d10v_callback->printf_filtered) (d10v_callback, "\n");
 554       do_trace_output_flush ();
 555     }
 556 }
 557
 558 static void
 559 trace_output_flag ()
 560 {
 561   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 562     {
 563       (*d10v_callback->printf_filtered) (d10v_callback,
 564                                          " :: %*s",
 565                                          SIZE_VALUES,
 566                                          "");
 567       do_trace_output_finish ();
 568     }
 569 }
 570
 571
 572
 573
 574 #else
 575 #define trace_input(NAME, IN1, IN2, IN3)
 576 #define trace_output(RESULT)
 577 #endif
 578
 579 /* abs */
 580 void
 581 OP_4607 ()
 582 {
 583   int16 tmp;
 584   trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
 585   SET_PSW_F1 (PSW_F0);
 586   tmp = GPR(OP[0]);
 587   if (tmp < 0)
 588     {
 589       tmp = - tmp;
 590       SET_PSW_F0 (1);
 591     }
 592   else
 593     SET_PSW_F0 (0);
 594   SET_GPR (OP[0], tmp);
 595   trace_output_16 (tmp);
 596 }
 597
 598 /* abs */
 599 void
 600 OP_5607 ()
 601 {
 602   int64 tmp;
 603   trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
 604   SET_PSW_F1 (PSW_F0);
 605
 606   tmp = SEXT40 (ACC (OP[0]));
 607   if (tmp < 0 )
 608     {
 609       tmp = - tmp;
 610       if (PSW_ST)
 611         {
 612           if (tmp > SEXT40(MAX32))
 613             tmp = (MAX32);
 614           else if (tmp < SEXT40(MIN32))
 615             tmp = (MIN32);
 616           else
 617             tmp = (tmp & MASK40);
 618         }
 619       else
 620         tmp = (tmp & MASK40);
 621       SET_PSW_F0 (1);
 622     }
 623   else
 624     {
 625       tmp = (tmp & MASK40);
 626       SET_PSW_F0 (0);
 627     }
 628   SET_ACC (OP[0], tmp);
 629   trace_output_40 (tmp);
 630 }
 631
 632 /* add */
 633 void
 634 OP_200 ()
 635 {
 636   uint16 a = GPR (OP[0]);
 637   uint16 b = GPR (OP[1]);
 638   uint16 tmp = (a + b);
 639   trace_input ("add", OP_REG, OP_REG, OP_VOID);
 640   SET_PSW_C (a > tmp);
 641   SET_GPR (OP[0], tmp);
 642   trace_output_16 (tmp);
 643 }
 644
 645 /* add */
 646 void
 647 OP_1201 ()
 648 {
 649   int64 tmp;
 650   tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
 651
 652   trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
 653   if (PSW_ST)
 654     {
 655       if (tmp > SEXT40(MAX32))
 656         tmp = (MAX32);
 657       else if (tmp < SEXT40(MIN32))
 658         tmp = (MIN32);
 659       else
 660         tmp = (tmp & MASK40);
 661     }
 662   else
 663     tmp = (tmp & MASK40);
 664   SET_ACC (OP[0], tmp);
 665   trace_output_40 (tmp);
 666 }
 667
 668 /* add */
 669 void
 670 OP_1203 ()
 671 {
 672   int64 tmp;
 673   tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
 674
 675   trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
 676   if (PSW_ST)
 677     {
 678       if (tmp > SEXT40(MAX32))
 679         tmp = (MAX32);
 680       else if (tmp < SEXT40(MIN32))
 681         tmp = (MIN32);
 682       else
 683         tmp = (tmp & MASK40);
 684     }
 685   else
 686     tmp = (tmp & MASK40);
 687   SET_ACC (OP[0], tmp);
 688   trace_output_40 (tmp);
 689 }
 690
 691 /* add2w */
 692 void
 693 OP_1200 ()
 694 {
 695   uint32 tmp;
 696   uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
 697   uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
 698   trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
 699   tmp = a + b;
 700   SET_PSW_C (tmp < a);
 701   SET_GPR (OP[0] + 0, (tmp >> 16));
 702   SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
 703   trace_output_32 (tmp);
 704 }
 705
 706 /* add3 */
 707 void
 708 OP_1000000 ()
 709 {
 710   uint16 a = GPR (OP[1]);
 711   uint16 b = OP[2];
 712   uint16 tmp = (a + b);
 713   trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 714   SET_PSW_C (tmp < a);
 715   SET_GPR (OP[0], tmp);
 716   trace_output_16 (tmp);
 717 }
 718
 719 /* addac3 */
 720 void
 721 OP_17000200 ()
 722 {
 723   int64 tmp;
 724   tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 725
 726   trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 727   SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
 728   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 729   trace_output_32 (tmp);
 730 }
 731
 732 /* addac3 */
 733 void
 734 OP_17000202 ()
 735 {
 736   int64 tmp;
 737   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 738
 739   trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 740   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 741   SET_GPR (OP[0] + 1, tmp & 0xffff);
 742   trace_output_32 (tmp);
 743 }
 744
 745 /* addac3s */
 746 void
 747 OP_17001200 ()
 748 {
 749   int64 tmp;
 750   SET_PSW_F1 (PSW_F0);
 751
 752   trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 753   tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 754   if (tmp > SEXT40(MAX32))
 755     {
 756       tmp = (MAX32);
 757       SET_PSW_F0 (1);
 758     }
 759   else if (tmp < SEXT40(MIN32))
 760     {
 761       tmp = (MIN32);
 762       SET_PSW_F0 (1);
 763     }
 764   else
 765     {
 766       SET_PSW_F0 (0);
 767     }
 768   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 769   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 770   trace_output_32 (tmp);
 771 }
 772
 773 /* addac3s */
 774 void
 775 OP_17001202 ()
 776 {
 777   int64 tmp;
 778   SET_PSW_F1 (PSW_F0);
 779
 780   trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 781   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 782   if (tmp > SEXT40(MAX32))
 783     {
 784       tmp = (MAX32);
 785       SET_PSW_F0 (1);
 786     }
 787   else if (tmp < SEXT40(MIN32))
 788     {
 789       tmp = (MIN32);
 790       SET_PSW_F0 (1);
 791     }
 792   else
 793     {
 794       SET_PSW_F0 (0);
 795     }
 796   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 797   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 798   trace_output_32 (tmp);
 799 }
 800
 801 /* addi */
 802 void
 803 OP_201 ()
 804 {
 805   uint16 a = GPR (OP[0]);
 806   uint16 b;
 807   uint16 tmp;
 808   if (OP[1] == 0)
 809     OP[1] = 16;
 810   b = OP[1];
 811   tmp = (a + b);
 812   trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
 813   SET_PSW_C (tmp < a);
 814   SET_GPR (OP[0], tmp);
 815   trace_output_16 (tmp);
 816 }
 817
 818 /* and */
 819 void
 820 OP_C00 ()
 821 {
 822   uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
 823   trace_input ("and", OP_REG, OP_REG, OP_VOID);
 824   SET_GPR (OP[0], tmp);
 825   trace_output_16 (tmp);
 826 }
 827
 828 /* and3 */
 829 void
 830 OP_6000000 ()
 831 {
 832   uint16 tmp = GPR (OP[1]) & OP[2];
 833   trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 834   SET_GPR (OP[0], tmp);
 835   trace_output_16 (tmp);
 836 }
 837
 838 /* bclri */
 839 void
 840 OP_C01 ()
 841 {
 842   int16 tmp;
 843   trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
 844   tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
 845   SET_GPR (OP[0], tmp);
 846   trace_output_16 (tmp);
 847 }
 848
 849 /* bl.s */
 850 void
 851 OP_4900 ()
 852 {
 853   trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
 854   SET_GPR (13, PC + 1);
 855   JMP( PC + SEXT8 (OP[0]));
 856   trace_output_void ();
 857 }
 858
 859 /* bl.l */
 860 void
 861 OP_24800000 ()
 862 {
 863   trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
 864   SET_GPR (13, (PC + 1));
 865   JMP (PC + OP[0]);
 866   trace_output_void ();
 867 }
 868
 869 /* bnoti */
 870 void
 871 OP_A01 ()
 872 {
 873   int16 tmp;
 874   trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
 875   tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
 876   SET_GPR (OP[0], tmp);
 877   trace_output_16 (tmp);
 878 }
 879
 880 /* bra.s */
 881 void
 882 OP_4800 ()
 883 {
 884   trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 885   JMP (PC + SEXT8 (OP[0]));
 886   trace_output_void ();
 887 }
 888
 889 /* bra.l */
 890 void
 891 OP_24000000 ()
 892 {
 893   trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 894   JMP (PC + OP[0]);
 895   trace_output_void ();
 896 }
 897
 898 /* brf0f.s */
 899 void
 900 OP_4A00 ()
 901 {
 902   trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 903   if (!PSW_F0)
 904     JMP (PC + SEXT8 (OP[0]));
 905   trace_output_flag ();
 906 }
 907
 908 /* brf0f.l */
 909 void
 910 OP_25000000 ()
 911 {
 912   trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 913   if (!PSW_F0)
 914     JMP (PC + OP[0]);
 915   trace_output_flag ();
 916 }
 917
 918 /* brf0t.s */
 919 void
 920 OP_4B00 ()
 921 {
 922   trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 923   if (PSW_F0)
 924     JMP (PC + SEXT8 (OP[0]));
 925   trace_output_flag ();
 926 }
 927
 928 /* brf0t.l */
 929 void
 930 OP_25800000 ()
 931 {
 932   trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 933   if (PSW_F0)
 934     JMP (PC + OP[0]);
 935   trace_output_flag ();
 936 }
 937
 938 /* bseti */
 939 void
 940 OP_801 ()
 941 {
 942   int16 tmp;
 943   trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
 944   tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
 945   SET_GPR (OP[0], tmp);
 946   trace_output_16 (tmp);
 947 }
 948
 949 /* btsti */
 950 void
 951 OP_E01 ()
 952 {
 953   trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
 954   SET_PSW_F1 (PSW_F0);
 955   SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
 956   trace_output_flag ();
 957 }
 958
 959 /* clrac */
 960 void
 961 OP_5601 ()
 962 {
 963   trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
 964   SET_ACC (OP[0], 0);
 965   trace_output_40 (0);
 966 }
 967
 968 /* cmp */
 969 void
 970 OP_600 ()
 971 {
 972   trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
 973   SET_PSW_F1 (PSW_F0);
 974   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
 975   trace_output_flag ();
 976 }
 977
 978 /* cmp */
 979 void
 980 OP_1603 ()
 981 {
 982   trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
 983   SET_PSW_F1 (PSW_F0);
 984   SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
 985   trace_output_flag ();
 986 }
 987
 988 /* cmpeq */
 989 void
 990 OP_400 ()
 991 {
 992   trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
 993   SET_PSW_F1 (PSW_F0);
 994   SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
 995   trace_output_flag ();
 996 }
 997
 998 /* cmpeq */
 999 void
1000 OP_1403 ()
1001 {
1002   trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1003   SET_PSW_F1 (PSW_F0);
1004   SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1005   trace_output_flag ();
1006 }
1007
1008 /* cmpeqi.s */
1009 void
1010 OP_401 ()
1011 {
1012   trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1013   SET_PSW_F1 (PSW_F0);
1014   SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1015   trace_output_flag ();
1016 }
1017
1018 /* cmpeqi.l */
1019 void
1020 OP_2000000 ()
1021 {
1022   trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1023   SET_PSW_F1 (PSW_F0);
1024   SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1025   trace_output_flag ();
1026 }
1027
1028 /* cmpi.s */
1029 void
1030 OP_601 ()
1031 {
1032   trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1033   SET_PSW_F1 (PSW_F0);
1034   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1035   trace_output_flag ();
1036 }
1037
1038 /* cmpi.l */
1039 void
1040 OP_3000000 ()
1041 {
1042   trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1043   SET_PSW_F1 (PSW_F0);
1044   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1045   trace_output_flag ();
1046 }
1047
1048 /* cmpu */
1049 void
1050 OP_4600 ()
1051 {
1052   trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1053   SET_PSW_F1 (PSW_F0);
1054   SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1055   trace_output_flag ();
1056 }
1057
1058 /* cmpui */
1059 void
1060 OP_23000000 ()
1061 {
1062   trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1063   SET_PSW_F1 (PSW_F0);
1064   SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1065   trace_output_flag ();
1066 }
1067
1068 /* cpfg */
1069 void
1070 OP_4E09 ()
1071 {
1072   uint8 val;
1073
1074   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1075
1076   if (OP[1] == 0)
1077     val = PSW_F0;
1078   else if (OP[1] == 1)
1079     val = PSW_F1;
1080   else
1081     val = PSW_C;
1082   if (OP[0] == 0)
1083     SET_PSW_F0 (val);
1084   else
1085     SET_PSW_F1 (val);
1086
1087   trace_output_flag ();
1088 }
1089
1090 /* cpfg */
1091 void
1092 OP_4E0F ()
1093 {
1094   uint8 val;
1095
1096   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1097
1098   if (OP[1] == 0)
1099     val = PSW_F0;
1100   else if (OP[1] == 1)
1101     val = PSW_F1;
1102   else
1103     val = PSW_C;
1104   if (OP[0] == 0)
1105     SET_PSW_F0 (val);
1106   else
1107     SET_PSW_F1 (val);
1108
1109   trace_output_flag ();
1110 }
1111
1112 /* dbt */
1113 void
1114 OP_5F20 ()
1115 {
1116   /* d10v_callback->printf_filtered(d10v_callback, "***** DBT *****  PC=%x\n",PC); */
1117
1118   /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1119      The conditional below is for either of the instruction pairs
1120      ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1121      where the dbt instruction should be interpreted.
1122
1123      The module `sim-break' provides a more effective mechanism for
1124      detecting GDB planted breakpoints.  The code below may,
1125      eventually, be changed to use that mechanism. */
1126
1127   if (State.ins_type == INS_LEFT
1128       || State.ins_type == INS_RIGHT)
1129     {
1130       trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1131       SET_DPC (PC + 1);
1132       SET_DPSW (PSW);
1133       SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1134       JMP (DBT_VECTOR_START);
1135       trace_output_void ();
1136     }
1137   else
1138     {
1139       State.exception = SIGTRAP;
1140     }
1141 }
1142
1143 /* divs */
1144 void
1145 OP_14002800 ()
1146 {
1147   uint16 foo, tmp, tmpf;
1148   uint16 hi;
1149   uint16 lo;
1150
1151   trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1152   foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1153   tmp = (int16)foo - (int16)(GPR (OP[1]));
1154   tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1155   hi = ((tmpf == 1) ? tmp : foo);
1156   lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1157   SET_GPR (OP[0] + 0, hi);
1158   SET_GPR (OP[0] + 1, lo);
1159   trace_output_32 (((uint32) hi << 16) | lo);
1160 }
1161
1162 /* exef0f */
1163 void
1164 OP_4E04 ()
1165 {
1166   trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1167   State.exe = (PSW_F0 == 0);
1168   trace_output_flag ();
1169 }
1170
1171 /* exef0t */
1172 void
1173 OP_4E24 ()
1174 {
1175   trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1176   State.exe = (PSW_F0 != 0);
1177   trace_output_flag ();
1178 }
1179
1180 /* exef1f */
1181 void
1182 OP_4E40 ()
1183 {
1184   trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1185   State.exe = (PSW_F1 == 0);
1186   trace_output_flag ();
1187 }
1188
1189 /* exef1t */
1190 void
1191 OP_4E42 ()
1192 {
1193   trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1194   State.exe = (PSW_F1 != 0);
1195   trace_output_flag ();
1196 }
1197
1198 /* exefaf */
1199 void
1200 OP_4E00 ()
1201 {
1202   trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1203   State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1204   trace_output_flag ();
1205 }
1206
1207 /* exefat */
1208 void
1209 OP_4E02 ()
1210 {
1211   trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1212   State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1213   trace_output_flag ();
1214 }
1215
1216 /* exetaf */
1217 void
1218 OP_4E20 ()
1219 {
1220   trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1221   State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1222   trace_output_flag ();
1223 }
1224
1225 /* exetat */
1226 void
1227 OP_4E22 ()
1228 {
1229   trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1230   State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1231   trace_output_flag ();
1232 }
1233
1234 /* exp */
1235 void
1236 OP_15002A00 ()
1237 {
1238   uint32 tmp, foo;
1239   int i;
1240
1241   trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1242   if (((int16)GPR (OP[1])) >= 0)
1243     tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1244   else
1245     tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1246
1247   foo = 0x40000000;
1248   for (i=1;i<17;i++)
1249     {
1250       if (tmp & foo)
1251         {
1252           SET_GPR (OP[0], (i - 1));
1253           trace_output_16 (i - 1);
1254           return;
1255         }
1256       foo >>= 1;
1257     }
1258   SET_GPR (OP[0], 16);
1259   trace_output_16 (16);
1260 }
1261
1262 /* exp */
1263 void
1264 OP_15002A02 ()
1265 {
1266   int64 tmp, foo;
1267   int i;
1268
1269   trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1270   tmp = SEXT40(ACC (OP[1]));
1271   if (tmp < 0)
1272     tmp = ~tmp & MASK40;
1273
1274   foo = 0x4000000000LL;
1275   for (i=1;i<25;i++)
1276     {
1277       if (tmp & foo)
1278         {
1279           SET_GPR (OP[0], i - 9);
1280           trace_output_16 (i - 9);
1281           return;
1282         }
1283       foo >>= 1;
1284     }
1285   SET_GPR (OP[0], 16);
1286   trace_output_16 (16);
1287 }
1288
1289 /* jl */
1290 void
1291 OP_4D00 ()
1292 {
1293   trace_input ("jl", OP_REG, OP_R0, OP_R1);
1294   SET_GPR (13, PC + 1);
1295   JMP (GPR (OP[0]));
1296   trace_output_void ();
1297 }
1298
1299 /* jmp */
1300 void
1301 OP_4C00 ()
1302 {
1303   trace_input ("jmp", OP_REG,
1304                (OP[0] == 13) ? OP_R0 : OP_VOID,
1305                (OP[0] == 13) ? OP_R1 : OP_VOID);
1306
1307   JMP (GPR (OP[0]));
1308   trace_output_void ();
1309 }
1310
1311 /* ld */
1312 void
1313 OP_30000000 ()
1314 {
1315   uint16 tmp;
1316   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1317   tmp = RW (OP[1] + GPR (OP[2]));
1318   SET_GPR (OP[0], tmp);
1319   trace_output_16 (tmp);
1320 }
1321
1322 /* ld */
1323 void
1324 OP_6401 ()
1325 {
1326   uint16 tmp;
1327   trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1328   tmp = RW (GPR (OP[1]));
1329   SET_GPR (OP[0], tmp);
1330   if (OP[0] != OP[1])
1331     INC_ADDR (OP[1], -2);
1332   trace_output_16 (tmp);
1333 }
1334
1335 /* ld */
1336 void
1337 OP_6001 ()
1338 {
1339   uint16 tmp;
1340   trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1341   tmp = RW (GPR (OP[1]));
1342   SET_GPR (OP[0], tmp);
1343   if (OP[0] != OP[1])
1344     INC_ADDR (OP[1], 2);
1345   trace_output_16 (tmp);
1346 }
1347
1348 /* ld */
1349 void
1350 OP_6000 ()
1351 {
1352   uint16 tmp;
1353   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1354   tmp = RW (GPR (OP[1]));
1355   SET_GPR (OP[0], tmp);
1356   trace_output_16 (tmp);
1357 }
1358
1359 /* ld */
1360 void
1361 OP_32010000 ()
1362 {
1363   uint16 tmp;
1364
1365   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1366   tmp = RW (OP[1]);
1367   SET_GPR (OP[0], tmp);
1368   trace_output_16 (tmp);
1369 }
1370
1371 /* ld2w */
1372 void
1373 OP_31000000 ()
1374 {
1375   int32 tmp;
1376   uint16 addr = GPR (OP[2]);
1377   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1378   tmp = RLW (OP[1] + addr);
1379   SET_GPR32 (OP[0], tmp);
1380   trace_output_32 (tmp);
1381 }
1382
1383 /* ld2w */
1384 void
1385 OP_6601 ()
1386 {
1387   uint16 addr = GPR (OP[1]);
1388   int32 tmp;
1389   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1390   tmp = RLW (addr);
1391   SET_GPR32 (OP[0], tmp);
1392   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1393     INC_ADDR (OP[1], -4);
1394   trace_output_32 (tmp);
1395 }
1396
1397 /* ld2w */
1398 void
1399 OP_6201 ()
1400 {
1401   int32 tmp;
1402   uint16 addr = GPR (OP[1]);
1403   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1404   tmp = RLW (addr);
1405   SET_GPR32 (OP[0], tmp);
1406   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1407     INC_ADDR (OP[1], 4);
1408   trace_output_32 (tmp);
1409 }
1410
1411 /* ld2w */
1412 void
1413 OP_6200 ()
1414 {
1415   uint16 addr = GPR (OP[1]);
1416   int32 tmp;
1417   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1418   tmp = RLW (addr + 0);
1419   SET_GPR32 (OP[0], tmp);
1420   trace_output_32 (tmp);
1421 }
1422
1423 /* ld2w */
1424 void
1425 OP_33010000 ()
1426 {
1427   int32 tmp;
1428
1429   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1430   tmp = RLW (OP[1]);
1431   SET_GPR32 (OP[0], tmp);
1432   trace_output_32 (tmp);
1433 }
1434
1435 /* ldb */
1436 void
1437 OP_38000000 ()
1438 {
1439   int16 tmp;
1440   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1441   tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1442   SET_GPR (OP[0], tmp);
1443   trace_output_16 (tmp);
1444 }
1445
1446 /* ldb */
1447 void
1448 OP_7000 ()
1449 {
1450   int16 tmp;
1451   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1452   tmp = SEXT8 (RB (GPR (OP[1])));
1453   SET_GPR (OP[0], tmp);
1454   trace_output_16 (tmp);
1455 }
1456
1457 /* ldi.s */
1458 void
1459 OP_4001 ()
1460 {
1461   int16 tmp;
1462   trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1463   tmp = SEXT4 (OP[1]);
1464   SET_GPR (OP[0], tmp);
1465   trace_output_16 (tmp);
1466 }
1467
1468 /* ldi.l */
1469 void
1470 OP_20000000 ()
1471 {
1472   int16 tmp;
1473   trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1474   tmp = OP[1];
1475   SET_GPR (OP[0], tmp);
1476   trace_output_16 (tmp);
1477 }
1478
1479 /* ldub */
1480 void
1481 OP_39000000 ()
1482 {
1483   int16 tmp;
1484   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1485   tmp = RB (OP[1] + GPR (OP[2]));
1486   SET_GPR (OP[0], tmp);
1487   trace_output_16 (tmp);
1488 }
1489
1490 /* ldub */
1491 void
1492 OP_7200 ()
1493 {
1494   int16 tmp;
1495   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1496   tmp = RB (GPR (OP[1]));
1497   SET_GPR (OP[0], tmp);
1498   trace_output_16 (tmp);
1499 }
1500
1501 /* mac */
1502 void
1503 OP_2A00 ()
1504 {
1505   int64 tmp;
1506
1507   trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1508   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1509
1510   if (PSW_FX)
1511     tmp = SEXT40( (tmp << 1) & MASK40);
1512
1513   if (PSW_ST && tmp > SEXT40(MAX32))
1514     tmp = (MAX32);
1515
1516   tmp += SEXT40 (ACC (OP[0]));
1517   if (PSW_ST)
1518     {
1519       if (tmp > SEXT40(MAX32))
1520         tmp = (MAX32);
1521       else if (tmp < SEXT40(MIN32))
1522         tmp = (MIN32);
1523       else
1524         tmp = (tmp & MASK40);
1525     }
1526   else
1527     tmp = (tmp & MASK40);
1528   SET_ACC (OP[0], tmp);
1529   trace_output_40 (tmp);
1530 }
1531
1532 /* macsu */
1533 void
1534 OP_1A00 ()
1535 {
1536   int64 tmp;
1537
1538   trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1539   tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1540   if (PSW_FX)
1541     tmp = SEXT40 ((tmp << 1) & MASK40);
1542   tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1543   SET_ACC (OP[0], tmp);
1544   trace_output_40 (tmp);
1545 }
1546
1547 /* macu */
1548 void
1549 OP_3A00 ()
1550 {
1551   uint64 tmp;
1552   uint32 src1;
1553   uint32 src2;
1554
1555   trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1556   src1 = (uint16) GPR (OP[1]);
1557   src2 = (uint16) GPR (OP[2]);
1558   tmp = src1 * src2;
1559   if (PSW_FX)
1560     tmp = (tmp << 1);
1561   tmp = ((ACC (OP[0]) + tmp) & MASK40);
1562   SET_ACC (OP[0], tmp);
1563   trace_output_40 (tmp);
1564 }
1565
1566 /* max */
1567 void
1568 OP_2600 ()
1569 {
1570   int16 tmp;
1571   trace_input ("max", OP_REG, OP_REG, OP_VOID);
1572   SET_PSW_F1 (PSW_F0);
1573   if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1574     {
1575       tmp = GPR (OP[1]);
1576       SET_PSW_F0 (1);
1577     }
1578   else
1579     {
1580       tmp = GPR (OP[0]);
1581       SET_PSW_F0 (0);
1582     }
1583   SET_GPR (OP[0], tmp);
1584   trace_output_16 (tmp);
1585 }
1586
1587 /* max */
1588 void
1589 OP_3600 ()
1590 {
1591   int64 tmp;
1592
1593   trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1594   SET_PSW_F1 (PSW_F0);
1595   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1596   if (tmp > SEXT40 (ACC (OP[0])))
1597     {
1598       tmp = (tmp & MASK40);
1599       SET_PSW_F0 (1);
1600     }
1601   else
1602     {
1603       tmp = ACC (OP[0]);
1604       SET_PSW_F0 (0);
1605     }
1606   SET_ACC (OP[0], tmp);
1607   trace_output_40 (tmp);
1608 }
1609
1610 /* max */
1611 void
1612 OP_3602 ()
1613 {
1614   int64 tmp;
1615   trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1616   SET_PSW_F1 (PSW_F0);
1617   if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1618     {
1619       tmp = ACC (OP[1]);
1620       SET_PSW_F0 (1);
1621     }
1622   else
1623     {
1624       tmp = ACC (OP[0]);
1625       SET_PSW_F0 (0);
1626     }
1627   SET_ACC (OP[0], tmp);
1628   trace_output_40 (tmp);
1629 }
1630
1631
1632 /* min */
1633 void
1634 OP_2601 ()
1635 {
1636   int16 tmp;
1637   trace_input ("min", OP_REG, OP_REG, OP_VOID);
1638   SET_PSW_F1 (PSW_F0);
1639   if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1640     {
1641       tmp = GPR (OP[1]);
1642       SET_PSW_F0 (1);
1643     }
1644   else
1645     {
1646       tmp = GPR (OP[0]);
1647       SET_PSW_F0 (0);
1648     }
1649   SET_GPR (OP[0], tmp);
1650   trace_output_16 (tmp);
1651 }
1652
1653 /* min */
1654 void
1655 OP_3601 ()
1656 {
1657   int64 tmp;
1658
1659   trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1660   SET_PSW_F1 (PSW_F0);
1661   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1662   if (tmp < SEXT40(ACC (OP[0])))
1663     {
1664       tmp = (tmp & MASK40);
1665       SET_PSW_F0 (1);
1666     }
1667   else
1668     {
1669       tmp = ACC (OP[0]);
1670       SET_PSW_F0 (0);
1671     }
1672   SET_ACC (OP[0], tmp);
1673   trace_output_40 (tmp);
1674 }
1675
1676 /* min */
1677 void
1678 OP_3603 ()
1679 {
1680   int64 tmp;
1681   trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1682   SET_PSW_F1 (PSW_F0);
1683   if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1684     {
1685       tmp = ACC (OP[1]);
1686       SET_PSW_F0 (1);
1687     }
1688   else
1689     {
1690       tmp = ACC (OP[0]);
1691       SET_PSW_F0 (0);
1692     }
1693   SET_ACC (OP[0], tmp);
1694   trace_output_40 (tmp);
1695 }
1696
1697 /* msb */
1698 void
1699 OP_2800 ()
1700 {
1701   int64 tmp;
1702
1703   trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1704   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1705
1706   if (PSW_FX)
1707     tmp = SEXT40 ((tmp << 1) & MASK40);
1708
1709   if (PSW_ST && tmp > SEXT40(MAX32))
1710     tmp = (MAX32);
1711
1712   tmp = SEXT40(ACC (OP[0])) - tmp;
1713   if (PSW_ST)
1714     {
1715       if (tmp > SEXT40(MAX32))
1716         tmp = (MAX32);
1717       else if (tmp < SEXT40(MIN32))
1718         tmp = (MIN32);
1719       else
1720         tmp = (tmp & MASK40);
1721     }
1722   else
1723     {
1724       tmp = (tmp & MASK40);
1725     }
1726   SET_ACC (OP[0], tmp);
1727   trace_output_40 (tmp);
1728 }
1729
1730 /* msbsu */
1731 void
1732 OP_1800 ()
1733 {
1734   int64 tmp;
1735
1736   trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1737   tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1738   if (PSW_FX)
1739     tmp = SEXT40( (tmp << 1) & MASK40);
1740   tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1741   SET_ACC (OP[0], tmp);
1742   trace_output_40 (tmp);
1743 }
1744
1745 /* msbu */
1746 void
1747 OP_3800 ()
1748 {
1749   uint64 tmp;
1750   uint32 src1;
1751   uint32 src2;
1752
1753   trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1754   src1 = (uint16) GPR (OP[1]);
1755   src2 = (uint16) GPR (OP[2]);
1756   tmp = src1 * src2;
1757   if (PSW_FX)
1758     tmp = (tmp << 1);
1759   tmp = ((ACC (OP[0]) - tmp) & MASK40);
1760   SET_ACC (OP[0], tmp);
1761   trace_output_40 (tmp);
1762 }
1763
1764 /* mul */
1765 void
1766 OP_2E00 ()
1767 {
1768   int16 tmp;
1769   trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1770   tmp = GPR (OP[0]) * GPR (OP[1]);
1771   SET_GPR (OP[0], tmp);
1772   trace_output_16 (tmp);
1773 }
1774
1775 /* mulx */
1776 void
1777 OP_2C00 ()
1778 {
1779   int64 tmp;
1780
1781   trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1782   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1783
1784   if (PSW_FX)
1785     tmp = SEXT40 ((tmp << 1) & MASK40);
1786
1787   if (PSW_ST && tmp > SEXT40(MAX32))
1788     tmp = (MAX32);
1789   else
1790     tmp = (tmp & MASK40);
1791   SET_ACC (OP[0], tmp);
1792   trace_output_40 (tmp);
1793 }
1794
1795 /* mulxsu */
1796 void
1797 OP_1C00 ()
1798 {
1799   int64 tmp;
1800
1801   trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1802   tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1803
1804   if (PSW_FX)
1805     tmp <<= 1;
1806   tmp = (tmp & MASK40);
1807   SET_ACC (OP[0], tmp);
1808   trace_output_40 (tmp);
1809 }
1810
1811 /* mulxu */
1812 void
1813 OP_3C00 ()
1814 {
1815   uint64 tmp;
1816   uint32 src1;
1817   uint32 src2;
1818
1819   trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1820   src1 = (uint16) GPR (OP[1]);
1821   src2 = (uint16) GPR (OP[2]);
1822   tmp = src1 * src2;
1823   if (PSW_FX)
1824     tmp <<= 1;
1825   tmp = (tmp & MASK40);
1826   SET_ACC (OP[0], tmp);
1827   trace_output_40 (tmp);
1828 }
1829
1830 /* mv */
1831 void
1832 OP_4000 ()
1833 {
1834   int16 tmp;
1835   trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1836   tmp = GPR (OP[1]);
1837   SET_GPR (OP[0], tmp);
1838   trace_output_16 (tmp);
1839 }
1840
1841 /* mv2w */
1842 void
1843 OP_5000 ()
1844 {
1845   int32 tmp;
1846   trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1847   tmp = GPR32 (OP[1]);
1848   SET_GPR32 (OP[0], tmp);
1849   trace_output_32 (tmp);
1850 }
1851
1852 /* mv2wfac */
1853 void
1854 OP_3E00 ()
1855 {
1856   int32 tmp;
1857   trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1858   tmp = ACC (OP[1]);
1859   SET_GPR32 (OP[0], tmp);
1860   trace_output_32 (tmp);
1861 }
1862
1863 /* mv2wtac */
1864 void
1865 OP_3E01 ()
1866 {
1867   int64 tmp;
1868   trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1869   tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1870   SET_ACC (OP[1], tmp);
1871   trace_output_40 (tmp);
1872 }
1873
1874 /* mvac */
1875 void
1876 OP_3E03 ()
1877 {
1878   int64 tmp;
1879   trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1880   tmp = ACC (OP[1]);
1881   SET_ACC (OP[0], tmp);
1882   trace_output_40 (tmp);
1883 }
1884
1885 /* mvb */
1886 void
1887 OP_5400 ()
1888 {
1889   int16 tmp;
1890   trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1891   tmp = SEXT8 (GPR (OP[1]) & 0xff);
1892   SET_GPR (OP[0], tmp);
1893   trace_output_16 (tmp);
1894 }
1895
1896 /* mvf0f */
1897 void
1898 OP_4400 ()
1899 {
1900   int16 tmp;
1901   trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1902   if (PSW_F0 == 0)
1903     {
1904       tmp = GPR (OP[1]);
1905       SET_GPR (OP[0], tmp);
1906     }
1907   else
1908     tmp = GPR (OP[0]);
1909   trace_output_16 (tmp);
1910 }
1911
1912 /* mvf0t */
1913 void
1914 OP_4401 ()
1915 {
1916   int16 tmp;
1917   trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1918   if (PSW_F0)
1919     {
1920       tmp = GPR (OP[1]);
1921       SET_GPR (OP[0], tmp);
1922     }
1923   else
1924     tmp = GPR (OP[0]);
1925   trace_output_16 (tmp);
1926 }
1927
1928 /* mvfacg */
1929 void
1930 OP_1E04 ()
1931 {
1932   int16 tmp;
1933   trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1934   tmp = ((ACC (OP[1]) >> 32) & 0xff);
1935   SET_GPR (OP[0], tmp);
1936   trace_output_16 (tmp);
1937 }
1938
1939 /* mvfachi */
1940 void
1941 OP_1E00 ()
1942 {
1943   int16 tmp;
1944   trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1945   tmp = (ACC (OP[1]) >> 16);
1946   SET_GPR (OP[0], tmp);
1947   trace_output_16 (tmp);
1948 }
1949
1950 /* mvfaclo */
1951 void
1952 OP_1E02 ()
1953 {
1954   int16 tmp;
1955   trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1956   tmp = ACC (OP[1]);
1957   SET_GPR (OP[0], tmp);
1958   trace_output_16 (tmp);
1959 }
1960
1961 /* mvfc */
1962 void
1963 OP_5200 ()
1964 {
1965   int16 tmp;
1966   trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1967   tmp = CREG (OP[1]);
1968   SET_GPR (OP[0], tmp);
1969   trace_output_16 (tmp);
1970 }
1971
1972 /* mvtacg */
1973 void
1974 OP_1E41 ()
1975 {
1976   int64 tmp;
1977   trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1978   tmp = ((ACC (OP[1]) & MASK32)
1979          | ((int64)(GPR (OP[0]) & 0xff) << 32));
1980   SET_ACC (OP[1], tmp);
1981   trace_output_40 (tmp);
1982 }
1983
1984 /* mvtachi */
1985 void
1986 OP_1E01 ()
1987 {
1988   uint64 tmp;
1989   trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1990   tmp = ACC (OP[1]) & 0xffff;
1991   tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1992   SET_ACC (OP[1], tmp);
1993   trace_output_40 (tmp);
1994 }
1995
1996 /* mvtaclo */
1997 void
1998 OP_1E21 ()
1999 {
2000   int64 tmp;
2001   trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2002   tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2003   SET_ACC (OP[1], tmp);
2004   trace_output_40 (tmp);
2005 }
2006
2007 /* mvtc */
2008 void
2009 OP_5600 ()
2010 {
2011   int16 tmp;
2012   trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2013   tmp = GPR (OP[0]);
2014   tmp = SET_CREG (OP[1], tmp);
2015   trace_output_16 (tmp);
2016 }
2017
2018 /* mvub */
2019 void
2020 OP_5401 ()
2021 {
2022   int16 tmp;
2023   trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2024   tmp = (GPR (OP[1]) & 0xff);
2025   SET_GPR (OP[0], tmp);
2026   trace_output_16 (tmp);
2027 }
2028
2029 /* neg */
2030 void
2031 OP_4605 ()
2032 {
2033   int16 tmp;
2034   trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2035   tmp = - GPR (OP[0]);
2036   SET_GPR (OP[0], tmp);
2037   trace_output_16 (tmp);
2038 }
2039
2040 /* neg */
2041 void
2042 OP_5605 ()
2043 {
2044   int64 tmp;
2045
2046   trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2047   tmp = -SEXT40(ACC (OP[0]));
2048   if (PSW_ST)
2049     {
2050       if (tmp > SEXT40(MAX32))
2051         tmp = (MAX32);
2052       else if (tmp < SEXT40(MIN32))
2053         tmp = (MIN32);
2054       else
2055         tmp = (tmp & MASK40);
2056     }
2057   else
2058     tmp = (tmp & MASK40);
2059   SET_ACC (OP[0], tmp);
2060   trace_output_40 (tmp);
2061 }
2062
2063
2064 /* nop */
2065 void
2066 OP_5E00 ()
2067 {
2068   trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2069
2070   ins_type_counters[ (int)State.ins_type ]--;   /* don't count nops as normal instructions */
2071   switch (State.ins_type)
2072     {
2073     default:
2074       ins_type_counters[ (int)INS_UNKNOWN ]++;
2075       break;
2076
2077     case INS_LEFT_PARALLEL:
2078       /* Don't count a parallel op that includes a NOP as a true parallel op */
2079       ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2080       ins_type_counters[ (int)INS_RIGHT ]++;
2081       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2082       break;
2083
2084     case INS_LEFT:
2085     case INS_LEFT_COND_EXE:
2086       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2087       break;
2088
2089     case INS_RIGHT_PARALLEL:
2090       /* Don't count a parallel op that includes a NOP as a true parallel op */
2091       ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2092       ins_type_counters[ (int)INS_LEFT ]++;
2093       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2094       break;
2095
2096     case INS_RIGHT:
2097     case INS_RIGHT_COND_EXE:
2098       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2099       break;
2100     }
2101
2102   trace_output_void ();
2103 }
2104
2105 /* not */
2106 void
2107 OP_4603 ()
2108 {
2109   int16 tmp;
2110   trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2111   tmp = ~GPR (OP[0]);
2112   SET_GPR (OP[0], tmp);
2113   trace_output_16 (tmp);
2114 }
2115
2116 /* or */
2117 void
2118 OP_800 ()
2119 {
2120   int16 tmp;
2121   trace_input ("or", OP_REG, OP_REG, OP_VOID);
2122   tmp = (GPR (OP[0]) | GPR (OP[1]));
2123   SET_GPR (OP[0], tmp);
2124   trace_output_16 (tmp);
2125 }
2126
2127 /* or3 */
2128 void
2129 OP_4000000 ()
2130 {
2131   int16 tmp;
2132   trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2133   tmp = (GPR (OP[1]) | OP[2]);
2134   SET_GPR (OP[0], tmp);
2135   trace_output_16 (tmp);
2136 }
2137
2138 /* rac */
2139 void
2140 OP_5201 ()
2141 {
2142   int64 tmp;
2143   int shift = SEXT3 (OP[2]);
2144
2145   trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2146   if (OP[1] != 0)
2147     {
2148       (*d10v_callback->printf_filtered) (d10v_callback,
2149                                          "ERROR at PC 0x%x: instruction only valid for A0\n",
2150                                          PC<<2);
2151       State.exception = SIGILL;
2152     }
2153
2154   SET_PSW_F1 (PSW_F0);
2155   tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2156   if (shift >=0)
2157     tmp <<= shift;
2158   else
2159     tmp >>= -shift;
2160   tmp += 0x8000;
2161   tmp >>= 16; /* look at bits 0:43 */
2162   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2163     {
2164       tmp = 0x7fffffff;
2165       SET_PSW_F0 (1);
2166     }
2167   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2168     {
2169       tmp = 0x80000000;
2170       SET_PSW_F0 (1);
2171     }
2172   else
2173     {
2174       SET_PSW_F0 (0);
2175     }
2176   SET_GPR32 (OP[0], tmp);
2177   trace_output_32 (tmp);
2178 }
2179
2180 /* rachi */
2181 void
2182 OP_4201 ()
2183 {
2184   signed64 tmp;
2185   int shift = SEXT3 (OP[2]);
2186
2187   trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2188   SET_PSW_F1 (PSW_F0);
2189   if (shift >=0)
2190     tmp = SEXT40 (ACC (OP[1])) << shift;
2191   else
2192     tmp = SEXT40 (ACC (OP[1])) >> -shift;
2193   tmp += 0x8000;
2194
2195   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2196     {
2197       tmp = 0x7fff;
2198       SET_PSW_F0 (1);
2199     }
2200   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2201     {
2202       tmp = 0x8000;
2203       SET_PSW_F0 (1);
2204     }
2205   else
2206     {
2207       tmp = (tmp >> 16);
2208       SET_PSW_F0 (0);
2209     }
2210   SET_GPR (OP[0], tmp);
2211   trace_output_16 (tmp);
2212 }
2213
2214 /* rep */
2215 void
2216 OP_27000000 ()
2217 {
2218   trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2219   SET_RPT_S (PC + 1);
2220   SET_RPT_E (PC + OP[1]);
2221   SET_RPT_C (GPR (OP[0]));
2222   SET_PSW_RP (1);
2223   if (GPR (OP[0]) == 0)
2224     {
2225       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2226       State.exception = SIGILL;
2227     }
2228   if (OP[1] < 4)
2229     {
2230       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2231       State.exception = SIGILL;
2232     }
2233   trace_output_void ();
2234 }
2235
2236 /* repi */
2237 void
2238 OP_2F000000 ()
2239 {
2240   trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2241   SET_RPT_S (PC + 1);
2242   SET_RPT_E (PC + OP[1]);
2243   SET_RPT_C (OP[0]);
2244   SET_PSW_RP (1);
2245   if (OP[0] == 0)
2246     {
2247       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2248       State.exception = SIGILL;
2249     }
2250   if (OP[1] < 4)
2251     {
2252       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2253       State.exception = SIGILL;
2254     }
2255   trace_output_void ();
2256 }
2257
2258 /* rtd */
2259 void
2260 OP_5F60 ()
2261 {
2262   trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2263   SET_CREG (PSW_CR, DPSW);
2264   JMP(DPC);
2265   trace_output_void ();
2266 }
2267
2268 /* rte */
2269 void
2270 OP_5F40 ()
2271 {
2272   trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2273   SET_CREG (PSW_CR, BPSW);
2274   JMP(BPC);
2275   trace_output_void ();
2276 }
2277
2278 /* sac */
2279 void OP_5209 ()
2280 {
2281   int64 tmp;
2282
2283   trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2284
2285   tmp = SEXT40(ACC (OP[1]));
2286
2287   SET_PSW_F1 (PSW_F0);
2288
2289   if (tmp > SEXT40(MAX32))
2290     {
2291       tmp = (MAX32);
2292       SET_PSW_F0 (1);
2293     }
2294   else if (tmp < SEXT40(MIN32))
2295     {
2296       tmp = 0x80000000;
2297       SET_PSW_F0 (1);
2298     }
2299   else
2300     {
2301       tmp = (tmp & MASK32);
2302       SET_PSW_F0 (0);
2303     }
2304
2305   SET_GPR32 (OP[0], tmp);
2306
2307   trace_output_40 (tmp);
2308 }
2309
2310 /* sachi */
2311 void
2312 OP_4209 ()
2313 {
2314   int64 tmp;
2315
2316   trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2317
2318   tmp = SEXT40(ACC (OP[1]));
2319
2320   SET_PSW_F1 (PSW_F0);
2321
2322   if (tmp > SEXT40(MAX32))
2323     {
2324       tmp = 0x7fff;
2325       SET_PSW_F0 (1);
2326     }
2327   else if (tmp < SEXT40(MIN32))
2328     {
2329       tmp = 0x8000;
2330       SET_PSW_F0 (1);
2331     }
2332   else
2333     {
2334       tmp >>= 16;
2335       SET_PSW_F0 (0);
2336     }
2337
2338   SET_GPR (OP[0], tmp);
2339
2340   trace_output_16 (OP[0]);
2341 }
2342
2343 /* sadd */
2344 void
2345 OP_1223 ()
2346 {
2347   int64 tmp;
2348
2349   trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2350   tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2351   if (PSW_ST)
2352     {
2353       if (tmp > SEXT40(MAX32))
2354         tmp = (MAX32);
2355       else if (tmp < SEXT40(MIN32))
2356         tmp = (MIN32);
2357       else
2358         tmp = (tmp & MASK40);
2359     }
2360   else
2361     tmp = (tmp & MASK40);
2362   SET_ACC (OP[0], tmp);
2363   trace_output_40 (tmp);
2364 }
2365
2366 /* setf0f */
2367 void
2368 OP_4611 ()
2369 {
2370   int16 tmp;
2371   trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2372   tmp = ((PSW_F0 == 0) ? 1 : 0);
2373   SET_GPR (OP[0], tmp);
2374   trace_output_16 (tmp);
2375 }
2376
2377 /* setf0t */
2378 void
2379 OP_4613 ()
2380 {
2381   int16 tmp;
2382   trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2383   tmp = ((PSW_F0 == 1) ? 1 : 0);
2384   SET_GPR (OP[0], tmp);
2385   trace_output_16 (tmp);
2386 }
2387
2388 /* slae */
2389 void
2390 OP_3220 ()
2391 {
2392   int64 tmp;
2393   int16 reg;
2394
2395   trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2396
2397   reg = SEXT16 (GPR (OP[1]));
2398
2399   if (reg >= 17 || reg <= -17)
2400     {
2401       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2402       State.exception = SIGILL;
2403       return;
2404     }
2405
2406   tmp = SEXT40 (ACC (OP[0]));
2407
2408   if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2409     {
2410       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2411       State.exception = SIGILL;
2412       return;
2413     }
2414
2415   if (reg >= 0 && reg <= 16)
2416     {
2417       tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2418       if (PSW_ST)
2419         {
2420           if (tmp > SEXT40(MAX32))
2421             tmp = (MAX32);
2422           else if (tmp < SEXT40(MIN32))
2423             tmp = (MIN32);
2424           else
2425             tmp = (tmp & MASK40);
2426         }
2427       else
2428         tmp = (tmp & MASK40);
2429     }
2430   else
2431     {
2432       tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2433     }
2434
2435   SET_ACC(OP[0], tmp);
2436
2437   trace_output_40(tmp);
2438 }
2439
2440 /* sleep */
2441 void
2442 OP_5FC0 ()
2443 {
2444   trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2445   SET_PSW_IE (1);
2446   trace_output_void ();
2447 }
2448
2449 /* sll */
2450 void
2451 OP_2200 ()
2452 {
2453   int16 tmp;
2454   trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2455   tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2456   SET_GPR (OP[0], tmp);
2457   trace_output_16 (tmp);
2458 }
2459
2460 /* sll */
2461 void
2462 OP_3200 ()
2463 {
2464   int64 tmp;
2465   trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2466   if ((GPR (OP[1]) & 31) <= 16)
2467     tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2468   else
2469     {
2470       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2471       State.exception = SIGILL;
2472       return;
2473     }
2474
2475   if (PSW_ST)
2476     {
2477       if (tmp > SEXT40(MAX32))
2478         tmp = (MAX32);
2479       else if (tmp < SEXT40(MIN32))
2480         tmp = (MIN32);
2481       else
2482         tmp = (tmp & MASK40);
2483     }
2484   else
2485     tmp = (tmp & MASK40);
2486   SET_ACC (OP[0], tmp);
2487   trace_output_40 (tmp);
2488 }
2489
2490 /* slli */
2491 void
2492 OP_2201 ()
2493 {
2494   int16 tmp;
2495   trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2496   tmp = (GPR (OP[0]) << OP[1]);
2497   SET_GPR (OP[0], tmp);
2498   trace_output_16 (tmp);
2499 }
2500
2501 /* slli */
2502 void
2503 OP_3201 ()
2504 {
2505   int64 tmp;
2506
2507   if (OP[1] == 0)
2508     OP[1] = 16;
2509
2510   trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2511   tmp = SEXT40(ACC (OP[0])) << OP[1];
2512
2513   if (PSW_ST)
2514     {
2515       if (tmp > SEXT40(MAX32))
2516         tmp = (MAX32);
2517       else if (tmp < SEXT40(MIN32))
2518         tmp = (MIN32);
2519       else
2520         tmp = (tmp & MASK40);
2521     }
2522   else
2523     tmp = (tmp & MASK40);
2524   SET_ACC (OP[0], tmp);
2525   trace_output_40 (tmp);
2526 }
2527
2528 /* slx */
2529 void
2530 OP_460B ()
2531 {
2532   int16 tmp;
2533   trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2534   tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2535   SET_GPR (OP[0], tmp);
2536   trace_output_16 (tmp);
2537 }
2538
2539 /* sra */
2540 void
2541 OP_2400 ()
2542 {
2543   int16 tmp;
2544   trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2545   tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2546   SET_GPR (OP[0], tmp);
2547   trace_output_16 (tmp);
2548 }
2549
2550 /* sra */
2551 void
2552 OP_3400 ()
2553 {
2554   trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2555   if ((GPR (OP[1]) & 31) <= 16)
2556     {
2557       int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2558       SET_ACC (OP[0], tmp);
2559       trace_output_40 (tmp);
2560     }
2561   else
2562     {
2563       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2564       State.exception = SIGILL;
2565       return;
2566     }
2567 }
2568
2569 /* srai */
2570 void
2571 OP_2401 ()
2572 {
2573   int16 tmp;
2574   trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2575   tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2576   SET_GPR (OP[0], tmp);
2577   trace_output_16 (tmp);
2578 }
2579
2580 /* srai */
2581 void
2582 OP_3401 ()
2583 {
2584   int64 tmp;
2585   if (OP[1] == 0)
2586     OP[1] = 16;
2587
2588   trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2589   tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2590   SET_ACC (OP[0], tmp);
2591   trace_output_40 (tmp);
2592 }
2593
2594 /* srl */
2595 void
2596 OP_2000 ()
2597 {
2598   int16 tmp;
2599   trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2600   tmp = (GPR (OP[0]) >>  (GPR (OP[1]) & 0xf));
2601   SET_GPR (OP[0], tmp);
2602   trace_output_16 (tmp);
2603 }
2604
2605 /* srl */
2606 void
2607 OP_3000 ()
2608 {
2609   trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2610   if ((GPR (OP[1]) & 31) <= 16)
2611     {
2612       int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2613       SET_ACC (OP[0], tmp);
2614       trace_output_40 (tmp);
2615     }
2616   else
2617     {
2618       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2619       State.exception = SIGILL;
2620       return;
2621     }
2622
2623 }
2624
2625 /* srli */
2626 void
2627 OP_2001 ()
2628 {
2629   int16 tmp;
2630   trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2631   tmp = (GPR (OP[0]) >> OP[1]);
2632   SET_GPR (OP[0], tmp);
2633   trace_output_16 (tmp);
2634 }
2635
2636 /* srli */
2637 void
2638 OP_3001 ()
2639 {
2640   int64 tmp;
2641   if (OP[1] == 0)
2642     OP[1] = 16;
2643
2644   trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2645   tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2646   SET_ACC (OP[0], tmp);
2647   trace_output_40 (tmp);
2648 }
2649
2650 /* srx */
2651 void
2652 OP_4609 ()
2653 {
2654   uint16 tmp;
2655   trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2656   tmp = PSW_F0 << 15;
2657   tmp = ((GPR (OP[0]) >> 1) | tmp);
2658   SET_GPR (OP[0], tmp);
2659   trace_output_16 (tmp);
2660 }
2661
2662 /* st */
2663 void
2664 OP_34000000 ()
2665 {
2666   trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2667   SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2668   trace_output_void ();
2669 }
2670
2671 /* st */
2672 void
2673 OP_6800 ()
2674 {
2675   trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2676   SW (GPR (OP[1]), GPR (OP[0]));
2677   trace_output_void ();
2678 }
2679
2680 /* st */
2681 void
2682 OP_6C1F ()
2683 {
2684   uint16 addr = GPR (OP[1]) - 2;
2685   trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2686   if (OP[1] != 15)
2687     {
2688       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2689       State.exception = SIGILL;
2690       return;
2691     }
2692   SW (addr, GPR (OP[0]));
2693   SET_GPR (OP[1], addr);
2694   trace_output_void ();
2695 }
2696
2697 /* st */
2698 void
2699 OP_6801 ()
2700 {
2701   trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2702   SW (GPR (OP[1]), GPR (OP[0]));
2703   INC_ADDR (OP[1], 2);
2704   trace_output_void ();
2705 }
2706
2707 /* st */
2708 void
2709 OP_6C01 ()
2710 {
2711   trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2712   if ( OP[1] == 15 )
2713     {
2714       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2715       State.exception = SIGILL;
2716       return;
2717     }
2718   SW (GPR (OP[1]), GPR (OP[0]));
2719   INC_ADDR (OP[1], -2);
2720   trace_output_void ();
2721 }
2722
2723 /* st */
2724 void
2725 OP_36010000 ()
2726 {
2727   trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2728   SW (OP[1], GPR (OP[0]));
2729   trace_output_void ();
2730 }
2731
2732 /* st2w */
2733 void
2734 OP_35000000 ()
2735 {
2736   trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2737   SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2738   SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2739   trace_output_void ();
2740 }
2741
2742 /* st2w */
2743 void
2744 OP_6A00 ()
2745 {
2746   trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2747   SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2748   SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2749   trace_output_void ();
2750 }
2751
2752 /* st2w */
2753 void
2754 OP_6E1F ()
2755 {
2756   uint16 addr = GPR (OP[1]) - 4;
2757   trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2758   if ( OP[1] != 15 )
2759     {
2760       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2761       State.exception = SIGILL;
2762       return;
2763     }
2764   SW (addr + 0, GPR (OP[0] + 0));
2765   SW (addr + 2, GPR (OP[0] + 1));
2766   SET_GPR (OP[1], addr);
2767   trace_output_void ();
2768 }
2769
2770 /* st2w */
2771 void
2772 OP_6A01 ()
2773 {
2774   trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2775   SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2776   SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2777   INC_ADDR (OP[1], 4);
2778   trace_output_void ();
2779 }
2780
2781 /* st2w */
2782 void
2783 OP_6E01 ()
2784 {
2785   trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2786   if ( OP[1] == 15 )
2787     {
2788       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2789       State.exception = SIGILL;
2790       return;
2791     }
2792   SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2793   SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2794   INC_ADDR (OP[1], -4);
2795   trace_output_void ();
2796 }
2797
2798 /* st2w */
2799 void
2800 OP_37010000 ()
2801 {
2802   trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2803   SW (OP [1] + 0, GPR (OP[0] + 0));
2804   SW (OP [1] + 2, GPR (OP[0] + 1));
2805   trace_output_void ();
2806 }
2807
2808 /* stb */
2809 void
2810 OP_3C000000 ()
2811 {
2812   trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2813   SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2814   trace_output_void ();
2815 }
2816
2817 /* stb */
2818 void
2819 OP_7800 ()
2820 {
2821   trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2822   SB (GPR (OP[1]), GPR (OP[0]));
2823   trace_output_void ();
2824 }
2825
2826 /* stop */
2827 void
2828 OP_5FE0 ()
2829 {
2830   trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2831   State.exception = SIG_D10V_STOP;
2832   trace_output_void ();
2833 }
2834
2835 /* sub */
2836 void
2837 OP_0 ()
2838 {
2839   uint16 a = GPR (OP[0]);
2840   uint16 b = GPR (OP[1]);
2841   uint16 tmp = (a - b);
2842   trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2843   /* see ../common/sim-alu.h for a more extensive discussion on how to
2844      compute the carry/overflow bits. */
2845   SET_PSW_C (a >= b);
2846   SET_GPR (OP[0], tmp);
2847   trace_output_16 (tmp);
2848 }
2849
2850 /* sub */
2851 void
2852 OP_1001 ()
2853 {
2854   int64 tmp;
2855
2856   trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2857   tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2858   if (PSW_ST)
2859     {
2860       if (tmp > SEXT40(MAX32))
2861         tmp = (MAX32);
2862       else if (tmp < SEXT40(MIN32))
2863         tmp = (MIN32);
2864       else
2865         tmp = (tmp & MASK40);
2866     }
2867   else
2868     tmp = (tmp & MASK40);
2869   SET_ACC (OP[0], tmp);
2870
2871   trace_output_40 (tmp);
2872 }
2873
2874 /* sub */
2875
2876 void
2877 OP_1003 ()
2878 {
2879   int64 tmp;
2880
2881   trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2882   tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2883   if (PSW_ST)
2884     {
2885       if (tmp > SEXT40(MAX32))
2886         tmp = (MAX32);
2887       else if (tmp < SEXT40(MIN32))
2888         tmp = (MIN32);
2889       else
2890         tmp = (tmp & MASK40);
2891     }
2892   else
2893     tmp = (tmp & MASK40);
2894   SET_ACC (OP[0], tmp);
2895
2896   trace_output_40 (tmp);
2897 }
2898
2899 /* sub2w */
2900 void
2901 OP_1000 ()
2902 {
2903   uint32 tmp, a, b;
2904
2905   trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2906   a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2907   b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2908   /* see ../common/sim-alu.h for a more extensive discussion on how to
2909      compute the carry/overflow bits */
2910   tmp = a - b;
2911   SET_PSW_C (a >= b);
2912   SET_GPR32 (OP[0], tmp);
2913   trace_output_32 (tmp);
2914 }
2915
2916 /* subac3 */
2917 void
2918 OP_17000000 ()
2919 {
2920   int64 tmp;
2921
2922   trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2923   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2924   SET_GPR32 (OP[0], tmp);
2925   trace_output_32 (tmp);
2926 }
2927
2928 /* subac3 */
2929 void
2930 OP_17000002 ()
2931 {
2932   int64 tmp;
2933
2934   trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2935   tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2936   SET_GPR32 (OP[0], tmp);
2937   trace_output_32 (tmp);
2938 }
2939
2940 /* subac3s */
2941 void
2942 OP_17001000 ()
2943 {
2944   int64 tmp;
2945
2946   trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2947   SET_PSW_F1 (PSW_F0);
2948   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2949   if (tmp > SEXT40(MAX32))
2950     {
2951       tmp = (MAX32);
2952       SET_PSW_F0 (1);
2953     }
2954   else if (tmp < SEXT40(MIN32))
2955     {
2956       tmp = (MIN32);
2957       SET_PSW_F0 (1);
2958     }
2959   else
2960     {
2961       SET_PSW_F0 (0);
2962     }
2963   SET_GPR32 (OP[0], tmp);
2964   trace_output_32 (tmp);
2965 }
2966
2967 /* subac3s */
2968 void
2969 OP_17001002 ()
2970 {
2971   int64 tmp;
2972
2973   trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2974   SET_PSW_F1 (PSW_F0);
2975   tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2976   if (tmp > SEXT40(MAX32))
2977     {
2978       tmp = (MAX32);
2979       SET_PSW_F0 (1);
2980     }
2981   else if (tmp < SEXT40(MIN32))
2982     {
2983       tmp = (MIN32);
2984       SET_PSW_F0 (1);
2985     }
2986   else
2987     {
2988       SET_PSW_F0 (0);
2989     }
2990   SET_GPR32 (OP[0], tmp);
2991   trace_output_32 (tmp);
2992 }
2993
2994 /* subi */
2995 void
2996 OP_1 ()
2997 {
2998   unsigned tmp;
2999   if (OP[1] == 0)
3000     OP[1] = 16;
3001
3002   trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3003   /* see ../common/sim-alu.h for a more extensive discussion on how to
3004      compute the carry/overflow bits. */
3005   /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3006   tmp = ((unsigned)(unsigned16) GPR (OP[0])
3007          + (unsigned)(unsigned16) ( - OP[1]));
3008   SET_PSW_C (tmp >= (1 << 16));
3009   SET_GPR (OP[0], tmp);
3010   trace_output_16 (tmp);
3011 }
3012
3013 /* trap */
3014 void
3015 OP_5F00 ()
3016 {
3017   trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3018   trace_output_void ();
3019
3020   switch (OP[0])
3021     {
3022     default:
3023 #if (DEBUG & DEBUG_TRAP) == 0
3024       {
3025         uint16 vec = OP[0] + TRAP_VECTOR_START;
3026         SET_BPC (PC + 1);
3027         SET_BPSW (PSW);
3028         SET_PSW (PSW & PSW_SM_BIT);
3029         JMP (vec);
3030         break;
3031       }
3032 #else                   /* if debugging use trap to print registers */
3033       {
3034         int i;
3035         static int first_time = 1;
3036
3037         if (first_time)
3038           {
3039             first_time = 0;
3040             (*d10v_callback->printf_filtered) (d10v_callback, "Trap  #     PC ");
3041             for (i = 0; i < 16; i++)
3042               (*d10v_callback->printf_filtered) (d10v_callback, "  %sr%d", (i > 9) ? "" : " ", i);
3043             (*d10v_callback->printf_filtered) (d10v_callback, "         a0         a1 f0 f1 c\n");
3044           }
3045
3046         (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3047
3048         for (i = 0; i < 16; i++)
3049           (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3050
3051         for (i = 0; i < 2; i++)
3052           (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3053                                              ((int)(ACC (i) >> 32) & 0xff),
3054                                              ((unsigned long) ACC (i)) & 0xffffffff);
3055
3056         (*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
3057                                            PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3058         (*d10v_callback->flush_stdout) (d10v_callback);
3059         break;
3060       }
3061 #endif
3062     case 15:                    /* new system call trap */
3063       /* Trap 15 is used for simulating low-level I/O */
3064       {
3065         unsigned32 result = 0;
3066         errno = 0;
3067
3068 /* Registers passed to trap 0 */
3069
3070 #define FUNC   GPR (4)  /* function number */
3071 #define PARM1  GPR (0)  /* optional parm 1 */
3072 #define PARM2  GPR (1)  /* optional parm 2 */
3073 #define PARM3  GPR (2)  /* optional parm 3 */
3074 #define PARM4  GPR (3)  /* optional parm 3 */
3075
3076 /* Registers set by trap 0 */
3077
3078 #define RETVAL(X)   do { result = (X); SET_GPR (0, result); } while (0)
3079 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3080 #define RETERR(X) SET_GPR (4, (X))              /* return error code */
3081
3082 /* Turn a pointer in a register into a pointer into real memory. */
3083
3084 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3085
3086         switch (FUNC)
3087           {
3088 #if !defined(__GO32__) && !defined(_WIN32)
3089           case TARGET_SYS_fork:
3090             trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3091             RETVAL (fork ());
3092             trace_output_16 (result);
3093             break;
3094
3095 #define getpid() 47
3096           case TARGET_SYS_getpid:
3097             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3098             RETVAL (getpid ());
3099             trace_output_16 (result);
3100             break;
3101
3102           case TARGET_SYS_kill:
3103             trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3104             if (PARM1 == getpid ())
3105               {
3106                 trace_output_void ();
3107                 State.exception = PARM2;
3108               }
3109             else
3110               {
3111                 int os_sig = -1;
3112                 switch (PARM2)
3113                   {
3114 #ifdef SIGHUP
3115                   case 1: os_sig = SIGHUP;      break;
3116 #endif
3117 #ifdef SIGINT
3118                   case 2: os_sig = SIGINT;      break;
3119 #endif
3120 #ifdef SIGQUIT
3121                   case 3: os_sig = SIGQUIT;     break;
3122 #endif
3123 #ifdef SIGILL
3124                   case 4: os_sig = SIGILL;      break;
3125 #endif
3126 #ifdef SIGTRAP
3127                   case 5: os_sig = SIGTRAP;     break;
3128 #endif
3129 #ifdef SIGABRT
3130                   case 6: os_sig = SIGABRT;     break;
3131 #elif defined(SIGIOT)
3132                   case 6: os_sig = SIGIOT;      break;
3133 #endif
3134 #ifdef SIGEMT
3135                   case 7: os_sig = SIGEMT;      break;
3136 #endif
3137 #ifdef SIGFPE
3138                   case 8: os_sig = SIGFPE;      break;
3139 #endif
3140 #ifdef SIGKILL
3141                   case 9: os_sig = SIGKILL;     break;
3142 #endif
3143 #ifdef SIGBUS
3144                   case 10: os_sig = SIGBUS;     break;
3145 #endif
3146 #ifdef SIGSEGV
3147                   case 11: os_sig = SIGSEGV;    break;
3148 #endif
3149 #ifdef SIGSYS
3150                   case 12: os_sig = SIGSYS;     break;
3151 #endif
3152 #ifdef SIGPIPE
3153                   case 13: os_sig = SIGPIPE;    break;
3154 #endif
3155 #ifdef SIGALRM
3156                   case 14: os_sig = SIGALRM;    break;
3157 #endif
3158 #ifdef SIGTERM
3159                   case 15: os_sig = SIGTERM;    break;
3160 #endif
3161 #ifdef SIGURG
3162                   case 16: os_sig = SIGURG;     break;
3163 #endif
3164 #ifdef SIGSTOP
3165                   case 17: os_sig = SIGSTOP;    break;
3166 #endif
3167 #ifdef SIGTSTP
3168                   case 18: os_sig = SIGTSTP;    break;
3169 #endif
3170 #ifdef SIGCONT
3171                   case 19: os_sig = SIGCONT;    break;
3172 #endif
3173 #ifdef SIGCHLD
3174                   case 20: os_sig = SIGCHLD;    break;
3175 #elif defined(SIGCLD)
3176                   case 20: os_sig = SIGCLD;     break;
3177 #endif
3178 #ifdef SIGTTIN
3179                   case 21: os_sig = SIGTTIN;    break;
3180 #endif
3181 #ifdef SIGTTOU
3182                   case 22: os_sig = SIGTTOU;    break;
3183 #endif
3184 #ifdef SIGIO
3185                   case 23: os_sig = SIGIO;      break;
3186 #elif defined (SIGPOLL)
3187                   case 23: os_sig = SIGPOLL;    break;
3188 #endif
3189 #ifdef SIGXCPU
3190                   case 24: os_sig = SIGXCPU;    break;
3191 #endif
3192 #ifdef SIGXFSZ
3193                   case 25: os_sig = SIGXFSZ;    break;
3194 #endif
3195 #ifdef SIGVTALRM
3196                   case 26: os_sig = SIGVTALRM;  break;
3197 #endif
3198 #ifdef SIGPROF
3199                   case 27: os_sig = SIGPROF;    break;
3200 #endif
3201 #ifdef SIGWINCH
3202                   case 28: os_sig = SIGWINCH;   break;
3203 #endif
3204 #ifdef SIGLOST
3205                   case 29: os_sig = SIGLOST;    break;
3206 #endif
3207 #ifdef SIGUSR1
3208                   case 30: os_sig = SIGUSR1;    break;
3209 #endif
3210 #ifdef SIGUSR2
3211                   case 31: os_sig = SIGUSR2;    break;
3212 #endif
3213                   }
3214
3215                 if (os_sig == -1)
3216                   {
3217                     trace_output_void ();
3218                     (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3219                     (*d10v_callback->flush_stdout) (d10v_callback);
3220                     State.exception = SIGILL;
3221                   }
3222                 else
3223                   {
3224                     RETVAL (kill (PARM1, PARM2));
3225                     trace_output_16 (result);
3226                   }
3227               }
3228             break;
3229
3230           case TARGET_SYS_execve:
3231             trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3232             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3233                              (char **)MEMPTR (PARM3)));
3234             trace_output_16 (result);
3235             break;
3236
3237 #ifdef TARGET_SYS_execv
3238           case TARGET_SYS_execv:
3239             trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3240             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3241             trace_output_16 (result);
3242             break;
3243 #endif
3244
3245           case TARGET_SYS_pipe:
3246             {
3247               reg_t buf;
3248               int host_fd[2];
3249
3250               trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3251               buf = PARM1;
3252               RETVAL (pipe (host_fd));
3253               SW (buf, host_fd[0]);
3254               buf += sizeof(uint16);
3255               SW (buf, host_fd[1]);
3256               trace_output_16 (result);
3257             }
3258           break;
3259
3260 #if 0
3261 #ifdef TARGET_SYS_wait
3262           case TARGET_SYS_wait:
3263             {
3264               int status;
3265               trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3266               RETVAL (wait (&status));
3267               if (PARM1)
3268                 SW (PARM1, status);
3269               trace_output_16 (result);
3270             }
3271           break;
3272 #endif
3273 #endif
3274 #else
3275           case TARGET_SYS_getpid:
3276             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3277             RETVAL (1);
3278             trace_output_16 (result);
3279             break;
3280
3281           case TARGET_SYS_kill:
3282             trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3283             trace_output_void ();
3284             State.exception = PARM2;
3285             break;
3286 #endif
3287
3288           case TARGET_SYS_read:
3289             trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3290             RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3291                                           PARM3));
3292             trace_output_16 (result);
3293             break;
3294
3295           case TARGET_SYS_write:
3296             trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3297             if (PARM1 == 1)
3298               RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3299                                                          MEMPTR (PARM2), PARM3));
3300             else
3301               RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3302                                                   MEMPTR (PARM2), PARM3));
3303             trace_output_16 (result);
3304             break;
3305
3306           case TARGET_SYS_lseek:
3307             trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3308             RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3309                                             ((((unsigned long) PARM2) << 16)
3310                                              || (unsigned long) PARM3),
3311                                             PARM4));
3312             trace_output_32 (result);
3313             break;
3314
3315           case TARGET_SYS_close:
3316             trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3317             RETVAL (d10v_callback->close (d10v_callback, PARM1));
3318             trace_output_16 (result);
3319             break;
3320
3321           case TARGET_SYS_open:
3322             trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3323             RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3324             trace_output_16 (result);
3325             break;
3326
3327           case TARGET_SYS_exit:
3328             trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3329             State.exception = SIG_D10V_EXIT;
3330             trace_output_void ();
3331             break;
3332
3333 #ifdef TARGET_SYS_stat
3334           case TARGET_SYS_stat:
3335             trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3336             /* stat system call */
3337             {
3338               struct stat host_stat;
3339               reg_t buf;
3340
3341               RETVAL (stat (MEMPTR (PARM1), &host_stat));
3342
3343               buf = PARM2;
3344
3345               /* The hard-coded offsets and sizes were determined by using
3346                * the D10V compiler on a test program that used struct stat.
3347                */
3348               SW  (buf,    host_stat.st_dev);
3349               SW  (buf+2,  host_stat.st_ino);
3350               SW  (buf+4,  host_stat.st_mode);
3351               SW  (buf+6,  host_stat.st_nlink);
3352               SW  (buf+8,  host_stat.st_uid);
3353               SW  (buf+10, host_stat.st_gid);
3354               SW  (buf+12, host_stat.st_rdev);
3355               SLW (buf+16, host_stat.st_size);
3356               SLW (buf+20, host_stat.st_atime);
3357               SLW (buf+28, host_stat.st_mtime);
3358               SLW (buf+36, host_stat.st_ctime);
3359             }
3360             trace_output_16 (result);
3361             break;
3362 #endif
3363
3364           case TARGET_SYS_chown:
3365             trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3366             RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3367             trace_output_16 (result);
3368             break;
3369
3370           case TARGET_SYS_chmod:
3371             trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3372             RETVAL (chmod (MEMPTR (PARM1), PARM2));
3373             trace_output_16 (result);
3374             break;
3375
3376 #if 0
3377 #ifdef TARGET_SYS_utime
3378           case TARGET_SYS_utime:
3379             trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3380             /* Cast the second argument to void *, to avoid type mismatch
3381                if a prototype is present.  */
3382             RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3383             trace_output_16 (result);
3384             break;
3385 #endif
3386 #endif
3387
3388 #if 0
3389 #ifdef TARGET_SYS_time
3390           case TARGET_SYS_time:
3391             trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3392             RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3393             trace_output_32 (result);
3394             break;
3395 #endif
3396 #endif
3397
3398           default:
3399             d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3400           }
3401         if ((uint16) result == (uint16) -1)
3402           RETERR (d10v_callback->get_errno(d10v_callback));
3403         else
3404           RETERR (0);
3405         break;
3406       }
3407     }
3408 }
3409
3410 /* tst0i */
3411 void
3412 OP_7000000 ()
3413 {
3414   trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3415   SET_PSW_F1 (PSW_F0);;
3416   SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3417   trace_output_flag ();
3418 }
3419
3420 /* tst1i */
3421 void
3422 OP_F000000 ()
3423 {
3424   trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3425   SET_PSW_F1 (PSW_F0);
3426   SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3427   trace_output_flag ();
3428 }
3429
3430 /* wait */
3431 void
3432 OP_5F80 ()
3433 {
3434   trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3435   SET_PSW_IE (1);
3436   trace_output_void ();
3437 }
3438
3439 /* xor */
3440 void
3441 OP_A00 ()
3442 {
3443   int16 tmp;
3444   trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3445   tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3446   SET_GPR (OP[0], tmp);
3447   trace_output_16 (tmp);
3448 }
3449
3450 /* xor3 */
3451 void
3452 OP_5000000 ()
3453 {
3454   int16 tmp;
3455   trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3456   tmp = (GPR (OP[1]) ^ OP[2]);
3457   SET_GPR (OP[0], tmp);
3458   trace_output_16 (tmp);
3459 }