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[deliverable/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "sys/syscall.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R0,
41 OP_R1,
42 OP_R2,
43 OP_R0R1
44 };
45
46
47 void
48 move_to_cr (int cr, reg_t val)
49 {
50 switch (cr)
51 {
52 case PSW_CR:
53 State.sp[State.SM] = State.regs[SP_IDX]; /* save old SP */
54 State.SM = (val & PSW_SM_BIT) != 0;
55 State.EA = (val & PSW_EA_BIT) != 0;
56 State.DB = (val & PSW_DB_BIT) != 0;
57 State.DM = (val & PSW_DM_BIT) != 0;
58 State.IE = (val & PSW_IE_BIT) != 0;
59 State.RP = (val & PSW_RP_BIT) != 0;
60 State.MD = (val & PSW_MD_BIT) != 0;
61 State.FX = (val & PSW_FX_BIT) != 0;
62 State.ST = (val & PSW_ST_BIT) != 0;
63 State.F0 = (val & PSW_F0_BIT) != 0;
64 State.F1 = (val & PSW_F1_BIT) != 0;
65 State.C = (val & PSW_C_BIT) != 0;
66 State.regs[SP_IDX] = State.sp[State.SM]; /* restore new SP */
67 if (State.ST && !State.FX)
68 {
69 (*d10v_callback->printf_filtered)
70 (d10v_callback,
71 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
72 PC<<2);
73 State.exception = SIGILL;
74 }
75 State.cregs[cr] = (val & ~0x4032);
76 break;
77 case BPSW_CR:
78 case DPSW_CR:
79 State.cregs[cr] = (val & ~0x4032);
80 break;
81 case MOD_S_CR:
82 case MOD_E_CR:
83 State.cregs[cr] = (val & ~0x1);
84 break;
85 default:
86 State.cregs[cr] = val;
87 break;
88 }
89 }
90
91 reg_t
92 move_from_cr (int cr)
93 {
94 reg_t val = 0;
95 switch (cr)
96 {
97 case PSW_CR:
98 if (State.SM) val |= PSW_SM_BIT;
99 if (State.EA) val |= PSW_EA_BIT;
100 if (State.DB) val |= PSW_DB_BIT;
101 if (State.DM) val |= PSW_DM_BIT;
102 if (State.IE) val |= PSW_IE_BIT;
103 if (State.RP) val |= PSW_RP_BIT;
104 if (State.MD) val |= PSW_MD_BIT;
105 if (State.FX) val |= PSW_FX_BIT;
106 if (State.ST) val |= PSW_ST_BIT;
107 if (State.F0) val |= PSW_F0_BIT;
108 if (State.F1) val |= PSW_F1_BIT;
109 if (State.C) val |= PSW_C_BIT;
110 break;
111 default:
112 val = State.cregs[cr];
113 break;
114 }
115 return val;
116 }
117
118
119 #ifdef DEBUG
120 static void trace_input_func PARAMS ((char *name,
121 enum op_types in1,
122 enum op_types in2,
123 enum op_types in3));
124
125 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
126
127 static void trace_output_func PARAMS ((enum op_types result));
128
129 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
130
131 #ifndef SIZE_INSTRUCTION
132 #define SIZE_INSTRUCTION 8
133 #endif
134
135 #ifndef SIZE_OPERANDS
136 #define SIZE_OPERANDS 18
137 #endif
138
139 #ifndef SIZE_VALUES
140 #define SIZE_VALUES 13
141 #endif
142
143 #ifndef SIZE_LOCATION
144 #define SIZE_LOCATION 20
145 #endif
146
147 #ifndef SIZE_PC
148 #define SIZE_PC 6
149 #endif
150
151 #ifndef SIZE_LINE_NUMBER
152 #define SIZE_LINE_NUMBER 4
153 #endif
154
155 static void
156 trace_input_func (name, in1, in2, in3)
157 char *name;
158 enum op_types in1;
159 enum op_types in2;
160 enum op_types in3;
161 {
162 char *comma;
163 enum op_types in[3];
164 int i;
165 char buf[1024];
166 char *p;
167 long tmp;
168 char *type;
169 const char *filename;
170 const char *functionname;
171 unsigned int linenumber;
172 bfd_vma byte_pc;
173
174 if ((d10v_debug & DEBUG_TRACE) == 0)
175 return;
176
177 switch (State.ins_type)
178 {
179 default:
180 case INS_UNKNOWN: type = " ?"; break;
181 case INS_LEFT: type = " L"; break;
182 case INS_RIGHT: type = " R"; break;
183 case INS_LEFT_PARALLEL: type = "*L"; break;
184 case INS_RIGHT_PARALLEL: type = "*R"; break;
185 case INS_LEFT_COND_TEST: type = "?L"; break;
186 case INS_RIGHT_COND_TEST: type = "?R"; break;
187 case INS_LEFT_COND_EXE: type = "&L"; break;
188 case INS_RIGHT_COND_EXE: type = "&R"; break;
189 case INS_LONG: type = " B"; break;
190 }
191
192 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
193 (*d10v_callback->printf_filtered) (d10v_callback,
194 "0x%.*x %s: %-*s ",
195 SIZE_PC, (unsigned)PC,
196 type,
197 SIZE_INSTRUCTION, name);
198
199 else
200 {
201 buf[0] = '\0';
202 byte_pc = decode_pc ();
203 if (text && byte_pc >= text_start && byte_pc < text_end)
204 {
205 filename = (const char *)0;
206 functionname = (const char *)0;
207 linenumber = 0;
208 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
209 &filename, &functionname, &linenumber))
210 {
211 p = buf;
212 if (linenumber)
213 {
214 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
215 p += strlen (p);
216 }
217 else
218 {
219 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
220 p += SIZE_LINE_NUMBER+2;
221 }
222
223 if (functionname)
224 {
225 sprintf (p, "%s ", functionname);
226 p += strlen (p);
227 }
228 else if (filename)
229 {
230 char *q = strrchr (filename, '/');
231 sprintf (p, "%s ", (q) ? q+1 : filename);
232 p += strlen (p);
233 }
234
235 if (*p == ' ')
236 *p = '\0';
237 }
238 }
239
240 (*d10v_callback->printf_filtered) (d10v_callback,
241 "0x%.*x %s: %-*.*s %-*s ",
242 SIZE_PC, (unsigned)PC,
243 type,
244 SIZE_LOCATION, SIZE_LOCATION, buf,
245 SIZE_INSTRUCTION, name);
246 }
247
248 in[0] = in1;
249 in[1] = in2;
250 in[2] = in3;
251 comma = "";
252 p = buf;
253 for (i = 0; i < 3; i++)
254 {
255 switch (in[i])
256 {
257 case OP_VOID:
258 case OP_R0:
259 case OP_R1:
260 case OP_R2:
261 case OP_R0R1:
262 break;
263
264 case OP_REG:
265 case OP_REG_OUTPUT:
266 case OP_DREG:
267 case OP_DREG_OUTPUT:
268 sprintf (p, "%sr%d", comma, OP[i]);
269 p += strlen (p);
270 comma = ",";
271 break;
272
273 case OP_CR:
274 case OP_CR_OUTPUT:
275 case OP_CR_REVERSE:
276 sprintf (p, "%scr%d", comma, OP[i]);
277 p += strlen (p);
278 comma = ",";
279 break;
280
281 case OP_ACCUM:
282 case OP_ACCUM_OUTPUT:
283 case OP_ACCUM_REVERSE:
284 sprintf (p, "%sa%d", comma, OP[i]);
285 p += strlen (p);
286 comma = ",";
287 break;
288
289 case OP_CONSTANT16:
290 sprintf (p, "%s%d", comma, OP[i]);
291 p += strlen (p);
292 comma = ",";
293 break;
294
295 case OP_CONSTANT8:
296 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
297 p += strlen (p);
298 comma = ",";
299 break;
300
301 case OP_CONSTANT4:
302 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
303 p += strlen (p);
304 comma = ",";
305 break;
306
307 case OP_CONSTANT3:
308 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
309 p += strlen (p);
310 comma = ",";
311 break;
312
313 case OP_MEMREF:
314 sprintf (p, "%s@r%d", comma, OP[i]);
315 p += strlen (p);
316 comma = ",";
317 break;
318
319 case OP_MEMREF2:
320 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
321 p += strlen (p);
322 comma = ",";
323 break;
324
325 case OP_POSTINC:
326 sprintf (p, "%s@r%d+", comma, OP[i]);
327 p += strlen (p);
328 comma = ",";
329 break;
330
331 case OP_POSTDEC:
332 sprintf (p, "%s@r%d-", comma, OP[i]);
333 p += strlen (p);
334 comma = ",";
335 break;
336
337 case OP_PREDEC:
338 sprintf (p, "%s@-r%d", comma, OP[i]);
339 p += strlen (p);
340 comma = ",";
341 break;
342
343 case OP_FLAG:
344 case OP_FLAG_OUTPUT:
345 if (OP[i] == 0)
346 sprintf (p, "%sf0", comma);
347
348 else if (OP[i] == 1)
349 sprintf (p, "%sf1", comma);
350
351 else
352 sprintf (p, "%sc", comma);
353
354 p += strlen (p);
355 comma = ",";
356 break;
357 }
358 }
359
360 if ((d10v_debug & DEBUG_VALUES) == 0)
361 {
362 *p++ = '\n';
363 *p = '\0';
364 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
365 }
366 else
367 {
368 *p = '\0';
369 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
370
371 p = buf;
372 for (i = 0; i < 3; i++)
373 {
374 buf[0] = '\0';
375 switch (in[i])
376 {
377 case OP_VOID:
378 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
379 break;
380
381 case OP_REG_OUTPUT:
382 case OP_DREG_OUTPUT:
383 case OP_CR_OUTPUT:
384 case OP_ACCUM_OUTPUT:
385 case OP_FLAG_OUTPUT:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
387 break;
388
389 case OP_REG:
390 case OP_MEMREF:
391 case OP_POSTDEC:
392 case OP_POSTINC:
393 case OP_PREDEC:
394 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
395 (uint16)State.regs[OP[i]]);
396 break;
397
398 case OP_DREG:
399 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
400 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
401 break;
402
403 case OP_CR:
404 case OP_CR_REVERSE:
405 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
406 (uint16)State.cregs[OP[i]]);
407 break;
408
409 case OP_ACCUM:
410 case OP_ACCUM_REVERSE:
411 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
412 ((int)(State.a[OP[i]] >> 32) & 0xff),
413 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
414 break;
415
416 case OP_CONSTANT16:
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)OP[i]);
419 break;
420
421 case OP_CONSTANT4:
422 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
423 (uint16)SEXT4(OP[i]));
424 break;
425
426 case OP_CONSTANT8:
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
428 (uint16)SEXT8(OP[i]));
429 break;
430
431 case OP_CONSTANT3:
432 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
433 (uint16)SEXT3(OP[i]));
434 break;
435
436 case OP_FLAG:
437 if (OP[i] == 0)
438 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
439 State.F0 != 0);
440
441 else if (OP[i] == 1)
442 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
443 State.F1 != 0);
444
445 else
446 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
447 State.C != 0);
448
449 break;
450
451 case OP_MEMREF2:
452 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
453 (uint16)OP[i]);
454 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
455 (uint16)State.regs[OP[++i]]);
456 break;
457
458 case OP_R0:
459 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
460 (uint16)State.regs[0]);
461 break;
462
463 case OP_R1:
464 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
465 (uint16)State.regs[1]);
466 break;
467
468 case OP_R2:
469 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
470 (uint16)State.regs[2]);
471 break;
472
473 case OP_R0R1:
474 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
475 (uint16)State.regs[0]);
476 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
477 (uint16)State.regs[1]);
478 i++;
479 break;
480 }
481 }
482 }
483
484 (*d10v_callback->flush_stdout) (d10v_callback);
485 }
486
487 static void
488 trace_output_func (result)
489 enum op_types result;
490 {
491 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
492 {
493 long tmp;
494
495 switch (result)
496 {
497 default:
498 putchar ('\n');
499 break;
500
501 case OP_REG:
502 case OP_REG_OUTPUT:
503 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
504 (uint16)State.regs[OP[0]],
505 State.F0 != 0, State.F1 != 0, State.C != 0);
506 break;
507
508 case OP_DREG:
509 case OP_DREG_OUTPUT:
510 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
511 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
512 State.F0 != 0, State.F1 != 0, State.C != 0);
513 break;
514
515 case OP_CR:
516 case OP_CR_OUTPUT:
517 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
518 (uint16)State.cregs[OP[0]],
519 State.F0 != 0, State.F1 != 0, State.C != 0);
520 break;
521
522 case OP_CR_REVERSE:
523 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
524 (uint16)State.cregs[OP[1]],
525 State.F0 != 0, State.F1 != 0, State.C != 0);
526 break;
527
528 case OP_ACCUM:
529 case OP_ACCUM_OUTPUT:
530 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
531 ((int)(State.a[OP[0]] >> 32) & 0xff),
532 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
533 State.F0 != 0, State.F1 != 0, State.C != 0);
534 break;
535
536 case OP_ACCUM_REVERSE:
537 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
538 ((int)(State.a[OP[1]] >> 32) & 0xff),
539 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
540 State.F0 != 0, State.F1 != 0, State.C != 0);
541 break;
542
543 case OP_FLAG:
544 case OP_FLAG_OUTPUT:
545 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
546 State.F0 != 0, State.F1 != 0, State.C != 0);
547 break;
548
549 case OP_R0:
550 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
551 (uint16)State.regs[0],
552 State.F0 != 0, State.F1 != 0, State.C != 0);
553 break;
554
555 case OP_R0R1:
556 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
557 (uint16)State.regs[0], (uint16)State.regs[1],
558 State.F0 != 0, State.F1 != 0, State.C != 0);
559 break;
560 }
561 }
562
563 (*d10v_callback->flush_stdout) (d10v_callback);
564 }
565
566 #else
567 #define trace_input(NAME, IN1, IN2, IN3)
568 #define trace_output(RESULT)
569 #endif
570
571 /* abs */
572 void
573 OP_4607 ()
574 {
575 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
576 State.F1 = State.F0;
577 if ((int16)(State.regs[OP[0]]) < 0)
578 {
579 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
580 State.F0 = 1;
581 }
582 else
583 State.F0 = 0;
584 trace_output (OP_REG);
585 }
586
587 /* abs */
588 void
589 OP_5607 ()
590 {
591 int64 tmp;
592
593 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
594 State.F1 = State.F0;
595 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
596
597 if (State.a[OP[0]] < 0 )
598 {
599 tmp = -State.a[OP[0]];
600 if (State.ST)
601 {
602 if (tmp > MAX32)
603 State.a[OP[0]] = MAX32;
604 else if (tmp < MIN32)
605 State.a[OP[0]] = MIN32;
606 else
607 State.a[OP[0]] = tmp & MASK40;
608 }
609 else
610 State.a[OP[0]] = tmp & MASK40;
611 State.F0 = 1;
612 }
613 else
614 State.F0 = 0;
615 trace_output (OP_ACCUM);
616 }
617
618 /* add */
619 void
620 OP_200 ()
621 {
622 uint16 tmp = State.regs[OP[0]];
623 trace_input ("add", OP_REG, OP_REG, OP_VOID);
624 State.regs[OP[0]] += State.regs[OP[1]];
625 if ( tmp > State.regs[OP[0]])
626 State.C = 1;
627 else
628 State.C = 0;
629 trace_output (OP_REG);
630 }
631
632 /* add */
633 void
634 OP_1201 ()
635 {
636 int64 tmp;
637 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
638
639 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
640 if (State.ST)
641 {
642 if ( tmp > MAX32)
643 State.a[OP[0]] = MAX32;
644 else if ( tmp < MIN32)
645 State.a[OP[0]] = MIN32;
646 else
647 State.a[OP[0]] = tmp & MASK40;
648 }
649 else
650 State.a[OP[0]] = tmp & MASK40;
651 trace_output (OP_ACCUM);
652 }
653
654 /* add */
655 void
656 OP_1203 ()
657 {
658 int64 tmp;
659 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
660
661 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
662 if (State.ST)
663 {
664 if (tmp > MAX32)
665 State.a[OP[0]] = MAX32;
666 else if ( tmp < MIN32)
667 State.a[OP[0]] = MIN32;
668 else
669 State.a[OP[0]] = tmp & MASK40;
670 }
671 else
672 State.a[OP[0]] = tmp & MASK40;
673 trace_output (OP_ACCUM);
674 }
675
676 /* add2w */
677 void
678 OP_1200 ()
679 {
680 uint32 tmp;
681 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
682 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
683
684 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
685 tmp = a + b;
686 State.C = (tmp < a);
687 State.regs[OP[0]] = tmp >> 16;
688 State.regs[OP[0]+1] = tmp & 0xFFFF;
689 trace_output (OP_DREG);
690 }
691
692 /* add3 */
693 void
694 OP_1000000 ()
695 {
696 uint16 tmp = State.regs[OP[1]];
697 State.regs[OP[0]] = tmp + OP[2];
698
699 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
700 State.C = (State.regs[OP[0]] < tmp);
701 trace_output (OP_REG);
702 }
703
704 /* addac3 */
705 void
706 OP_17000200 ()
707 {
708 int64 tmp;
709 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
710
711 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
712 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
713 State.regs[OP[0]+1] = tmp & 0xffff;
714 trace_output (OP_DREG);
715 }
716
717 /* addac3 */
718 void
719 OP_17000202 ()
720 {
721 int64 tmp;
722 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
723
724 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
725 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
726 State.regs[OP[0]+1] = tmp & 0xffff;
727 trace_output (OP_DREG);
728 }
729
730 /* addac3s */
731 void
732 OP_17001200 ()
733 {
734 int64 tmp;
735 State.F1 = State.F0;
736
737 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
738 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
739 if ( tmp > MAX32)
740 {
741 State.regs[OP[0]] = 0x7fff;
742 State.regs[OP[0]+1] = 0xffff;
743 State.F0 = 1;
744 }
745 else if (tmp < MIN32)
746 {
747 State.regs[OP[0]] = 0x8000;
748 State.regs[OP[0]+1] = 0;
749 State.F0 = 1;
750 }
751 else
752 {
753 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
754 State.regs[OP[0]+1] = tmp & 0xffff;
755 State.F0 = 0;
756 }
757 trace_output (OP_DREG);
758 }
759
760 /* addac3s */
761 void
762 OP_17001202 ()
763 {
764 int64 tmp;
765 State.F1 = State.F0;
766
767 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
768 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
769 if ( tmp > MAX32)
770 {
771 State.regs[OP[0]] = 0x7fff;
772 State.regs[OP[0]+1] = 0xffff;
773 State.F0 = 1;
774 }
775 else if (tmp < MIN32)
776 {
777 State.regs[OP[0]] = 0x8000;
778 State.regs[OP[0]+1] = 0;
779 State.F0 = 1;
780 }
781 else
782 {
783 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
784 State.regs[OP[0]+1] = tmp & 0xffff;
785 State.F0 = 0;
786 }
787 trace_output (OP_DREG);
788 }
789
790 /* addi */
791 void
792 OP_201 ()
793 {
794 uint tmp = State.regs[OP[0]];
795 if (OP[1] == 0)
796 OP[1] = 16;
797
798 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
799 State.regs[OP[0]] += OP[1];
800 State.C = (State.regs[OP[0]] < tmp);
801 trace_output (OP_REG);
802 }
803
804 /* and */
805 void
806 OP_C00 ()
807 {
808 trace_input ("and", OP_REG, OP_REG, OP_VOID);
809 State.regs[OP[0]] &= State.regs[OP[1]];
810 trace_output (OP_REG);
811 }
812
813 /* and3 */
814 void
815 OP_6000000 ()
816 {
817 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
818 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
819 trace_output (OP_REG);
820 }
821
822 /* bclri */
823 void
824 OP_C01 ()
825 {
826 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
827 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
828 trace_output (OP_REG);
829 }
830
831 /* bl.s */
832 void
833 OP_4900 ()
834 {
835 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
836 State.regs[13] = PC+1;
837 JMP( PC + SEXT8 (OP[0]));
838 trace_output (OP_VOID);
839 }
840
841 /* bl.l */
842 void
843 OP_24800000 ()
844 {
845 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
846 State.regs[13] = PC+1;
847 JMP (PC + OP[0]);
848 trace_output (OP_VOID);
849 }
850
851 /* bnoti */
852 void
853 OP_A01 ()
854 {
855 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
856 State.regs[OP[0]] ^= 0x8000 >> OP[1];
857 trace_output (OP_REG);
858 }
859
860 /* bra.s */
861 void
862 OP_4800 ()
863 {
864 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
865 JMP (PC + SEXT8 (OP[0]));
866 trace_output (OP_VOID);
867 }
868
869 /* bra.l */
870 void
871 OP_24000000 ()
872 {
873 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
874 JMP (PC + OP[0]);
875 trace_output (OP_VOID);
876 }
877
878 /* brf0f.s */
879 void
880 OP_4A00 ()
881 {
882 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
883 if (State.F0 == 0)
884 JMP (PC + SEXT8 (OP[0]));
885 trace_output (OP_FLAG);
886 }
887
888 /* brf0f.l */
889 void
890 OP_25000000 ()
891 {
892 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
893 if (State.F0 == 0)
894 JMP (PC + OP[0]);
895 trace_output (OP_FLAG);
896 }
897
898 /* brf0t.s */
899 void
900 OP_4B00 ()
901 {
902 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
903 if (State.F0)
904 JMP (PC + SEXT8 (OP[0]));
905 trace_output (OP_FLAG);
906 }
907
908 /* brf0t.l */
909 void
910 OP_25800000 ()
911 {
912 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
913 if (State.F0)
914 JMP (PC + OP[0]);
915 trace_output (OP_FLAG);
916 }
917
918 /* bseti */
919 void
920 OP_801 ()
921 {
922 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
923 State.regs[OP[0]] |= 0x8000 >> OP[1];
924 trace_output (OP_REG);
925 }
926
927 /* btsti */
928 void
929 OP_E01 ()
930 {
931 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
932 State.F1 = State.F0;
933 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
934 trace_output (OP_FLAG);
935 }
936
937 /* clrac */
938 void
939 OP_5601 ()
940 {
941 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
942 State.a[OP[0]] = 0;
943 trace_output (OP_ACCUM);
944 }
945
946 /* cmp */
947 void
948 OP_600 ()
949 {
950 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
951 State.F1 = State.F0;
952 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
953 trace_output (OP_FLAG);
954 }
955
956 /* cmp */
957 void
958 OP_1603 ()
959 {
960 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
961 State.F1 = State.F0;
962 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
963 trace_output (OP_FLAG);
964 }
965
966 /* cmpeq */
967 void
968 OP_400 ()
969 {
970 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
971 State.F1 = State.F0;
972 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
973 trace_output (OP_FLAG);
974 }
975
976 /* cmpeq */
977 void
978 OP_1403 ()
979 {
980 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
981 State.F1 = State.F0;
982 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
983 trace_output (OP_FLAG);
984 }
985
986 /* cmpeqi.s */
987 void
988 OP_401 ()
989 {
990 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
991 State.F1 = State.F0;
992 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
993 trace_output (OP_FLAG);
994 }
995
996 /* cmpeqi.l */
997 void
998 OP_2000000 ()
999 {
1000 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1001 State.F1 = State.F0;
1002 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
1003 trace_output (OP_FLAG);
1004 }
1005
1006 /* cmpi.s */
1007 void
1008 OP_601 ()
1009 {
1010 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1011 State.F1 = State.F0;
1012 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
1013 trace_output (OP_FLAG);
1014 }
1015
1016 /* cmpi.l */
1017 void
1018 OP_3000000 ()
1019 {
1020 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1021 State.F1 = State.F0;
1022 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
1023 trace_output (OP_FLAG);
1024 }
1025
1026 /* cmpu */
1027 void
1028 OP_4600 ()
1029 {
1030 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1031 State.F1 = State.F0;
1032 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
1033 trace_output (OP_FLAG);
1034 }
1035
1036 /* cmpui */
1037 void
1038 OP_23000000 ()
1039 {
1040 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1041 State.F1 = State.F0;
1042 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
1043 trace_output (OP_FLAG);
1044 }
1045
1046 /* cpfg */
1047 void
1048 OP_4E09 ()
1049 {
1050 uint8 *src, *dst;
1051
1052 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1053 if (OP[0] == 0)
1054 dst = &State.F0;
1055 else
1056 dst = &State.F1;
1057
1058 if (OP[1] == 0)
1059 src = &State.F0;
1060 else if (OP[1] == 1)
1061 src = &State.F1;
1062 else
1063 src = &State.C;
1064
1065 *dst = *src;
1066 trace_output (OP_FLAG);
1067 }
1068
1069 /* dbt */
1070 void
1071 OP_5F20 ()
1072 {
1073 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1074 State.exception = SIGTRAP;
1075 }
1076
1077 /* divs */
1078 void
1079 OP_14002800 ()
1080 {
1081 uint16 foo, tmp, tmpf;
1082
1083 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1084 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1085 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1086 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1087 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1088 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1089 trace_output (OP_DREG);
1090 }
1091
1092 /* exef0f */
1093 void
1094 OP_4E04 ()
1095 {
1096 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1097 State.exe = (State.F0 == 0);
1098 trace_output (OP_FLAG);
1099 }
1100
1101 /* exef0t */
1102 void
1103 OP_4E24 ()
1104 {
1105 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1106 State.exe = (State.F0 != 0);
1107 trace_output (OP_FLAG);
1108 }
1109
1110 /* exef1f */
1111 void
1112 OP_4E40 ()
1113 {
1114 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1115 State.exe = (State.F1 == 0);
1116 trace_output (OP_FLAG);
1117 }
1118
1119 /* exef1t */
1120 void
1121 OP_4E42 ()
1122 {
1123 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1124 State.exe = (State.F1 != 0);
1125 trace_output (OP_FLAG);
1126 }
1127
1128 /* exefaf */
1129 void
1130 OP_4E00 ()
1131 {
1132 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1133 State.exe = (State.F0 == 0) & (State.F1 == 0);
1134 trace_output (OP_FLAG);
1135 }
1136
1137 /* exefat */
1138 void
1139 OP_4E02 ()
1140 {
1141 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1142 State.exe = (State.F0 == 0) & (State.F1 != 0);
1143 trace_output (OP_FLAG);
1144 }
1145
1146 /* exetaf */
1147 void
1148 OP_4E20 ()
1149 {
1150 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1151 State.exe = (State.F0 != 0) & (State.F1 == 0);
1152 trace_output (OP_FLAG);
1153 }
1154
1155 /* exetat */
1156 void
1157 OP_4E22 ()
1158 {
1159 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1160 State.exe = (State.F0 != 0) & (State.F1 != 0);
1161 trace_output (OP_FLAG);
1162 }
1163
1164 /* exp */
1165 void
1166 OP_15002A00 ()
1167 {
1168 uint32 tmp, foo;
1169 int i;
1170
1171 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1172 if (((int16)State.regs[OP[1]]) >= 0)
1173 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1174 else
1175 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1176
1177 foo = 0x40000000;
1178 for (i=1;i<17;i++)
1179 {
1180 if (tmp & foo)
1181 {
1182 State.regs[OP[0]] = i-1;
1183 trace_output (OP_REG);
1184 return;
1185 }
1186 foo >>= 1;
1187 }
1188 State.regs[OP[0]] = 16;
1189 trace_output (OP_REG);
1190 }
1191
1192 /* exp */
1193 void
1194 OP_15002A02 ()
1195 {
1196 int64 tmp, foo;
1197 int i;
1198
1199 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1200 tmp = SEXT40(State.a[OP[1]]);
1201 if (tmp < 0)
1202 tmp = ~tmp & MASK40;
1203
1204 foo = 0x4000000000LL;
1205 for (i=1;i<25;i++)
1206 {
1207 if (tmp & foo)
1208 {
1209 State.regs[OP[0]] = i-9;
1210 trace_output (OP_REG);
1211 return;
1212 }
1213 foo >>= 1;
1214 }
1215 State.regs[OP[0]] = 16;
1216 trace_output (OP_REG);
1217 }
1218
1219 /* jl */
1220 void
1221 OP_4D00 ()
1222 {
1223 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1224 State.regs[13] = PC+1;
1225 JMP (State.regs[OP[0]]);
1226 trace_output (OP_VOID);
1227 }
1228
1229 /* jmp */
1230 void
1231 OP_4C00 ()
1232 {
1233 trace_input ("jmp", OP_REG,
1234 (OP[0] == 13) ? OP_R0 : OP_VOID,
1235 (OP[0] == 13) ? OP_R1 : OP_VOID);
1236
1237 JMP (State.regs[OP[0]]);
1238 trace_output (OP_VOID);
1239 }
1240
1241 /* ld */
1242 void
1243 OP_30000000 ()
1244 {
1245 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1246 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1247 trace_output (OP_REG);
1248 }
1249
1250 /* ld */
1251 void
1252 OP_6401 ()
1253 {
1254 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1255 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1256 INC_ADDR(State.regs[OP[1]],-2);
1257 trace_output (OP_REG);
1258 }
1259
1260 /* ld */
1261 void
1262 OP_6001 ()
1263 {
1264 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1265 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1266 INC_ADDR(State.regs[OP[1]],2);
1267 trace_output (OP_REG);
1268 }
1269
1270 /* ld */
1271 void
1272 OP_6000 ()
1273 {
1274 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1275 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1276 trace_output (OP_REG);
1277 }
1278
1279 /* ld2w */
1280 void
1281 OP_31000000 ()
1282 {
1283 uint16 addr = State.regs[OP[2]];
1284 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1285 State.regs[OP[0]] = RW (OP[1] + addr);
1286 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1287 trace_output (OP_DREG);
1288 }
1289
1290 /* ld2w */
1291 void
1292 OP_6601 ()
1293 {
1294 uint16 addr = State.regs[OP[1]];
1295 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1296 State.regs[OP[0]] = RW (addr);
1297 State.regs[OP[0]+1] = RW (addr+2);
1298 INC_ADDR(State.regs[OP[1]],-4);
1299 trace_output (OP_DREG);
1300 }
1301
1302 /* ld2w */
1303 void
1304 OP_6201 ()
1305 {
1306 uint16 addr = State.regs[OP[1]];
1307 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1308 State.regs[OP[0]] = RW (addr);
1309 State.regs[OP[0]+1] = RW (addr+2);
1310 INC_ADDR(State.regs[OP[1]],4);
1311 trace_output (OP_DREG);
1312 }
1313
1314 /* ld2w */
1315 void
1316 OP_6200 ()
1317 {
1318 uint16 addr = State.regs[OP[1]];
1319 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1320 State.regs[OP[0]] = RW (addr);
1321 State.regs[OP[0]+1] = RW (addr+2);
1322 trace_output (OP_DREG);
1323 }
1324
1325 /* ldb */
1326 void
1327 OP_38000000 ()
1328 {
1329 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1330 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1331 trace_output (OP_REG);
1332 }
1333
1334 /* ldb */
1335 void
1336 OP_7000 ()
1337 {
1338 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1339 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1340 trace_output (OP_REG);
1341 }
1342
1343 /* ldi.s */
1344 void
1345 OP_4001 ()
1346 {
1347 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1348 State.regs[OP[0]] = SEXT4(OP[1]);
1349 trace_output (OP_REG);
1350 }
1351
1352 /* ldi.l */
1353 void
1354 OP_20000000 ()
1355 {
1356 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1357 State.regs[OP[0]] = OP[1];
1358 trace_output (OP_REG);
1359 }
1360
1361 /* ldub */
1362 void
1363 OP_39000000 ()
1364 {
1365 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1366 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1367 trace_output (OP_REG);
1368 }
1369
1370 /* ldub */
1371 void
1372 OP_7200 ()
1373 {
1374 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1375 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1376 trace_output (OP_REG);
1377 }
1378
1379 /* mac */
1380 void
1381 OP_2A00 ()
1382 {
1383 int64 tmp;
1384
1385 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1386 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1387
1388 if (State.FX)
1389 tmp = SEXT40( (tmp << 1) & MASK40);
1390
1391 if (State.ST && tmp > MAX32)
1392 tmp = MAX32;
1393
1394 tmp += SEXT40(State.a[OP[0]]);
1395 if (State.ST)
1396 {
1397 if (tmp > MAX32)
1398 State.a[OP[0]] = MAX32;
1399 else if (tmp < MIN32)
1400 State.a[OP[0]] = MIN32;
1401 else
1402 State.a[OP[0]] = tmp & MASK40;
1403 }
1404 else
1405 State.a[OP[0]] = tmp & MASK40;
1406 trace_output (OP_ACCUM);
1407 }
1408
1409 /* macsu */
1410 void
1411 OP_1A00 ()
1412 {
1413 int64 tmp;
1414
1415 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1416 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1417 if (State.FX)
1418 tmp = SEXT40( (tmp << 1) & MASK40);
1419
1420 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1421 trace_output (OP_ACCUM);
1422 }
1423
1424 /* macu */
1425 void
1426 OP_3A00 ()
1427 {
1428 uint64 tmp;
1429 uint32 src1;
1430 uint32 src2;
1431
1432 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1433 src1 = (uint16) State.regs[OP[1]];
1434 src2 = (uint16) State.regs[OP[2]];
1435 tmp = src1 * src2;
1436 if (State.FX)
1437 tmp = (tmp << 1);
1438 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
1439 trace_output (OP_ACCUM);
1440 }
1441
1442 /* max */
1443 void
1444 OP_2600 ()
1445 {
1446 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1447 State.F1 = State.F0;
1448 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1449 {
1450 State.regs[OP[0]] = State.regs[OP[1]];
1451 State.F0 = 1;
1452 }
1453 else
1454 State.F0 = 0;
1455 trace_output (OP_REG);
1456 }
1457
1458 /* max */
1459 void
1460 OP_3600 ()
1461 {
1462 int64 tmp;
1463
1464 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1465 State.F1 = State.F0;
1466 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1467 if (tmp > SEXT40(State.a[OP[0]]))
1468 {
1469 State.a[OP[0]] = tmp & MASK40;
1470 State.F0 = 1;
1471 }
1472 else
1473 State.F0 = 0;
1474 trace_output (OP_ACCUM);
1475 }
1476
1477 /* max */
1478 void
1479 OP_3602 ()
1480 {
1481 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1482 State.F1 = State.F0;
1483 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1484 {
1485 State.a[OP[0]] = State.a[OP[1]];
1486 State.F0 = 1;
1487 }
1488 else
1489 State.F0 = 0;
1490 trace_output (OP_ACCUM);
1491 }
1492
1493
1494 /* min */
1495 void
1496 OP_2601 ()
1497 {
1498 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1499 State.F1 = State.F0;
1500 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1501 {
1502 State.regs[OP[0]] = State.regs[OP[1]];
1503 State.F0 = 1;
1504 }
1505 else
1506 State.F0 = 0;
1507 trace_output (OP_REG);
1508 }
1509
1510 /* min */
1511 void
1512 OP_3601 ()
1513 {
1514 int64 tmp;
1515
1516 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1517 State.F1 = State.F0;
1518 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1519 if (tmp < SEXT40(State.a[OP[0]]))
1520 {
1521 State.a[OP[0]] = tmp & MASK40;
1522 State.F0 = 1;
1523 }
1524 else
1525 State.F0 = 0;
1526 trace_output (OP_ACCUM);
1527 }
1528
1529 /* min */
1530 void
1531 OP_3603 ()
1532 {
1533 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1534 State.F1 = State.F0;
1535 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1536 {
1537 State.a[OP[0]] = State.a[OP[1]];
1538 State.F0 = 1;
1539 }
1540 else
1541 State.F0 = 0;
1542 trace_output (OP_ACCUM);
1543 }
1544
1545 /* msb */
1546 void
1547 OP_2800 ()
1548 {
1549 int64 tmp;
1550
1551 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1552 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1553
1554 if (State.FX)
1555 tmp = SEXT40 ((tmp << 1) & MASK40);
1556
1557 if (State.ST && tmp > MAX32)
1558 tmp = MAX32;
1559
1560 tmp = SEXT40(State.a[OP[0]]) - tmp;
1561 if (State.ST)
1562 {
1563 if (tmp > MAX32)
1564 State.a[OP[0]] = MAX32;
1565 else if (tmp < MIN32)
1566 State.a[OP[0]] = MIN32;
1567 else
1568 State.a[OP[0]] = tmp & MASK40;
1569 }
1570 else
1571 State.a[OP[0]] = tmp & MASK40;
1572 trace_output (OP_ACCUM);
1573 }
1574
1575 /* msbsu */
1576 void
1577 OP_1800 ()
1578 {
1579 int64 tmp;
1580
1581 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1582 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1583 if (State.FX)
1584 tmp = SEXT40( (tmp << 1) & MASK40);
1585
1586 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1587 trace_output (OP_ACCUM);
1588 }
1589
1590 /* msbu */
1591 void
1592 OP_3800 ()
1593 {
1594 uint64 tmp;
1595 uint32 src1;
1596 uint32 src2;
1597
1598 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1599 src1 = (uint16) State.regs[OP[1]];
1600 src2 = (uint16) State.regs[OP[2]];
1601 tmp = src1 * src2;
1602 if (State.FX)
1603 tmp = (tmp << 1);
1604
1605 State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
1606 trace_output (OP_ACCUM);
1607 }
1608
1609 /* mul */
1610 void
1611 OP_2E00 ()
1612 {
1613 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1614 State.regs[OP[0]] *= State.regs[OP[1]];
1615 trace_output (OP_REG);
1616 }
1617
1618 /* mulx */
1619 void
1620 OP_2C00 ()
1621 {
1622 int64 tmp;
1623
1624 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1625 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1626
1627 if (State.FX)
1628 tmp = SEXT40 ((tmp << 1) & MASK40);
1629
1630 if (State.ST && tmp > MAX32)
1631 State.a[OP[0]] = MAX32;
1632 else
1633 State.a[OP[0]] = tmp & MASK40;
1634 trace_output (OP_ACCUM);
1635 }
1636
1637 /* mulxsu */
1638 void
1639 OP_1C00 ()
1640 {
1641 int64 tmp;
1642
1643 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1644 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1645
1646 if (State.FX)
1647 tmp <<= 1;
1648
1649 State.a[OP[0]] = tmp & MASK40;
1650 trace_output (OP_ACCUM);
1651 }
1652
1653 /* mulxu */
1654 void
1655 OP_3C00 ()
1656 {
1657 uint64 tmp;
1658 uint32 src1;
1659 uint32 src2;
1660
1661 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1662 src1 = (uint16) State.regs[OP[1]];
1663 src2 = (uint16) State.regs[OP[2]];
1664 tmp = src1 * src2;
1665 if (State.FX)
1666 tmp <<= 1;
1667
1668 State.a[OP[0]] = tmp & MASK40;
1669 trace_output (OP_ACCUM);
1670 }
1671
1672 /* mv */
1673 void
1674 OP_4000 ()
1675 {
1676 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1677 State.regs[OP[0]] = State.regs[OP[1]];
1678 trace_output (OP_REG);
1679 }
1680
1681 /* mv2w */
1682 void
1683 OP_5000 ()
1684 {
1685 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1686 State.regs[OP[0]] = State.regs[OP[1]];
1687 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1688 trace_output (OP_DREG);
1689 }
1690
1691 /* mv2wfac */
1692 void
1693 OP_3E00 ()
1694 {
1695 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1696 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1697 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1698 trace_output (OP_DREG);
1699 }
1700
1701 /* mv2wtac */
1702 void
1703 OP_3E01 ()
1704 {
1705 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1706 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1707 trace_output (OP_ACCUM_REVERSE);
1708 }
1709
1710 /* mvac */
1711 void
1712 OP_3E03 ()
1713 {
1714 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1715 State.a[OP[0]] = State.a[OP[1]];
1716 trace_output (OP_ACCUM);
1717 }
1718
1719 /* mvb */
1720 void
1721 OP_5400 ()
1722 {
1723 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1724 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1725 trace_output (OP_REG);
1726 }
1727
1728 /* mvf0f */
1729 void
1730 OP_4400 ()
1731 {
1732 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1733 if (State.F0 == 0)
1734 State.regs[OP[0]] = State.regs[OP[1]];
1735 trace_output (OP_REG);
1736 }
1737
1738 /* mvf0t */
1739 void
1740 OP_4401 ()
1741 {
1742 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1743 if (State.F0)
1744 State.regs[OP[0]] = State.regs[OP[1]];
1745 trace_output (OP_REG);
1746 }
1747
1748 /* mvfacg */
1749 void
1750 OP_1E04 ()
1751 {
1752 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1753 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1754 trace_output (OP_ACCUM);
1755 }
1756
1757 /* mvfachi */
1758 void
1759 OP_1E00 ()
1760 {
1761 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1762 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1763 trace_output (OP_REG);
1764 }
1765
1766 /* mvfaclo */
1767 void
1768 OP_1E02 ()
1769 {
1770 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1771 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1772 trace_output (OP_REG);
1773 }
1774
1775 /* mvfc */
1776 void
1777 OP_5200 ()
1778 {
1779 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1780 State.regs[OP[0]] = move_from_cr (OP[1]);
1781 trace_output (OP_REG);
1782 }
1783
1784 /* mvtacg */
1785 void
1786 OP_1E41 ()
1787 {
1788 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1789 State.a[OP[1]] &= MASK32;
1790 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1791 trace_output (OP_ACCUM_REVERSE);
1792 }
1793
1794 /* mvtachi */
1795 void
1796 OP_1E01 ()
1797 {
1798 uint16 tmp;
1799
1800 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1801 tmp = State.a[OP[1]] & 0xffff;
1802 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1803 trace_output (OP_ACCUM_REVERSE);
1804 }
1805
1806 /* mvtaclo */
1807 void
1808 OP_1E21 ()
1809 {
1810 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1811 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1812 trace_output (OP_ACCUM_REVERSE);
1813 }
1814
1815 /* mvtc */
1816 void
1817 OP_5600 ()
1818 {
1819 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1820 move_to_cr (OP[1], State.regs[OP[0]]);
1821 trace_output (OP_CR_REVERSE);
1822 }
1823
1824 /* mvub */
1825 void
1826 OP_5401 ()
1827 {
1828 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1829 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1830 trace_output (OP_REG);
1831 }
1832
1833 /* neg */
1834 void
1835 OP_4605 ()
1836 {
1837 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1838 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1839 trace_output (OP_REG);
1840 }
1841
1842 /* neg */
1843 void
1844 OP_5605 ()
1845 {
1846 int64 tmp;
1847
1848 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1849 tmp = -SEXT40(State.a[OP[0]]);
1850 if (State.ST)
1851 {
1852 if ( tmp > MAX32)
1853 State.a[OP[0]] = MAX32;
1854 else if (tmp < MIN32)
1855 State.a[OP[0]] = MIN32;
1856 else
1857 State.a[OP[0]] = tmp & MASK40;
1858 }
1859 else
1860 State.a[OP[0]] = tmp & MASK40;
1861 trace_output (OP_ACCUM);
1862 }
1863
1864
1865 /* nop */
1866 void
1867 OP_5E00 ()
1868 {
1869 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1870
1871 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1872 switch (State.ins_type)
1873 {
1874 default:
1875 ins_type_counters[ (int)INS_UNKNOWN ]++;
1876 break;
1877
1878 case INS_LEFT_PARALLEL:
1879 /* Don't count a parallel op that includes a NOP as a true parallel op */
1880 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1881 ins_type_counters[ (int)INS_RIGHT ]++;
1882 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1883 break;
1884
1885 case INS_LEFT:
1886 case INS_LEFT_COND_EXE:
1887 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1888 break;
1889
1890 case INS_RIGHT_PARALLEL:
1891 /* Don't count a parallel op that includes a NOP as a true parallel op */
1892 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1893 ins_type_counters[ (int)INS_LEFT ]++;
1894 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1895 break;
1896
1897 case INS_RIGHT:
1898 case INS_RIGHT_COND_EXE:
1899 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1900 break;
1901 }
1902
1903 trace_output (OP_VOID);
1904 }
1905
1906 /* not */
1907 void
1908 OP_4603 ()
1909 {
1910 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1911 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1912 trace_output (OP_REG);
1913 }
1914
1915 /* or */
1916 void
1917 OP_800 ()
1918 {
1919 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1920 State.regs[OP[0]] |= State.regs[OP[1]];
1921 trace_output (OP_REG);
1922 }
1923
1924 /* or3 */
1925 void
1926 OP_4000000 ()
1927 {
1928 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1929 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1930 trace_output (OP_REG);
1931 }
1932
1933 /* rac */
1934 void
1935 OP_5201 ()
1936 {
1937 int64 tmp;
1938 int shift = SEXT3 (OP[2]);
1939
1940 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1941 if (OP[1] != 0)
1942 {
1943 (*d10v_callback->printf_filtered) (d10v_callback,
1944 "ERROR at PC 0x%x: instruction only valid for A0\n",
1945 PC<<2);
1946 State.exception = SIGILL;
1947 }
1948
1949 State.F1 = State.F0;
1950 tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
1951 if (shift >=0)
1952 tmp <<= shift;
1953 else
1954 tmp >>= -shift;
1955 tmp += 0x8000;
1956 tmp >>= 16; /* look at bits 0:43 */
1957 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1958 {
1959 State.regs[OP[0]] = 0x7fff;
1960 State.regs[OP[0]+1] = 0xffff;
1961 State.F0 = 1;
1962 }
1963 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1964 {
1965 State.regs[OP[0]] = 0x8000;
1966 State.regs[OP[0]+1] = 0;
1967 State.F0 = 1;
1968 }
1969 else
1970 {
1971 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1972 State.regs[OP[0]+1] = tmp & 0xffff;
1973 State.F0 = 0;
1974 }
1975 trace_output (OP_DREG);
1976 }
1977
1978 /* rachi */
1979 void
1980 OP_4201 ()
1981 {
1982 signed64 tmp;
1983 int shift = SEXT3 (OP[2]);
1984
1985 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1986 State.F1 = State.F0;
1987 if (shift >=0)
1988 tmp = SEXT40 (State.a[OP[1]]) << shift;
1989 else
1990 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
1991 tmp += 0x8000;
1992
1993 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1994 {
1995 State.regs[OP[0]] = 0x7fff;
1996 State.F0 = 1;
1997 }
1998 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1999 {
2000 State.regs[OP[0]] = 0x8000;
2001 State.F0 = 1;
2002 }
2003 else
2004 {
2005 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2006 State.F0 = 0;
2007 }
2008 trace_output (OP_REG);
2009 }
2010
2011 /* rep */
2012 void
2013 OP_27000000 ()
2014 {
2015 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2016 RPT_S = PC + 1;
2017 RPT_E = PC + OP[1];
2018 RPT_C = State.regs[OP[0]];
2019 State.RP = 1;
2020 if (RPT_C == 0)
2021 {
2022 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2023 State.exception = SIGILL;
2024 }
2025 if (OP[1] < 4)
2026 {
2027 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2028 State.exception = SIGILL;
2029 }
2030 trace_output (OP_VOID);
2031 }
2032
2033 /* repi */
2034 void
2035 OP_2F000000 ()
2036 {
2037 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2038 RPT_S = PC + 1;
2039 RPT_E = PC + OP[1];
2040 RPT_C = OP[0];
2041 State.RP = 1;
2042 if (RPT_C == 0)
2043 {
2044 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2045 State.exception = SIGILL;
2046 }
2047 if (OP[1] < 4)
2048 {
2049 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2050 State.exception = SIGILL;
2051 }
2052 trace_output (OP_VOID);
2053 }
2054
2055 /* rtd */
2056 void
2057 OP_5F60 ()
2058 {
2059 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2060 State.exception = SIGILL;
2061 }
2062
2063 /* rte */
2064 void
2065 OP_5F40 ()
2066 {
2067 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2068 move_to_cr (PSW_CR, BPSW);
2069 JMP(BPC);
2070 trace_output (OP_VOID);
2071 }
2072
2073 /* sadd */
2074 void
2075 OP_1223 ()
2076 {
2077 int64 tmp;
2078
2079 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2080 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2081 if (State.ST)
2082 {
2083 if (tmp > MAX32)
2084 State.a[OP[0]] = MAX32;
2085 else if (tmp < MIN32)
2086 State.a[OP[0]] = MIN32;
2087 else
2088 State.a[OP[0]] = tmp & MASK40;
2089 }
2090 else
2091 State.a[OP[0]] = tmp & MASK40;
2092 trace_output (OP_ACCUM);
2093 }
2094
2095 /* setf0f */
2096 void
2097 OP_4611 ()
2098 {
2099 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2100 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2101 trace_output (OP_REG);
2102 }
2103
2104 /* setf0t */
2105 void
2106 OP_4613 ()
2107 {
2108 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2109 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2110 trace_output (OP_REG);
2111 }
2112
2113 /* sleep */
2114 void
2115 OP_5FC0 ()
2116 {
2117 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2118 State.IE = 1;
2119 trace_output (OP_VOID);
2120 }
2121
2122 /* sll */
2123 void
2124 OP_2200 ()
2125 {
2126 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2127 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2128 trace_output (OP_REG);
2129 }
2130
2131 /* sll */
2132 void
2133 OP_3200 ()
2134 {
2135 int64 tmp;
2136 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2137 if ((State.regs[OP[1]] & 31) <= 16)
2138 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2139 else
2140 {
2141 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2142 State.exception = SIGILL;
2143 return;
2144 }
2145
2146 if (State.ST)
2147 {
2148 if (tmp > MAX32)
2149 State.a[OP[0]] = MAX32;
2150 else if (tmp < 0xffffff80000000LL)
2151 State.a[OP[0]] = MIN32;
2152 else
2153 State.a[OP[0]] = tmp & MASK40;
2154 }
2155 else
2156 State.a[OP[0]] = tmp & MASK40;
2157 trace_output (OP_ACCUM);
2158 }
2159
2160 /* slli */
2161 void
2162 OP_2201 ()
2163 {
2164 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2165 State.regs[OP[0]] <<= OP[1];
2166 trace_output (OP_REG);
2167 }
2168
2169 /* slli */
2170 void
2171 OP_3201 ()
2172 {
2173 int64 tmp;
2174
2175 if (OP[1] == 0)
2176 OP[1] = 16;
2177
2178 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2179 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2180
2181 if (State.ST)
2182 {
2183 if (tmp > MAX32)
2184 State.a[OP[0]] = MAX32;
2185 else if (tmp < 0xffffff80000000LL)
2186 State.a[OP[0]] = MIN32;
2187 else
2188 State.a[OP[0]] = tmp & MASK40;
2189 }
2190 else
2191 State.a[OP[0]] = tmp & MASK40;
2192 trace_output (OP_ACCUM);
2193 }
2194
2195 /* slx */
2196 void
2197 OP_460B ()
2198 {
2199 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2200 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2201 trace_output (OP_REG);
2202 }
2203
2204 /* sra */
2205 void
2206 OP_2400 ()
2207 {
2208 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2209 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2210 trace_output (OP_REG);
2211 }
2212
2213 /* sra */
2214 void
2215 OP_3400 ()
2216 {
2217 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2218 if ((State.regs[OP[1]] & 31) <= 16)
2219 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2220 else
2221 {
2222 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2223 State.exception = SIGILL;
2224 return;
2225 }
2226
2227 trace_output (OP_ACCUM);
2228 }
2229
2230 /* srai */
2231 void
2232 OP_2401 ()
2233 {
2234 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2235 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2236 trace_output (OP_REG);
2237 }
2238
2239 /* srai */
2240 void
2241 OP_3401 ()
2242 {
2243 if (OP[1] == 0)
2244 OP[1] = 16;
2245
2246 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2247 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2248 trace_output (OP_ACCUM);
2249 }
2250
2251 /* srl */
2252 void
2253 OP_2000 ()
2254 {
2255 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2256 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2257 trace_output (OP_REG);
2258 }
2259
2260 /* srl */
2261 void
2262 OP_3000 ()
2263 {
2264 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2265 if ((State.regs[OP[1]] & 31) <= 16)
2266 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2267 else
2268 {
2269 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2270 State.exception = SIGILL;
2271 return;
2272 }
2273
2274 trace_output (OP_ACCUM);
2275 }
2276
2277 /* srli */
2278 void
2279 OP_2001 ()
2280 {
2281 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2282 State.regs[OP[0]] >>= OP[1];
2283 trace_output (OP_REG);
2284 }
2285
2286 /* srli */
2287 void
2288 OP_3001 ()
2289 {
2290 if (OP[1] == 0)
2291 OP[1] = 16;
2292
2293 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2294 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2295 trace_output (OP_ACCUM);
2296 }
2297
2298 /* srx */
2299 void
2300 OP_4609 ()
2301 {
2302 uint16 tmp;
2303
2304 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2305 tmp = State.F0 << 15;
2306 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2307 trace_output (OP_REG);
2308 }
2309
2310 /* st */
2311 void
2312 OP_34000000 ()
2313 {
2314 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2315 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2316 trace_output (OP_VOID);
2317 }
2318
2319 /* st */
2320 void
2321 OP_6800 ()
2322 {
2323 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2324 SW (State.regs[OP[1]], State.regs[OP[0]]);
2325 trace_output (OP_VOID);
2326 }
2327
2328 /* st */
2329 void
2330 OP_6C1F ()
2331 {
2332 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2333 if ( OP[1] != 15 )
2334 {
2335 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2336 State.exception = SIGILL;
2337 return;
2338 }
2339 State.regs[OP[1]] -= 2;
2340 SW (State.regs[OP[1]], State.regs[OP[0]]);
2341 trace_output (OP_VOID);
2342 }
2343
2344 /* st */
2345 void
2346 OP_6801 ()
2347 {
2348 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2349 SW (State.regs[OP[1]], State.regs[OP[0]]);
2350 INC_ADDR (State.regs[OP[1]],2);
2351 trace_output (OP_VOID);
2352 }
2353
2354 /* st */
2355 void
2356 OP_6C01 ()
2357 {
2358 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2359 if ( OP[1] == 15 )
2360 {
2361 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2362 State.exception = SIGILL;
2363 return;
2364 }
2365 SW (State.regs[OP[1]], State.regs[OP[0]]);
2366 INC_ADDR (State.regs[OP[1]],-2);
2367 trace_output (OP_VOID);
2368 }
2369
2370 /* st2w */
2371 void
2372 OP_35000000 ()
2373 {
2374 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2375 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2376 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2377 trace_output (OP_VOID);
2378 }
2379
2380 /* st2w */
2381 void
2382 OP_6A00 ()
2383 {
2384 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2385 SW (State.regs[OP[1]], State.regs[OP[0]]);
2386 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2387 trace_output (OP_VOID);
2388 }
2389
2390 /* st2w */
2391 void
2392 OP_6E1F ()
2393 {
2394 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2395 if ( OP[1] != 15 )
2396 {
2397 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2398 State.exception = SIGILL;
2399 return;
2400 }
2401 State.regs[OP[1]] -= 4;
2402 SW (State.regs[OP[1]], State.regs[OP[0]]);
2403 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2404 trace_output (OP_VOID);
2405 }
2406
2407 /* st2w */
2408 void
2409 OP_6A01 ()
2410 {
2411 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2412 SW (State.regs[OP[1]], State.regs[OP[0]]);
2413 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2414 INC_ADDR (State.regs[OP[1]],4);
2415 trace_output (OP_VOID);
2416 }
2417
2418 /* st2w */
2419 void
2420 OP_6E01 ()
2421 {
2422 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2423 if ( OP[1] == 15 )
2424 {
2425 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2426 State.exception = SIGILL;
2427 return;
2428 }
2429 SW (State.regs[OP[1]], State.regs[OP[0]]);
2430 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2431 INC_ADDR (State.regs[OP[1]],-4);
2432 trace_output (OP_VOID);
2433 }
2434
2435 /* stb */
2436 void
2437 OP_3C000000 ()
2438 {
2439 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2440 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2441 trace_output (OP_VOID);
2442 }
2443
2444 /* stb */
2445 void
2446 OP_7800 ()
2447 {
2448 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2449 SB (State.regs[OP[1]], State.regs[OP[0]]);
2450 trace_output (OP_VOID);
2451 }
2452
2453 /* stop */
2454 void
2455 OP_5FE0 ()
2456 {
2457 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2458 State.exception = SIG_D10V_STOP;
2459 trace_output (OP_VOID);
2460 }
2461
2462 /* sub */
2463 void
2464 OP_0 ()
2465 {
2466 uint16 tmp;
2467
2468 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2469 /* see ../common/sim-alu.h for a more extensive discussion on how to
2470 compute the carry/overflow bits. */
2471 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2472 State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
2473 State.regs[OP[0]] = tmp;
2474 trace_output (OP_REG);
2475 }
2476
2477 /* sub */
2478 void
2479 OP_1001 ()
2480 {
2481 int64 tmp;
2482
2483 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2484 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2485 if (State.ST)
2486 {
2487 if ( tmp > MAX32)
2488 State.a[OP[0]] = MAX32;
2489 else if ( tmp < MIN32)
2490 State.a[OP[0]] = MIN32;
2491 else
2492 State.a[OP[0]] = tmp & MASK40;
2493 }
2494 else
2495 State.a[OP[0]] = tmp & MASK40;
2496
2497 trace_output (OP_ACCUM);
2498 }
2499
2500 /* sub */
2501
2502 void
2503 OP_1003 ()
2504 {
2505 int64 tmp;
2506
2507 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2508 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2509 if (State.ST)
2510 {
2511 if (tmp > MAX32)
2512 State.a[OP[0]] = MAX32;
2513 else if ( tmp < MIN32)
2514 State.a[OP[0]] = MIN32;
2515 else
2516 State.a[OP[0]] = tmp & MASK40;
2517 }
2518 else
2519 State.a[OP[0]] = tmp & MASK40;
2520
2521 trace_output (OP_ACCUM);
2522 }
2523
2524 /* sub2w */
2525 void
2526 OP_1000 ()
2527 {
2528 uint32 tmp,a,b;
2529
2530 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2531 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2532 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2533 /* see ../common/sim-alu.h for a more extensive discussion on how to
2534 compute the carry/overflow bits */
2535 tmp = a - b;
2536 State.C = (a >= b);
2537 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2538 State.regs[OP[0]+1] = tmp & 0xffff;
2539 trace_output (OP_DREG);
2540 }
2541
2542 /* subac3 */
2543 void
2544 OP_17000000 ()
2545 {
2546 int64 tmp;
2547
2548 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2549 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2550 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2551 State.regs[OP[0]+1] = tmp & 0xffff;
2552 trace_output (OP_DREG);
2553 }
2554
2555 /* subac3 */
2556 void
2557 OP_17000002 ()
2558 {
2559 int64 tmp;
2560
2561 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2562 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2563 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2564 State.regs[OP[0]+1] = tmp & 0xffff;
2565 trace_output (OP_DREG);
2566 }
2567
2568 /* subac3s */
2569 void
2570 OP_17001000 ()
2571 {
2572 int64 tmp;
2573
2574 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2575 State.F1 = State.F0;
2576 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2577 if ( tmp > MAX32)
2578 {
2579 State.regs[OP[0]] = 0x7fff;
2580 State.regs[OP[0]+1] = 0xffff;
2581 State.F0 = 1;
2582 }
2583 else if (tmp < MIN32)
2584 {
2585 State.regs[OP[0]] = 0x8000;
2586 State.regs[OP[0]+1] = 0;
2587 State.F0 = 1;
2588 }
2589 else
2590 {
2591 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2592 State.regs[OP[0]+1] = tmp & 0xffff;
2593 State.F0 = 0;
2594 }
2595 trace_output (OP_DREG);
2596 }
2597
2598 /* subac3s */
2599 void
2600 OP_17001002 ()
2601 {
2602 int64 tmp;
2603
2604 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2605 State.F1 = State.F0;
2606 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2607 if ( tmp > MAX32)
2608 {
2609 State.regs[OP[0]] = 0x7fff;
2610 State.regs[OP[0]+1] = 0xffff;
2611 State.F0 = 1;
2612 }
2613 else if (tmp < MIN32)
2614 {
2615 State.regs[OP[0]] = 0x8000;
2616 State.regs[OP[0]+1] = 0;
2617 State.F0 = 1;
2618 }
2619 else
2620 {
2621 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2622 State.regs[OP[0]+1] = tmp & 0xffff;
2623 State.F0 = 0;
2624 }
2625 trace_output (OP_DREG);
2626 }
2627
2628 /* subi */
2629 void
2630 OP_1 ()
2631 {
2632 unsigned tmp;
2633 if (OP[1] == 0)
2634 OP[1] = 16;
2635
2636 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2637 /* see ../common/sim-alu.h for a more extensive discussion on how to
2638 compute the carry/overflow bits. */
2639 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2640 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2641 + (unsigned)(unsigned16) ( - OP[1]));
2642 State.C = (tmp >= (1 << 16));
2643 State.regs[OP[0]] = tmp;
2644 trace_output (OP_REG);
2645 }
2646
2647 /* trap */
2648 void
2649 OP_5F00 ()
2650 {
2651 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2652 trace_output (OP_VOID);
2653
2654 switch (OP[0])
2655 {
2656 default:
2657 #if (DEBUG & DEBUG_TRAP) == 0
2658 {
2659 uint16 vec = OP[0] + TRAP_VECTOR_START;
2660 BPC = PC + 1;
2661 move_to_cr (BPSW_CR, PSW);
2662 move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
2663 JMP (vec);
2664 break;
2665 }
2666 #else /* if debugging use trap to print registers */
2667 {
2668 int i;
2669 static int first_time = 1;
2670
2671 if (first_time)
2672 {
2673 first_time = 0;
2674 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2675 for (i = 0; i < 16; i++)
2676 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2677 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2678 }
2679
2680 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2681
2682 for (i = 0; i < 16; i++)
2683 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2684
2685 for (i = 0; i < 2; i++)
2686 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2687 ((int)(State.a[i] >> 32) & 0xff),
2688 ((unsigned long)State.a[i]) & 0xffffffff);
2689
2690 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2691 State.F0 != 0, State.F1 != 0, State.C != 0);
2692 (*d10v_callback->flush_stdout) (d10v_callback);
2693 break;
2694 }
2695 #endif
2696 case 15: /* new system call trap */
2697 /* Trap 15 is used for simulating low-level I/O */
2698 {
2699 errno = 0;
2700
2701 /* Registers passed to trap 0 */
2702
2703 #define FUNC State.regs[4] /* function number */
2704 #define PARM1 State.regs[0] /* optional parm 1 */
2705 #define PARM2 State.regs[1] /* optional parm 2 */
2706 #define PARM3 State.regs[2] /* optional parm 3 */
2707 #define PARM4 State.regs[3] /* optional parm 3 */
2708
2709 /* Registers set by trap 0 */
2710
2711 #define RETVAL State.regs[0] /* return value */
2712 #define RETVAL_HIGH State.regs[0] /* return value */
2713 #define RETVAL_LOW State.regs[1] /* return value */
2714 #define RETERR State.regs[4] /* return error code */
2715
2716 /* Turn a pointer in a register into a pointer into real memory. */
2717
2718 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2719
2720 switch (FUNC)
2721 {
2722 #if !defined(__GO32__) && !defined(_WIN32)
2723 case SYS_fork:
2724 RETVAL = fork ();
2725 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2726 trace_output (OP_R0);
2727 break;
2728
2729 case SYS_getpid:
2730 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2731 RETVAL = getpid ();
2732 trace_output (OP_R0);
2733 break;
2734
2735 case SYS_kill:
2736 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2737 if (PARM1 == getpid ())
2738 {
2739 trace_output (OP_VOID);
2740 State.exception = PARM2;
2741 }
2742 else
2743 {
2744 int os_sig = -1;
2745 switch (PARM2)
2746 {
2747 #ifdef SIGHUP
2748 case 1: os_sig = SIGHUP; break;
2749 #endif
2750 #ifdef SIGINT
2751 case 2: os_sig = SIGINT; break;
2752 #endif
2753 #ifdef SIGQUIT
2754 case 3: os_sig = SIGQUIT; break;
2755 #endif
2756 #ifdef SIGILL
2757 case 4: os_sig = SIGILL; break;
2758 #endif
2759 #ifdef SIGTRAP
2760 case 5: os_sig = SIGTRAP; break;
2761 #endif
2762 #ifdef SIGABRT
2763 case 6: os_sig = SIGABRT; break;
2764 #elif defined(SIGIOT)
2765 case 6: os_sig = SIGIOT; break;
2766 #endif
2767 #ifdef SIGEMT
2768 case 7: os_sig = SIGEMT; break;
2769 #endif
2770 #ifdef SIGFPE
2771 case 8: os_sig = SIGFPE; break;
2772 #endif
2773 #ifdef SIGKILL
2774 case 9: os_sig = SIGKILL; break;
2775 #endif
2776 #ifdef SIGBUS
2777 case 10: os_sig = SIGBUS; break;
2778 #endif
2779 #ifdef SIGSEGV
2780 case 11: os_sig = SIGSEGV; break;
2781 #endif
2782 #ifdef SIGSYS
2783 case 12: os_sig = SIGSYS; break;
2784 #endif
2785 #ifdef SIGPIPE
2786 case 13: os_sig = SIGPIPE; break;
2787 #endif
2788 #ifdef SIGALRM
2789 case 14: os_sig = SIGALRM; break;
2790 #endif
2791 #ifdef SIGTERM
2792 case 15: os_sig = SIGTERM; break;
2793 #endif
2794 #ifdef SIGURG
2795 case 16: os_sig = SIGURG; break;
2796 #endif
2797 #ifdef SIGSTOP
2798 case 17: os_sig = SIGSTOP; break;
2799 #endif
2800 #ifdef SIGTSTP
2801 case 18: os_sig = SIGTSTP; break;
2802 #endif
2803 #ifdef SIGCONT
2804 case 19: os_sig = SIGCONT; break;
2805 #endif
2806 #ifdef SIGCHLD
2807 case 20: os_sig = SIGCHLD; break;
2808 #elif defined(SIGCLD)
2809 case 20: os_sig = SIGCLD; break;
2810 #endif
2811 #ifdef SIGTTIN
2812 case 21: os_sig = SIGTTIN; break;
2813 #endif
2814 #ifdef SIGTTOU
2815 case 22: os_sig = SIGTTOU; break;
2816 #endif
2817 #ifdef SIGIO
2818 case 23: os_sig = SIGIO; break;
2819 #elif defined (SIGPOLL)
2820 case 23: os_sig = SIGPOLL; break;
2821 #endif
2822 #ifdef SIGXCPU
2823 case 24: os_sig = SIGXCPU; break;
2824 #endif
2825 #ifdef SIGXFSZ
2826 case 25: os_sig = SIGXFSZ; break;
2827 #endif
2828 #ifdef SIGVTALRM
2829 case 26: os_sig = SIGVTALRM; break;
2830 #endif
2831 #ifdef SIGPROF
2832 case 27: os_sig = SIGPROF; break;
2833 #endif
2834 #ifdef SIGWINCH
2835 case 28: os_sig = SIGWINCH; break;
2836 #endif
2837 #ifdef SIGLOST
2838 case 29: os_sig = SIGLOST; break;
2839 #endif
2840 #ifdef SIGUSR1
2841 case 30: os_sig = SIGUSR1; break;
2842 #endif
2843 #ifdef SIGUSR2
2844 case 31: os_sig = SIGUSR2; break;
2845 #endif
2846 }
2847
2848 if (os_sig == -1)
2849 {
2850 trace_output (OP_VOID);
2851 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2852 (*d10v_callback->flush_stdout) (d10v_callback);
2853 State.exception = SIGILL;
2854 }
2855 else
2856 {
2857 RETVAL = kill (PARM1, PARM2);
2858 trace_output (OP_R0);
2859 }
2860 }
2861 break;
2862
2863 case SYS_execve:
2864 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2865 (char **)MEMPTR (PARM3));
2866 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
2867 trace_output (OP_R0);
2868 break;
2869
2870 #ifdef SYS_execv
2871 case SYS_execv:
2872 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2873 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
2874 trace_output (OP_R0);
2875 break;
2876 #endif
2877
2878 case SYS_pipe:
2879 {
2880 reg_t buf;
2881 int host_fd[2];
2882
2883 buf = PARM1;
2884 RETVAL = pipe (host_fd);
2885 SW (buf, host_fd[0]);
2886 buf += sizeof(uint16);
2887 SW (buf, host_fd[1]);
2888 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
2889 trace_output (OP_R0);
2890 }
2891 break;
2892
2893 #ifdef SYS_wait
2894 case SYS_wait:
2895 {
2896 int status;
2897
2898 RETVAL = wait (&status);
2899 if (PARM1)
2900 SW (PARM1, status);
2901 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
2902 trace_output (OP_R0);
2903 }
2904 break;
2905 #endif
2906 #else
2907 case SYS_getpid:
2908 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2909 RETVAL = 1;
2910 trace_output (OP_R0);
2911 break;
2912
2913 case SYS_kill:
2914 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2915 trace_output (OP_VOID);
2916 State.exception = PARM2;
2917 break;
2918 #endif
2919
2920 case SYS_read:
2921 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2922 PARM3);
2923 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
2924 trace_output (OP_R0);
2925 break;
2926
2927 case SYS_write:
2928 if (PARM1 == 1)
2929 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2930 MEMPTR (PARM2), PARM3);
2931 else
2932 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2933 MEMPTR (PARM2), PARM3);
2934 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
2935 trace_output (OP_R0);
2936 break;
2937
2938 case SYS_lseek:
2939 {
2940 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2941 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2942 PARM4);
2943 RETVAL_HIGH = ret >> 16;
2944 RETVAL_LOW = ret & 0xffff;
2945 }
2946 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
2947 trace_output (OP_R0R1);
2948 break;
2949
2950 case SYS_close:
2951 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2952 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
2953 trace_output (OP_R0);
2954 break;
2955
2956 case SYS_open:
2957 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2958 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2959 trace_output (OP_R0);
2960 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2961 trace_output (OP_R0);
2962 break;
2963
2964 case SYS_exit:
2965 State.exception = SIG_D10V_EXIT;
2966 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
2967 trace_output (OP_VOID);
2968 break;
2969
2970 case SYS_stat:
2971 /* stat system call */
2972 {
2973 struct stat host_stat;
2974 reg_t buf;
2975
2976 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2977
2978 buf = PARM2;
2979
2980 /* The hard-coded offsets and sizes were determined by using
2981 * the D10V compiler on a test program that used struct stat.
2982 */
2983 SW (buf, host_stat.st_dev);
2984 SW (buf+2, host_stat.st_ino);
2985 SW (buf+4, host_stat.st_mode);
2986 SW (buf+6, host_stat.st_nlink);
2987 SW (buf+8, host_stat.st_uid);
2988 SW (buf+10, host_stat.st_gid);
2989 SW (buf+12, host_stat.st_rdev);
2990 SLW (buf+16, host_stat.st_size);
2991 SLW (buf+20, host_stat.st_atime);
2992 SLW (buf+28, host_stat.st_mtime);
2993 SLW (buf+36, host_stat.st_ctime);
2994 }
2995 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
2996 trace_output (OP_R0);
2997 break;
2998
2999 case SYS_chown:
3000 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
3001 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3002 trace_output (OP_R0);
3003 break;
3004
3005 case SYS_chmod:
3006 RETVAL = chmod (MEMPTR (PARM1), PARM2);
3007 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3008 trace_output (OP_R0);
3009 break;
3010
3011 #ifdef SYS_utime
3012 case SYS_utime:
3013 /* Cast the second argument to void *, to avoid type mismatch
3014 if a prototype is present. */
3015 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
3016 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3017 trace_output (OP_R0);
3018 break;
3019 #endif
3020
3021 #ifdef SYS_time
3022 case SYS_time:
3023 {
3024 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
3025 RETVAL_HIGH = ret >> 16;
3026 RETVAL_LOW = ret & 0xffff;
3027 }
3028 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3029 trace_output (OP_R0R1);
3030 break;
3031 #endif
3032
3033 default:
3034 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3035 }
3036 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
3037 break;
3038 }
3039 }
3040 }
3041
3042 /* tst0i */
3043 void
3044 OP_7000000 ()
3045 {
3046 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3047 State.F1 = State.F0;
3048 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
3049 trace_output (OP_FLAG);
3050 }
3051
3052 /* tst1i */
3053 void
3054 OP_F000000 ()
3055 {
3056 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3057 State.F1 = State.F0;
3058 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3059 trace_output (OP_FLAG);
3060 }
3061
3062 /* wait */
3063 void
3064 OP_5F80 ()
3065 {
3066 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3067 State.IE = 1;
3068 trace_output (OP_VOID);
3069 }
3070
3071 /* xor */
3072 void
3073 OP_A00 ()
3074 {
3075 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3076 State.regs[OP[0]] ^= State.regs[OP[1]];
3077 trace_output (OP_REG);
3078 }
3079
3080 /* xor3 */
3081 void
3082 OP_5000000 ()
3083 {
3084 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3085 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3086 trace_output (OP_REG);
3087 }
3088
GDB Binutils - Deliverables
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