16 #include "targ-vals.h"
18 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
51 PSW_MASK
= (PSW_SM_BIT
62 /* The following bits in the PSW _can't_ be set by instructions such
64 PSW_HW_MASK
= (PSW_MASK
| PSW_DM_BIT
)
68 move_to_cr (SIM_DESC sd
, SIM_CPU
*cpu
, int cr
, reg_t mask
, reg_t val
, int psw_hw_p
)
70 /* A MASK bit is set when the corresponding bit in the CR should
72 /* This assumes that (VAL & MASK) == 0 */
80 if ((mask
& PSW_SM_BIT
) == 0)
82 int new_psw_sm
= (val
& PSW_SM_BIT
) != 0;
84 SET_HELD_SP (PSW_SM
, GPR (SP_IDX
));
85 if (PSW_SM
!= new_psw_sm
)
87 SET_GPR (SP_IDX
, HELD_SP (new_psw_sm
));
89 if ((mask
& (PSW_ST_BIT
| PSW_FX_BIT
)) == 0)
91 if (val
& PSW_ST_BIT
&& !(val
& PSW_FX_BIT
))
95 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
97 EXCEPTION (SIM_SIGILL
);
100 /* keep an up-to-date psw around for tracing */
101 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
105 /* Just like PSW, mask things like DM out. */
118 /* only issue an update if the register is being changed */
119 if ((State
.cregs
[cr
] & ~mask
) != val
)
120 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
125 static void trace_input_func (SIM_DESC sd
,
131 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
133 #ifndef SIZE_INSTRUCTION
134 #define SIZE_INSTRUCTION 8
137 #ifndef SIZE_OPERANDS
138 #define SIZE_OPERANDS 18
142 #define SIZE_VALUES 13
145 #ifndef SIZE_LOCATION
146 #define SIZE_LOCATION 20
153 #ifndef SIZE_LINE_NUMBER
154 #define SIZE_LINE_NUMBER 4
158 trace_input_func (SIM_DESC sd
, const char *name
, enum op_types in1
, enum op_types in2
, enum op_types in3
)
167 const char *filename
;
168 const char *functionname
;
169 unsigned int linenumber
;
172 if ((d10v_debug
& DEBUG_TRACE
) == 0)
175 switch (State
.ins_type
)
178 case INS_UNKNOWN
: type
= " ?"; break;
179 case INS_LEFT
: type
= " L"; break;
180 case INS_RIGHT
: type
= " R"; break;
181 case INS_LEFT_PARALLEL
: type
= "*L"; break;
182 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
183 case INS_LEFT_COND_TEST
: type
= "?L"; break;
184 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
185 case INS_LEFT_COND_EXE
: type
= "&L"; break;
186 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
187 case INS_LONG
: type
= " B"; break;
190 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
193 SIZE_PC
, (unsigned)PC
,
195 SIZE_INSTRUCTION
, name
);
201 if (STATE_TEXT_SECTION (sd
)
202 && byte_pc
>= STATE_TEXT_START (sd
)
203 && byte_pc
< STATE_TEXT_END (sd
))
205 filename
= (const char *)0;
206 functionname
= (const char *)0;
208 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
209 STATE_TEXT_SECTION (sd
),
210 (struct bfd_symbol
**)0,
211 byte_pc
- STATE_TEXT_START (sd
),
212 &filename
, &functionname
, &linenumber
))
217 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
222 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
223 p
+= SIZE_LINE_NUMBER
+2;
228 sprintf (p
, "%s ", functionname
);
233 char *q
= strrchr (filename
, '/');
234 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
244 "0x%.*x %s: %-*.*s %-*s ",
245 SIZE_PC
, (unsigned)PC
,
247 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
248 SIZE_INSTRUCTION
, name
);
256 for (i
= 0; i
< 3; i
++)
270 sprintf (p
, "%sr%d", comma
, OP
[i
]);
278 sprintf (p
, "%scr%d", comma
, OP
[i
]);
284 case OP_ACCUM_OUTPUT
:
285 case OP_ACCUM_REVERSE
:
286 sprintf (p
, "%sa%d", comma
, OP
[i
]);
292 sprintf (p
, "%s%d", comma
, OP
[i
]);
298 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
304 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
310 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
316 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
322 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
328 sprintf (p
, "%s@%d", comma
, OP
[i
]);
334 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
340 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
346 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
354 sprintf (p
, "%sf0", comma
);
357 sprintf (p
, "%sf1", comma
);
360 sprintf (p
, "%sc", comma
);
368 if ((d10v_debug
& DEBUG_VALUES
) == 0)
372 sim_io_printf (sd
, "%s", buf
);
377 sim_io_printf (sd
, "%-*s", SIZE_OPERANDS
, buf
);
380 for (i
= 0; i
< 3; i
++)
386 sim_io_printf (sd
, "%*s", SIZE_VALUES
, "");
392 case OP_ACCUM_OUTPUT
:
394 sim_io_printf (sd
, "%*s", SIZE_VALUES
, "---");
402 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
403 (uint16
) GPR (OP
[i
]));
407 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "", (uint16
) OP
[i
]);
411 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
412 sim_io_printf (sd
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
417 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
418 (uint16
) CREG (OP
[i
]));
422 case OP_ACCUM_REVERSE
:
423 sim_io_printf (sd
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
424 ((int)(ACC (OP
[i
]) >> 32) & 0xff),
425 ((unsigned long) ACC (OP
[i
])) & 0xffffffff);
429 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
434 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
435 (uint16
)SEXT4(OP
[i
]));
439 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
440 (uint16
)SEXT8(OP
[i
]));
444 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
445 (uint16
)SEXT3(OP
[i
]));
450 sim_io_printf (sd
, "%*sF0 = %d", SIZE_VALUES
-6, "",
454 sim_io_printf (sd
, "%*sF1 = %d", SIZE_VALUES
-6, "",
458 sim_io_printf (sd
, "%*sC = %d", SIZE_VALUES
-5, "",
464 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
466 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
467 (uint16
)GPR (OP
[i
+ 1]));
472 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
477 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
482 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
490 sim_io_flush_stdout (sd
);
494 do_trace_output_flush (SIM_DESC sd
)
496 sim_io_flush_stdout (sd
);
500 do_trace_output_finish (SIM_DESC sd
)
503 " F0=%d F1=%d C=%d\n",
504 (State
.trace
.psw
& PSW_F0_BIT
) != 0,
505 (State
.trace
.psw
& PSW_F1_BIT
) != 0,
506 (State
.trace
.psw
& PSW_C_BIT
) != 0);
507 sim_io_flush_stdout (sd
);
511 trace_output_40 (SIM_DESC sd
, uint64 val
)
513 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
516 " :: %*s0x%.2x%.8lx",
519 ((int)(val
>> 32) & 0xff),
520 ((unsigned long) val
) & 0xffffffff);
521 do_trace_output_finish (sd
);
526 trace_output_32 (SIM_DESC sd
, uint32 val
)
528 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
535 do_trace_output_finish (sd
);
540 trace_output_16 (SIM_DESC sd
, uint16 val
)
542 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
549 do_trace_output_finish (sd
);
554 trace_output_void (SIM_DESC sd
)
556 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
558 sim_io_printf (sd
, "\n");
559 do_trace_output_flush (sd
);
564 trace_output_flag (SIM_DESC sd
)
566 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
572 do_trace_output_finish (sd
);
580 #define trace_input(NAME, IN1, IN2, IN3)
581 #define trace_output(RESULT)
586 OP_4607 (SIM_DESC sd
, SIM_CPU
*cpu
)
589 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
599 SET_GPR (OP
[0], tmp
);
600 trace_output_16 (sd
, tmp
);
605 OP_5607 (SIM_DESC sd
, SIM_CPU
*cpu
)
608 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
611 tmp
= SEXT40 (ACC (OP
[0]));
617 if (tmp
> SEXT40(MAX32
))
619 else if (tmp
< SEXT40(MIN32
))
622 tmp
= (tmp
& MASK40
);
625 tmp
= (tmp
& MASK40
);
630 tmp
= (tmp
& MASK40
);
633 SET_ACC (OP
[0], tmp
);
634 trace_output_40 (sd
, tmp
);
639 OP_200 (SIM_DESC sd
, SIM_CPU
*cpu
)
641 uint16 a
= GPR (OP
[0]);
642 uint16 b
= GPR (OP
[1]);
643 uint16 tmp
= (a
+ b
);
644 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
646 SET_GPR (OP
[0], tmp
);
647 trace_output_16 (sd
, tmp
);
652 OP_1201 (SIM_DESC sd
, SIM_CPU
*cpu
)
655 tmp
= SEXT40(ACC (OP
[0])) + (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
657 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
660 if (tmp
> SEXT40(MAX32
))
662 else if (tmp
< SEXT40(MIN32
))
665 tmp
= (tmp
& MASK40
);
668 tmp
= (tmp
& MASK40
);
669 SET_ACC (OP
[0], tmp
);
670 trace_output_40 (sd
, tmp
);
675 OP_1203 (SIM_DESC sd
, SIM_CPU
*cpu
)
678 tmp
= SEXT40(ACC (OP
[0])) + SEXT40(ACC (OP
[1]));
680 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
683 if (tmp
> SEXT40(MAX32
))
685 else if (tmp
< SEXT40(MIN32
))
688 tmp
= (tmp
& MASK40
);
691 tmp
= (tmp
& MASK40
);
692 SET_ACC (OP
[0], tmp
);
693 trace_output_40 (sd
, tmp
);
698 OP_1200 (SIM_DESC sd
, SIM_CPU
*cpu
)
701 uint32 a
= (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1);
702 uint32 b
= (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
703 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
706 SET_GPR (OP
[0] + 0, (tmp
>> 16));
707 SET_GPR (OP
[0] + 1, (tmp
& 0xFFFF));
708 trace_output_32 (sd
, tmp
);
713 OP_1000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
715 uint16 a
= GPR (OP
[1]);
717 uint16 tmp
= (a
+ b
);
718 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
720 SET_GPR (OP
[0], tmp
);
721 trace_output_16 (sd
, tmp
);
726 OP_17000200 (SIM_DESC sd
, SIM_CPU
*cpu
)
729 tmp
= SEXT40(ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
731 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
732 SET_GPR (OP
[0] + 0, ((tmp
>> 16) & 0xffff));
733 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
734 trace_output_32 (sd
, tmp
);
739 OP_17000202 (SIM_DESC sd
, SIM_CPU
*cpu
)
742 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
744 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
745 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
746 SET_GPR (OP
[0] + 1, tmp
& 0xffff);
747 trace_output_32 (sd
, tmp
);
752 OP_17001200 (SIM_DESC sd
, SIM_CPU
*cpu
)
757 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
758 tmp
= SEXT40 (ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
759 if (tmp
> SEXT40(MAX32
))
764 else if (tmp
< SEXT40(MIN32
))
773 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
774 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
775 trace_output_32 (sd
, tmp
);
780 OP_17001202 (SIM_DESC sd
, SIM_CPU
*cpu
)
785 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
786 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
787 if (tmp
> SEXT40(MAX32
))
792 else if (tmp
< SEXT40(MIN32
))
801 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
802 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
803 trace_output_32 (sd
, tmp
);
808 OP_201 (SIM_DESC sd
, SIM_CPU
*cpu
)
810 uint16 a
= GPR (OP
[0]);
817 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
819 SET_GPR (OP
[0], tmp
);
820 trace_output_16 (sd
, tmp
);
825 OP_C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
827 uint16 tmp
= GPR (OP
[0]) & GPR (OP
[1]);
828 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
829 SET_GPR (OP
[0], tmp
);
830 trace_output_16 (sd
, tmp
);
835 OP_6000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
837 uint16 tmp
= GPR (OP
[1]) & OP
[2];
838 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
839 SET_GPR (OP
[0], tmp
);
840 trace_output_16 (sd
, tmp
);
845 OP_C01 (SIM_DESC sd
, SIM_CPU
*cpu
)
848 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
849 tmp
= (GPR (OP
[0]) &~(0x8000 >> OP
[1]));
850 SET_GPR (OP
[0], tmp
);
851 trace_output_16 (sd
, tmp
);
856 OP_4900 (SIM_DESC sd
, SIM_CPU
*cpu
)
858 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
859 SET_GPR (13, PC
+ 1);
860 JMP( PC
+ SEXT8 (OP
[0]));
861 trace_output_void (sd
);
866 OP_24800000 (SIM_DESC sd
, SIM_CPU
*cpu
)
868 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
869 SET_GPR (13, (PC
+ 1));
871 trace_output_void (sd
);
876 OP_A01 (SIM_DESC sd
, SIM_CPU
*cpu
)
879 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
880 tmp
= (GPR (OP
[0]) ^ (0x8000 >> OP
[1]));
881 SET_GPR (OP
[0], tmp
);
882 trace_output_16 (sd
, tmp
);
887 OP_4800 (SIM_DESC sd
, SIM_CPU
*cpu
)
889 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
890 JMP (PC
+ SEXT8 (OP
[0]));
891 trace_output_void (sd
);
896 OP_24000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
898 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
900 trace_output_void (sd
);
905 OP_4A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
907 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
909 JMP (PC
+ SEXT8 (OP
[0]));
910 trace_output_flag (sd
);
915 OP_25000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
917 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
920 trace_output_flag (sd
);
925 OP_4B00 (SIM_DESC sd
, SIM_CPU
*cpu
)
927 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
929 JMP (PC
+ SEXT8 (OP
[0]));
930 trace_output_flag (sd
);
935 OP_25800000 (SIM_DESC sd
, SIM_CPU
*cpu
)
937 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
940 trace_output_flag (sd
);
945 OP_801 (SIM_DESC sd
, SIM_CPU
*cpu
)
948 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
949 tmp
= (GPR (OP
[0]) | (0x8000 >> OP
[1]));
950 SET_GPR (OP
[0], tmp
);
951 trace_output_16 (sd
, tmp
);
956 OP_E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
958 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
960 SET_PSW_F0 ((GPR (OP
[0]) & (0x8000 >> OP
[1])) ? 1 : 0);
961 trace_output_flag (sd
);
966 OP_5601 (SIM_DESC sd
, SIM_CPU
*cpu
)
968 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
970 trace_output_40 (sd
, 0);
975 OP_600 (SIM_DESC sd
, SIM_CPU
*cpu
)
977 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
979 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(GPR (OP
[1]))) ? 1 : 0);
980 trace_output_flag (sd
);
985 OP_1603 (SIM_DESC sd
, SIM_CPU
*cpu
)
987 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
989 SET_PSW_F0 ((SEXT40(ACC (OP
[0])) < SEXT40(ACC (OP
[1]))) ? 1 : 0);
990 trace_output_flag (sd
);
995 OP_400 (SIM_DESC sd
, SIM_CPU
*cpu
)
997 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
999 SET_PSW_F0 ((GPR (OP
[0]) == GPR (OP
[1])) ? 1 : 0);
1000 trace_output_flag (sd
);
1005 OP_1403 (SIM_DESC sd
, SIM_CPU
*cpu
)
1007 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1008 SET_PSW_F1 (PSW_F0
);
1009 SET_PSW_F0 (((ACC (OP
[0]) & MASK40
) == (ACC (OP
[1]) & MASK40
)) ? 1 : 0);
1010 trace_output_flag (sd
);
1015 OP_401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1017 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1018 SET_PSW_F1 (PSW_F0
);
1019 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
) SEXT4 (OP
[1])) ? 1 : 0);
1020 trace_output_flag (sd
);
1025 OP_2000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1027 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1028 SET_PSW_F1 (PSW_F0
);
1029 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
)OP
[1]) ? 1 : 0);
1030 trace_output_flag (sd
);
1035 OP_601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1037 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1038 SET_PSW_F1 (PSW_F0
);
1039 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)SEXT4(OP
[1])) ? 1 : 0);
1040 trace_output_flag (sd
);
1045 OP_3000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1047 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1048 SET_PSW_F1 (PSW_F0
);
1049 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(OP
[1])) ? 1 : 0);
1050 trace_output_flag (sd
);
1055 OP_4600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1057 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1058 SET_PSW_F1 (PSW_F0
);
1059 SET_PSW_F0 ((GPR (OP
[0]) < GPR (OP
[1])) ? 1 : 0);
1060 trace_output_flag (sd
);
1065 OP_23000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1067 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1068 SET_PSW_F1 (PSW_F0
);
1069 SET_PSW_F0 ((GPR (OP
[0]) < (reg_t
)OP
[1]) ? 1 : 0);
1070 trace_output_flag (sd
);
1075 OP_4E09 (SIM_DESC sd
, SIM_CPU
*cpu
)
1079 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1083 else if (OP
[1] == 1)
1092 trace_output_flag (sd
);
1097 OP_4E0F (SIM_DESC sd
, SIM_CPU
*cpu
)
1101 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1105 else if (OP
[1] == 1)
1114 trace_output_flag (sd
);
1119 OP_5F20 (SIM_DESC sd
, SIM_CPU
*cpu
)
1121 /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */
1123 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1124 The conditional below is for either of the instruction pairs
1125 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1126 where the dbt instruction should be interpreted.
1128 The module `sim-break' provides a more effective mechanism for
1129 detecting GDB planted breakpoints. The code below may,
1130 eventually, be changed to use that mechanism. */
1132 if (State
.ins_type
== INS_LEFT
1133 || State
.ins_type
== INS_RIGHT
)
1135 trace_input ("dbt", OP_VOID
, OP_VOID
, OP_VOID
);
1138 SET_HW_PSW (PSW_DM_BIT
| (PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1139 JMP (DBT_VECTOR_START
);
1140 trace_output_void (sd
);
1143 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1148 OP_14002800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1150 uint16 foo
, tmp
, tmpf
;
1154 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1155 foo
= (GPR (OP
[0]) << 1) | (GPR (OP
[0] + 1) >> 15);
1156 tmp
= (int16
)foo
- (int16
)(GPR (OP
[1]));
1157 tmpf
= (foo
>= GPR (OP
[1])) ? 1 : 0;
1158 hi
= ((tmpf
== 1) ? tmp
: foo
);
1159 lo
= ((GPR (OP
[0] + 1) << 1) | tmpf
);
1160 SET_GPR (OP
[0] + 0, hi
);
1161 SET_GPR (OP
[0] + 1, lo
);
1162 trace_output_32 (sd
, ((uint32
) hi
<< 16) | lo
);
1167 OP_4E04 (SIM_DESC sd
, SIM_CPU
*cpu
)
1169 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1170 State
.exe
= (PSW_F0
== 0);
1171 trace_output_flag (sd
);
1176 OP_4E24 (SIM_DESC sd
, SIM_CPU
*cpu
)
1178 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1179 State
.exe
= (PSW_F0
!= 0);
1180 trace_output_flag (sd
);
1185 OP_4E40 (SIM_DESC sd
, SIM_CPU
*cpu
)
1187 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1188 State
.exe
= (PSW_F1
== 0);
1189 trace_output_flag (sd
);
1194 OP_4E42 (SIM_DESC sd
, SIM_CPU
*cpu
)
1196 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1197 State
.exe
= (PSW_F1
!= 0);
1198 trace_output_flag (sd
);
1203 OP_4E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1205 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1206 State
.exe
= (PSW_F0
== 0) & (PSW_F1
== 0);
1207 trace_output_flag (sd
);
1212 OP_4E02 (SIM_DESC sd
, SIM_CPU
*cpu
)
1214 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1215 State
.exe
= (PSW_F0
== 0) & (PSW_F1
!= 0);
1216 trace_output_flag (sd
);
1221 OP_4E20 (SIM_DESC sd
, SIM_CPU
*cpu
)
1223 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1224 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
== 0);
1225 trace_output_flag (sd
);
1230 OP_4E22 (SIM_DESC sd
, SIM_CPU
*cpu
)
1232 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1233 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
!= 0);
1234 trace_output_flag (sd
);
1239 OP_15002A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1244 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1245 if (((int16
)GPR (OP
[1])) >= 0)
1246 tmp
= (GPR (OP
[1]) << 16) | GPR (OP
[1] + 1);
1248 tmp
= ~((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
1255 SET_GPR (OP
[0], (i
- 1));
1256 trace_output_16 (sd
, i
- 1);
1261 SET_GPR (OP
[0], 16);
1262 trace_output_16 (sd
, 16);
1267 OP_15002A02 (SIM_DESC sd
, SIM_CPU
*cpu
)
1272 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1273 tmp
= SEXT40(ACC (OP
[1]));
1275 tmp
= ~tmp
& MASK40
;
1277 foo
= 0x4000000000LL
;
1282 SET_GPR (OP
[0], i
- 9);
1283 trace_output_16 (sd
, i
- 9);
1288 SET_GPR (OP
[0], 16);
1289 trace_output_16 (sd
, 16);
1294 OP_4D00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1296 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1297 SET_GPR (13, PC
+ 1);
1299 trace_output_void (sd
);
1304 OP_4C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1306 trace_input ("jmp", OP_REG
,
1307 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1308 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1311 trace_output_void (sd
);
1316 OP_30000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1319 uint16 addr
= OP
[1] + GPR (OP
[2]);
1320 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1323 trace_output_void (sd
);
1324 EXCEPTION (SIM_SIGBUS
);
1327 SET_GPR (OP
[0], tmp
);
1328 trace_output_16 (sd
, tmp
);
1333 OP_6401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1336 uint16 addr
= GPR (OP
[1]);
1337 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1340 trace_output_void (sd
);
1341 EXCEPTION (SIM_SIGBUS
);
1344 SET_GPR (OP
[0], tmp
);
1346 INC_ADDR (OP
[1], -2);
1347 trace_output_16 (sd
, tmp
);
1352 OP_6001 (SIM_DESC sd
, SIM_CPU
*cpu
)
1355 uint16 addr
= GPR (OP
[1]);
1356 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1359 trace_output_void (sd
);
1360 EXCEPTION (SIM_SIGBUS
);
1363 SET_GPR (OP
[0], tmp
);
1365 INC_ADDR (OP
[1], 2);
1366 trace_output_16 (sd
, tmp
);
1371 OP_6000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1374 uint16 addr
= GPR (OP
[1]);
1375 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1378 trace_output_void (sd
);
1379 EXCEPTION (SIM_SIGBUS
);
1382 SET_GPR (OP
[0], tmp
);
1383 trace_output_16 (sd
, tmp
);
1388 OP_32010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1391 uint16 addr
= OP
[1];
1392 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1395 trace_output_void (sd
);
1396 EXCEPTION (SIM_SIGBUS
);
1399 SET_GPR (OP
[0], tmp
);
1400 trace_output_16 (sd
, tmp
);
1405 OP_31000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1408 uint16 addr
= OP
[1] + GPR (OP
[2]);
1409 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1412 trace_output_void (sd
);
1413 EXCEPTION (SIM_SIGBUS
);
1416 SET_GPR32 (OP
[0], tmp
);
1417 trace_output_32 (sd
, tmp
);
1422 OP_6601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1424 uint16 addr
= GPR (OP
[1]);
1426 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1429 trace_output_void (sd
);
1430 EXCEPTION (SIM_SIGBUS
);
1433 SET_GPR32 (OP
[0], tmp
);
1434 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1435 INC_ADDR (OP
[1], -4);
1436 trace_output_32 (sd
, tmp
);
1441 OP_6201 (SIM_DESC sd
, SIM_CPU
*cpu
)
1444 uint16 addr
= GPR (OP
[1]);
1445 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1448 trace_output_void (sd
);
1449 EXCEPTION (SIM_SIGBUS
);
1452 SET_GPR32 (OP
[0], tmp
);
1453 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1454 INC_ADDR (OP
[1], 4);
1455 trace_output_32 (sd
, tmp
);
1460 OP_6200 (SIM_DESC sd
, SIM_CPU
*cpu
)
1462 uint16 addr
= GPR (OP
[1]);
1464 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1467 trace_output_void (sd
);
1468 EXCEPTION (SIM_SIGBUS
);
1471 SET_GPR32 (OP
[0], tmp
);
1472 trace_output_32 (sd
, tmp
);
1477 OP_33010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1480 uint16 addr
= OP
[1];
1481 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1484 trace_output_void (sd
);
1485 EXCEPTION (SIM_SIGBUS
);
1488 SET_GPR32 (OP
[0], tmp
);
1489 trace_output_32 (sd
, tmp
);
1494 OP_38000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1497 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1498 tmp
= SEXT8 (RB (OP
[1] + GPR (OP
[2])));
1499 SET_GPR (OP
[0], tmp
);
1500 trace_output_16 (sd
, tmp
);
1505 OP_7000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1508 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1509 tmp
= SEXT8 (RB (GPR (OP
[1])));
1510 SET_GPR (OP
[0], tmp
);
1511 trace_output_16 (sd
, tmp
);
1516 OP_4001 (SIM_DESC sd
, SIM_CPU
*cpu
)
1519 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1520 tmp
= SEXT4 (OP
[1]);
1521 SET_GPR (OP
[0], tmp
);
1522 trace_output_16 (sd
, tmp
);
1527 OP_20000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1530 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1532 SET_GPR (OP
[0], tmp
);
1533 trace_output_16 (sd
, tmp
);
1538 OP_39000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1541 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1542 tmp
= RB (OP
[1] + GPR (OP
[2]));
1543 SET_GPR (OP
[0], tmp
);
1544 trace_output_16 (sd
, tmp
);
1549 OP_7200 (SIM_DESC sd
, SIM_CPU
*cpu
)
1552 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1553 tmp
= RB (GPR (OP
[1]));
1554 SET_GPR (OP
[0], tmp
);
1555 trace_output_16 (sd
, tmp
);
1560 OP_2A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1564 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1565 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1568 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1570 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1573 tmp
+= SEXT40 (ACC (OP
[0]));
1576 if (tmp
> SEXT40(MAX32
))
1578 else if (tmp
< SEXT40(MIN32
))
1581 tmp
= (tmp
& MASK40
);
1584 tmp
= (tmp
& MASK40
);
1585 SET_ACC (OP
[0], tmp
);
1586 trace_output_40 (sd
, tmp
);
1591 OP_1A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1595 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1596 tmp
= SEXT40 ((int16
) GPR (OP
[1]) * GPR (OP
[2]));
1598 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1599 tmp
= ((SEXT40 (ACC (OP
[0])) + tmp
) & MASK40
);
1600 SET_ACC (OP
[0], tmp
);
1601 trace_output_40 (sd
, tmp
);
1606 OP_3A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1612 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1613 src1
= (uint16
) GPR (OP
[1]);
1614 src2
= (uint16
) GPR (OP
[2]);
1618 tmp
= ((ACC (OP
[0]) + tmp
) & MASK40
);
1619 SET_ACC (OP
[0], tmp
);
1620 trace_output_40 (sd
, tmp
);
1625 OP_2600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1628 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1629 SET_PSW_F1 (PSW_F0
);
1630 if ((int16
) GPR (OP
[1]) > (int16
)GPR (OP
[0]))
1640 SET_GPR (OP
[0], tmp
);
1641 trace_output_16 (sd
, tmp
);
1646 OP_3600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1650 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1651 SET_PSW_F1 (PSW_F0
);
1652 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1653 if (tmp
> SEXT40 (ACC (OP
[0])))
1655 tmp
= (tmp
& MASK40
);
1663 SET_ACC (OP
[0], tmp
);
1664 trace_output_40 (sd
, tmp
);
1669 OP_3602 (SIM_DESC sd
, SIM_CPU
*cpu
)
1672 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1673 SET_PSW_F1 (PSW_F0
);
1674 if (SEXT40 (ACC (OP
[1])) > SEXT40 (ACC (OP
[0])))
1684 SET_ACC (OP
[0], tmp
);
1685 trace_output_40 (sd
, tmp
);
1691 OP_2601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1694 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1695 SET_PSW_F1 (PSW_F0
);
1696 if ((int16
)GPR (OP
[1]) < (int16
)GPR (OP
[0]))
1706 SET_GPR (OP
[0], tmp
);
1707 trace_output_16 (sd
, tmp
);
1712 OP_3601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1716 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1717 SET_PSW_F1 (PSW_F0
);
1718 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1719 if (tmp
< SEXT40(ACC (OP
[0])))
1721 tmp
= (tmp
& MASK40
);
1729 SET_ACC (OP
[0], tmp
);
1730 trace_output_40 (sd
, tmp
);
1735 OP_3603 (SIM_DESC sd
, SIM_CPU
*cpu
)
1738 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1739 SET_PSW_F1 (PSW_F0
);
1740 if (SEXT40(ACC (OP
[1])) < SEXT40(ACC (OP
[0])))
1750 SET_ACC (OP
[0], tmp
);
1751 trace_output_40 (sd
, tmp
);
1756 OP_2800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1760 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1761 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1764 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1766 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1769 tmp
= SEXT40(ACC (OP
[0])) - tmp
;
1772 if (tmp
> SEXT40(MAX32
))
1774 else if (tmp
< SEXT40(MIN32
))
1777 tmp
= (tmp
& MASK40
);
1781 tmp
= (tmp
& MASK40
);
1783 SET_ACC (OP
[0], tmp
);
1784 trace_output_40 (sd
, tmp
);
1789 OP_1800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1793 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1794 tmp
= SEXT40 ((int16
)GPR (OP
[1]) * GPR (OP
[2]));
1796 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1797 tmp
= ((SEXT40 (ACC (OP
[0])) - tmp
) & MASK40
);
1798 SET_ACC (OP
[0], tmp
);
1799 trace_output_40 (sd
, tmp
);
1804 OP_3800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1810 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1811 src1
= (uint16
) GPR (OP
[1]);
1812 src2
= (uint16
) GPR (OP
[2]);
1816 tmp
= ((ACC (OP
[0]) - tmp
) & MASK40
);
1817 SET_ACC (OP
[0], tmp
);
1818 trace_output_40 (sd
, tmp
);
1823 OP_2E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1826 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1827 tmp
= GPR (OP
[0]) * GPR (OP
[1]);
1828 SET_GPR (OP
[0], tmp
);
1829 trace_output_16 (sd
, tmp
);
1834 OP_2C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1838 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1839 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1842 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1844 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1847 tmp
= (tmp
& MASK40
);
1848 SET_ACC (OP
[0], tmp
);
1849 trace_output_40 (sd
, tmp
);
1854 OP_1C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1858 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1859 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * GPR (OP
[2]));
1863 tmp
= (tmp
& MASK40
);
1864 SET_ACC (OP
[0], tmp
);
1865 trace_output_40 (sd
, tmp
);
1870 OP_3C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1876 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1877 src1
= (uint16
) GPR (OP
[1]);
1878 src2
= (uint16
) GPR (OP
[2]);
1882 tmp
= (tmp
& MASK40
);
1883 SET_ACC (OP
[0], tmp
);
1884 trace_output_40 (sd
, tmp
);
1889 OP_4000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1892 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1894 SET_GPR (OP
[0], tmp
);
1895 trace_output_16 (sd
, tmp
);
1900 OP_5000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1903 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1904 tmp
= GPR32 (OP
[1]);
1905 SET_GPR32 (OP
[0], tmp
);
1906 trace_output_32 (sd
, tmp
);
1911 OP_3E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1914 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1916 SET_GPR32 (OP
[0], tmp
);
1917 trace_output_32 (sd
, tmp
);
1922 OP_3E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
1925 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1926 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1)) & MASK40
);
1927 SET_ACC (OP
[1], tmp
);
1928 trace_output_40 (sd
, tmp
);
1933 OP_3E03 (SIM_DESC sd
, SIM_CPU
*cpu
)
1936 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1938 SET_ACC (OP
[0], tmp
);
1939 trace_output_40 (sd
, tmp
);
1944 OP_5400 (SIM_DESC sd
, SIM_CPU
*cpu
)
1947 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1948 tmp
= SEXT8 (GPR (OP
[1]) & 0xff);
1949 SET_GPR (OP
[0], tmp
);
1950 trace_output_16 (sd
, tmp
);
1955 OP_4400 (SIM_DESC sd
, SIM_CPU
*cpu
)
1958 trace_input ("mvf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1962 SET_GPR (OP
[0], tmp
);
1966 trace_output_16 (sd
, tmp
);
1971 OP_4401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1974 trace_input ("mvf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1978 SET_GPR (OP
[0], tmp
);
1982 trace_output_16 (sd
, tmp
);
1987 OP_1E04 (SIM_DESC sd
, SIM_CPU
*cpu
)
1990 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1991 tmp
= ((ACC (OP
[1]) >> 32) & 0xff);
1992 SET_GPR (OP
[0], tmp
);
1993 trace_output_16 (sd
, tmp
);
1998 OP_1E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2001 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2002 tmp
= (ACC (OP
[1]) >> 16);
2003 SET_GPR (OP
[0], tmp
);
2004 trace_output_16 (sd
, tmp
);
2009 OP_1E02 (SIM_DESC sd
, SIM_CPU
*cpu
)
2012 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2014 SET_GPR (OP
[0], tmp
);
2015 trace_output_16 (sd
, tmp
);
2020 OP_5200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2023 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
2025 SET_GPR (OP
[0], tmp
);
2026 trace_output_16 (sd
, tmp
);
2031 OP_1E41 (SIM_DESC sd
, SIM_CPU
*cpu
)
2034 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
2035 tmp
= ((ACC (OP
[1]) & MASK32
)
2036 | ((int64
)(GPR (OP
[0]) & 0xff) << 32));
2037 SET_ACC (OP
[1], tmp
);
2038 trace_output_40 (sd
, tmp
);
2043 OP_1E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2046 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
2047 tmp
= ACC (OP
[1]) & 0xffff;
2048 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | tmp
) & MASK40
);
2049 SET_ACC (OP
[1], tmp
);
2050 trace_output_40 (sd
, tmp
);
2055 OP_1E21 (SIM_DESC sd
, SIM_CPU
*cpu
)
2058 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
2059 tmp
= ((SEXT16 (GPR (OP
[0]))) & MASK40
);
2060 SET_ACC (OP
[1], tmp
);
2061 trace_output_40 (sd
, tmp
);
2066 OP_5600 (SIM_DESC sd
, SIM_CPU
*cpu
)
2069 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
2071 tmp
= SET_CREG (OP
[1], tmp
);
2072 trace_output_16 (sd
, tmp
);
2077 OP_5401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2080 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
2081 tmp
= (GPR (OP
[1]) & 0xff);
2082 SET_GPR (OP
[0], tmp
);
2083 trace_output_16 (sd
, tmp
);
2088 OP_4605 (SIM_DESC sd
, SIM_CPU
*cpu
)
2091 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
2092 tmp
= - GPR (OP
[0]);
2093 SET_GPR (OP
[0], tmp
);
2094 trace_output_16 (sd
, tmp
);
2099 OP_5605 (SIM_DESC sd
, SIM_CPU
*cpu
)
2103 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
2104 tmp
= -SEXT40(ACC (OP
[0]));
2107 if (tmp
> SEXT40(MAX32
))
2109 else if (tmp
< SEXT40(MIN32
))
2112 tmp
= (tmp
& MASK40
);
2115 tmp
= (tmp
& MASK40
);
2116 SET_ACC (OP
[0], tmp
);
2117 trace_output_40 (sd
, tmp
);
2123 OP_5E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2125 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
2127 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
2128 switch (State
.ins_type
)
2131 ins_type_counters
[ (int)INS_UNKNOWN
]++;
2134 case INS_LEFT_PARALLEL
:
2135 /* Don't count a parallel op that includes a NOP as a true parallel op */
2136 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
2137 ins_type_counters
[ (int)INS_RIGHT
]++;
2138 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2142 case INS_LEFT_COND_EXE
:
2143 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2146 case INS_RIGHT_PARALLEL
:
2147 /* Don't count a parallel op that includes a NOP as a true parallel op */
2148 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
2149 ins_type_counters
[ (int)INS_LEFT
]++;
2150 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2154 case INS_RIGHT_COND_EXE
:
2155 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2159 trace_output_void (sd
);
2164 OP_4603 (SIM_DESC sd
, SIM_CPU
*cpu
)
2167 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
2169 SET_GPR (OP
[0], tmp
);
2170 trace_output_16 (sd
, tmp
);
2175 OP_800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2178 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
2179 tmp
= (GPR (OP
[0]) | GPR (OP
[1]));
2180 SET_GPR (OP
[0], tmp
);
2181 trace_output_16 (sd
, tmp
);
2186 OP_4000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2189 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2190 tmp
= (GPR (OP
[1]) | OP
[2]);
2191 SET_GPR (OP
[0], tmp
);
2192 trace_output_16 (sd
, tmp
);
2197 OP_5201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2200 int shift
= SEXT3 (OP
[2]);
2202 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2206 "ERROR at PC 0x%x: instruction only valid for A0\n",
2208 EXCEPTION (SIM_SIGILL
);
2211 SET_PSW_F1 (PSW_F0
);
2212 tmp
= SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2218 tmp
>>= 16; /* look at bits 0:43 */
2219 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2224 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2233 SET_GPR32 (OP
[0], tmp
);
2234 trace_output_32 (sd
, tmp
);
2239 OP_4201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2242 int shift
= SEXT3 (OP
[2]);
2244 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2245 SET_PSW_F1 (PSW_F0
);
2247 tmp
= SEXT40 (ACC (OP
[1])) << shift
;
2249 tmp
= SEXT40 (ACC (OP
[1])) >> -shift
;
2252 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2257 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2267 SET_GPR (OP
[0], tmp
);
2268 trace_output_16 (sd
, tmp
);
2273 OP_27000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2275 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2277 SET_RPT_E (PC
+ OP
[1]);
2278 SET_RPT_C (GPR (OP
[0]));
2280 if (GPR (OP
[0]) == 0)
2282 sim_io_printf (sd
, "ERROR: rep with count=0 is illegal.\n");
2283 EXCEPTION (SIM_SIGILL
);
2287 sim_io_printf (sd
, "ERROR: rep must include at least 4 instructions.\n");
2288 EXCEPTION (SIM_SIGILL
);
2290 trace_output_void (sd
);
2295 OP_2F000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2297 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2299 SET_RPT_E (PC
+ OP
[1]);
2304 sim_io_printf (sd
, "ERROR: repi with count=0 is illegal.\n");
2305 EXCEPTION (SIM_SIGILL
);
2309 sim_io_printf (sd
, "ERROR: repi must include at least 4 instructions.\n");
2310 EXCEPTION (SIM_SIGILL
);
2312 trace_output_void (sd
);
2317 OP_5F60 (SIM_DESC sd
, SIM_CPU
*cpu
)
2319 trace_input ("rtd", OP_VOID
, OP_VOID
, OP_VOID
);
2320 SET_CREG (PSW_CR
, DPSW
);
2322 trace_output_void (sd
);
2327 OP_5F40 (SIM_DESC sd
, SIM_CPU
*cpu
)
2329 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2330 SET_CREG (PSW_CR
, BPSW
);
2332 trace_output_void (sd
);
2336 void OP_5209 (SIM_DESC sd
, SIM_CPU
*cpu
)
2340 trace_input ("sac", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2342 tmp
= SEXT40(ACC (OP
[1]));
2344 SET_PSW_F1 (PSW_F0
);
2346 if (tmp
> SEXT40(MAX32
))
2351 else if (tmp
< SEXT40(MIN32
))
2358 tmp
= (tmp
& MASK32
);
2362 SET_GPR32 (OP
[0], tmp
);
2364 trace_output_40 (sd
, tmp
);
2369 OP_4209 (SIM_DESC sd
, SIM_CPU
*cpu
)
2373 trace_input ("sachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2375 tmp
= SEXT40(ACC (OP
[1]));
2377 SET_PSW_F1 (PSW_F0
);
2379 if (tmp
> SEXT40(MAX32
))
2384 else if (tmp
< SEXT40(MIN32
))
2395 SET_GPR (OP
[0], tmp
);
2397 trace_output_16 (sd
, OP
[0]);
2402 OP_1223 (SIM_DESC sd
, SIM_CPU
*cpu
)
2406 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2407 tmp
= SEXT40(ACC (OP
[0])) + (SEXT40(ACC (OP
[1])) >> 16);
2410 if (tmp
> SEXT40(MAX32
))
2412 else if (tmp
< SEXT40(MIN32
))
2415 tmp
= (tmp
& MASK40
);
2418 tmp
= (tmp
& MASK40
);
2419 SET_ACC (OP
[0], tmp
);
2420 trace_output_40 (sd
, tmp
);
2425 OP_4611 (SIM_DESC sd
, SIM_CPU
*cpu
)
2428 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2429 tmp
= ((PSW_F0
== 0) ? 1 : 0);
2430 SET_GPR (OP
[0], tmp
);
2431 trace_output_16 (sd
, tmp
);
2436 OP_4613 (SIM_DESC sd
, SIM_CPU
*cpu
)
2439 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2440 tmp
= ((PSW_F0
== 1) ? 1 : 0);
2441 SET_GPR (OP
[0], tmp
);
2442 trace_output_16 (sd
, tmp
);
2447 OP_3220 (SIM_DESC sd
, SIM_CPU
*cpu
)
2452 trace_input ("slae", OP_ACCUM
, OP_REG
, OP_VOID
);
2454 reg
= SEXT16 (GPR (OP
[1]));
2456 if (reg
>= 17 || reg
<= -17)
2458 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", reg
);
2459 EXCEPTION (SIM_SIGILL
);
2462 tmp
= SEXT40 (ACC (OP
[0]));
2464 if (PSW_ST
&& (tmp
< SEXT40 (MIN32
) || tmp
> SEXT40 (MAX32
)))
2466 sim_io_printf (sd
, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp
>> 32) & 0xff), ((unsigned long) tmp
) & 0xffffffff);
2467 EXCEPTION (SIM_SIGILL
);
2470 if (reg
>= 0 && reg
<= 16)
2472 tmp
= SEXT56 ((SEXT56 (tmp
)) << (GPR (OP
[1])));
2475 if (tmp
> SEXT40(MAX32
))
2477 else if (tmp
< SEXT40(MIN32
))
2480 tmp
= (tmp
& MASK40
);
2483 tmp
= (tmp
& MASK40
);
2487 tmp
= (SEXT40 (ACC (OP
[0]))) >> (-GPR (OP
[1]));
2490 SET_ACC(OP
[0], tmp
);
2492 trace_output_40 (sd
, tmp
);
2497 OP_5FC0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2499 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2501 trace_output_void (sd
);
2506 OP_2200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2509 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2510 tmp
= (GPR (OP
[0]) << (GPR (OP
[1]) & 0xf));
2511 SET_GPR (OP
[0], tmp
);
2512 trace_output_16 (sd
, tmp
);
2517 OP_3200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2520 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2521 if ((GPR (OP
[1]) & 31) <= 16)
2522 tmp
= SEXT40 (ACC (OP
[0])) << (GPR (OP
[1]) & 31);
2525 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2526 EXCEPTION (SIM_SIGILL
);
2531 if (tmp
> SEXT40(MAX32
))
2533 else if (tmp
< SEXT40(MIN32
))
2536 tmp
= (tmp
& MASK40
);
2539 tmp
= (tmp
& MASK40
);
2540 SET_ACC (OP
[0], tmp
);
2541 trace_output_40 (sd
, tmp
);
2546 OP_2201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2549 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2550 tmp
= (GPR (OP
[0]) << OP
[1]);
2551 SET_GPR (OP
[0], tmp
);
2552 trace_output_16 (sd
, tmp
);
2557 OP_3201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2564 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2565 tmp
= SEXT40(ACC (OP
[0])) << OP
[1];
2569 if (tmp
> SEXT40(MAX32
))
2571 else if (tmp
< SEXT40(MIN32
))
2574 tmp
= (tmp
& MASK40
);
2577 tmp
= (tmp
& MASK40
);
2578 SET_ACC (OP
[0], tmp
);
2579 trace_output_40 (sd
, tmp
);
2584 OP_460B (SIM_DESC sd
, SIM_CPU
*cpu
)
2587 trace_input ("slx", OP_REG
, OP_VOID
, OP_VOID
);
2588 tmp
= ((GPR (OP
[0]) << 1) | PSW_F0
);
2589 SET_GPR (OP
[0], tmp
);
2590 trace_output_16 (sd
, tmp
);
2595 OP_2400 (SIM_DESC sd
, SIM_CPU
*cpu
)
2598 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2599 tmp
= (((int16
)(GPR (OP
[0]))) >> (GPR (OP
[1]) & 0xf));
2600 SET_GPR (OP
[0], tmp
);
2601 trace_output_16 (sd
, tmp
);
2606 OP_3400 (SIM_DESC sd
, SIM_CPU
*cpu
)
2608 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2609 if ((GPR (OP
[1]) & 31) <= 16)
2611 int64 tmp
= ((SEXT40(ACC (OP
[0])) >> (GPR (OP
[1]) & 31)) & MASK40
);
2612 SET_ACC (OP
[0], tmp
);
2613 trace_output_40 (sd
, tmp
);
2617 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2618 EXCEPTION (SIM_SIGILL
);
2624 OP_2401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2627 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2628 tmp
= (((int16
)(GPR (OP
[0]))) >> OP
[1]);
2629 SET_GPR (OP
[0], tmp
);
2630 trace_output_16 (sd
, tmp
);
2635 OP_3401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2641 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2642 tmp
= ((SEXT40(ACC (OP
[0])) >> OP
[1]) & MASK40
);
2643 SET_ACC (OP
[0], tmp
);
2644 trace_output_40 (sd
, tmp
);
2649 OP_2000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2652 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2653 tmp
= (GPR (OP
[0]) >> (GPR (OP
[1]) & 0xf));
2654 SET_GPR (OP
[0], tmp
);
2655 trace_output_16 (sd
, tmp
);
2660 OP_3000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2662 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2663 if ((GPR (OP
[1]) & 31) <= 16)
2665 int64 tmp
= ((uint64
)((ACC (OP
[0]) & MASK40
) >> (GPR (OP
[1]) & 31)));
2666 SET_ACC (OP
[0], tmp
);
2667 trace_output_40 (sd
, tmp
);
2671 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2672 EXCEPTION (SIM_SIGILL
);
2679 OP_2001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2682 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2683 tmp
= (GPR (OP
[0]) >> OP
[1]);
2684 SET_GPR (OP
[0], tmp
);
2685 trace_output_16 (sd
, tmp
);
2690 OP_3001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2696 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2697 tmp
= ((uint64
)(ACC (OP
[0]) & MASK40
) >> OP
[1]);
2698 SET_ACC (OP
[0], tmp
);
2699 trace_output_40 (sd
, tmp
);
2704 OP_4609 (SIM_DESC sd
, SIM_CPU
*cpu
)
2707 trace_input ("srx", OP_REG
, OP_VOID
, OP_VOID
);
2709 tmp
= ((GPR (OP
[0]) >> 1) | tmp
);
2710 SET_GPR (OP
[0], tmp
);
2711 trace_output_16 (sd
, tmp
);
2716 OP_34000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2718 uint16 addr
= OP
[1] + GPR (OP
[2]);
2719 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2722 trace_output_void (sd
);
2723 EXCEPTION (SIM_SIGBUS
);
2725 SW (addr
, GPR (OP
[0]));
2726 trace_output_void (sd
);
2731 OP_6800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2733 uint16 addr
= GPR (OP
[1]);
2734 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2737 trace_output_void (sd
);
2738 EXCEPTION (SIM_SIGBUS
);
2740 SW (addr
, GPR (OP
[0]));
2741 trace_output_void (sd
);
2747 OP_6C1F (SIM_DESC sd
, SIM_CPU
*cpu
)
2749 uint16 addr
= GPR (OP
[1]) - 2;
2750 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2753 sim_io_printf (sd
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2754 EXCEPTION (SIM_SIGILL
);
2758 trace_output_void (sd
);
2759 EXCEPTION (SIM_SIGBUS
);
2761 SW (addr
, GPR (OP
[0]));
2762 SET_GPR (OP
[1], addr
);
2763 trace_output_void (sd
);
2768 OP_6801 (SIM_DESC sd
, SIM_CPU
*cpu
)
2770 uint16 addr
= GPR (OP
[1]);
2771 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2774 trace_output_void (sd
);
2775 EXCEPTION (SIM_SIGBUS
);
2777 SW (addr
, GPR (OP
[0]));
2778 INC_ADDR (OP
[1], 2);
2779 trace_output_void (sd
);
2784 OP_6C01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2786 uint16 addr
= GPR (OP
[1]);
2787 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2790 sim_io_printf (sd
, "ERROR: cannot post-decrement register r15 (SP).\n");
2791 EXCEPTION (SIM_SIGILL
);
2795 trace_output_void (sd
);
2796 EXCEPTION (SIM_SIGBUS
);
2798 SW (addr
, GPR (OP
[0]));
2799 INC_ADDR (OP
[1], -2);
2800 trace_output_void (sd
);
2805 OP_36010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2807 uint16 addr
= OP
[1];
2808 trace_input ("st", OP_REG
, OP_MEMREF3
, OP_VOID
);
2811 trace_output_void (sd
);
2812 EXCEPTION (SIM_SIGBUS
);
2814 SW (addr
, GPR (OP
[0]));
2815 trace_output_void (sd
);
2820 OP_35000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2822 uint16 addr
= GPR (OP
[2])+ OP
[1];
2823 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2826 trace_output_void (sd
);
2827 EXCEPTION (SIM_SIGBUS
);
2829 SW (addr
+ 0, GPR (OP
[0] + 0));
2830 SW (addr
+ 2, GPR (OP
[0] + 1));
2831 trace_output_void (sd
);
2836 OP_6A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2838 uint16 addr
= GPR (OP
[1]);
2839 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2842 trace_output_void (sd
);
2843 EXCEPTION (SIM_SIGBUS
);
2845 SW (addr
+ 0, GPR (OP
[0] + 0));
2846 SW (addr
+ 2, GPR (OP
[0] + 1));
2847 trace_output_void (sd
);
2852 OP_6E1F (SIM_DESC sd
, SIM_CPU
*cpu
)
2854 uint16 addr
= GPR (OP
[1]) - 4;
2855 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2858 sim_io_printf (sd
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2859 EXCEPTION (SIM_SIGILL
);
2863 trace_output_void (sd
);
2864 EXCEPTION (SIM_SIGBUS
);
2866 SW (addr
+ 0, GPR (OP
[0] + 0));
2867 SW (addr
+ 2, GPR (OP
[0] + 1));
2868 SET_GPR (OP
[1], addr
);
2869 trace_output_void (sd
);
2874 OP_6A01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2876 uint16 addr
= GPR (OP
[1]);
2877 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2880 trace_output_void (sd
);
2881 EXCEPTION (SIM_SIGBUS
);
2883 SW (addr
+ 0, GPR (OP
[0] + 0));
2884 SW (addr
+ 2, GPR (OP
[0] + 1));
2885 INC_ADDR (OP
[1], 4);
2886 trace_output_void (sd
);
2891 OP_6E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2893 uint16 addr
= GPR (OP
[1]);
2894 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2897 sim_io_printf (sd
, "ERROR: cannot post-decrement register r15 (SP).\n");
2898 EXCEPTION (SIM_SIGILL
);
2902 trace_output_void (sd
);
2903 EXCEPTION (SIM_SIGBUS
);
2905 SW (addr
+ 0, GPR (OP
[0] + 0));
2906 SW (addr
+ 2, GPR (OP
[0] + 1));
2907 INC_ADDR (OP
[1], -4);
2908 trace_output_void (sd
);
2913 OP_37010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2915 uint16 addr
= OP
[1];
2916 trace_input ("st2w", OP_DREG
, OP_MEMREF3
, OP_VOID
);
2919 trace_output_void (sd
);
2920 EXCEPTION (SIM_SIGBUS
);
2922 SW (addr
+ 0, GPR (OP
[0] + 0));
2923 SW (addr
+ 2, GPR (OP
[0] + 1));
2924 trace_output_void (sd
);
2929 OP_3C000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2931 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2932 SB (GPR (OP
[2]) + OP
[1], GPR (OP
[0]));
2933 trace_output_void (sd
);
2938 OP_7800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2940 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2941 SB (GPR (OP
[1]), GPR (OP
[0]));
2942 trace_output_void (sd
);
2947 OP_5FE0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2949 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2950 trace_output_void (sd
);
2951 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_exited
, 0);
2956 OP_0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2958 uint16 a
= GPR (OP
[0]);
2959 uint16 b
= GPR (OP
[1]);
2960 uint16 tmp
= (a
- b
);
2961 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2962 /* see ../common/sim-alu.h for a more extensive discussion on how to
2963 compute the carry/overflow bits. */
2965 SET_GPR (OP
[0], tmp
);
2966 trace_output_16 (sd
, tmp
);
2971 OP_1001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2975 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2976 tmp
= SEXT40(ACC (OP
[0])) - (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
2979 if (tmp
> SEXT40(MAX32
))
2981 else if (tmp
< SEXT40(MIN32
))
2984 tmp
= (tmp
& MASK40
);
2987 tmp
= (tmp
& MASK40
);
2988 SET_ACC (OP
[0], tmp
);
2990 trace_output_40 (sd
, tmp
);
2996 OP_1003 (SIM_DESC sd
, SIM_CPU
*cpu
)
3000 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
3001 tmp
= SEXT40(ACC (OP
[0])) - SEXT40(ACC (OP
[1]));
3004 if (tmp
> SEXT40(MAX32
))
3006 else if (tmp
< SEXT40(MIN32
))
3009 tmp
= (tmp
& MASK40
);
3012 tmp
= (tmp
& MASK40
);
3013 SET_ACC (OP
[0], tmp
);
3015 trace_output_40 (sd
, tmp
);
3020 OP_1000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3024 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
3025 a
= (uint32
)((GPR (OP
[0]) << 16) | GPR (OP
[0] + 1));
3026 b
= (uint32
)((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
3027 /* see ../common/sim-alu.h for a more extensive discussion on how to
3028 compute the carry/overflow bits */
3031 SET_GPR32 (OP
[0], tmp
);
3032 trace_output_32 (sd
, tmp
);
3037 OP_17000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3041 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3042 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40 (ACC (OP
[2]));
3043 SET_GPR32 (OP
[0], tmp
);
3044 trace_output_32 (sd
, tmp
);
3049 OP_17000002 (SIM_DESC sd
, SIM_CPU
*cpu
)
3053 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3054 tmp
= SEXT40 (ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3055 SET_GPR32 (OP
[0], tmp
);
3056 trace_output_32 (sd
, tmp
);
3061 OP_17001000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3065 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3066 SET_PSW_F1 (PSW_F0
);
3067 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40(ACC (OP
[2]));
3068 if (tmp
> SEXT40(MAX32
))
3073 else if (tmp
< SEXT40(MIN32
))
3082 SET_GPR32 (OP
[0], tmp
);
3083 trace_output_32 (sd
, tmp
);
3088 OP_17001002 (SIM_DESC sd
, SIM_CPU
*cpu
)
3092 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3093 SET_PSW_F1 (PSW_F0
);
3094 tmp
= SEXT40(ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3095 if (tmp
> SEXT40(MAX32
))
3100 else if (tmp
< SEXT40(MIN32
))
3109 SET_GPR32 (OP
[0], tmp
);
3110 trace_output_32 (sd
, tmp
);
3115 OP_1 (SIM_DESC sd
, SIM_CPU
*cpu
)
3121 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3122 /* see ../common/sim-alu.h for a more extensive discussion on how to
3123 compute the carry/overflow bits. */
3124 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3125 tmp
= ((unsigned)(unsigned16
) GPR (OP
[0])
3126 + (unsigned)(unsigned16
) ( - OP
[1]));
3127 SET_PSW_C (tmp
>= (1 << 16));
3128 SET_GPR (OP
[0], tmp
);
3129 trace_output_16 (sd
, tmp
);
3134 OP_5F00 (SIM_DESC sd
, SIM_CPU
*cpu
)
3136 host_callback
*cb
= STATE_CALLBACK (sd
);
3138 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
3139 trace_output_void (sd
);
3144 #if (DEBUG & DEBUG_TRAP) == 0
3146 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
3149 SET_PSW (PSW
& PSW_SM_BIT
);
3153 #else /* if debugging use trap to print registers */
3156 static int first_time
= 1;
3161 sim_io_printf (sd
, "Trap # PC ");
3162 for (i
= 0; i
< 16; i
++)
3163 sim_io_printf (sd
, " %sr%d", (i
> 9) ? "" : " ", i
);
3164 sim_io_printf (sd
, " a0 a1 f0 f1 c\n");
3167 sim_io_printf (sd
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
3169 for (i
= 0; i
< 16; i
++)
3170 sim_io_printf (sd
, " %.4x", (int) GPR (i
));
3172 for (i
= 0; i
< 2; i
++)
3173 sim_io_printf (sd
, " %.2x%.8lx",
3174 ((int)(ACC (i
) >> 32) & 0xff),
3175 ((unsigned long) ACC (i
)) & 0xffffffff);
3177 sim_io_printf (sd
, " %d %d %d\n",
3178 PSW_F0
!= 0, PSW_F1
!= 0, PSW_C
!= 0);
3179 sim_io_flush_stdout (sd
);
3183 case 15: /* new system call trap */
3184 /* Trap 15 is used for simulating low-level I/O */
3186 unsigned32 result
= 0;
3189 /* Registers passed to trap 0 */
3191 #define FUNC GPR (4) /* function number */
3192 #define PARM1 GPR (0) /* optional parm 1 */
3193 #define PARM2 GPR (1) /* optional parm 2 */
3194 #define PARM3 GPR (2) /* optional parm 3 */
3195 #define PARM4 GPR (3) /* optional parm 3 */
3197 /* Registers set by trap 0 */
3199 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3200 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3201 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3203 /* Turn a pointer in a register into a pointer into real memory. */
3205 #define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
3209 #if !defined(__GO32__) && !defined(_WIN32)
3210 case TARGET_SYS_fork
:
3211 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
3213 trace_output_16 (sd
, result
);
3217 case TARGET_SYS_getpid
:
3218 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3220 trace_output_16 (sd
, result
);
3223 case TARGET_SYS_kill
:
3224 trace_input ("<kill>", OP_R0
, OP_R1
, OP_VOID
);
3225 if (PARM1
== getpid ())
3227 trace_output_void (sd
);
3228 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, PARM2
);
3236 case 1: os_sig
= SIGHUP
; break;
3239 case 2: os_sig
= SIGINT
; break;
3242 case 3: os_sig
= SIGQUIT
; break;
3245 case 4: os_sig
= SIGILL
; break;
3248 case 5: os_sig
= SIGTRAP
; break;
3251 case 6: os_sig
= SIGABRT
; break;
3252 #elif defined(SIGIOT)
3253 case 6: os_sig
= SIGIOT
; break;
3256 case 7: os_sig
= SIGEMT
; break;
3259 case 8: os_sig
= SIGFPE
; break;
3262 case 9: os_sig
= SIGKILL
; break;
3265 case 10: os_sig
= SIGBUS
; break;
3268 case 11: os_sig
= SIGSEGV
; break;
3271 case 12: os_sig
= SIGSYS
; break;
3274 case 13: os_sig
= SIGPIPE
; break;
3277 case 14: os_sig
= SIGALRM
; break;
3280 case 15: os_sig
= SIGTERM
; break;
3283 case 16: os_sig
= SIGURG
; break;
3286 case 17: os_sig
= SIGSTOP
; break;
3289 case 18: os_sig
= SIGTSTP
; break;
3292 case 19: os_sig
= SIGCONT
; break;
3295 case 20: os_sig
= SIGCHLD
; break;
3296 #elif defined(SIGCLD)
3297 case 20: os_sig
= SIGCLD
; break;
3300 case 21: os_sig
= SIGTTIN
; break;
3303 case 22: os_sig
= SIGTTOU
; break;
3306 case 23: os_sig
= SIGIO
; break;
3307 #elif defined (SIGPOLL)
3308 case 23: os_sig
= SIGPOLL
; break;
3311 case 24: os_sig
= SIGXCPU
; break;
3314 case 25: os_sig
= SIGXFSZ
; break;
3317 case 26: os_sig
= SIGVTALRM
; break;
3320 case 27: os_sig
= SIGPROF
; break;
3323 case 28: os_sig
= SIGWINCH
; break;
3326 case 29: os_sig
= SIGLOST
; break;
3329 case 30: os_sig
= SIGUSR1
; break;
3332 case 31: os_sig
= SIGUSR2
; break;
3338 trace_output_void (sd
);
3339 sim_io_printf (sd
, "Unknown signal %d\n", PARM2
);
3340 sim_io_flush_stdout (sd
);
3341 EXCEPTION (SIM_SIGILL
);
3345 RETVAL (kill (PARM1
, PARM2
));
3346 trace_output_16 (sd
, result
);
3351 case TARGET_SYS_execve
:
3352 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
3353 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
3354 (char **)MEMPTR (PARM3
)));
3355 trace_output_16 (sd
, result
);
3358 #ifdef TARGET_SYS_execv
3359 case TARGET_SYS_execv
:
3360 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
3361 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
3362 trace_output_16 (sd
, result
);
3366 case TARGET_SYS_pipe
:
3371 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
3373 RETVAL (pipe (host_fd
));
3374 SW (buf
, host_fd
[0]);
3375 buf
+= sizeof(uint16
);
3376 SW (buf
, host_fd
[1]);
3377 trace_output_16 (sd
, result
);
3382 #ifdef TARGET_SYS_wait
3383 case TARGET_SYS_wait
:
3386 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
3387 RETVAL (wait (&status
));
3390 trace_output_16 (sd
, result
);
3396 case TARGET_SYS_getpid
:
3397 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3399 trace_output_16 (sd
, result
);
3402 case TARGET_SYS_kill
:
3403 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
3404 trace_output_void (sd
);
3405 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, PARM2
);
3409 case TARGET_SYS_read
:
3410 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
3411 RETVAL (cb
->read (cb
, PARM1
, MEMPTR (PARM2
), PARM3
));
3412 trace_output_16 (sd
, result
);
3415 case TARGET_SYS_write
:
3416 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
3418 RETVAL ((int)cb
->write_stdout (cb
, MEMPTR (PARM2
), PARM3
));
3420 RETVAL ((int)cb
->write (cb
, PARM1
, MEMPTR (PARM2
), PARM3
));
3421 trace_output_16 (sd
, result
);
3424 case TARGET_SYS_lseek
:
3425 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
3426 RETVAL32 (cb
->lseek (cb
, PARM1
,
3427 ((((unsigned long) PARM2
) << 16)
3428 || (unsigned long) PARM3
),
3430 trace_output_32 (sd
, result
);
3433 case TARGET_SYS_close
:
3434 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
3435 RETVAL (cb
->close (cb
, PARM1
));
3436 trace_output_16 (sd
, result
);
3439 case TARGET_SYS_open
:
3440 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
3441 RETVAL (cb
->open (cb
, MEMPTR (PARM1
), PARM2
));
3442 trace_output_16 (sd
, result
);
3445 case TARGET_SYS_exit
:
3446 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
3447 trace_output_void (sd
);
3448 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_exited
, GPR (0));
3451 #ifdef TARGET_SYS_stat
3452 case TARGET_SYS_stat
:
3453 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
3454 /* stat system call */
3456 struct stat host_stat
;
3459 RETVAL (stat (MEMPTR (PARM1
), &host_stat
));
3463 /* The hard-coded offsets and sizes were determined by using
3464 * the D10V compiler on a test program that used struct stat.
3466 SW (buf
, host_stat
.st_dev
);
3467 SW (buf
+2, host_stat
.st_ino
);
3468 SW (buf
+4, host_stat
.st_mode
);
3469 SW (buf
+6, host_stat
.st_nlink
);
3470 SW (buf
+8, host_stat
.st_uid
);
3471 SW (buf
+10, host_stat
.st_gid
);
3472 SW (buf
+12, host_stat
.st_rdev
);
3473 SLW (buf
+16, host_stat
.st_size
);
3474 SLW (buf
+20, host_stat
.st_atime
);
3475 SLW (buf
+28, host_stat
.st_mtime
);
3476 SLW (buf
+36, host_stat
.st_ctime
);
3478 trace_output_16 (sd
, result
);
3482 case TARGET_SYS_chown
:
3483 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3484 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
3485 trace_output_16 (sd
, result
);
3488 case TARGET_SYS_chmod
:
3489 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3490 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
3491 trace_output_16 (sd
, result
);
3495 #ifdef TARGET_SYS_utime
3496 case TARGET_SYS_utime
:
3497 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3498 /* Cast the second argument to void *, to avoid type mismatch
3499 if a prototype is present. */
3500 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
3501 trace_output_16 (sd
, result
);
3507 #ifdef TARGET_SYS_time
3508 case TARGET_SYS_time
:
3509 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3510 RETVAL32 (time (PARM1
? MEMPTR (PARM1
) : NULL
));
3511 trace_output_32 (sd
, result
);
3517 cb
->error (cb
, "Unknown syscall %d", FUNC
);
3519 if ((uint16
) result
== (uint16
) -1)
3520 RETERR (cb
->get_errno (cb
));
3530 OP_7000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3532 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3533 SET_PSW_F1 (PSW_F0
);;
3534 SET_PSW_F0 ((GPR (OP
[0]) & OP
[1]) ? 1 : 0);
3535 trace_output_flag (sd
);
3540 OP_F000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3542 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3543 SET_PSW_F1 (PSW_F0
);
3544 SET_PSW_F0 ((~(GPR (OP
[0])) & OP
[1]) ? 1 : 0);
3545 trace_output_flag (sd
);
3550 OP_5F80 (SIM_DESC sd
, SIM_CPU
*cpu
)
3552 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3554 trace_output_void (sd
);
3559 OP_A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
3562 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3563 tmp
= (GPR (OP
[0]) ^ GPR (OP
[1]));
3564 SET_GPR (OP
[0], tmp
);
3565 trace_output_16 (sd
, tmp
);
3570 OP_5000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3573 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3574 tmp
= (GPR (OP
[1]) ^ OP
[2]);
3575 SET_GPR (OP
[0], tmp
);
3576 trace_output_16 (sd
, tmp
);
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