13 #include "sys/syscall.h"
15 extern char *strrchr ();
47 static void trace_input_func
PARAMS ((char *name
,
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
54 static void trace_output_func
PARAMS ((enum op_types result
));
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
63 #define SIZE_OPERANDS 18
67 #define SIZE_VALUES 13
71 #define SIZE_LOCATION 20
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
83 trace_input_func (name
, in1
, in2
, in3
)
97 const char *functionname
;
98 unsigned int linenumber
;
101 if ((d10v_debug
& DEBUG_TRACE
) == 0)
104 switch (State
.ins_type
)
107 case INS_UNKNOWN
: type
= " ?"; break;
108 case INS_LEFT
: type
= " L"; break;
109 case INS_RIGHT
: type
= " R"; break;
110 case INS_LEFT_PARALLEL
: type
= "*L"; break;
111 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
112 case INS_LEFT_COND_TEST
: type
= "?L"; break;
113 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
114 case INS_LEFT_COND_EXE
: type
= "&L"; break;
115 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
116 case INS_LONG
: type
= " B"; break;
119 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
120 (*d10v_callback
->printf_filtered
) (d10v_callback
,
122 SIZE_PC
, (unsigned)PC
,
124 SIZE_INSTRUCTION
, name
);
129 byte_pc
= decode_pc ();
130 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
132 filename
= (const char *)0;
133 functionname
= (const char *)0;
135 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
136 &filename
, &functionname
, &linenumber
))
141 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
146 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
147 p
+= SIZE_LINE_NUMBER
+2;
152 sprintf (p
, "%s ", functionname
);
157 char *q
= strrchr (filename
, '/');
158 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
167 (*d10v_callback
->printf_filtered
) (d10v_callback
,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC
, (unsigned)PC
,
171 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
172 SIZE_INSTRUCTION
, name
);
180 for (i
= 0; i
< 3; i
++)
195 sprintf (p
, "%sr%d", comma
, OP
[i
]);
203 sprintf (p
, "%scr%d", comma
, OP
[i
]);
209 case OP_ACCUM_OUTPUT
:
210 case OP_ACCUM_REVERSE
:
211 sprintf (p
, "%sa%d", comma
, OP
[i
]);
217 sprintf (p
, "%s%d", comma
, OP
[i
]);
223 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
229 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
235 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
241 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
247 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
253 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
259 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
265 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
273 sprintf (p
, "%sf0", comma
);
276 sprintf (p
, "%sf1", comma
);
279 sprintf (p
, "%sc", comma
);
287 if ((d10v_debug
& DEBUG_VALUES
) == 0)
291 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
296 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
299 for (i
= 0; i
< 3; i
++)
305 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
311 case OP_ACCUM_OUTPUT
:
313 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
321 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
322 (uint16
)State
.regs
[OP
[i
]]);
326 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
327 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
332 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
333 (uint16
)State
.cregs
[OP
[i
]]);
337 case OP_ACCUM_REVERSE
:
338 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
339 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
340 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
344 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
349 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
350 (uint16
)SEXT4(OP
[i
]));
354 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
355 (uint16
)SEXT8(OP
[i
]));
359 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
360 (uint16
)SEXT3(OP
[i
]));
365 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
373 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
379 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
381 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
382 (uint16
)State
.regs
[OP
[++i
]]);
386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
387 (uint16
)State
.regs
[2]);
391 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
392 (uint16
)State
.regs
[3]);
396 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
397 (uint16
)State
.regs
[4]);
401 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
402 (uint16
)State
.regs
[2]);
403 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
404 (uint16
)State
.regs
[3]);
411 (*d10v_callback
->flush_stdout
) (d10v_callback
);
415 trace_output_func (result
)
416 enum op_types result
;
418 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
431 (uint16
)State
.regs
[OP
[0]],
432 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
437 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
439 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
445 (uint16
)State
.cregs
[OP
[0]],
446 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
451 (uint16
)State
.cregs
[OP
[1]],
452 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
456 case OP_ACCUM_OUTPUT
:
457 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
458 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
459 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
460 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
463 case OP_ACCUM_REVERSE
:
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
465 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
466 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
467 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
472 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
473 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
478 (uint16
)State
.regs
[2],
479 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
483 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
484 (uint16
)State
.regs
[2], (uint16
)State
.regs
[3],
485 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
490 (*d10v_callback
->flush_stdout
) (d10v_callback
);
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
502 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
504 if ((int16
)(State
.regs
[OP
[0]]) < 0)
506 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
511 trace_output (OP_REG
);
520 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
522 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
524 if (State
.a
[OP
[0]] < 0 )
526 tmp
= -State
.a
[OP
[0]];
530 State
.a
[OP
[0]] = MAX32
;
531 else if (tmp
< MIN32
)
532 State
.a
[OP
[0]] = MIN32
;
534 State
.a
[OP
[0]] = tmp
& MASK40
;
537 State
.a
[OP
[0]] = tmp
& MASK40
;
542 trace_output (OP_ACCUM
);
549 uint16 tmp
= State
.regs
[OP
[0]];
550 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
551 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
552 if ( tmp
> State
.regs
[OP
[0]])
556 trace_output (OP_REG
);
564 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
566 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
570 State
.a
[OP
[0]] = MAX32
;
571 else if ( tmp
< MIN32
)
572 State
.a
[OP
[0]] = MIN32
;
574 State
.a
[OP
[0]] = tmp
& MASK40
;
577 State
.a
[OP
[0]] = tmp
& MASK40
;
578 trace_output (OP_ACCUM
);
586 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
588 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
592 State
.a
[OP
[0]] = MAX32
;
593 else if ( tmp
< MIN32
)
594 State
.a
[OP
[0]] = MIN32
;
596 State
.a
[OP
[0]] = tmp
& MASK40
;
599 State
.a
[OP
[0]] = tmp
& MASK40
;
600 trace_output (OP_ACCUM
);
608 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
609 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
611 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
613 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
617 State
.regs
[OP
[0]] = tmp
>> 16;
618 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
619 trace_output (OP_DREG
);
626 uint16 tmp
= State
.regs
[OP
[0]];
627 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
629 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
630 if ( tmp
> State
.regs
[OP
[0]])
634 trace_output (OP_REG
);
642 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
644 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
645 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
646 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
647 trace_output (OP_DREG
);
655 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
657 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
658 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
659 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
660 trace_output (OP_DREG
);
670 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
671 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
674 State
.regs
[OP
[0]] = 0x7fff;
675 State
.regs
[OP
[0]+1] = 0xffff;
678 else if (tmp
< MIN32
)
680 State
.regs
[OP
[0]] = 0x8000;
681 State
.regs
[OP
[0]+1] = 0;
686 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
687 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
690 trace_output (OP_DREG
);
700 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
701 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
704 State
.regs
[OP
[0]] = 0x7fff;
705 State
.regs
[OP
[0]+1] = 0xffff;
708 else if (tmp
< MIN32
)
710 State
.regs
[OP
[0]] = 0x8000;
711 State
.regs
[OP
[0]+1] = 0;
716 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
717 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
720 trace_output (OP_DREG
);
727 uint tmp
= State
.regs
[OP
[0]];
730 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
731 State
.regs
[OP
[0]] += OP
[1];
732 if (tmp
> State
.regs
[OP
[0]])
736 trace_output (OP_REG
);
743 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
744 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
745 trace_output (OP_REG
);
752 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
753 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
754 trace_output (OP_REG
);
761 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
762 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
763 trace_output (OP_REG
);
770 trace_input ("bl.s", OP_CONSTANT8
, OP_R2
, OP_R3
);
771 State
.regs
[13] = PC
+1;
772 JMP( PC
+ SEXT8 (OP
[0]));
773 trace_output (OP_VOID
);
780 trace_input ("bl.l", OP_CONSTANT16
, OP_R2
, OP_R3
);
781 State
.regs
[13] = PC
+1;
783 trace_output (OP_VOID
);
790 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
791 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
792 trace_output (OP_REG
);
799 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
800 JMP (PC
+ SEXT8 (OP
[0]));
801 trace_output (OP_VOID
);
808 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
810 trace_output (OP_VOID
);
817 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
819 JMP (PC
+ SEXT8 (OP
[0]));
820 trace_output (OP_FLAG
);
827 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
830 trace_output (OP_FLAG
);
837 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
839 JMP (PC
+ SEXT8 (OP
[0]));
840 trace_output (OP_FLAG
);
847 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
850 trace_output (OP_FLAG
);
857 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
858 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
859 trace_output (OP_REG
);
866 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
868 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
869 trace_output (OP_FLAG
);
876 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
878 trace_output (OP_ACCUM
);
885 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
887 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
888 trace_output (OP_FLAG
);
895 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
897 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
898 trace_output (OP_FLAG
);
905 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
907 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
908 trace_output (OP_FLAG
);
915 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
917 State
.F0
= ((State
.a
[OP
[0]] & MASK40
) == (State
.a
[OP
[1]] & MASK40
)) ? 1 : 0;
918 trace_output (OP_FLAG
);
925 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
927 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
928 trace_output (OP_FLAG
);
935 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
937 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
938 trace_output (OP_FLAG
);
945 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
947 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
948 trace_output (OP_FLAG
);
955 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
957 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
958 trace_output (OP_FLAG
);
965 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
967 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
968 trace_output (OP_FLAG
);
975 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
977 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
978 trace_output (OP_FLAG
);
987 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1001 trace_output (OP_FLAG
);
1008 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1009 State
.exception
= SIGTRAP
;
1016 uint16 foo
, tmp
, tmpf
;
1018 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1019 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1020 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1021 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1022 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1023 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1024 trace_output (OP_DREG
);
1031 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1032 State
.exe
= (State
.F0
== 0);
1033 trace_output (OP_FLAG
);
1040 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1041 State
.exe
= (State
.F0
!= 0);
1042 trace_output (OP_FLAG
);
1049 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1050 State
.exe
= (State
.F1
== 0);
1051 trace_output (OP_FLAG
);
1058 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1059 State
.exe
= (State
.F1
!= 0);
1060 trace_output (OP_FLAG
);
1067 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1068 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1069 trace_output (OP_FLAG
);
1076 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1077 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1078 trace_output (OP_FLAG
);
1085 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1086 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1087 trace_output (OP_FLAG
);
1094 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1095 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1096 trace_output (OP_FLAG
);
1106 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1107 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1108 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1110 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1117 State
.regs
[OP
[0]] = i
-1;
1118 trace_output (OP_REG
);
1123 State
.regs
[OP
[0]] = 16;
1124 trace_output (OP_REG
);
1134 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1135 tmp
= SEXT40(State
.a
[OP
[1]]);
1137 tmp
= ~tmp
& MASK40
;
1139 foo
= 0x4000000000LL
;
1144 State
.regs
[OP
[0]] = i
-9;
1145 trace_output (OP_REG
);
1150 State
.regs
[OP
[0]] = 16;
1151 trace_output (OP_REG
);
1158 trace_input ("jl", OP_REG
, OP_R2
, OP_R3
);
1159 State
.regs
[13] = PC
+1;
1160 JMP (State
.regs
[OP
[0]]);
1161 trace_output (OP_VOID
);
1168 trace_input ("jmp", OP_REG
,
1169 (OP
[0] == 13) ? OP_R2
: OP_VOID
,
1170 (OP
[0] == 13) ? OP_R3
: OP_VOID
);
1172 JMP (State
.regs
[OP
[0]]);
1173 trace_output (OP_VOID
);
1180 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1181 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1182 trace_output (OP_REG
);
1189 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1192 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
1193 State
.exception
= SIGILL
;
1196 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1197 INC_ADDR(State
.regs
[OP
[1]],-2);
1198 trace_output (OP_REG
);
1205 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1206 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1207 INC_ADDR(State
.regs
[OP
[1]],2);
1208 trace_output (OP_REG
);
1215 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1216 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1217 trace_output (OP_REG
);
1224 uint16 addr
= State
.regs
[OP
[2]];
1225 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1226 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1227 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1228 trace_output (OP_DREG
);
1235 uint16 addr
= State
.regs
[OP
[1]];
1236 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1239 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
1240 State
.exception
= SIGILL
;
1243 State
.regs
[OP
[0]] = RW (addr
);
1244 State
.regs
[OP
[0]+1] = RW (addr
+2);
1245 INC_ADDR(State
.regs
[OP
[1]],-4);
1246 trace_output (OP_DREG
);
1253 uint16 addr
= State
.regs
[OP
[1]];
1254 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1255 State
.regs
[OP
[0]] = RW (addr
);
1256 State
.regs
[OP
[0]+1] = RW (addr
+2);
1257 INC_ADDR(State
.regs
[OP
[1]],4);
1258 trace_output (OP_DREG
);
1265 uint16 addr
= State
.regs
[OP
[1]];
1266 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1267 State
.regs
[OP
[0]] = RW (addr
);
1268 State
.regs
[OP
[0]+1] = RW (addr
+2);
1269 trace_output (OP_DREG
);
1276 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1277 State
.regs
[OP
[0]] = SEXT8 (RB (OP
[1] + State
.regs
[OP
[2]]));
1278 trace_output (OP_REG
);
1285 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1286 State
.regs
[OP
[0]] = SEXT8 (RB (State
.regs
[OP
[1]]));
1287 trace_output (OP_REG
);
1294 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1295 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1296 trace_output (OP_REG
);
1303 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1304 State
.regs
[OP
[0]] = OP
[1];
1305 trace_output (OP_REG
);
1312 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1313 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1314 trace_output (OP_REG
);
1321 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1322 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1323 trace_output (OP_REG
);
1332 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1333 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1336 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1338 if (State
.ST
&& tmp
> MAX32
)
1341 tmp
+= SEXT40(State
.a
[OP
[0]]);
1345 State
.a
[OP
[0]] = MAX32
;
1346 else if (tmp
< MIN32
)
1347 State
.a
[OP
[0]] = MIN32
;
1349 State
.a
[OP
[0]] = tmp
& MASK40
;
1352 State
.a
[OP
[0]] = tmp
& MASK40
;
1353 trace_output (OP_ACCUM
);
1362 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1363 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1365 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1367 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1368 trace_output (OP_ACCUM
);
1377 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1378 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1380 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1381 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1382 trace_output (OP_ACCUM
);
1389 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1390 State
.F1
= State
.F0
;
1391 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1393 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1398 trace_output (OP_REG
);
1407 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1408 State
.F1
= State
.F0
;
1409 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1410 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1412 State
.a
[OP
[0]] = tmp
& MASK40
;
1417 trace_output (OP_ACCUM
);
1424 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1425 State
.F1
= State
.F0
;
1426 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1428 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1433 trace_output (OP_ACCUM
);
1441 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1442 State
.F1
= State
.F0
;
1443 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1445 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1450 trace_output (OP_REG
);
1459 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1460 State
.F1
= State
.F0
;
1461 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1462 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1464 State
.a
[OP
[0]] = tmp
& MASK40
;
1469 trace_output (OP_ACCUM
);
1476 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1477 State
.F1
= State
.F0
;
1478 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1480 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1485 trace_output (OP_ACCUM
);
1494 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1495 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1498 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1500 if (State
.ST
&& tmp
> MAX32
)
1503 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1507 State
.a
[OP
[0]] = MAX32
;
1508 else if (tmp
< MIN32
)
1509 State
.a
[OP
[0]] = MIN32
;
1511 State
.a
[OP
[0]] = tmp
& MASK40
;
1514 State
.a
[OP
[0]] = tmp
& MASK40
;
1515 trace_output (OP_ACCUM
);
1524 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1525 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1527 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1529 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1530 trace_output (OP_ACCUM
);
1539 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1540 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1542 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1544 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1545 trace_output (OP_ACCUM
);
1552 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1553 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1554 trace_output (OP_REG
);
1563 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1564 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1567 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1569 if (State
.ST
&& tmp
> MAX32
)
1570 State
.a
[OP
[0]] = MAX32
;
1572 State
.a
[OP
[0]] = tmp
& MASK40
;
1573 trace_output (OP_ACCUM
);
1582 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1583 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1588 State
.a
[OP
[0]] = tmp
& MASK40
;
1589 trace_output (OP_ACCUM
);
1598 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1599 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1604 State
.a
[OP
[0]] = tmp
& MASK40
;
1605 trace_output (OP_ACCUM
);
1612 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1613 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1614 trace_output (OP_REG
);
1621 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1622 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1623 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1624 trace_output (OP_DREG
);
1631 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1632 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1633 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1634 trace_output (OP_DREG
);
1641 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1642 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1643 trace_output (OP_ACCUM_REVERSE
);
1650 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1651 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1652 trace_output (OP_ACCUM
);
1659 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1660 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1661 trace_output (OP_REG
);
1668 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1670 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1671 trace_output (OP_REG
);
1678 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1680 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1681 trace_output (OP_REG
);
1688 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1689 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1690 trace_output (OP_ACCUM
);
1697 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1698 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1699 trace_output (OP_REG
);
1706 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1707 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1708 trace_output (OP_REG
);
1715 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1718 /* PSW is treated specially */
1720 if (State
.SM
) PSW
|= 0x8000;
1721 if (State
.EA
) PSW
|= 0x2000;
1722 if (State
.DB
) PSW
|= 0x1000;
1723 if (State
.IE
) PSW
|= 0x400;
1724 if (State
.RP
) PSW
|= 0x200;
1725 if (State
.MD
) PSW
|= 0x100;
1726 if (State
.FX
) PSW
|= 0x80;
1727 if (State
.ST
) PSW
|= 0x40;
1728 if (State
.F0
) PSW
|= 8;
1729 if (State
.F1
) PSW
|= 4;
1730 if (State
.C
) PSW
|= 1;
1732 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1733 trace_output (OP_REG
);
1740 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1741 State
.a
[OP
[1]] &= MASK32
;
1742 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1743 trace_output (OP_ACCUM_REVERSE
);
1752 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1753 tmp
= State
.a
[OP
[1]] & 0xffff;
1754 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1755 trace_output (OP_ACCUM_REVERSE
);
1762 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1763 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1764 trace_output (OP_ACCUM_REVERSE
);
1771 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1772 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1775 /* PSW is treated specially */
1776 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1777 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1778 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1779 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1780 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1781 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1782 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1783 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1784 State
.F0
= (PSW
& 8) ? 1 : 0;
1785 State
.F1
= (PSW
& 4) ? 1 : 0;
1787 if (State
.ST
&& !State
.FX
)
1789 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1790 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1792 State
.exception
= SIGILL
;
1795 trace_output (OP_CR_REVERSE
);
1802 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1803 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1804 trace_output (OP_REG
);
1811 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1812 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1813 trace_output (OP_REG
);
1822 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1823 tmp
= -SEXT40(State
.a
[OP
[0]]);
1827 State
.a
[OP
[0]] = MAX32
;
1828 else if (tmp
< MIN32
)
1829 State
.a
[OP
[0]] = MIN32
;
1831 State
.a
[OP
[0]] = tmp
& MASK40
;
1834 State
.a
[OP
[0]] = tmp
& MASK40
;
1835 trace_output (OP_ACCUM
);
1843 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1845 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
1846 switch (State
.ins_type
)
1849 ins_type_counters
[ (int)INS_UNKNOWN
]++;
1852 case INS_LEFT_PARALLEL
:
1853 /* Don't count a parallel op that includes a NOP as a true parallel op */
1854 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
1855 ins_type_counters
[ (int)INS_RIGHT
]++;
1856 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1860 case INS_LEFT_COND_EXE
:
1861 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1864 case INS_RIGHT_PARALLEL
:
1865 /* Don't count a parallel op that includes a NOP as a true parallel op */
1866 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
1867 ins_type_counters
[ (int)INS_LEFT
]++;
1868 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1872 case INS_RIGHT_COND_EXE
:
1873 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1877 trace_output (OP_VOID
);
1884 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1885 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1886 trace_output (OP_REG
);
1893 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1894 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1895 trace_output (OP_REG
);
1902 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1903 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1904 trace_output (OP_REG
);
1912 int shift
= SEXT3 (OP
[2]);
1914 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1917 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1918 "ERROR at PC 0x%x: instruction only valid for A0\n",
1920 State
.exception
= SIGILL
;
1923 State
.F1
= State
.F0
;
1925 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1927 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1928 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1931 State
.regs
[OP
[0]] = 0x7fff;
1932 State
.regs
[OP
[0]+1] = 0xffff;
1935 else if (tmp
< MIN32
)
1937 State
.regs
[OP
[0]] = 0x8000;
1938 State
.regs
[OP
[0]+1] = 0;
1943 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1944 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1947 trace_output (OP_DREG
);
1955 int shift
= SEXT3 (OP
[2]);
1957 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1958 State
.F1
= State
.F0
;
1960 tmp
= SEXT44 (State
.a
[1]) << shift
;
1962 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1967 State
.regs
[OP
[0]] = 0x7fff;
1970 else if (tmp
< 0xfff80000000LL
)
1972 State
.regs
[OP
[0]] = 0x8000;
1977 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1980 trace_output (OP_REG
);
1987 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1990 RPT_C
= State
.regs
[OP
[0]];
1994 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1995 State
.exception
= SIGILL
;
1999 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2000 State
.exception
= SIGILL
;
2002 trace_output (OP_VOID
);
2009 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2016 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2017 State
.exception
= SIGILL
;
2021 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2022 State
.exception
= SIGILL
;
2024 trace_output (OP_VOID
);
2031 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
2032 State
.exception
= SIGILL
;
2039 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2042 trace_output (OP_VOID
);
2051 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2052 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2056 State
.a
[OP
[0]] = MAX32
;
2057 else if (tmp
< MIN32
)
2058 State
.a
[OP
[0]] = MIN32
;
2060 State
.a
[OP
[0]] = tmp
& MASK40
;
2063 State
.a
[OP
[0]] = tmp
& MASK40
;
2064 trace_output (OP_ACCUM
);
2071 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2072 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2073 trace_output (OP_REG
);
2080 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2081 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2082 trace_output (OP_REG
);
2089 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2091 trace_output (OP_VOID
);
2098 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2099 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2100 trace_output (OP_REG
);
2108 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2109 if ((State
.regs
[OP
[1]] & 31) <= 16)
2110 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2113 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2114 State
.exception
= SIGILL
;
2121 State
.a
[OP
[0]] = MAX32
;
2122 else if (tmp
< 0xffffff80000000LL
)
2123 State
.a
[OP
[0]] = MIN32
;
2125 State
.a
[OP
[0]] = tmp
& MASK40
;
2128 State
.a
[OP
[0]] = tmp
& MASK40
;
2129 trace_output (OP_ACCUM
);
2136 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2137 State
.regs
[OP
[0]] <<= OP
[1];
2138 trace_output (OP_REG
);
2150 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2151 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2156 State
.a
[OP
[0]] = MAX32
;
2157 else if (tmp
< 0xffffff80000000LL
)
2158 State
.a
[OP
[0]] = MIN32
;
2160 State
.a
[OP
[0]] = tmp
& MASK40
;
2163 State
.a
[OP
[0]] = tmp
& MASK40
;
2164 trace_output (OP_ACCUM
);
2171 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2172 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2173 trace_output (OP_REG
);
2180 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2181 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2182 trace_output (OP_REG
);
2189 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2190 if ((State
.regs
[OP
[1]] & 31) <= 16)
2191 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> (State
.regs
[OP
[1]] & 31)) & MASK40
;
2194 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2195 State
.exception
= SIGILL
;
2199 trace_output (OP_ACCUM
);
2206 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2207 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2208 trace_output (OP_REG
);
2218 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2219 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> OP
[1]) & MASK40
;
2220 trace_output (OP_ACCUM
);
2227 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2228 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2229 trace_output (OP_REG
);
2236 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2237 if ((State
.regs
[OP
[1]] & 31) <= 16)
2238 State
.a
[OP
[0]] = (uint64
)((State
.a
[OP
[0]] & MASK40
) >> (State
.regs
[OP
[1]] & 31));
2241 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2242 State
.exception
= SIGILL
;
2246 trace_output (OP_ACCUM
);
2253 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2254 State
.regs
[OP
[0]] >>= OP
[1];
2255 trace_output (OP_REG
);
2265 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2266 State
.a
[OP
[0]] = (uint64
)(State
.a
[OP
[0]] & MASK40
) >> OP
[1];
2267 trace_output (OP_ACCUM
);
2276 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2277 tmp
= State
.F0
<< 15;
2278 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2279 trace_output (OP_REG
);
2286 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2287 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2288 trace_output (OP_VOID
);
2295 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2296 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2297 trace_output (OP_VOID
);
2304 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2307 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2308 State
.exception
= SIGILL
;
2311 State
.regs
[OP
[1]] -= 2;
2312 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2313 trace_output (OP_VOID
);
2320 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2321 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2322 INC_ADDR (State
.regs
[OP
[1]],2);
2323 trace_output (OP_VOID
);
2330 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2333 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2334 State
.exception
= SIGILL
;
2337 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2338 INC_ADDR (State
.regs
[OP
[1]],-2);
2339 trace_output (OP_VOID
);
2346 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2347 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2348 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2349 trace_output (OP_VOID
);
2356 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2357 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2358 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2359 trace_output (OP_VOID
);
2366 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2370 State
.exception
= SIGILL
;
2373 State
.regs
[OP
[1]] -= 4;
2374 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2375 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2376 trace_output (OP_VOID
);
2383 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2387 State
.exception
= SIGILL
;
2390 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2391 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2392 INC_ADDR (State
.regs
[OP
[1]],4);
2393 trace_output (OP_VOID
);
2400 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2401 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2402 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2403 INC_ADDR (State
.regs
[OP
[1]],-4);
2404 trace_output (OP_VOID
);
2411 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2412 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2413 trace_output (OP_VOID
);
2420 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2421 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2422 trace_output (OP_VOID
);
2429 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2430 State
.exception
= SIG_D10V_STOP
;
2431 trace_output (OP_VOID
);
2440 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2441 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2442 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2443 State
.regs
[OP
[0]] = tmp
& 0xffff;
2444 trace_output (OP_REG
);
2453 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2454 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2458 State
.a
[OP
[0]] = MAX32
;
2459 else if ( tmp
< MIN32
)
2460 State
.a
[OP
[0]] = MIN32
;
2462 State
.a
[OP
[0]] = tmp
& MASK40
;
2465 State
.a
[OP
[0]] = tmp
& MASK40
;
2467 trace_output (OP_ACCUM
);
2477 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2478 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2482 State
.a
[OP
[0]] = MAX32
;
2483 else if ( tmp
< MIN32
)
2484 State
.a
[OP
[0]] = MIN32
;
2486 State
.a
[OP
[0]] = tmp
& MASK40
;
2489 State
.a
[OP
[0]] = tmp
& MASK40
;
2491 trace_output (OP_ACCUM
);
2501 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2502 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2503 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2505 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2506 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2507 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2508 trace_output (OP_DREG
);
2517 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2518 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2519 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2520 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2521 trace_output (OP_DREG
);
2530 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2531 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2532 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2533 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2534 trace_output (OP_DREG
);
2543 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2544 State
.F1
= State
.F0
;
2545 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2548 State
.regs
[OP
[0]] = 0x7fff;
2549 State
.regs
[OP
[0]+1] = 0xffff;
2552 else if (tmp
< MIN32
)
2554 State
.regs
[OP
[0]] = 0x8000;
2555 State
.regs
[OP
[0]+1] = 0;
2560 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2561 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2564 trace_output (OP_DREG
);
2573 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2574 State
.F1
= State
.F0
;
2575 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2578 State
.regs
[OP
[0]] = 0x7fff;
2579 State
.regs
[OP
[0]+1] = 0xffff;
2582 else if (tmp
< MIN32
)
2584 State
.regs
[OP
[0]] = 0x8000;
2585 State
.regs
[OP
[0]+1] = 0;
2590 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2591 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2594 trace_output (OP_DREG
);
2605 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2606 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2607 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2608 State
.regs
[OP
[0]] = tmp
& 0xffff;
2609 trace_output (OP_REG
);
2616 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2617 trace_output (OP_VOID
);
2623 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2624 State
.exception
= SIGILL
;
2626 /* Use any other traps for batch debugging. */
2629 static int first_time
= 1;
2634 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2635 for (i
= 0; i
< 16; i
++)
2636 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2637 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2640 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2642 for (i
= 0; i
< 16; i
++)
2643 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2645 for (i
= 0; i
< 2; i
++)
2646 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2647 ((int)(State
.a
[i
] >> 32) & 0xff),
2648 ((unsigned long)State
.a
[i
]) & 0xffffffff);
2650 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2651 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2652 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2657 /* Trap 0 is used for simulating low-level I/O */
2661 /* Registers passed to trap 0 */
2663 #define FUNC State.regs[6] /* function number */
2664 #define PARM1 State.regs[2] /* optional parm 1 */
2665 #define PARM2 State.regs[3] /* optional parm 2 */
2666 #define PARM3 State.regs[4] /* optional parm 3 */
2667 #define PARM4 State.regs[5] /* optional parm 3 */
2669 /* Registers set by trap 0 */
2671 #define RETVAL State.regs[2] /* return value */
2672 #define RETVAL_HIGH State.regs[2] /* return value */
2673 #define RETVAL_LOW State.regs[3] /* return value */
2674 #define RETERR State.regs[4] /* return error code */
2676 /* Turn a pointer in a register into a pointer into real memory. */
2678 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2682 #if !defined(__GO32__) && !defined(_WIN32)
2685 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2686 trace_output (OP_R2
);
2690 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2692 trace_output (OP_R2
);
2696 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2697 if (PARM1
== getpid ())
2699 trace_output (OP_VOID
);
2700 State
.exception
= PARM2
;
2708 case 1: os_sig
= SIGHUP
; break;
2711 case 2: os_sig
= SIGINT
; break;
2714 case 3: os_sig
= SIGQUIT
; break;
2717 case 4: os_sig
= SIGILL
; break;
2720 case 5: os_sig
= SIGTRAP
; break;
2723 case 6: os_sig
= SIGABRT
; break;
2724 #elif defined(SIGIOT)
2725 case 6: os_sig
= SIGIOT
; break;
2728 case 7: os_sig
= SIGEMT
; break;
2731 case 8: os_sig
= SIGFPE
; break;
2734 case 9: os_sig
= SIGKILL
; break;
2737 case 10: os_sig
= SIGBUS
; break;
2740 case 11: os_sig
= SIGSEGV
; break;
2743 case 12: os_sig
= SIGSYS
; break;
2746 case 13: os_sig
= SIGPIPE
; break;
2749 case 14: os_sig
= SIGALRM
; break;
2752 case 15: os_sig
= SIGTERM
; break;
2755 case 16: os_sig
= SIGURG
; break;
2758 case 17: os_sig
= SIGSTOP
; break;
2761 case 18: os_sig
= SIGTSTP
; break;
2764 case 19: os_sig
= SIGCONT
; break;
2767 case 20: os_sig
= SIGCHLD
; break;
2768 #elif defined(SIGCLD)
2769 case 20: os_sig
= SIGCLD
; break;
2772 case 21: os_sig
= SIGTTIN
; break;
2775 case 22: os_sig
= SIGTTOU
; break;
2778 case 23: os_sig
= SIGIO
; break;
2779 #elif defined (SIGPOLL)
2780 case 23: os_sig
= SIGPOLL
; break;
2783 case 24: os_sig
= SIGXCPU
; break;
2786 case 25: os_sig
= SIGXFSZ
; break;
2789 case 26: os_sig
= SIGVTALRM
; break;
2792 case 27: os_sig
= SIGPROF
; break;
2795 case 28: os_sig
= SIGWINCH
; break;
2798 case 29: os_sig
= SIGLOST
; break;
2801 case 30: os_sig
= SIGUSR1
; break;
2804 case 31: os_sig
= SIGUSR2
; break;
2810 trace_output (OP_VOID
);
2811 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2812 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2813 State
.exception
= SIGILL
;
2817 RETVAL
= kill (PARM1
, PARM2
);
2818 trace_output (OP_R2
);
2824 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2825 (char **)MEMPTR (PARM3
));
2826 trace_input ("<execve>", OP_R2
, OP_R3
, OP_R4
);
2827 trace_output (OP_R2
);
2831 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2832 trace_input ("<execv>", OP_R2
, OP_R3
, OP_VOID
);
2833 trace_output (OP_R2
);
2842 RETVAL
= pipe (host_fd
);
2843 SW (buf
, host_fd
[0]);
2844 buf
+= sizeof(uint16
);
2845 SW (buf
, host_fd
[1]);
2846 trace_input ("<pipe>", OP_R2
, OP_VOID
, OP_VOID
);
2847 trace_output (OP_R2
);
2855 RETVAL
= wait (&status
);
2858 trace_input ("<wait>", OP_R2
, OP_VOID
, OP_VOID
);
2859 trace_output (OP_R2
);
2864 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2866 trace_output (OP_R2
);
2870 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2871 trace_output (OP_VOID
);
2872 State
.exception
= PARM2
;
2877 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2879 trace_input ("<read>", OP_R2
, OP_R3
, OP_R4
);
2880 trace_output (OP_R2
);
2885 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2886 MEMPTR (PARM2
), PARM3
);
2888 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2889 MEMPTR (PARM2
), PARM3
);
2890 trace_input ("<write>", OP_R2
, OP_R3
, OP_R4
);
2891 trace_output (OP_R2
);
2896 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2897 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2899 RETVAL_HIGH
= ret
>> 16;
2900 RETVAL_LOW
= ret
& 0xffff;
2902 trace_input ("<lseek>", OP_R2
, OP_R3
, OP_R4
);
2903 trace_output (OP_R2R3
);
2907 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2908 trace_input ("<close>", OP_R2
, OP_VOID
, OP_VOID
);
2909 trace_output (OP_R2
);
2913 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2914 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2915 trace_output (OP_R2
);
2916 trace_input ("<open>", OP_R2
, OP_R3
, OP_R4
);
2917 trace_output (OP_R2
);
2921 State
.exception
= SIG_D10V_EXIT
;
2922 trace_input ("<exit>", OP_R2
, OP_VOID
, OP_VOID
);
2923 trace_output (OP_VOID
);
2927 /* stat system call */
2929 struct stat host_stat
;
2932 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2936 /* The hard-coded offsets and sizes were determined by using
2937 * the D10V compiler on a test program that used struct stat.
2939 SW (buf
, host_stat
.st_dev
);
2940 SW (buf
+2, host_stat
.st_ino
);
2941 SW (buf
+4, host_stat
.st_mode
);
2942 SW (buf
+6, host_stat
.st_nlink
);
2943 SW (buf
+8, host_stat
.st_uid
);
2944 SW (buf
+10, host_stat
.st_gid
);
2945 SW (buf
+12, host_stat
.st_rdev
);
2946 SLW (buf
+16, host_stat
.st_size
);
2947 SLW (buf
+20, host_stat
.st_atime
);
2948 SLW (buf
+28, host_stat
.st_mtime
);
2949 SLW (buf
+36, host_stat
.st_ctime
);
2951 trace_input ("<stat>", OP_R2
, OP_R3
, OP_VOID
);
2952 trace_output (OP_R2
);
2956 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2957 trace_input ("<chown>", OP_R2
, OP_R3
, OP_R4
);
2958 trace_output (OP_R2
);
2962 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2963 trace_input ("<chmod>", OP_R2
, OP_R3
, OP_R4
);
2964 trace_output (OP_R2
);
2968 /* Cast the second argument to void *, to avoid type mismatch
2969 if a prototype is present. */
2970 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2971 trace_input ("<utime>", OP_R2
, OP_R3
, OP_R4
);
2972 trace_output (OP_R2
);
2977 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
2978 RETVAL_HIGH
= ret
>> 16;
2979 RETVAL_LOW
= ret
& 0xffff;
2981 trace_input ("<time>", OP_R2
, OP_R3
, OP_R4
);
2982 trace_output (OP_R2R3
);
2988 RETERR
= d10v_callback
->get_errno(d10v_callback
);
2993 /* Trap 1 prints a string */
2995 char *fstr
= dmem_addr(State
.regs
[2]);
2996 fputs (fstr
, stdout
);
3001 /* Trap 2 calls printf */
3003 char *fstr
= dmem_addr(State
.regs
[2]);
3004 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
3005 (int16
)State
.regs
[3],
3006 (int16
)State
.regs
[4],
3007 (int16
)State
.regs
[5]);
3008 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3013 /* Trap 3 writes a character */
3014 putchar (State
.regs
[2]);
3024 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3025 State
.F1
= State
.F0
;
3026 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
3027 trace_output (OP_FLAG
);
3034 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3035 State
.F1
= State
.F0
;
3036 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
3037 trace_output (OP_FLAG
);
3044 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3046 trace_output (OP_VOID
);
3053 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3054 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3055 trace_output (OP_REG
);
3062 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3063 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3064 trace_output (OP_REG
);
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