2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V1.8 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 675
19 * Mass Ave, Cambridge, MA 02139, USA.
23 /* The control space devices */
25 #include <sys/types.h>
27 #include <sys/ioctl.h>
28 #include <sys/fcntl.h>
33 extern int32 sis_verbose
;
35 extern char uart_dev1
[], uart_dev2
[];
37 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
40 /* MEC register addresses */
42 #define MEC_UARTA 0x0E0
43 #define MEC_UARTB 0x0E4
44 #define MEC_UART_CTRL 0x0E8
45 #define MEC_TIMER_CTRL 0x098
46 #define MEC_RTC_COUNTER 0x080
47 #define MEC_RTC_RELOAD 0x080
48 #define MEC_RTC_SCALER 0x084
49 #define MEC_GPT_COUNTER 0x088
50 #define MEC_GPT_RELOAD 0x088
51 #define MEC_GPT_SCALER 0x08C
55 #define MEC_SFSR 0x0A0
56 #define MEC_FFAR 0x0A4
62 #define MEC_MEMCFG 0x010
64 #define MEC_MAR0 0x020
65 #define MEC_MAR1 0x024
67 #define MEC_WDOG 0x060
68 #define MEC_TRAPD 0x064
69 #define MEC_PWDR 0x008
70 #define SIM_LOAD 0x0F0
72 /* Memory exception causes */
79 /* Size of UART buffers (bytes) */
82 /* Number of simulator ticks between flushing the UARTS. */
83 /* For good performance, keep above 1000 */
84 #define UART_FLUSH_TIME 3000
86 /* MEC timer control register bits */
91 #define TCR_TCRCR 0x100
92 #define TCR_TCRCL 0x200
93 #define TCR_TCRSE 0x400
94 #define TCR_TCRSL 0x800
96 /* New uart defines */
97 #define UART_TX_TIME 1000
98 #define UART_RX_TIME 1000
100 #define UARTA_SRE 0x2
101 #define UARTA_HRE 0x4
102 #define UARTA_OR 0x40
103 #define UARTA_CLR 0x80
104 #define UARTB_DR 0x10000
105 #define UARTB_SRE 0x20000
106 #define UARTB_HRE 0x40000
107 #define UARTB_OR 0x400000
108 #define UARTB_CLR 0x800000
110 #define UART_DR 0x100
111 #define UART_TSE 0x200
112 #define UART_THE 0x400
116 static char fname
[256];
117 static uint32 find
= 0;
118 static char simfn
[] = "simload";
119 static uint32 brk_point
= 0;
120 static uint32 watch_point
= 0;
121 static uint32 mec_dbg
= 0;
122 static uint32 mec_sfsr
= 0x078;
123 static uint32 mec_ffar
= 0;
124 static uint32 mec_ipr
= 0;
125 static uint32 mec_imr
= 0x3fff;
126 static uint32 mec_icr
= 0;
127 static uint32 mec_ifr
= 0;
128 static uint32 mec_mcr
; /* MEC control register */
129 static uint32 mec_memcfg
; /* Memory control register */
130 static uint32 mec_wcr
; /* MEC waitstate register */
131 static uint32 mec_mar0
; /* MEC access registers (2) */
132 static uint32 mec_mar1
; /* MEC access registers (2) */
133 static uint32 mec_regs
[64];
134 static uint32 posted_irq
;
135 static uint32 mec_ersr
= 0; /* MEC error and status register */
136 static uint32 mec_emr
= 0x60; /* MEC error mask register */
137 static uint32 mec_tcr
= 0; /* MEC test comtrol register */
139 static uint32 rtc_counter
= 0xffffffff;
140 static uint32 rtc_reload
= 0xffffffff;
141 static uint32 rtc_scaler
= 0xff;
142 static uint32 rtc_enabled
= 0;
143 static uint32 rtc_cr
= 0;
144 static uint32 rtc_se
= 0;
145 static uint32 rtc_cont
= 0;
147 static uint32 gpt_counter
= 0xffffffff;
148 static uint32 gpt_reload
= 0xffffffff;
149 static uint32 gpt_scaler
= 0xffff;
150 static uint32 gpt_enabled
= 0;
151 static uint32 gpt_cr
= 0;
152 static uint32 gpt_se
= 0;
153 static uint32 gpt_cont
= 0;
155 static uint32 wdog_scaler
;
156 static uint32 wdog_counter
;
157 static uint32 wdog_rst_delay
;
158 static uint32 wdog_rston
;
161 static uint32 gpt_irqon
= 1;
162 static uint32 rtc_irqon
= 1;
166 init
, disabled
, enabled
, stopped
169 static enum wdog_type wdog_status
;
171 /* Memory support variables */
173 static uint32 mem_ramr_ws
; /* RAM read waitstates */
174 static uint32 mem_ramw_ws
; /* RAM write waitstates */
175 static uint32 mem_romr_ws
; /* ROM read waitstates */
176 static uint32 mem_romw_ws
; /* ROM write waitstates */
177 static uint32 mem_ramsz
; /* RAM size */
178 static uint32 mem_romsz
; /* RAM size */
179 static uint32 mem_banksz
; /* RAM bank size */
180 static uint32 mem_accprot
; /* RAM write protection enabled */
182 /* UART support variables */
184 static unsigned char Adata
, Bdata
;
185 static int32 fd1
, fd2
; /* file descriptor for input file */
186 static int32 Ucontrol
; /* UART status register */
187 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
189 static int32 anum
, aind
= 0;
190 static int32 bnum
, bind
= 0;
191 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
192 static unsigned wnuma
;
193 static unsigned wnumb
;
194 static FILE *f1
= NULL
, *f2
= NULL
;
196 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
197 static uint32 uart_stat_reg
;
198 static uint32 uarta_data
, uartb_data
;
204 uint32
rtc_counter_read();
205 void rtc_scaler_set();
206 void rtc_reload_set();
207 uint32
gpt_counter_read();
208 void gpt_scaler_set();
209 void gpt_reload_set();
212 void uart_irq_start();
225 /* Power-on reset init */
235 /* IU error mode manager */
242 if ((mec_emr
& 0x1) == 0) {
243 if (mec_mcr
& 0x20) {
246 printf("Error manager reset - IU in error mode at 0x%08x\n", pc
);
251 /* Check memory settings */
256 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
257 mem_banksz
= ((mec_memcfg
>> 10) & 7) + 18 - 6;
258 mem_romsz
= (4 * 1024) << ((mec_memcfg
>> 18) & 7);
260 printf("RAM size: %d K, ROM size: %d K, protection bank size: %d K\n",
261 mem_ramsz
>> 10, mem_romsz
>> 10, 1 << mem_banksz
);
267 mem_ramr_ws
= mec_wcr
& 3;
268 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
269 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
270 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
272 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
273 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
279 mem_accprot
= (mec_mcr
>> 3) & 1;
280 if (sis_verbose
&& mem_accprot
)
281 printf("Memory access protection enabled\n");
282 if (sis_verbose
&& (mec_mcr
& 2))
283 printf("Software reset enabled\n");
284 if (sis_verbose
&& (mec_mcr
& 1))
285 printf("Power-down mode enabled\n");
288 /* Flush ports when simulator stops */
327 mec_memcfg
= 0x10000;
328 mec_mcr
= 0x01b50014;
332 mec_ersr
= 0; /* MEC error and status register */
333 mec_emr
= 0x60; /* MEC error mask register */
334 mec_tcr
= 0; /* MEC test comtrol register */
342 anum
= aind
= bnum
= bind
= 0;
344 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
345 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
347 rtc_counter
= 0xffffffff;
348 rtc_reload
= 0xffffffff;
355 gpt_counter
= 0xffffffff;
356 gpt_reload
= 0xffffffff;
364 wdog_rst_delay
= 255;
365 wdog_counter
= 0xffff;
385 printf("interrupt %d acknowledged\n",level
);
386 irq_test
= mec_tcr
& 0x80000;
387 if ((irq_test
) && (mec_ifr
& (1 << level
)))
388 mec_ifr
&= ~(1 << level
);
390 mec_ipr
&= ~(1 << level
);
391 posted_irq
&= ~(1 << level
);
394 if (uart_stat_reg
& 1)
396 if (uart_stat_reg
& 0x100)
408 itmp
= ((mec_ipr
| mec_ifr
) & ~mec_imr
) & 0x0fffe;
410 for (i
= 15; i
> 0; i
--) {
411 if (((itmp
>> i
) & 1) != 0) {
412 if ((posted_irq
& (1 << i
)) == 0) {
414 printf("interrupt %d generated\n",i
);
415 set_int(i
, mec_intack
, i
);
416 posted_irq
|= (1 << i
);
427 mec_ipr
|= (1 << level
);
432 set_sfsr(fault
, addr
, asi
, read
)
439 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
460 if ((mec_dbg
& 0x80000) && (addr
== brk_point
) &&
461 ((asi
== 9) || (asi
== 8))) {
462 mec_dbg
|= 0x00800000;
463 if (mec_dbg
& 0x00200000) {
464 set_sfsr(BREAK_EXC
, addr
, asi
, 1);
472 chk_watch(addr
, read
, asi
)
478 if ((mec_dbg
& 0x40000) && (asi
!= 9) && (asi
!= 8) &&
479 (((mec_dbg
& 0x10000) && (read
== 0)) || ((mec_dbg
& 0x20000) && read
))) {
480 if (((addr
^ watch_point
) &
481 (0xffff0000 | (mec_dbg
& 0x0ffff))) == 0) {
482 mec_dbg
|= 0x00400000;
483 if (mec_dbg
& 0x100000) {
484 set_sfsr(WATCH_EXC
, addr
, asi
, read
);
493 mec_read(addr
, asi
, data
)
499 switch (addr
& 0x0ff) {
512 *data
= read_uart(addr
);
517 *data
= read_uart(addr
);
520 case MEC_RTC_COUNTER
:
521 *data
= rtc_counter_read();
524 case MEC_GPT_COUNTER
:
525 *data
= gpt_counter_read();
551 strcpy(fname
, "simload");
552 *data
= bfd_load(fname
);
582 printf("Warning, read from unimplemented MEC register %x\n\r", addr
);
583 *data
= mec_regs
[((addr
& 0x0ff) >> 2)];
590 mec_write(addr
, data
)
595 switch (addr
& 0x0ff) {
601 printf(" Software reset issued\n");
620 write_uart(addr
, data
);
624 gpt_reload_set(data
);
628 gpt_scaler_set(data
);
636 rtc_reload_set(data
);
640 rtc_scaler_set(data
);
648 mec_imr
= data
& 0x7ffe;
653 mec_icr
&= ~data
& 0x0fffe;
657 mec_ifr
= data
& 0xfffe;
661 fname
[find
++] = (char) data
;
670 mec_memcfg
= data
& ~0xC0e08000;
688 wdog_scaler
= (data
>> 16) & 0x0ff;
689 wdog_counter
= data
& 0x0ffff;
690 wdog_rst_delay
= data
>> 24;
692 if (wdog_status
== stopped
)
694 wdog_status
= enabled
;
698 if (wdog_status
== init
) {
699 wdog_status
= disabled
;
701 printf("Watchdog disabled\n");
712 printf("Warning, write to unimplemented MEC register %x\n\r",
714 mec_regs
[((addr
& 0x0ffc) >> 2)] = data
;
728 int32 pty_remote
= 1;
732 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NDELAY
| O_NONBLOCK
)) < 0) {
733 printf("Warning, couldn't open output device %s\n", uart_dev1
);
735 printf("serial port A on %s\n", uart_dev1
);
736 f1
= fdopen(fd1
, "r+");
739 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NDELAY
| O_NONBLOCK
)) < 0) {
740 printf("Warning, couldn't open output device %s\n", uart_dev2
);
742 printf("serial port B on %s\n", uart_dev2
);
743 f2
= fdopen(fd2
, "r+");
757 switch (addr
& 0xff) {
759 case 0xE0: /* UART 1 */
762 if ((aind
+ 1) < anum
)
764 return (0x700 | (uint32
) aq
[aind
++]);
767 anum
= fread(aq
, 1, UARTBUF
, f1
);
772 if ((aind
+ 1) < anum
)
774 return (0x700 | (uint32
) aq
[aind
++]);
776 return (0x600 | (uint32
) aq
[aind
]);
782 uarta_data
&= ~UART_DR
;
783 uart_stat_reg
&= ~UARTA_DR
;
788 case 0xE4: /* UART 2 */
791 if ((bind
+ 1) < bnum
)
793 return (0x700 | (uint32
) bq
[bind
++]);
796 bnum
= fread(bq
, 1, UARTBUF
, f2
);
801 if ((bind
+ 1) < bnum
)
803 return (0x700 | (uint32
) bq
[bind
++]);
805 return (0x600 | (uint32
) bq
[bind
]);
811 uartb_data
&= ~UART_DR
;
812 uart_stat_reg
&= ~UARTB_DR
;
817 case 0xE8: /* UART status register */
821 Ucontrol
|= 0x00000001;
824 anum
= fread(aq
, 1, UARTBUF
, f1
);
828 Ucontrol
|= 0x00000001;
834 Ucontrol
|= 0x00010000;
837 bnum
= fread(bq
, 1, UARTBUF
, f2
);
841 Ucontrol
|= 0x00010000;
847 Ucontrol
|= 0x00060006;
850 return (uart_stat_reg
);
855 printf("Read from unimplemented MEC register (%x)\n", addr
);
862 write_uart(addr
, data
)
870 c
= (unsigned char) data
;
871 switch (addr
& 0xff) {
873 case 0xE0: /* UART A */
880 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1
);
887 if (uart_stat_reg
& UARTA_SRE
) {
889 uart_stat_reg
&= ~UARTA_SRE
;
890 event(uarta_tx
, 0, UART_TX_TIME
);
893 uart_stat_reg
&= ~UARTA_HRE
;
898 case 0xE4: /* UART B */
905 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2
);
912 if (uart_stat_reg
& UARTB_SRE
) {
914 uart_stat_reg
&= ~UARTB_SRE
;
915 event(uartb_tx
, 0, UART_TX_TIME
);
918 uart_stat_reg
&= ~UARTB_HRE
;
922 case 0xE8: /* UART status register */
924 if (data
& UARTA_CLR
) {
925 uart_stat_reg
&= 0xFFFF0000;
926 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
928 if (data
& UARTB_CLR
) {
929 uart_stat_reg
&= 0x0000FFFF;
930 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
936 printf("Write to unimplemented MEC register (%x)\n", addr
);
945 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1
);
950 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2
);
961 while ((f1
? fwrite(&uarta_sreg
, 1, 1, f1
) : 1) != 1);
962 if (uart_stat_reg
& UARTA_HRE
) {
963 uart_stat_reg
|= UARTA_SRE
;
965 uarta_sreg
= uarta_hreg
;
966 uart_stat_reg
|= UARTA_HRE
;
967 event(uarta_tx
, 0, UART_TX_TIME
);
975 while (fwrite(&uartb_sreg
, 1, 1, f2
) != 1);
976 if (uart_stat_reg
& UARTB_HRE
) {
977 uart_stat_reg
|= UARTB_SRE
;
979 uartb_sreg
= uartb_hreg
;
980 uart_stat_reg
|= UARTB_HRE
;
981 event(uartb_tx
, 0, UART_TX_TIME
);
993 rsize
= fread(&rxd
, 1, 1, f1
);
995 uarta_data
= UART_DR
| rxd
;
996 if (uart_stat_reg
& UARTA_HRE
)
997 uarta_data
|= UART_THE
;
998 if (uart_stat_reg
& UARTA_SRE
)
999 uarta_data
|= UART_TSE
;
1000 if (uart_stat_reg
& UARTA_DR
) {
1001 uart_stat_reg
|= UARTA_OR
;
1002 mec_irq(7); /* UART error interrupt */
1004 uart_stat_reg
|= UARTA_DR
;
1007 rsize
= fread(&rxd
, 1, 1, f2
);
1009 uartb_data
= UART_DR
| rxd
;
1010 if (uart_stat_reg
& UARTB_HRE
)
1011 uartb_data
|= UART_THE
;
1012 if (uart_stat_reg
& UARTB_SRE
)
1013 uartb_data
|= UART_TSE
;
1014 if (uart_stat_reg
& UARTB_DR
) {
1015 uart_stat_reg
|= UARTB_OR
;
1016 mec_irq(7); /* UART error interrupt */
1018 uart_stat_reg
|= UARTB_DR
;
1021 event(uart_rx
, 0, UART_RX_TIME
);
1028 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1029 flush_uart(); /* Flush UART ports */
1030 event(uart_intr
, 0, UART_FLUSH_TIME
);
1038 event(uart_intr
, 0, UART_FLUSH_TIME
);
1040 event(uart_rx
, 0, UART_RX_TIME
);
1050 if (wdog_status
== disabled
) {
1051 wdog_status
= stopped
;
1056 event(wdog_intr
, 0, wdog_scaler
+ 1);
1059 printf("Watchdog reset!\n");
1065 wdog_counter
= wdog_rst_delay
;
1066 event(wdog_intr
, 0, wdog_scaler
+ 1);
1075 event(wdog_intr
, 0, wdog_scaler
+ 1);
1077 printf("Watchdog started, scaler = %d, counter = %d\n",
1078 wdog_scaler
, wdog_counter
);
1089 if (rtc_counter
== 0) {
1093 rtc_counter
= rtc_reload
;
1102 printf("RTC interrupt lost (MEC rev.0)\n");
1108 rtc_counter
= rtc_reload
;
1117 rtc_counter
= rtc_reload
;
1124 if (rtc_se
&& rtc_cont
) {
1125 event(rtc_intr
, 0, rtc_scaler
+ 1);
1129 printf("RTC stopped\n\r");
1138 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1139 event(rtc_intr
, 0, rtc_scaler
+ 1);
1146 return (rtc_counter
);
1153 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1167 if (gpt_counter
== 0) {
1171 gpt_counter
= gpt_reload
;
1180 printf("GPT interrupt lost (MEC rev.0)\n");
1186 gpt_counter
= gpt_reload
;
1194 gpt_counter
= gpt_reload
;
1200 if (gpt_se
&& gpt_cont
) {
1201 event(gpt_intr
, 0, gpt_scaler
+ 1);
1205 printf("GPT stopped\n\r");
1214 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1215 event(gpt_intr
, 0, gpt_scaler
+ 1);
1222 return (gpt_counter
);
1229 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1245 if ((mecrev0
) && (val
& 0x500))
1249 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1250 if (val
& TCR_TCRCL
) {
1251 rtc_counter
= rtc_reload
;
1254 if (val
& TCR_TCRSL
) {
1257 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1258 if (rtc_cont
&& rtc_se
&& (rtc_enabled
== 0))
1262 if ((mecrev0
) && (val
& 0x5))
1266 gpt_cr
= (val
& TCR_GACR
);
1267 if (val
& TCR_GACL
) {
1268 gpt_counter
= gpt_reload
;
1271 if (val
& TCR_GACL
) {
1274 gpt_se
= (val
& TCR_GASE
) >> 2;
1275 if (gpt_cont
&& gpt_se
&& (gpt_enabled
== 0))
1280 /* Memory emulation */
1282 /* ROM size 512 Kbyte */
1283 #define ROM_SZ 0x080000
1285 /* RAM size 4 Mbyte */
1286 #define RAM_START 0x02000000
1287 #define RAM_END 0x02400000
1288 #define RAM_MASK 0x003fffff
1291 #define MEC_START 0x01f80000
1292 #define MEC_END 0x01f80100
1294 /* Memory exception waitstates */
1297 /* ERC32 always adds one waitstate during ldd/std */
1301 extern int32 sis_verbose
;
1303 static uint32 romb
[ROM_SZ
/ 4];
1304 static uint32 ramb
[(RAM_END
- RAM_START
) / 4];
1307 memory_read(asi
, addr
, data
, ws
)
1318 if (mec_dbg
& 0x80000) {
1319 if (chk_brk(addr
, asi
)) {
1324 if (mec_dbg
& 0x40000) {
1325 if (chk_watch(addr
, 1, asi
)) {
1332 if (addr
< mem_romsz
) {
1333 *data
= romb
[addr
>> 2];
1336 } else if ((addr
>= RAM_START
) && (addr
< (RAM_START
+ mem_ramsz
))) {
1337 *data
= ramb
[(addr
& RAM_MASK
) >> 2];
1340 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1341 mexc
= mec_read(addr
, asi
, data
);
1343 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1350 printf("Memory exception at %x (illegal address)\n", addr
);
1351 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1357 memory_write(asi
, addr
, data
, sz
, ws
)
1371 if (mec_dbg
& 0x40000) {
1372 if (chk_watch(addr
, 0, asi
)) {
1379 if ((addr
>= RAM_START
) && (addr
< (RAM_START
+ mem_ramsz
))) {
1381 bank
= (addr
& RAM_MASK
) >> mem_banksz
;
1383 ? !((1 << bank
) & mec_mar0
)
1384 : !((1 << (bank
- 32) & mec_mar1
))) {
1385 printf("Memory access protection error at %x\n", addr
);
1386 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1392 waddr
= (addr
& RAM_MASK
) >> 2;
1395 byte_addr
= addr
& 3;
1396 byte_mask
= 0x0ff << (24 - (8 * byte_addr
));
1397 ramb
[waddr
] = (ramb
[waddr
] & ~byte_mask
)
1398 | ((*data
& 0x0ff) << (24 - (8 * byte_addr
)));
1401 byte_addr
= (addr
& 2) >> 1;
1402 byte_mask
= 0x0ffff << (16 - (16 * byte_addr
));
1403 ramb
[waddr
] = (ramb
[waddr
] & ~byte_mask
)
1404 | ((*data
& 0x0ffff) << (16 - (16 * byte_addr
)));
1407 ramb
[waddr
] = *data
;
1410 ramb
[waddr
] = data
[0];
1411 ramb
[waddr
+ 1] = data
[1];
1412 *ws
+= mem_ramw_ws
+ STD_WS
;
1416 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1417 if ((sz
!= 2) || (asi
!= 0xb)) {
1418 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1422 mexc
= mec_write(addr
, *data
);
1424 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1433 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1438 get_mem_ptr(addr
, size
)
1444 brom
= (char *) romb
;
1445 bram
= (char *) ramb
;
1446 if ((addr
+ size
) < ROM_SZ
) {
1447 return (&brom
[addr
]);
1448 } else if ((addr
>= RAM_START
) && ((addr
+ size
) < RAM_END
)) {
1449 return (&bram
[(addr
& RAM_MASK
)]);
1451 return ((char *) -1);
1455 sis_memory_write(addr
, data
, length
)
1463 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1465 #ifdef HOST_LITTLE_ENDIAN
1466 for (i
= 0; i
< length
; i
++) {
1467 mem
[i
^ 0x3] = data
[i
];
1470 memcpy(mem
, data
, length
);
1476 sis_memory_read(addr
, data
, length
)
1484 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1487 #ifdef HOST_LITTLE_ENDIAN
1488 for (i
= 0; i
< length
; i
++) {
1489 data
[i
] = mem
[i
^ 0x3];
1492 memcpy(data
, mem
, length
);
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