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[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
1 /* Copyright (C) 1995-2015 Free Software Foundation, Inc.
2
3 This program is free software; you can redistribute it and/or modify
4 it under the terms of the GNU General Public License as published by
5 the Free Software Foundation; either version 3 of the License, or
6 (at your option) any later version.
7
8 This program is distributed in the hope that it will be useful,
9 but WITHOUT ANY WARRANTY; without even the implied warranty of
10 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 GNU General Public License for more details.
12
13 You should have received a copy of the GNU General Public License
14 along with this program. If not, see <http://www.gnu.org/licenses/>. */
15
16 /* The control space devices */
17
18 #include "config.h"
19 #include <sys/types.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <termios.h>
23 #include <sys/fcntl.h>
24 #include <sys/file.h>
25 #include <unistd.h>
26 #include "sis.h"
27 #include "sim-config.h"
28
29 extern int ctrl_c;
30 extern int32 sis_verbose;
31 extern int32 sparclite, sparclite_board;
32 extern int rom8,wrp,uben;
33 extern char uart_dev1[], uart_dev2[];
34
35 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
36
37 /* MEC registers */
38 #define MEC_START 0x01f80000
39 #define MEC_END 0x01f80100
40
41 /* Memory exception waitstates */
42 #define MEM_EX_WS 1
43
44 /* ERC32 always adds one waitstate during RAM std */
45 #define STD_WS 1
46
47 #ifdef ERRINJ
48 extern int errmec;
49 #endif
50
51 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
52 #define MOK 0
53
54 /* MEC register addresses */
55
56 #define MEC_MCR 0x000
57 #define MEC_SFR 0x004
58 #define MEC_PWDR 0x008
59 #define MEC_MEMCFG 0x010
60 #define MEC_IOCR 0x014
61 #define MEC_WCR 0x018
62
63 #define MEC_MAR0 0x020
64 #define MEC_MAR1 0x024
65
66 #define MEC_SSA1 0x020
67 #define MEC_SEA1 0x024
68 #define MEC_SSA2 0x028
69 #define MEC_SEA2 0x02C
70 #define MEC_ISR 0x044
71 #define MEC_IPR 0x048
72 #define MEC_IMR 0x04C
73 #define MEC_ICR 0x050
74 #define MEC_IFR 0x054
75 #define MEC_WDOG 0x060
76 #define MEC_TRAPD 0x064
77 #define MEC_RTC_COUNTER 0x080
78 #define MEC_RTC_RELOAD 0x080
79 #define MEC_RTC_SCALER 0x084
80 #define MEC_GPT_COUNTER 0x088
81 #define MEC_GPT_RELOAD 0x088
82 #define MEC_GPT_SCALER 0x08C
83 #define MEC_TIMER_CTRL 0x098
84 #define MEC_SFSR 0x0A0
85 #define MEC_FFAR 0x0A4
86 #define MEC_ERSR 0x0B0
87 #define MEC_DBG 0x0C0
88 #define MEC_TCR 0x0D0
89
90 #define MEC_BRK 0x0C4
91 #define MEC_WPR 0x0C8
92
93 #define MEC_UARTA 0x0E0
94 #define MEC_UARTB 0x0E4
95 #define MEC_UART_CTRL 0x0E8
96 #define SIM_LOAD 0x0F0
97
98 /* Memory exception causes */
99 #define PROT_EXC 0x3
100 #define UIMP_ACC 0x4
101 #define MEC_ACC 0x6
102 #define WATCH_EXC 0xa
103 #define BREAK_EXC 0xb
104
105 /* Size of UART buffers (bytes) */
106 #define UARTBUF 1024
107
108 /* Number of simulator ticks between flushing the UARTS. */
109 /* For good performance, keep above 1000 */
110 #define UART_FLUSH_TIME 3000
111
112 /* MEC timer control register bits */
113 #define TCR_GACR 1
114 #define TCR_GACL 2
115 #define TCR_GASE 4
116 #define TCR_GASL 8
117 #define TCR_TCRCR 0x100
118 #define TCR_TCRCL 0x200
119 #define TCR_TCRSE 0x400
120 #define TCR_TCRSL 0x800
121
122 /* New uart defines */
123 #define UART_TX_TIME 1000
124 #define UART_RX_TIME 1000
125 #define UARTA_DR 0x1
126 #define UARTA_SRE 0x2
127 #define UARTA_HRE 0x4
128 #define UARTA_OR 0x40
129 #define UARTA_CLR 0x80
130 #define UARTB_DR 0x10000
131 #define UARTB_SRE 0x20000
132 #define UARTB_HRE 0x40000
133 #define UARTB_OR 0x400000
134 #define UARTB_CLR 0x800000
135
136 #define UART_DR 0x100
137 #define UART_TSE 0x200
138 #define UART_THE 0x400
139
140 /* MEC registers */
141
142 static char fname[256];
143 static int32 find = 0;
144 static uint32 mec_ssa[2]; /* Write protection start address */
145 static uint32 mec_sea[2]; /* Write protection end address */
146 static uint32 mec_wpr[2]; /* Write protection control fields */
147 static uint32 mec_sfsr;
148 static uint32 mec_ffar;
149 static uint32 mec_ipr;
150 static uint32 mec_imr;
151 static uint32 mec_isr;
152 static uint32 mec_icr;
153 static uint32 mec_ifr;
154 static uint32 mec_mcr; /* MEC control register */
155 static uint32 mec_memcfg; /* Memory control register */
156 static uint32 mec_wcr; /* MEC waitstate register */
157 static uint32 mec_iocr; /* MEC IO control register */
158 static uint32 posted_irq;
159 static uint32 mec_ersr; /* MEC error and status register */
160 static uint32 mec_tcr; /* MEC test comtrol register */
161
162 static uint32 rtc_counter;
163 static uint32 rtc_reload;
164 static uint32 rtc_scaler;
165 static uint32 rtc_scaler_start;
166 static uint32 rtc_enabled;
167 static uint32 rtc_cr;
168 static uint32 rtc_se;
169
170 static uint32 gpt_counter;
171 static uint32 gpt_reload;
172 static uint32 gpt_scaler;
173 static uint32 gpt_scaler_start;
174 static uint32 gpt_enabled;
175 static uint32 gpt_cr;
176 static uint32 gpt_se;
177
178 static uint32 wdog_scaler;
179 static uint32 wdog_counter;
180 static uint32 wdog_rst_delay;
181 static uint32 wdog_rston;
182
183 enum wdog_type {
184 init, disabled, enabled, stopped
185 };
186
187 static enum wdog_type wdog_status;
188
189
190 /* ROM size 1024 Kbyte */
191 #define ROM_SZ 0x100000
192 #define ROM_MASK 0x0fffff
193
194 /* RAM size 4 Mbyte */
195 #define RAM_START 0x02000000
196 #define RAM_END 0x02400000
197 #define RAM_MASK 0x003fffff
198
199 /* SPARClite boards all seem to have RAM at the same place. */
200 #define RAM_START_SLITE 0x40000000
201 #define RAM_END_SLITE 0x40400000
202 #define RAM_MASK_SLITE 0x003fffff
203
204 /* Memory support variables */
205
206 static uint32 mem_ramr_ws; /* RAM read waitstates */
207 static uint32 mem_ramw_ws; /* RAM write waitstates */
208 static uint32 mem_romr_ws; /* ROM read waitstates */
209 static uint32 mem_romw_ws; /* ROM write waitstates */
210 static uint32 mem_ramstart; /* RAM start */
211 static uint32 mem_ramend; /* RAM end */
212 static uint32 mem_rammask; /* RAM address mask */
213 static uint32 mem_ramsz; /* RAM size */
214 static uint32 mem_romsz; /* ROM size */
215 static uint32 mem_accprot; /* RAM write protection enabled */
216 static uint32 mem_blockprot; /* RAM block write protection enabled */
217
218 static unsigned char romb[ROM_SZ];
219 static unsigned char ramb[RAM_END - RAM_START];
220
221
222 /* UART support variables */
223
224 static int32 fd1, fd2; /* file descriptor for input file */
225 static int32 Ucontrol; /* UART status register */
226 static unsigned char aq[UARTBUF], bq[UARTBUF];
227 static int32 anum, aind = 0;
228 static int32 bnum, bind = 0;
229 static char wbufa[UARTBUF], wbufb[UARTBUF];
230 static unsigned wnuma;
231 static unsigned wnumb;
232 static FILE *f1in, *f1out, *f2in, *f2out;
233 static struct termios ioc1, ioc2, iocold1, iocold2;
234 static int f1open = 0, f2open = 0;
235
236 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
237 static uint32 uart_stat_reg;
238 static uint32 uarta_data, uartb_data;
239
240 #ifdef ERA
241 int era = 0;
242 int erareg;
243 #endif
244
245 /* Forward declarations */
246
247 static void decode_ersr (void);
248 #ifdef ERRINJ
249 static void iucomperr (void);
250 #endif
251 static void mecparerror (void);
252 static void decode_memcfg (void);
253 static void decode_wcr (void);
254 static void decode_mcr (void);
255 static void close_port (void);
256 static void mec_reset (void);
257 static void mec_intack (int32 level);
258 static void chk_irq (void);
259 static void mec_irq (int32 level);
260 static void set_sfsr (uint32 fault, uint32 addr,
261 uint32 asi, uint32 read);
262 static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
263 static int mec_write (uint32 addr, uint32 data);
264 static void port_init (void);
265 static uint32 read_uart (uint32 addr);
266 static void write_uart (uint32 addr, uint32 data);
267 static void flush_uart (void);
268 static void uarta_tx (void);
269 static void uartb_tx (void);
270 static void uart_rx (caddr_t arg);
271 static void uart_intr (caddr_t arg);
272 static void uart_irq_start (void);
273 static void wdog_intr (caddr_t arg);
274 static void wdog_start (void);
275 static void rtc_intr (caddr_t arg);
276 static void rtc_start (void);
277 static uint32 rtc_counter_read (void);
278 static void rtc_scaler_set (uint32 val);
279 static void rtc_reload_set (uint32 val);
280 static void gpt_intr (caddr_t arg);
281 static void gpt_start (void);
282 static uint32 gpt_counter_read (void);
283 static void gpt_scaler_set (uint32 val);
284 static void gpt_reload_set (uint32 val);
285 static void timer_ctrl (uint32 val);
286 static unsigned char *
287 get_mem_ptr (uint32 addr, uint32 size);
288 static void store_bytes (unsigned char *mem, uint32 waddr,
289 uint32 *data, int sz, int32 *ws);
290
291 extern int ext_irl;
292
293
294 /* One-time init */
295
296 void
297 init_sim()
298 {
299 port_init();
300 }
301
302 /* Power-on reset init */
303
304 void
305 reset()
306 {
307 mec_reset();
308 uart_irq_start();
309 wdog_start();
310 }
311
312 static void
313 decode_ersr()
314 {
315 if (mec_ersr & 0x01) {
316 if (!(mec_mcr & 0x20)) {
317 if (mec_mcr & 0x40) {
318 sys_reset();
319 mec_ersr = 0x8000;
320 if (sis_verbose)
321 printf("Error manager reset - IU in error mode\n");
322 } else {
323 sys_halt();
324 mec_ersr |= 0x2000;
325 if (sis_verbose)
326 printf("Error manager halt - IU in error mode\n");
327 }
328 } else
329 mec_irq(1);
330 }
331 if (mec_ersr & 0x04) {
332 if (!(mec_mcr & 0x200)) {
333 if (mec_mcr & 0x400) {
334 sys_reset();
335 mec_ersr = 0x8000;
336 if (sis_verbose)
337 printf("Error manager reset - IU comparison error\n");
338 } else {
339 sys_halt();
340 mec_ersr |= 0x2000;
341 if (sis_verbose)
342 printf("Error manager halt - IU comparison error\n");
343 }
344 } else
345 mec_irq(1);
346 }
347 if (mec_ersr & 0x20) {
348 if (!(mec_mcr & 0x2000)) {
349 if (mec_mcr & 0x4000) {
350 sys_reset();
351 mec_ersr = 0x8000;
352 if (sis_verbose)
353 printf("Error manager reset - MEC hardware error\n");
354 } else {
355 sys_halt();
356 mec_ersr |= 0x2000;
357 if (sis_verbose)
358 printf("Error manager halt - MEC hardware error\n");
359 }
360 } else
361 mec_irq(1);
362 }
363 }
364
365 #ifdef ERRINJ
366 static void
367 iucomperr()
368 {
369 mec_ersr |= 0x04;
370 decode_ersr();
371 }
372 #endif
373
374 static void
375 mecparerror()
376 {
377 mec_ersr |= 0x20;
378 decode_ersr();
379 }
380
381
382 /* IU error mode manager */
383
384 void
385 error_mode(pc)
386 uint32 pc;
387 {
388
389 mec_ersr |= 0x1;
390 decode_ersr();
391 }
392
393
394 /* Check memory settings */
395
396 static void
397 decode_memcfg()
398 {
399 if (rom8) mec_memcfg &= ~0x20000;
400 else mec_memcfg |= 0x20000;
401
402 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
403 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
404
405 if (sparclite_board) {
406 mem_ramstart = RAM_START_SLITE;
407 mem_ramend = RAM_END_SLITE;
408 mem_rammask = RAM_MASK_SLITE;
409 }
410 else {
411 mem_ramstart = RAM_START;
412 mem_ramend = RAM_END;
413 mem_rammask = RAM_MASK;
414 }
415 if (sis_verbose)
416 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
417 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
418 }
419
420 static void
421 decode_wcr()
422 {
423 mem_ramr_ws = mec_wcr & 3;
424 mem_ramw_ws = (mec_wcr >> 2) & 3;
425 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
426 if (rom8) {
427 if (mem_romr_ws > 0 ) mem_romr_ws--;
428 mem_romr_ws = 5 + (4*mem_romr_ws);
429 }
430 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
431 if (sis_verbose)
432 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
433 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
434 }
435
436 static void
437 decode_mcr()
438 {
439 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
440 mem_blockprot = (mec_mcr >> 3) & 1;
441 if (sis_verbose && mem_accprot)
442 printf("Memory block write protection enabled\n");
443 if (mec_mcr & 0x08000) {
444 mec_ersr |= 0x20;
445 decode_ersr();
446 }
447 if (sis_verbose && (mec_mcr & 2))
448 printf("Software reset enabled\n");
449 if (sis_verbose && (mec_mcr & 1))
450 printf("Power-down mode enabled\n");
451 }
452
453 /* Flush ports when simulator stops */
454
455 void
456 sim_halt()
457 {
458 #ifdef FAST_UART
459 flush_uart();
460 #endif
461 }
462
463 int
464 sim_stop(SIM_DESC sd)
465 {
466 ctrl_c = 1;
467 return 1;
468 }
469
470 static void
471 close_port()
472 {
473 if (f1open && f1in != stdin)
474 fclose(f1in);
475 if (f2open && f2in != stdin)
476 fclose(f2in);
477 }
478
479 void
480 exit_sim()
481 {
482 close_port();
483 }
484
485 static void
486 mec_reset()
487 {
488 int i;
489
490 find = 0;
491 for (i = 0; i < 2; i++)
492 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
493 mec_mcr = 0x01350014;
494 mec_iocr = 0;
495 mec_sfsr = 0x078;
496 mec_ffar = 0;
497 mec_ipr = 0;
498 mec_imr = 0x7ffe;
499 mec_isr = 0;
500 mec_icr = 0;
501 mec_ifr = 0;
502 mec_memcfg = 0x10000;
503 mec_wcr = -1;
504 mec_ersr = 0; /* MEC error and status register */
505 mec_tcr = 0; /* MEC test comtrol register */
506
507 decode_memcfg();
508 decode_wcr();
509 decode_mcr();
510
511 posted_irq = 0;
512 wnuma = wnumb = 0;
513 anum = aind = bnum = bind = 0;
514
515 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
516 uarta_data = uartb_data = UART_THE | UART_TSE;
517
518 rtc_counter = 0xffffffff;
519 rtc_reload = 0xffffffff;
520 rtc_scaler = 0xff;
521 rtc_enabled = 0;
522 rtc_cr = 0;
523 rtc_se = 0;
524
525 gpt_counter = 0xffffffff;
526 gpt_reload = 0xffffffff;
527 gpt_scaler = 0xffff;
528 gpt_enabled = 0;
529 gpt_cr = 0;
530 gpt_se = 0;
531
532 wdog_scaler = 255;
533 wdog_rst_delay = 255;
534 wdog_counter = 0xffff;
535 wdog_rston = 0;
536 wdog_status = init;
537
538 #ifdef ERA
539 erareg = 0;
540 #endif
541
542 }
543
544
545
546 static void
547 mec_intack(level)
548 int32 level;
549 {
550 int irq_test;
551
552 if (sis_verbose)
553 printf("interrupt %d acknowledged\n", level);
554 irq_test = mec_tcr & 0x80000;
555 if ((irq_test) && (mec_ifr & (1 << level)))
556 mec_ifr &= ~(1 << level);
557 else
558 mec_ipr &= ~(1 << level);
559 chk_irq();
560 }
561
562 static void
563 chk_irq()
564 {
565 int32 i;
566 uint32 itmp;
567 int old_irl;
568
569 old_irl = ext_irl;
570 if (mec_tcr & 0x80000) itmp = mec_ifr;
571 else itmp = 0;
572 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
573 ext_irl = 0;
574 if (itmp != 0) {
575 for (i = 15; i > 0; i--) {
576 if (((itmp >> i) & 1) != 0) {
577 if ((sis_verbose) && (i > old_irl))
578 printf("IU irl: %d\n", i);
579 ext_irl = i;
580 set_int(i, mec_intack, i);
581 break;
582 }
583 }
584 }
585 }
586
587 static void
588 mec_irq(level)
589 int32 level;
590 {
591 mec_ipr |= (1 << level);
592 chk_irq();
593 }
594
595 static void
596 set_sfsr(fault, addr, asi, read)
597 uint32 fault;
598 uint32 addr;
599 uint32 asi;
600 uint32 read;
601 {
602 if ((asi == 0xa) || (asi == 0xb)) {
603 mec_ffar = addr;
604 mec_sfsr = (fault << 3) | (!read << 15);
605 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
606 switch (asi) {
607 case 0xa:
608 mec_sfsr |= 0x0004;
609 break;
610 case 0xb:
611 mec_sfsr |= 0x1004;
612 break;
613 }
614 }
615 }
616
617 static int32
618 mec_read(addr, asi, data)
619 uint32 addr;
620 uint32 asi;
621 uint32 *data;
622 {
623
624 switch (addr & 0x0ff) {
625
626 case MEC_MCR: /* 0x00 */
627 *data = mec_mcr;
628 break;
629
630 case MEC_MEMCFG: /* 0x10 */
631 *data = mec_memcfg;
632 break;
633
634 case MEC_IOCR:
635 *data = mec_iocr; /* 0x14 */
636 break;
637
638 case MEC_SSA1: /* 0x20 */
639 *data = mec_ssa[0] | (mec_wpr[0] << 23);
640 break;
641 case MEC_SEA1: /* 0x24 */
642 *data = mec_sea[0];
643 break;
644 case MEC_SSA2: /* 0x28 */
645 *data = mec_ssa[1] | (mec_wpr[1] << 23);
646 break;
647 case MEC_SEA2: /* 0x2c */
648 *data = mec_sea[1];
649 break;
650
651 case MEC_ISR: /* 0x44 */
652 *data = mec_isr;
653 break;
654
655 case MEC_IPR: /* 0x48 */
656 *data = mec_ipr;
657 break;
658
659 case MEC_IMR: /* 0x4c */
660 *data = mec_imr;
661 break;
662
663 case MEC_IFR: /* 0x54 */
664 *data = mec_ifr;
665 break;
666
667 case MEC_RTC_COUNTER: /* 0x80 */
668 *data = rtc_counter_read();
669 break;
670 case MEC_RTC_SCALER: /* 0x84 */
671 if (rtc_enabled)
672 *data = rtc_scaler - (now() - rtc_scaler_start);
673 else
674 *data = rtc_scaler;
675 break;
676
677 case MEC_GPT_COUNTER: /* 0x88 */
678 *data = gpt_counter_read();
679 break;
680
681 case MEC_GPT_SCALER: /* 0x8c */
682 if (rtc_enabled)
683 *data = gpt_scaler - (now() - gpt_scaler_start);
684 else
685 *data = gpt_scaler;
686 break;
687
688
689 case MEC_SFSR: /* 0xA0 */
690 *data = mec_sfsr;
691 break;
692
693 case MEC_FFAR: /* 0xA4 */
694 *data = mec_ffar;
695 break;
696
697 case SIM_LOAD:
698 fname[find] = 0;
699 if (find == 0)
700 strcpy(fname, "simload");
701 find = bfd_load(fname);
702 if (find == -1)
703 *data = 0;
704 else
705 *data = 1;
706 find = 0;
707 break;
708
709 case MEC_ERSR: /* 0xB0 */
710 *data = mec_ersr;
711 break;
712
713 case MEC_TCR: /* 0xD0 */
714 *data = mec_tcr;
715 break;
716
717 case MEC_UARTA: /* 0xE0 */
718 case MEC_UARTB: /* 0xE4 */
719 if (asi != 0xb) {
720 set_sfsr(MEC_ACC, addr, asi, 1);
721 return 1;
722 }
723 *data = read_uart(addr);
724 break;
725
726 case MEC_UART_CTRL: /* 0xE8 */
727
728 *data = read_uart(addr);
729 break;
730
731 case 0xF4: /* simulator RAM size in bytes */
732 *data = 4096*1024;
733 break;
734
735 case 0xF8: /* simulator ROM size in bytes */
736 *data = 1024*1024;
737 break;
738
739 default:
740 set_sfsr(MEC_ACC, addr, asi, 1);
741 return 1;
742 break;
743 }
744 return MOK;
745 }
746
747 static int
748 mec_write(addr, data)
749 uint32 addr;
750 uint32 data;
751 {
752 if (sis_verbose > 1)
753 printf("MEC write a: %08x, d: %08x\n",addr,data);
754 switch (addr & 0x0ff) {
755
756 case MEC_MCR:
757 mec_mcr = data;
758 decode_mcr();
759 if (mec_mcr & 0x08000) mecparerror();
760 break;
761
762 case MEC_SFR:
763 if (mec_mcr & 0x2) {
764 sys_reset();
765 mec_ersr = 0x4000;
766 if (sis_verbose)
767 printf(" Software reset issued\n");
768 }
769 break;
770
771 case MEC_IOCR:
772 mec_iocr = data;
773 if (mec_iocr & 0xC0C0C0C0) mecparerror();
774 break;
775
776 case MEC_SSA1: /* 0x20 */
777 if (data & 0xFE000000) mecparerror();
778 mec_ssa[0] = data & 0x7fffff;
779 mec_wpr[0] = (data >> 23) & 0x03;
780 mem_accprot = mec_wpr[0] || mec_wpr[1];
781 if (sis_verbose && mec_wpr[0])
782 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
783 mec_ssa[0] << 2, mec_sea[0] << 2);
784 break;
785 case MEC_SEA1: /* 0x24 */
786 if (data & 0xFF800000) mecparerror();
787 mec_sea[0] = data & 0x7fffff;
788 break;
789 case MEC_SSA2: /* 0x28 */
790 if (data & 0xFE000000) mecparerror();
791 mec_ssa[1] = data & 0x7fffff;
792 mec_wpr[1] = (data >> 23) & 0x03;
793 mem_accprot = mec_wpr[0] || mec_wpr[1];
794 if (sis_verbose && mec_wpr[1])
795 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
796 mec_ssa[1] << 2, mec_sea[1] << 2);
797 break;
798 case MEC_SEA2: /* 0x2c */
799 if (data & 0xFF800000) mecparerror();
800 mec_sea[1] = data & 0x7fffff;
801 break;
802
803 case MEC_UARTA:
804 case MEC_UARTB:
805 if (data & 0xFFFFFF00) mecparerror();
806 case MEC_UART_CTRL:
807 if (data & 0xFF00FF00) mecparerror();
808 write_uart(addr, data);
809 break;
810
811 case MEC_GPT_RELOAD:
812 gpt_reload_set(data);
813 break;
814
815 case MEC_GPT_SCALER:
816 if (data & 0xFFFF0000) mecparerror();
817 gpt_scaler_set(data);
818 break;
819
820 case MEC_TIMER_CTRL:
821 if (data & 0xFFFFF0F0) mecparerror();
822 timer_ctrl(data);
823 break;
824
825 case MEC_RTC_RELOAD:
826 rtc_reload_set(data);
827 break;
828
829 case MEC_RTC_SCALER:
830 if (data & 0xFFFFFF00) mecparerror();
831 rtc_scaler_set(data);
832 break;
833
834 case MEC_SFSR: /* 0xA0 */
835 if (data & 0xFFFF0880) mecparerror();
836 mec_sfsr = 0x78;
837 break;
838
839 case MEC_ISR:
840 if (data & 0xFFFFE000) mecparerror();
841 mec_isr = data;
842 break;
843
844 case MEC_IMR: /* 0x4c */
845
846 if (data & 0xFFFF8001) mecparerror();
847 mec_imr = data & 0x7ffe;
848 chk_irq();
849 break;
850
851 case MEC_ICR: /* 0x50 */
852
853 if (data & 0xFFFF0001) mecparerror();
854 mec_ipr &= ~data & 0x0fffe;
855 chk_irq();
856 break;
857
858 case MEC_IFR: /* 0x54 */
859
860 if (mec_tcr & 0x080000) {
861 if (data & 0xFFFF0001) mecparerror();
862 mec_ifr = data & 0xfffe;
863 chk_irq();
864 }
865 break;
866 case SIM_LOAD:
867 fname[find++] = (char) data;
868 break;
869
870
871 case MEC_MEMCFG: /* 0x10 */
872 if (data & 0xC0E08000) mecparerror();
873 mec_memcfg = data;
874 decode_memcfg();
875 if (mec_memcfg & 0xc0e08000)
876 mecparerror();
877 break;
878
879 case MEC_WCR: /* 0x18 */
880 mec_wcr = data;
881 decode_wcr();
882 break;
883
884 case MEC_ERSR: /* 0xB0 */
885 if (mec_tcr & 0x100000)
886 if (data & 0xFFFFEFC0) mecparerror();
887 mec_ersr = data & 0x103f;
888 break;
889
890 case MEC_TCR: /* 0xD0 */
891 if (data & 0xFFE1FFC0) mecparerror();
892 mec_tcr = data & 0x1e003f;
893 break;
894
895 case MEC_WDOG: /* 0x60 */
896 wdog_scaler = (data >> 16) & 0x0ff;
897 wdog_counter = data & 0x0ffff;
898 wdog_rst_delay = data >> 24;
899 wdog_rston = 0;
900 if (wdog_status == stopped)
901 wdog_start();
902 wdog_status = enabled;
903 break;
904
905 case MEC_TRAPD: /* 0x64 */
906 if (wdog_status == init) {
907 wdog_status = disabled;
908 if (sis_verbose)
909 printf("Watchdog disabled\n");
910 }
911 break;
912
913 case MEC_PWDR:
914 if (mec_mcr & 1)
915 wait_for_irq();
916 break;
917
918 default:
919 set_sfsr(MEC_ACC, addr, 0xb, 0);
920 return 1;
921 break;
922 }
923 return MOK;
924 }
925
926
927 /* MEC UARTS */
928
929 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
930
931 void
932 init_stdio()
933 {
934 if (dumbio)
935 return; /* do nothing */
936 if (!ifd1)
937 tcsetattr(0, TCSANOW, &ioc1);
938 if (!ifd2)
939 tcsetattr(0, TCSANOW, &ioc2);
940 }
941
942 void
943 restore_stdio()
944 {
945 if (dumbio)
946 return; /* do nothing */
947 if (!ifd1)
948 tcsetattr(0, TCSANOW, &iocold1);
949 if (!ifd2)
950 tcsetattr(0, TCSANOW, &iocold2);
951 }
952
953 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
954 ( dumbio \
955 ? (0) /* no bytes read, no delay */ \
956 : read( _fd_, _buf_, _len_ ) )
957
958
959 static void
960 port_init()
961 {
962
963 if (uben) {
964 f2in = stdin;
965 f1in = NULL;
966 f2out = stdout;
967 f1out = NULL;
968 } else {
969 f1in = stdin;
970 f2in = NULL;
971 f1out = stdout;
972 f2out = NULL;
973 }
974 if (uart_dev1[0] != 0)
975 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
976 printf("Warning, couldn't open output device %s\n", uart_dev1);
977 } else {
978 if (sis_verbose)
979 printf("serial port A on %s\n", uart_dev1);
980 f1in = f1out = fdopen(fd1, "r+");
981 setbuf(f1out, NULL);
982 f1open = 1;
983 }
984 if (f1in) ifd1 = fileno(f1in);
985 if (ifd1 == 0) {
986 if (sis_verbose)
987 printf("serial port A on stdin/stdout\n");
988 if (!dumbio) {
989 tcgetattr(ifd1, &ioc1);
990 iocold1 = ioc1;
991 ioc1.c_lflag &= ~(ICANON | ECHO);
992 ioc1.c_cc[VMIN] = 0;
993 ioc1.c_cc[VTIME] = 0;
994 }
995 f1open = 1;
996 }
997
998 if (f1out) {
999 ofd1 = fileno(f1out);
1000 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1001 }
1002
1003 if (uart_dev2[0] != 0)
1004 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1005 printf("Warning, couldn't open output device %s\n", uart_dev2);
1006 } else {
1007 if (sis_verbose)
1008 printf("serial port B on %s\n", uart_dev2);
1009 f2in = f2out = fdopen(fd2, "r+");
1010 setbuf(f2out, NULL);
1011 f2open = 1;
1012 }
1013 if (f2in) ifd2 = fileno(f2in);
1014 if (ifd2 == 0) {
1015 if (sis_verbose)
1016 printf("serial port B on stdin/stdout\n");
1017 if (!dumbio) {
1018 tcgetattr(ifd2, &ioc2);
1019 iocold2 = ioc2;
1020 ioc2.c_lflag &= ~(ICANON | ECHO);
1021 ioc2.c_cc[VMIN] = 0;
1022 ioc2.c_cc[VTIME] = 0;
1023 }
1024 f2open = 1;
1025 }
1026
1027 if (f2out) {
1028 ofd2 = fileno(f2out);
1029 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1030 }
1031
1032 wnuma = wnumb = 0;
1033
1034 }
1035
1036 static uint32
1037 read_uart(addr)
1038 uint32 addr;
1039 {
1040
1041 unsigned tmp;
1042
1043 tmp = 0;
1044 switch (addr & 0xff) {
1045
1046 case 0xE0: /* UART 1 */
1047 #ifndef _WIN32
1048 #ifdef FAST_UART
1049
1050 if (aind < anum) {
1051 if ((aind + 1) < anum)
1052 mec_irq(4);
1053 return (0x700 | (uint32) aq[aind++]);
1054 } else {
1055 if (f1open) {
1056 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1057 }
1058 if (anum > 0) {
1059 aind = 0;
1060 if ((aind + 1) < anum)
1061 mec_irq(4);
1062 return (0x700 | (uint32) aq[aind++]);
1063 } else {
1064 return (0x600 | (uint32) aq[aind]);
1065 }
1066
1067 }
1068 #else
1069 tmp = uarta_data;
1070 uarta_data &= ~UART_DR;
1071 uart_stat_reg &= ~UARTA_DR;
1072 return tmp;
1073 #endif
1074 #else
1075 return 0;
1076 #endif
1077 break;
1078
1079 case 0xE4: /* UART 2 */
1080 #ifndef _WIN32
1081 #ifdef FAST_UART
1082 if (bind < bnum) {
1083 if ((bind + 1) < bnum)
1084 mec_irq(5);
1085 return (0x700 | (uint32) bq[bind++]);
1086 } else {
1087 if (f2open) {
1088 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1089 }
1090 if (bnum > 0) {
1091 bind = 0;
1092 if ((bind + 1) < bnum)
1093 mec_irq(5);
1094 return (0x700 | (uint32) bq[bind++]);
1095 } else {
1096 return (0x600 | (uint32) bq[bind]);
1097 }
1098
1099 }
1100 #else
1101 tmp = uartb_data;
1102 uartb_data &= ~UART_DR;
1103 uart_stat_reg &= ~UARTB_DR;
1104 return tmp;
1105 #endif
1106 #else
1107 return 0;
1108 #endif
1109 break;
1110
1111 case 0xE8: /* UART status register */
1112 #ifndef _WIN32
1113 #ifdef FAST_UART
1114
1115 Ucontrol = 0;
1116 if (aind < anum) {
1117 Ucontrol |= 0x00000001;
1118 } else {
1119 if (f1open) {
1120 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1121 }
1122 if (anum > 0) {
1123 Ucontrol |= 0x00000001;
1124 aind = 0;
1125 mec_irq(4);
1126 }
1127 }
1128 if (bind < bnum) {
1129 Ucontrol |= 0x00010000;
1130 } else {
1131 if (f2open) {
1132 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1133 }
1134 if (bnum > 0) {
1135 Ucontrol |= 0x00010000;
1136 bind = 0;
1137 mec_irq(5);
1138 }
1139 }
1140
1141 Ucontrol |= 0x00060006;
1142 return Ucontrol;
1143 #else
1144 return uart_stat_reg;
1145 #endif
1146 #else
1147 return 0x00060006;
1148 #endif
1149 break;
1150 default:
1151 if (sis_verbose)
1152 printf("Read from unimplemented MEC register (%x)\n", addr);
1153
1154 }
1155 return 0;
1156 }
1157
1158 static void
1159 write_uart(addr, data)
1160 uint32 addr;
1161 uint32 data;
1162 {
1163 unsigned char c;
1164
1165 c = (unsigned char) data;
1166 switch (addr & 0xff) {
1167
1168 case 0xE0: /* UART A */
1169 #ifdef FAST_UART
1170 if (f1open) {
1171 if (wnuma < UARTBUF)
1172 wbufa[wnuma++] = c;
1173 else {
1174 while (wnuma)
1175 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1176 wbufa[wnuma++] = c;
1177 }
1178 }
1179 mec_irq(4);
1180 #else
1181 if (uart_stat_reg & UARTA_SRE) {
1182 uarta_sreg = c;
1183 uart_stat_reg &= ~UARTA_SRE;
1184 event(uarta_tx, 0, UART_TX_TIME);
1185 } else {
1186 uarta_hreg = c;
1187 uart_stat_reg &= ~UARTA_HRE;
1188 }
1189 #endif
1190 break;
1191
1192 case 0xE4: /* UART B */
1193 #ifdef FAST_UART
1194 if (f2open) {
1195 if (wnumb < UARTBUF)
1196 wbufb[wnumb++] = c;
1197 else {
1198 while (wnumb)
1199 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1200 wbufb[wnumb++] = c;
1201 }
1202 }
1203 mec_irq(5);
1204 #else
1205 if (uart_stat_reg & UARTB_SRE) {
1206 uartb_sreg = c;
1207 uart_stat_reg &= ~UARTB_SRE;
1208 event(uartb_tx, 0, UART_TX_TIME);
1209 } else {
1210 uartb_hreg = c;
1211 uart_stat_reg &= ~UARTB_HRE;
1212 }
1213 #endif
1214 break;
1215 case 0xE8: /* UART status register */
1216 #ifndef FAST_UART
1217 if (data & UARTA_CLR) {
1218 uart_stat_reg &= 0xFFFF0000;
1219 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1220 }
1221 if (data & UARTB_CLR) {
1222 uart_stat_reg &= 0x0000FFFF;
1223 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1224 }
1225 #endif
1226 break;
1227 default:
1228 if (sis_verbose)
1229 printf("Write to unimplemented MEC register (%x)\n", addr);
1230
1231 }
1232 }
1233
1234 static void
1235 flush_uart()
1236 {
1237 while (wnuma && f1open)
1238 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1239 while (wnumb && f2open)
1240 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1241 }
1242
1243
1244
1245 static void
1246 uarta_tx()
1247 {
1248
1249 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1250 if (uart_stat_reg & UARTA_HRE) {
1251 uart_stat_reg |= UARTA_SRE;
1252 } else {
1253 uarta_sreg = uarta_hreg;
1254 uart_stat_reg |= UARTA_HRE;
1255 event(uarta_tx, 0, UART_TX_TIME);
1256 }
1257 mec_irq(4);
1258 }
1259
1260 static void
1261 uartb_tx()
1262 {
1263 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1264 if (uart_stat_reg & UARTB_HRE) {
1265 uart_stat_reg |= UARTB_SRE;
1266 } else {
1267 uartb_sreg = uartb_hreg;
1268 uart_stat_reg |= UARTB_HRE;
1269 event(uartb_tx, 0, UART_TX_TIME);
1270 }
1271 mec_irq(5);
1272 }
1273
1274 static void
1275 uart_rx(arg)
1276 caddr_t arg;
1277 {
1278 int32 rsize;
1279 char rxd;
1280
1281
1282 rsize = 0;
1283 if (f1open)
1284 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1285 if (rsize > 0) {
1286 uarta_data = UART_DR | rxd;
1287 if (uart_stat_reg & UARTA_HRE)
1288 uarta_data |= UART_THE;
1289 if (uart_stat_reg & UARTA_SRE)
1290 uarta_data |= UART_TSE;
1291 if (uart_stat_reg & UARTA_DR) {
1292 uart_stat_reg |= UARTA_OR;
1293 mec_irq(7); /* UART error interrupt */
1294 }
1295 uart_stat_reg |= UARTA_DR;
1296 mec_irq(4);
1297 }
1298 rsize = 0;
1299 if (f2open)
1300 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1301 if (rsize) {
1302 uartb_data = UART_DR | rxd;
1303 if (uart_stat_reg & UARTB_HRE)
1304 uartb_data |= UART_THE;
1305 if (uart_stat_reg & UARTB_SRE)
1306 uartb_data |= UART_TSE;
1307 if (uart_stat_reg & UARTB_DR) {
1308 uart_stat_reg |= UARTB_OR;
1309 mec_irq(7); /* UART error interrupt */
1310 }
1311 uart_stat_reg |= UARTB_DR;
1312 mec_irq(5);
1313 }
1314 event(uart_rx, 0, UART_RX_TIME);
1315 }
1316
1317 static void
1318 uart_intr(arg)
1319 caddr_t arg;
1320 {
1321 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1322 flush_uart(); /* Flush UART ports */
1323 event(uart_intr, 0, UART_FLUSH_TIME);
1324 }
1325
1326
1327 static void
1328 uart_irq_start()
1329 {
1330 #ifdef FAST_UART
1331 event(uart_intr, 0, UART_FLUSH_TIME);
1332 #else
1333 #ifndef _WIN32
1334 event(uart_rx, 0, UART_RX_TIME);
1335 #endif
1336 #endif
1337 }
1338
1339 /* Watch-dog */
1340
1341 static void
1342 wdog_intr(arg)
1343 caddr_t arg;
1344 {
1345 if (wdog_status == disabled) {
1346 wdog_status = stopped;
1347 } else {
1348
1349 if (wdog_counter) {
1350 wdog_counter--;
1351 event(wdog_intr, 0, wdog_scaler + 1);
1352 } else {
1353 if (wdog_rston) {
1354 printf("Watchdog reset!\n");
1355 sys_reset();
1356 mec_ersr = 0xC000;
1357 } else {
1358 mec_irq(15);
1359 wdog_rston = 1;
1360 wdog_counter = wdog_rst_delay;
1361 event(wdog_intr, 0, wdog_scaler + 1);
1362 }
1363 }
1364 }
1365 }
1366
1367 static void
1368 wdog_start()
1369 {
1370 event(wdog_intr, 0, wdog_scaler + 1);
1371 if (sis_verbose)
1372 printf("Watchdog started, scaler = %d, counter = %d\n",
1373 wdog_scaler, wdog_counter);
1374 }
1375
1376
1377 /* MEC timers */
1378
1379
1380 static void
1381 rtc_intr(arg)
1382 caddr_t arg;
1383 {
1384 if (rtc_counter == 0) {
1385
1386 mec_irq(13);
1387 if (rtc_cr)
1388 rtc_counter = rtc_reload;
1389 else
1390 rtc_se = 0;
1391 } else
1392 rtc_counter -= 1;
1393 if (rtc_se) {
1394 event(rtc_intr, 0, rtc_scaler + 1);
1395 rtc_scaler_start = now();
1396 rtc_enabled = 1;
1397 } else {
1398 if (sis_verbose)
1399 printf("RTC stopped\n\r");
1400 rtc_enabled = 0;
1401 }
1402 }
1403
1404 static void
1405 rtc_start()
1406 {
1407 if (sis_verbose)
1408 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1409 event(rtc_intr, 0, rtc_scaler + 1);
1410 rtc_scaler_start = now();
1411 rtc_enabled = 1;
1412 }
1413
1414 static uint32
1415 rtc_counter_read()
1416 {
1417 return rtc_counter;
1418 }
1419
1420 static void
1421 rtc_scaler_set(val)
1422 uint32 val;
1423 {
1424 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1425 }
1426
1427 static void
1428 rtc_reload_set(val)
1429 uint32 val;
1430 {
1431 rtc_reload = val;
1432 }
1433
1434 static void
1435 gpt_intr(arg)
1436 caddr_t arg;
1437 {
1438 if (gpt_counter == 0) {
1439 mec_irq(12);
1440 if (gpt_cr)
1441 gpt_counter = gpt_reload;
1442 else
1443 gpt_se = 0;
1444 } else
1445 gpt_counter -= 1;
1446 if (gpt_se) {
1447 event(gpt_intr, 0, gpt_scaler + 1);
1448 gpt_scaler_start = now();
1449 gpt_enabled = 1;
1450 } else {
1451 if (sis_verbose)
1452 printf("GPT stopped\n\r");
1453 gpt_enabled = 0;
1454 }
1455 }
1456
1457 static void
1458 gpt_start()
1459 {
1460 if (sis_verbose)
1461 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1462 event(gpt_intr, 0, gpt_scaler + 1);
1463 gpt_scaler_start = now();
1464 gpt_enabled = 1;
1465 }
1466
1467 static uint32
1468 gpt_counter_read()
1469 {
1470 return gpt_counter;
1471 }
1472
1473 static void
1474 gpt_scaler_set(val)
1475 uint32 val;
1476 {
1477 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1478 }
1479
1480 static void
1481 gpt_reload_set(val)
1482 uint32 val;
1483 {
1484 gpt_reload = val;
1485 }
1486
1487 static void
1488 timer_ctrl(val)
1489 uint32 val;
1490 {
1491
1492 rtc_cr = ((val & TCR_TCRCR) != 0);
1493 if (val & TCR_TCRCL) {
1494 rtc_counter = rtc_reload;
1495 }
1496 if (val & TCR_TCRSL) {
1497 }
1498 rtc_se = ((val & TCR_TCRSE) != 0);
1499 if (rtc_se && (rtc_enabled == 0))
1500 rtc_start();
1501
1502 gpt_cr = (val & TCR_GACR);
1503 if (val & TCR_GACL) {
1504 gpt_counter = gpt_reload;
1505 }
1506 if (val & TCR_GACL) {
1507 }
1508 gpt_se = (val & TCR_GASE) >> 2;
1509 if (gpt_se && (gpt_enabled == 0))
1510 gpt_start();
1511 }
1512
1513 /* Store data in host byte order. MEM points to the beginning of the
1514 emulated memory; WADDR contains the index the emulated memory,
1515 DATA points to words in host byte order to be stored. SZ contains log(2)
1516 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1517 2 (one word), or 3 (two words); WS should return the number of
1518 wait-states. */
1519
1520 static void
1521 store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
1522 int32 *ws)
1523 {
1524 switch (sz) {
1525 case 0:
1526 waddr ^= EBT;
1527 mem[waddr] = *data & 0x0ff;
1528 *ws = mem_ramw_ws + 3;
1529 break;
1530 case 1:
1531 #ifdef HOST_LITTLE_ENDIAN
1532 waddr ^= 2;
1533 #endif
1534 memcpy (&mem[waddr], data, 2);
1535 *ws = mem_ramw_ws + 3;
1536 break;
1537 case 2:
1538 memcpy (&mem[waddr], data, 4);
1539 *ws = mem_ramw_ws;
1540 break;
1541 case 3:
1542 memcpy (&mem[waddr], data, 8);
1543 *ws = 2 * mem_ramw_ws + STD_WS;
1544 break;
1545 }
1546 }
1547
1548
1549 /* Memory emulation */
1550
1551 int
1552 memory_iread (uint32 addr, uint32 *data, int32 *ws)
1553 {
1554 uint32 asi;
1555 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1556 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1557 *ws = mem_ramr_ws;
1558 return 0;
1559 } else if (addr < mem_romsz) {
1560 memcpy (data, &romb[addr & ~3], 4);
1561 *ws = mem_romr_ws;
1562 return 0;
1563 }
1564
1565 if (sis_verbose)
1566 printf ("Memory exception at %x (illegal address)\n", addr);
1567 if (sregs.psr & 0x080)
1568 asi = 9;
1569 else
1570 asi = 8;
1571 set_sfsr (UIMP_ACC, addr, asi, 1);
1572 *ws = MEM_EX_WS;
1573 return 1;
1574 }
1575
1576 int
1577 memory_read(asi, addr, data, sz, ws)
1578 int32 asi;
1579 uint32 addr;
1580 uint32 *data;
1581 int32 sz;
1582 int32 *ws;
1583 {
1584 int32 mexc;
1585
1586 #ifdef ERRINJ
1587 if (errmec) {
1588 if (sis_verbose)
1589 printf("Inserted MEC error %d\n",errmec);
1590 set_sfsr(errmec, addr, asi, 1);
1591 if (errmec == 5) mecparerror();
1592 if (errmec == 6) iucomperr();
1593 errmec = 0;
1594 return 1;
1595 }
1596 #endif
1597
1598 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1599 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1600 *ws = mem_ramr_ws;
1601 return 0;
1602 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1603 mexc = mec_read(addr, asi, data);
1604 if (mexc) {
1605 set_sfsr(MEC_ACC, addr, asi, 1);
1606 *ws = MEM_EX_WS;
1607 } else {
1608 *ws = 0;
1609 }
1610 return mexc;
1611
1612 #ifdef ERA
1613
1614 } else if (era) {
1615 if ((addr < 0x100000) ||
1616 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1617 memcpy (data, &romb[addr & ROM_MASK & ~3], 4);
1618 *ws = 4;
1619 return 0;
1620 } else if ((addr >= 0x10000000) &&
1621 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1622 (mec_iocr & 0x10)) {
1623 *data = erareg;
1624 return 0;
1625 }
1626
1627 } else if (addr < mem_romsz) {
1628 memcpy (data, &romb[addr & ~3], 4);
1629 *ws = mem_romr_ws;
1630 return 0;
1631 #else
1632 } else if (addr < mem_romsz) {
1633 memcpy (data, &romb[addr & ~3], 4);
1634 *ws = mem_romr_ws;
1635 return 0;
1636 #endif
1637
1638 }
1639
1640 if (sis_verbose)
1641 printf ("Memory exception at %x (illegal address)\n", addr);
1642 set_sfsr(UIMP_ACC, addr, asi, 1);
1643 *ws = MEM_EX_WS;
1644 return 1;
1645 }
1646
1647 int
1648 memory_write(asi, addr, data, sz, ws)
1649 int32 asi;
1650 uint32 addr;
1651 uint32 *data;
1652 int32 sz;
1653 int32 *ws;
1654 {
1655 uint32 byte_addr;
1656 uint32 byte_mask;
1657 uint32 waddr;
1658 uint32 *ram;
1659 int32 mexc;
1660 int i;
1661 int wphit[2];
1662
1663 #ifdef ERRINJ
1664 if (errmec) {
1665 if (sis_verbose)
1666 printf("Inserted MEC error %d\n",errmec);
1667 set_sfsr(errmec, addr, asi, 0);
1668 if (errmec == 5) mecparerror();
1669 if (errmec == 6) iucomperr();
1670 errmec = 0;
1671 return 1;
1672 }
1673 #endif
1674
1675 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1676 if (mem_accprot) {
1677
1678 waddr = (addr & 0x7fffff) >> 2;
1679 for (i = 0; i < 2; i++)
1680 wphit[i] =
1681 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1682 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1683 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1684
1685 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1686 ((!mem_blockprot) &&
1687 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1688 )) {
1689 if (sis_verbose)
1690 printf("Memory access protection error at 0x%08x\n", addr);
1691 set_sfsr(PROT_EXC, addr, asi, 0);
1692 *ws = MEM_EX_WS;
1693 return 1;
1694 }
1695 }
1696 waddr = addr & mem_rammask;
1697 store_bytes (ramb, waddr, data, sz, ws);
1698 return 0;
1699 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1700 if ((sz != 2) || (asi != 0xb)) {
1701 set_sfsr(MEC_ACC, addr, asi, 0);
1702 *ws = MEM_EX_WS;
1703 return 1;
1704 }
1705 mexc = mec_write(addr, *data);
1706 if (mexc) {
1707 set_sfsr(MEC_ACC, addr, asi, 0);
1708 *ws = MEM_EX_WS;
1709 } else {
1710 *ws = 0;
1711 }
1712 return mexc;
1713
1714 #ifdef ERA
1715
1716 } else if (era) {
1717 if ((erareg & 2) &&
1718 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1719 addr &= ROM_MASK;
1720 *ws = sz == 3 ? 8 : 4;
1721 store_bytes (romb, addr, data, sz, ws);
1722 return 0;
1723 } else if ((addr >= 0x10000000) &&
1724 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1725 (mec_iocr & 0x10)) {
1726 erareg = *data & 0x0e;
1727 return 0;
1728 }
1729
1730 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1731 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1732 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1733
1734 *ws = mem_romw_ws + 1;
1735 if (sz == 3)
1736 *ws += mem_romw_ws + STD_WS;
1737 store_bytes (romb, addr, data, sz, ws);
1738 return 0;
1739
1740 #else
1741 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1742 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1743 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1744
1745 *ws = mem_romw_ws + 1;
1746 if (sz == 3)
1747 *ws += mem_romw_ws + STD_WS;
1748 store_bytes (romb, addr, data, sz, ws);
1749 return 0;
1750
1751 #endif
1752
1753 }
1754
1755 *ws = MEM_EX_WS;
1756 set_sfsr(UIMP_ACC, addr, asi, 0);
1757 return 1;
1758 }
1759
1760 static unsigned char *
1761 get_mem_ptr(addr, size)
1762 uint32 addr;
1763 uint32 size;
1764 {
1765 if ((addr + size) < ROM_SZ) {
1766 return &romb[addr];
1767 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1768 return &ramb[addr & mem_rammask];
1769 }
1770
1771 #ifdef ERA
1772 else if ((era) && ((addr <0x100000) ||
1773 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1774 return &romb[addr & ROM_MASK];
1775 }
1776 #endif
1777
1778 return (char *) -1;
1779 }
1780
1781 int
1782 sis_memory_write(addr, data, length)
1783 uint32 addr;
1784 const unsigned char *data;
1785 uint32 length;
1786 {
1787 char *mem;
1788
1789 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1790 return 0;
1791
1792 memcpy(mem, data, length);
1793 return length;
1794 }
1795
1796 int
1797 sis_memory_read(addr, data, length)
1798 uint32 addr;
1799 char *data;
1800 uint32 length;
1801 {
1802 char *mem;
1803
1804 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1805 return 0;
1806
1807 memcpy(data, mem, length);
1808 return length;
1809 }
1810
1811 extern struct pstate sregs;
1812
1813 void
1814 boot_init (void)
1815 {
1816 mec_write(MEC_WCR, 0); /* zero waitstates */
1817 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1818 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1819 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1820 sregs.wim = 2;
1821 sregs.psr = 0x110010e0;
1822 sregs.r[30] = RAM_END;
1823 sregs.r[14] = sregs.r[30] - 96 * 4;
1824 mec_mcr |= 1; /* power-down enabled */
1825 }
GDB Binutils - Deliverables
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