2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 675
19 * Mass Ave, Cambridge, MA 02139, USA.
23 /* The control space devices */
26 #include <sys/types.h>
30 #include <sys/fcntl.h>
35 #include "sim-config.h"
38 extern int32 sis_verbose
;
39 extern int32 sparclite
, sparclite_board
;
40 extern int rom8
,wrp
,uben
;
41 extern char uart_dev1
[], uart_dev2
[];
43 int dumbio
= 0; /* normal, smart, terminal oriented IO by default */
46 #define MEC_START 0x01f80000
47 #define MEC_END 0x01f80100
49 /* Memory exception waitstates */
52 /* ERC32 always adds one waitstate during RAM std */
59 /* The target's byte order is big-endian by default until we load a
60 little-endian program. */
62 int current_target_byte_order
= BIG_ENDIAN
;
64 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
67 /* MEC register addresses */
71 #define MEC_PWDR 0x008
72 #define MEC_MEMCFG 0x010
73 #define MEC_IOCR 0x014
76 #define MEC_MAR0 0x020
77 #define MEC_MAR1 0x024
79 #define MEC_SSA1 0x020
80 #define MEC_SEA1 0x024
81 #define MEC_SSA2 0x028
82 #define MEC_SEA2 0x02C
88 #define MEC_WDOG 0x060
89 #define MEC_TRAPD 0x064
90 #define MEC_RTC_COUNTER 0x080
91 #define MEC_RTC_RELOAD 0x080
92 #define MEC_RTC_SCALER 0x084
93 #define MEC_GPT_COUNTER 0x088
94 #define MEC_GPT_RELOAD 0x088
95 #define MEC_GPT_SCALER 0x08C
96 #define MEC_TIMER_CTRL 0x098
97 #define MEC_SFSR 0x0A0
98 #define MEC_FFAR 0x0A4
99 #define MEC_ERSR 0x0B0
100 #define MEC_DBG 0x0C0
101 #define MEC_TCR 0x0D0
103 #define MEC_BRK 0x0C4
104 #define MEC_WPR 0x0C8
106 #define MEC_UARTA 0x0E0
107 #define MEC_UARTB 0x0E4
108 #define MEC_UART_CTRL 0x0E8
109 #define SIM_LOAD 0x0F0
111 /* Memory exception causes */
115 #define WATCH_EXC 0xa
116 #define BREAK_EXC 0xb
118 /* Size of UART buffers (bytes) */
121 /* Number of simulator ticks between flushing the UARTS. */
122 /* For good performance, keep above 1000 */
123 #define UART_FLUSH_TIME 3000
125 /* MEC timer control register bits */
130 #define TCR_TCRCR 0x100
131 #define TCR_TCRCL 0x200
132 #define TCR_TCRSE 0x400
133 #define TCR_TCRSL 0x800
135 /* New uart defines */
136 #define UART_TX_TIME 1000
137 #define UART_RX_TIME 1000
139 #define UARTA_SRE 0x2
140 #define UARTA_HRE 0x4
141 #define UARTA_OR 0x40
142 #define UARTA_CLR 0x80
143 #define UARTB_DR 0x10000
144 #define UARTB_SRE 0x20000
145 #define UARTB_HRE 0x40000
146 #define UARTB_OR 0x400000
147 #define UARTB_CLR 0x800000
149 #define UART_DR 0x100
150 #define UART_TSE 0x200
151 #define UART_THE 0x400
155 static char fname
[256];
156 static int32 find
= 0;
157 static uint32 mec_ssa
[2]; /* Write protection start address */
158 static uint32 mec_sea
[2]; /* Write protection end address */
159 static uint32 mec_wpr
[2]; /* Write protection control fields */
160 static uint32 mec_sfsr
;
161 static uint32 mec_ffar
;
162 static uint32 mec_ipr
;
163 static uint32 mec_imr
;
164 static uint32 mec_isr
;
165 static uint32 mec_icr
;
166 static uint32 mec_ifr
;
167 static uint32 mec_mcr
; /* MEC control register */
168 static uint32 mec_memcfg
; /* Memory control register */
169 static uint32 mec_wcr
; /* MEC waitstate register */
170 static uint32 mec_iocr
; /* MEC IO control register */
171 static uint32 posted_irq
;
172 static uint32 mec_ersr
; /* MEC error and status register */
173 static uint32 mec_tcr
; /* MEC test comtrol register */
175 static uint32 rtc_counter
;
176 static uint32 rtc_reload
;
177 static uint32 rtc_scaler
;
178 static uint32 rtc_scaler_start
;
179 static uint32 rtc_enabled
;
180 static uint32 rtc_cr
;
181 static uint32 rtc_se
;
183 static uint32 gpt_counter
;
184 static uint32 gpt_reload
;
185 static uint32 gpt_scaler
;
186 static uint32 gpt_scaler_start
;
187 static uint32 gpt_enabled
;
188 static uint32 gpt_cr
;
189 static uint32 gpt_se
;
191 static uint32 wdog_scaler
;
192 static uint32 wdog_counter
;
193 static uint32 wdog_rst_delay
;
194 static uint32 wdog_rston
;
197 init
, disabled
, enabled
, stopped
200 static enum wdog_type wdog_status
;
203 /* ROM size 1024 Kbyte */
204 #define ROM_SZ 0x100000
205 #define ROM_MASK 0x0fffff
207 /* RAM size 4 Mbyte */
208 #define RAM_START 0x02000000
209 #define RAM_END 0x02400000
210 #define RAM_MASK 0x003fffff
212 /* SPARClite boards all seem to have RAM at the same place. */
213 #define RAM_START_SLITE 0x40000000
214 #define RAM_END_SLITE 0x40400000
215 #define RAM_MASK_SLITE 0x003fffff
217 /* Memory support variables */
219 static uint32 mem_ramr_ws
; /* RAM read waitstates */
220 static uint32 mem_ramw_ws
; /* RAM write waitstates */
221 static uint32 mem_romr_ws
; /* ROM read waitstates */
222 static uint32 mem_romw_ws
; /* ROM write waitstates */
223 static uint32 mem_ramstart
; /* RAM start */
224 static uint32 mem_ramend
; /* RAM end */
225 static uint32 mem_rammask
; /* RAM address mask */
226 static uint32 mem_ramsz
; /* RAM size */
227 static uint32 mem_romsz
; /* ROM size */
228 static uint32 mem_accprot
; /* RAM write protection enabled */
229 static uint32 mem_blockprot
; /* RAM block write protection enabled */
231 static unsigned char romb
[ROM_SZ
];
232 static unsigned char ramb
[RAM_END
- RAM_START
];
235 /* UART support variables */
237 static int32 fd1
, fd2
; /* file descriptor for input file */
238 static int32 Ucontrol
; /* UART status register */
239 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
240 static int32 anum
, aind
= 0;
241 static int32 bnum
, bind
= 0;
242 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
243 static unsigned wnuma
;
244 static unsigned wnumb
;
245 static FILE *f1in
, *f1out
, *f2in
, *f2out
;
246 static struct termios ioc1
, ioc2
, iocold1
, iocold2
;
247 static int f1open
= 0, f2open
= 0;
249 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
250 static uint32 uart_stat_reg
;
251 static uint32 uarta_data
, uartb_data
;
258 /* Forward declarations */
260 static void decode_ersr
PARAMS ((void));
262 static void iucomperr
PARAMS ((void));
264 static void mecparerror
PARAMS ((void));
265 static void decode_memcfg
PARAMS ((void));
266 static void decode_wcr
PARAMS ((void));
267 static void decode_mcr
PARAMS ((void));
268 static void close_port
PARAMS ((void));
269 static void mec_reset
PARAMS ((void));
270 static void mec_intack
PARAMS ((int32 level
));
271 static void chk_irq
PARAMS ((void));
272 static void mec_irq
PARAMS ((int32 level
));
273 static void set_sfsr
PARAMS ((uint32 fault
, uint32 addr
,
274 uint32 asi
, uint32 read
));
275 static int32 mec_read
PARAMS ((uint32 addr
, uint32 asi
, uint32
*data
));
276 static int mec_write
PARAMS ((uint32 addr
, uint32 data
));
277 static void port_init
PARAMS ((void));
278 static uint32 read_uart
PARAMS ((uint32 addr
));
279 static void write_uart
PARAMS ((uint32 addr
, uint32 data
));
280 static void flush_uart
PARAMS ((void));
281 static void uarta_tx
PARAMS ((void));
282 static void uartb_tx
PARAMS ((void));
283 static void uart_rx
PARAMS ((caddr_t arg
));
284 static void uart_intr
PARAMS ((caddr_t arg
));
285 static void uart_irq_start
PARAMS ((void));
286 static void wdog_intr
PARAMS ((caddr_t arg
));
287 static void wdog_start
PARAMS ((void));
288 static void rtc_intr
PARAMS ((caddr_t arg
));
289 static void rtc_start
PARAMS ((void));
290 static uint32 rtc_counter_read
PARAMS ((void));
291 static void rtc_scaler_set
PARAMS ((uint32 val
));
292 static void rtc_reload_set
PARAMS ((uint32 val
));
293 static void gpt_intr
PARAMS ((caddr_t arg
));
294 static void gpt_start
PARAMS ((void));
295 static uint32 gpt_counter_read
PARAMS ((void));
296 static void gpt_scaler_set
PARAMS ((uint32 val
));
297 static void gpt_reload_set
PARAMS ((uint32 val
));
298 static void timer_ctrl
PARAMS ((uint32 val
));
299 static unsigned char *
300 get_mem_ptr
PARAMS ((uint32 addr
, uint32 size
));
302 static void fetch_bytes
PARAMS ((int asi
, unsigned char *mem
,
303 uint32
*data
, int sz
));
305 static void store_bytes
PARAMS ((unsigned char *mem
, uint32
*data
, int sz
));
318 /* Power-on reset init */
331 if (mec_ersr
& 0x01) {
332 if (!(mec_mcr
& 0x20)) {
333 if (mec_mcr
& 0x40) {
337 printf("Error manager reset - IU in error mode\n");
342 printf("Error manager halt - IU in error mode\n");
347 if (mec_ersr
& 0x04) {
348 if (!(mec_mcr
& 0x200)) {
349 if (mec_mcr
& 0x400) {
353 printf("Error manager reset - IU comparison error\n");
358 printf("Error manager halt - IU comparison error\n");
363 if (mec_ersr
& 0x20) {
364 if (!(mec_mcr
& 0x2000)) {
365 if (mec_mcr
& 0x4000) {
369 printf("Error manager reset - MEC hardware error\n");
374 printf("Error manager halt - MEC hardware error\n");
398 /* IU error mode manager */
410 /* Check memory settings */
415 if (rom8
) mec_memcfg
&= ~0x20000;
416 else mec_memcfg
|= 0x20000;
418 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
419 mem_romsz
= (128 * 1024) << ((mec_memcfg
>> 18) & 7);
421 if (sparclite_board
) {
422 mem_ramstart
= RAM_START_SLITE
;
423 mem_ramend
= RAM_END_SLITE
;
424 mem_rammask
= RAM_MASK_SLITE
;
427 mem_ramstart
= RAM_START
;
428 mem_ramend
= RAM_END
;
429 mem_rammask
= RAM_MASK
;
432 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
433 mem_ramstart
, mem_ramsz
>> 10, mem_romsz
>> 10);
439 mem_ramr_ws
= mec_wcr
& 3;
440 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
441 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
443 if (mem_romr_ws
> 0 ) mem_romr_ws
--;
444 mem_romr_ws
= 5 + (4*mem_romr_ws
);
446 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
448 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
449 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
455 mem_accprot
= (mec_wpr
[0] | mec_wpr
[1]);
456 mem_blockprot
= (mec_mcr
>> 3) & 1;
457 if (sis_verbose
&& mem_accprot
)
458 printf("Memory block write protection enabled\n");
459 if (mec_mcr
& 0x08000) {
463 if (sis_verbose
&& (mec_mcr
& 2))
464 printf("Software reset enabled\n");
465 if (sis_verbose
&& (mec_mcr
& 1))
466 printf("Power-down mode enabled\n");
469 /* Flush ports when simulator stops */
480 sim_stop(SIM_DESC sd
)
489 if (f1open
&& f1in
!= stdin
)
491 if (f2open
&& f2in
!= stdin
)
507 for (i
= 0; i
< 2; i
++)
508 mec_ssa
[i
] = mec_sea
[i
] = mec_wpr
[i
] = 0;
509 mec_mcr
= 0x01350014;
518 mec_memcfg
= 0x10000;
520 mec_ersr
= 0; /* MEC error and status register */
521 mec_tcr
= 0; /* MEC test comtrol register */
529 anum
= aind
= bnum
= bind
= 0;
531 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
532 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
534 rtc_counter
= 0xffffffff;
535 rtc_reload
= 0xffffffff;
541 gpt_counter
= 0xffffffff;
542 gpt_reload
= 0xffffffff;
549 wdog_rst_delay
= 255;
550 wdog_counter
= 0xffff;
569 printf("interrupt %d acknowledged\n", level
);
570 irq_test
= mec_tcr
& 0x80000;
571 if ((irq_test
) && (mec_ifr
& (1 << level
)))
572 mec_ifr
&= ~(1 << level
);
574 mec_ipr
&= ~(1 << level
);
586 if (mec_tcr
& 0x80000) itmp
= mec_ifr
;
588 itmp
= ((mec_ipr
| itmp
) & ~mec_imr
) & 0x0fffe;
591 for (i
= 15; i
> 0; i
--) {
592 if (((itmp
>> i
) & 1) != 0) {
593 if ((sis_verbose
) && (i
> old_irl
))
594 printf("IU irl: %d\n", i
);
596 set_int(i
, mec_intack
, i
);
607 mec_ipr
|= (1 << level
);
612 set_sfsr(fault
, addr
, asi
, read
)
618 if ((asi
== 0xa) || (asi
== 0xb)) {
620 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
621 mec_sfsr
|= ((mec_sfsr
& 1) ^ 1) | (mec_sfsr
& 1);
634 mec_read(addr
, asi
, data
)
640 switch (addr
& 0x0ff) {
642 case MEC_MCR
: /* 0x00 */
646 case MEC_MEMCFG
: /* 0x10 */
651 *data
= mec_iocr
; /* 0x14 */
654 case MEC_SSA1
: /* 0x20 */
655 *data
= mec_ssa
[0] | (mec_wpr
[0] << 23);
657 case MEC_SEA1
: /* 0x24 */
660 case MEC_SSA2
: /* 0x28 */
661 *data
= mec_ssa
[1] | (mec_wpr
[1] << 23);
663 case MEC_SEA2
: /* 0x2c */
667 case MEC_ISR
: /* 0x44 */
671 case MEC_IPR
: /* 0x48 */
675 case MEC_IMR
: /* 0x4c */
679 case MEC_IFR
: /* 0x54 */
683 case MEC_RTC_COUNTER
: /* 0x80 */
684 *data
= rtc_counter_read();
686 case MEC_RTC_SCALER
: /* 0x84 */
688 *data
= rtc_scaler
- (now() - rtc_scaler_start
);
693 case MEC_GPT_COUNTER
: /* 0x88 */
694 *data
= gpt_counter_read();
697 case MEC_GPT_SCALER
: /* 0x8c */
699 *data
= gpt_scaler
- (now() - gpt_scaler_start
);
705 case MEC_SFSR
: /* 0xA0 */
709 case MEC_FFAR
: /* 0xA4 */
716 strcpy(fname
, "simload");
717 find
= bfd_load(fname
);
725 case MEC_ERSR
: /* 0xB0 */
729 case MEC_TCR
: /* 0xD0 */
733 case MEC_UARTA
: /* 0xE0 */
734 case MEC_UARTB
: /* 0xE4 */
736 set_sfsr(MEC_ACC
, addr
, asi
, 1);
739 *data
= read_uart(addr
);
742 case MEC_UART_CTRL
: /* 0xE8 */
744 *data
= read_uart(addr
);
748 set_sfsr(MEC_ACC
, addr
, asi
, 1);
756 mec_write(addr
, data
)
761 printf("MEC write a: %08x, d: %08x\n",addr
,data
);
762 switch (addr
& 0x0ff) {
767 if (mec_mcr
& 0x08000) mecparerror();
775 printf(" Software reset issued\n");
781 if (mec_iocr
& 0xC0C0C0C0) mecparerror();
784 case MEC_SSA1
: /* 0x20 */
785 if (data
& 0xFE000000) mecparerror();
786 mec_ssa
[0] = data
& 0x7fffff;
787 mec_wpr
[0] = (data
>> 23) & 0x03;
788 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
789 if (sis_verbose
&& mec_wpr
[0])
790 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
791 mec_ssa
[0] << 2, mec_sea
[0] << 2);
793 case MEC_SEA1
: /* 0x24 */
794 if (data
& 0xFF800000) mecparerror();
795 mec_sea
[0] = data
& 0x7fffff;
797 case MEC_SSA2
: /* 0x28 */
798 if (data
& 0xFE000000) mecparerror();
799 mec_ssa
[1] = data
& 0x7fffff;
800 mec_wpr
[1] = (data
>> 23) & 0x03;
801 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
802 if (sis_verbose
&& mec_wpr
[1])
803 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
804 mec_ssa
[1] << 2, mec_sea
[1] << 2);
806 case MEC_SEA2
: /* 0x2c */
807 if (data
& 0xFF800000) mecparerror();
808 mec_sea
[1] = data
& 0x7fffff;
813 if (data
& 0xFFFFFF00) mecparerror();
815 if (data
& 0xFF00FF00) mecparerror();
816 write_uart(addr
, data
);
820 gpt_reload_set(data
);
824 if (data
& 0xFFFF0000) mecparerror();
825 gpt_scaler_set(data
);
829 if (data
& 0xFFFFF0F0) mecparerror();
834 rtc_reload_set(data
);
838 if (data
& 0xFFFFFF00) mecparerror();
839 rtc_scaler_set(data
);
842 case MEC_SFSR
: /* 0xA0 */
843 if (data
& 0xFFFF0880) mecparerror();
848 if (data
& 0xFFFFE000) mecparerror();
852 case MEC_IMR
: /* 0x4c */
854 if (data
& 0xFFFF8001) mecparerror();
855 mec_imr
= data
& 0x7ffe;
859 case MEC_ICR
: /* 0x50 */
861 if (data
& 0xFFFF0001) mecparerror();
862 mec_ipr
&= ~data
& 0x0fffe;
866 case MEC_IFR
: /* 0x54 */
868 if (mec_tcr
& 0x080000) {
869 if (data
& 0xFFFF0001) mecparerror();
870 mec_ifr
= data
& 0xfffe;
875 fname
[find
++] = (char) data
;
879 case MEC_MEMCFG
: /* 0x10 */
880 if (data
& 0xC0E08000) mecparerror();
883 if (mec_memcfg
& 0xc0e08000)
887 case MEC_WCR
: /* 0x18 */
892 case MEC_ERSR
: /* 0xB0 */
893 if (mec_tcr
& 0x100000)
894 if (data
& 0xFFFFEFC0) mecparerror();
895 mec_ersr
= data
& 0x103f;
898 case MEC_TCR
: /* 0xD0 */
899 if (data
& 0xFFE1FFC0) mecparerror();
900 mec_tcr
= data
& 0x1e003f;
903 case MEC_WDOG
: /* 0x60 */
904 wdog_scaler
= (data
>> 16) & 0x0ff;
905 wdog_counter
= data
& 0x0ffff;
906 wdog_rst_delay
= data
>> 24;
908 if (wdog_status
== stopped
)
910 wdog_status
= enabled
;
913 case MEC_TRAPD
: /* 0x64 */
914 if (wdog_status
== init
) {
915 wdog_status
= disabled
;
917 printf("Watchdog disabled\n");
927 set_sfsr(MEC_ACC
, addr
, 0xb, 0);
937 static int ifd1
= -1, ifd2
= -1, ofd1
= -1, ofd2
= -1;
943 return; /* do nothing */
945 tcsetattr(0, TCSANOW
, &ioc1
);
947 tcsetattr(0, TCSANOW
, &ioc2
);
954 return; /* do nothing */
956 tcsetattr(0, TCSANOW
, &iocold1
);
958 tcsetattr(0, TCSANOW
, &iocold2
);
961 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
963 ? (0) /* no bytes read, no delay */ \
964 : read( _fd_, _buf_, _len_ ) )
982 if (uart_dev1
[0] != 0)
983 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NONBLOCK
)) < 0) {
984 printf("Warning, couldn't open output device %s\n", uart_dev1
);
987 printf("serial port A on %s\n", uart_dev1
);
988 f1in
= f1out
= fdopen(fd1
, "r+");
992 if (f1in
) ifd1
= fileno(f1in
);
995 printf("serial port A on stdin/stdout\n");
997 tcgetattr(ifd1
, &ioc1
);
999 ioc1
.c_lflag
&= ~(ICANON
| ECHO
);
1000 ioc1
.c_cc
[VMIN
] = 0;
1001 ioc1
.c_cc
[VTIME
] = 0;
1007 ofd1
= fileno(f1out
);
1008 if (!dumbio
&& ofd1
== 1) setbuf(f1out
, NULL
);
1011 if (uart_dev2
[0] != 0)
1012 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NONBLOCK
)) < 0) {
1013 printf("Warning, couldn't open output device %s\n", uart_dev2
);
1016 printf("serial port B on %s\n", uart_dev2
);
1017 f2in
= f2out
= fdopen(fd2
, "r+");
1018 setbuf(f2out
, NULL
);
1021 if (f2in
) ifd2
= fileno(f2in
);
1024 printf("serial port B on stdin/stdout\n");
1026 tcgetattr(ifd2
, &ioc2
);
1028 ioc2
.c_lflag
&= ~(ICANON
| ECHO
);
1029 ioc2
.c_cc
[VMIN
] = 0;
1030 ioc2
.c_cc
[VTIME
] = 0;
1036 ofd2
= fileno(f2out
);
1037 if (!dumbio
&& ofd2
== 1) setbuf(f2out
, NULL
);
1052 switch (addr
& 0xff) {
1054 case 0xE0: /* UART 1 */
1059 if ((aind
+ 1) < anum
)
1061 return (0x700 | (uint32
) aq
[aind
++]);
1064 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1068 if ((aind
+ 1) < anum
)
1070 return (0x700 | (uint32
) aq
[aind
++]);
1072 return (0x600 | (uint32
) aq
[aind
]);
1078 uarta_data
&= ~UART_DR
;
1079 uart_stat_reg
&= ~UARTA_DR
;
1087 case 0xE4: /* UART 2 */
1091 if ((bind
+ 1) < bnum
)
1093 return (0x700 | (uint32
) bq
[bind
++]);
1096 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1100 if ((bind
+ 1) < bnum
)
1102 return (0x700 | (uint32
) bq
[bind
++]);
1104 return (0x600 | (uint32
) bq
[bind
]);
1110 uartb_data
&= ~UART_DR
;
1111 uart_stat_reg
&= ~UARTB_DR
;
1119 case 0xE8: /* UART status register */
1125 Ucontrol
|= 0x00000001;
1128 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1131 Ucontrol
|= 0x00000001;
1137 Ucontrol
|= 0x00010000;
1140 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1143 Ucontrol
|= 0x00010000;
1149 Ucontrol
|= 0x00060006;
1152 return (uart_stat_reg
);
1160 printf("Read from unimplemented MEC register (%x)\n", addr
);
1167 write_uart(addr
, data
)
1173 c
= (unsigned char) data
;
1174 switch (addr
& 0xff) {
1176 case 0xE0: /* UART A */
1179 if (wnuma
< UARTBUF
)
1183 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1189 if (uart_stat_reg
& UARTA_SRE
) {
1191 uart_stat_reg
&= ~UARTA_SRE
;
1192 event(uarta_tx
, 0, UART_TX_TIME
);
1195 uart_stat_reg
&= ~UARTA_HRE
;
1200 case 0xE4: /* UART B */
1203 if (wnumb
< UARTBUF
)
1207 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1213 if (uart_stat_reg
& UARTB_SRE
) {
1215 uart_stat_reg
&= ~UARTB_SRE
;
1216 event(uartb_tx
, 0, UART_TX_TIME
);
1219 uart_stat_reg
&= ~UARTB_HRE
;
1223 case 0xE8: /* UART status register */
1225 if (data
& UARTA_CLR
) {
1226 uart_stat_reg
&= 0xFFFF0000;
1227 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
1229 if (data
& UARTB_CLR
) {
1230 uart_stat_reg
&= 0x0000FFFF;
1231 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
1237 printf("Write to unimplemented MEC register (%x)\n", addr
);
1245 while (wnuma
&& f1open
)
1246 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1247 while (wnumb
&& f2open
)
1248 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1257 while (f1open
&& fwrite(&uarta_sreg
, 1, 1, f1out
) != 1);
1258 if (uart_stat_reg
& UARTA_HRE
) {
1259 uart_stat_reg
|= UARTA_SRE
;
1261 uarta_sreg
= uarta_hreg
;
1262 uart_stat_reg
|= UARTA_HRE
;
1263 event(uarta_tx
, 0, UART_TX_TIME
);
1271 while (f2open
&& fwrite(&uartb_sreg
, 1, 1, f2out
) != 1);
1272 if (uart_stat_reg
& UARTB_HRE
) {
1273 uart_stat_reg
|= UARTB_SRE
;
1275 uartb_sreg
= uartb_hreg
;
1276 uart_stat_reg
|= UARTB_HRE
;
1277 event(uartb_tx
, 0, UART_TX_TIME
);
1292 rsize
= DO_STDIO_READ(ifd1
, &rxd
, 1);
1294 uarta_data
= UART_DR
| rxd
;
1295 if (uart_stat_reg
& UARTA_HRE
)
1296 uarta_data
|= UART_THE
;
1297 if (uart_stat_reg
& UARTA_SRE
)
1298 uarta_data
|= UART_TSE
;
1299 if (uart_stat_reg
& UARTA_DR
) {
1300 uart_stat_reg
|= UARTA_OR
;
1301 mec_irq(7); /* UART error interrupt */
1303 uart_stat_reg
|= UARTA_DR
;
1308 rsize
= DO_STDIO_READ(ifd2
, &rxd
, 1);
1310 uartb_data
= UART_DR
| rxd
;
1311 if (uart_stat_reg
& UARTB_HRE
)
1312 uartb_data
|= UART_THE
;
1313 if (uart_stat_reg
& UARTB_SRE
)
1314 uartb_data
|= UART_TSE
;
1315 if (uart_stat_reg
& UARTB_DR
) {
1316 uart_stat_reg
|= UARTB_OR
;
1317 mec_irq(7); /* UART error interrupt */
1319 uart_stat_reg
|= UARTB_DR
;
1322 event(uart_rx
, 0, UART_RX_TIME
);
1329 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1330 flush_uart(); /* Flush UART ports */
1331 event(uart_intr
, 0, UART_FLUSH_TIME
);
1339 event(uart_intr
, 0, UART_FLUSH_TIME
);
1342 event(uart_rx
, 0, UART_RX_TIME
);
1353 if (wdog_status
== disabled
) {
1354 wdog_status
= stopped
;
1359 event(wdog_intr
, 0, wdog_scaler
+ 1);
1362 printf("Watchdog reset!\n");
1368 wdog_counter
= wdog_rst_delay
;
1369 event(wdog_intr
, 0, wdog_scaler
+ 1);
1378 event(wdog_intr
, 0, wdog_scaler
+ 1);
1380 printf("Watchdog started, scaler = %d, counter = %d\n",
1381 wdog_scaler
, wdog_counter
);
1392 if (rtc_counter
== 0) {
1396 rtc_counter
= rtc_reload
;
1402 event(rtc_intr
, 0, rtc_scaler
+ 1);
1403 rtc_scaler_start
= now();
1407 printf("RTC stopped\n\r");
1416 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1417 event(rtc_intr
, 0, rtc_scaler
+ 1);
1418 rtc_scaler_start
= now();
1425 return (rtc_counter
);
1432 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1446 if (gpt_counter
== 0) {
1449 gpt_counter
= gpt_reload
;
1455 event(gpt_intr
, 0, gpt_scaler
+ 1);
1456 gpt_scaler_start
= now();
1460 printf("GPT stopped\n\r");
1469 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1470 event(gpt_intr
, 0, gpt_scaler
+ 1);
1471 gpt_scaler_start
= now();
1478 return (gpt_counter
);
1485 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1500 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1501 if (val
& TCR_TCRCL
) {
1502 rtc_counter
= rtc_reload
;
1504 if (val
& TCR_TCRSL
) {
1506 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1507 if (rtc_se
&& (rtc_enabled
== 0))
1510 gpt_cr
= (val
& TCR_GACR
);
1511 if (val
& TCR_GACL
) {
1512 gpt_counter
= gpt_reload
;
1514 if (val
& TCR_GACL
) {
1516 gpt_se
= (val
& TCR_GASE
) >> 2;
1517 if (gpt_se
&& (gpt_enabled
== 0))
1522 /* Retrieve data from target memory. MEM points to location from which
1523 to read the data; DATA points to words where retrieved data will be
1524 stored in host byte order. SZ contains log(2) of the number of bytes
1525 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1526 or 3 (two words). */
1529 fetch_bytes (asi
, mem
, data
, sz
)
1535 if (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
1536 || asi
== 8 || asi
== 9) {
1539 data
[1] = (((uint32
) mem
[7]) & 0xff) |
1540 ((((uint32
) mem
[6]) & 0xff) << 8) |
1541 ((((uint32
) mem
[5]) & 0xff) << 16) |
1542 ((((uint32
) mem
[4]) & 0xff) << 24);
1543 /* Fall through to 2 */
1545 data
[0] = (((uint32
) mem
[3]) & 0xff) |
1546 ((((uint32
) mem
[2]) & 0xff) << 8) |
1547 ((((uint32
) mem
[1]) & 0xff) << 16) |
1548 ((((uint32
) mem
[0]) & 0xff) << 24);
1551 data
[0] = (((uint32
) mem
[1]) & 0xff) |
1552 ((((uint32
) mem
[0]) & 0xff) << 8);
1555 data
[0] = mem
[0] & 0xff;
1562 data
[1] = ((((uint32
) mem
[7]) & 0xff) << 24) |
1563 ((((uint32
) mem
[6]) & 0xff) << 16) |
1564 ((((uint32
) mem
[5]) & 0xff) << 8) |
1565 (((uint32
) mem
[4]) & 0xff);
1566 /* Fall through to 4 */
1568 data
[0] = ((((uint32
) mem
[3]) & 0xff) << 24) |
1569 ((((uint32
) mem
[2]) & 0xff) << 16) |
1570 ((((uint32
) mem
[1]) & 0xff) << 8) |
1571 (((uint32
) mem
[0]) & 0xff);
1574 data
[0] = ((((uint32
) mem
[1]) & 0xff) << 8) |
1575 (((uint32
) mem
[0]) & 0xff);
1578 data
[0] = mem
[0] & 0xff;
1585 /* Store data in target byte order. MEM points to location to store data;
1586 DATA points to words in host byte order to be stored. SZ contains log(2)
1587 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1588 2 (one word), or 3 (two words). */
1591 store_bytes (mem
, data
, sz
)
1596 if (CURRENT_TARGET_BYTE_ORDER
== LITTLE_ENDIAN
) {
1599 mem
[7] = (data
[1] >> 24) & 0xff;
1600 mem
[6] = (data
[1] >> 16) & 0xff;
1601 mem
[5] = (data
[1] >> 8) & 0xff;
1602 mem
[4] = data
[1] & 0xff;
1603 /* Fall through to 2 */
1605 mem
[3] = (data
[0] >> 24) & 0xff;
1606 mem
[2] = (data
[0] >> 16) & 0xff;
1607 /* Fall through to 1 */
1609 mem
[1] = (data
[0] >> 8) & 0xff;
1610 /* Fall through to 0 */
1612 mem
[0] = data
[0] & 0xff;
1618 mem
[7] = data
[1] & 0xff;
1619 mem
[6] = (data
[1] >> 8) & 0xff;
1620 mem
[5] = (data
[1] >> 16) & 0xff;
1621 mem
[4] = (data
[1] >> 24) & 0xff;
1622 /* Fall through to 2 */
1624 mem
[3] = data
[0] & 0xff;
1625 mem
[2] = (data
[0] >> 8) & 0xff;
1626 mem
[1] = (data
[0] >> 16) & 0xff;
1627 mem
[0] = (data
[0] >> 24) & 0xff;
1630 mem
[1] = data
[0] & 0xff;
1631 mem
[0] = (data
[0] >> 8) & 0xff;
1634 mem
[0] = data
[0] & 0xff;
1642 /* Memory emulation */
1645 memory_read(asi
, addr
, data
, sz
, ws
)
1657 printf("Inserted MEC error %d\n",errmec
);
1658 set_sfsr(errmec
, addr
, asi
, 1);
1659 if (errmec
== 5) mecparerror();
1660 if (errmec
== 6) iucomperr();
1666 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1667 fetch_bytes (asi
, &ramb
[addr
& mem_rammask
], data
, sz
);
1670 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1671 mexc
= mec_read(addr
, asi
, data
);
1673 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1683 if ((addr
< 0x100000) ||
1684 ((addr
>= 0x80000000) && (addr
< 0x80100000))) {
1685 fetch_bytes (asi
, &romb
[addr
& ROM_MASK
], data
, sz
);
1688 } else if ((addr
>= 0x10000000) &&
1689 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1690 (mec_iocr
& 0x10)) {
1695 } else if (addr
< mem_romsz
) {
1696 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1701 } else if (addr
< mem_romsz
) {
1702 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1709 printf("Memory exception at %x (illegal address)\n", addr
);
1710 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1716 memory_write(asi
, addr
, data
, sz
, ws
)
1734 printf("Inserted MEC error %d\n",errmec
);
1735 set_sfsr(errmec
, addr
, asi
, 0);
1736 if (errmec
== 5) mecparerror();
1737 if (errmec
== 6) iucomperr();
1743 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1746 waddr
= (addr
& 0x7fffff) >> 2;
1747 for (i
= 0; i
< 2; i
++)
1749 (((asi
== 0xa) && (mec_wpr
[i
] & 1)) ||
1750 ((asi
== 0xb) && (mec_wpr
[i
] & 2))) &&
1751 ((waddr
>= mec_ssa
[i
]) && ((waddr
| (sz
== 3)) < mec_sea
[i
]));
1753 if (((mem_blockprot
) && (wphit
[0] || wphit
[1])) ||
1754 ((!mem_blockprot
) &&
1755 !((mec_wpr
[0] && wphit
[0]) || (mec_wpr
[1] && wphit
[1]))
1758 printf("Memory access protection error at 0x%08x\n", addr
);
1759 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1765 store_bytes (&ramb
[addr
& mem_rammask
], data
, sz
);
1770 *ws
= mem_ramw_ws
+ 3;
1776 *ws
= 2 * mem_ramw_ws
+ STD_WS
;
1780 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1781 if ((sz
!= 2) || (asi
!= 0xb)) {
1782 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1786 mexc
= mec_write(addr
, *data
);
1788 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1799 ((addr
< 0x100000) || ((addr
>= 0x80000000) && (addr
< 0x80100000)))) {
1801 *ws
= sz
== 3 ? 8 : 4;
1802 store_bytes (&romb
[addr
], data
, sz
);
1804 } else if ((addr
>= 0x10000000) &&
1805 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1806 (mec_iocr
& 0x10)) {
1807 erareg
= *data
& 0x0e;
1811 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1812 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1813 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1815 *ws
= mem_romw_ws
+ 1;
1817 *ws
+= mem_romw_ws
+ STD_WS
;
1818 store_bytes (&romb
[addr
], data
, sz
);
1822 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1823 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1824 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1826 *ws
= mem_romw_ws
+ 1;
1828 *ws
+= mem_romw_ws
+ STD_WS
;
1829 store_bytes (&romb
[addr
], data
, sz
);
1837 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1841 static unsigned char *
1842 get_mem_ptr(addr
, size
)
1846 if ((addr
+ size
) < ROM_SZ
) {
1847 return (&romb
[addr
]);
1848 } else if ((addr
>= mem_ramstart
) && ((addr
+ size
) < mem_ramend
)) {
1849 return (&ramb
[addr
& mem_rammask
]);
1853 else if ((era
) && ((addr
<0x100000) ||
1854 ((addr
>= (unsigned) 0x80000000) && ((addr
+ size
) < (unsigned) 0x80100000)))) {
1855 return (&romb
[addr
& ROM_MASK
]);
1859 return ((char *) -1);
1863 sis_memory_write(addr
, data
, length
)
1865 const unsigned char *data
;
1870 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1873 memcpy(mem
, data
, length
);
1878 sis_memory_read(addr
, data
, length
)
1885 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1888 memcpy(data
, mem
, length
);