1 /* This file is part of SIS (SPARC instruction simulator)
3 Copyright (C) 1995-2017 Free Software Foundation, Inc.
4 Contributed by Jiri Gaisler, European Space Agency
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* The control space devices */
22 #include <sys/types.h>
26 #include <sys/fcntl.h>
30 #include "sim-config.h"
33 extern int32 sis_verbose
;
34 extern int32 sparclite
, sparclite_board
;
35 extern int rom8
,wrp
,uben
;
36 extern char uart_dev1
[], uart_dev2
[];
38 int dumbio
= 0; /* normal, smart, terminal oriented IO by default */
41 #define MEC_START 0x01f80000
42 #define MEC_END 0x01f80100
44 /* Memory exception waitstates */
47 /* ERC32 always adds one waitstate during RAM std */
54 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
57 /* MEC register addresses */
61 #define MEC_PWDR 0x008
62 #define MEC_MEMCFG 0x010
63 #define MEC_IOCR 0x014
66 #define MEC_MAR0 0x020
67 #define MEC_MAR1 0x024
69 #define MEC_SSA1 0x020
70 #define MEC_SEA1 0x024
71 #define MEC_SSA2 0x028
72 #define MEC_SEA2 0x02C
78 #define MEC_WDOG 0x060
79 #define MEC_TRAPD 0x064
80 #define MEC_RTC_COUNTER 0x080
81 #define MEC_RTC_RELOAD 0x080
82 #define MEC_RTC_SCALER 0x084
83 #define MEC_GPT_COUNTER 0x088
84 #define MEC_GPT_RELOAD 0x088
85 #define MEC_GPT_SCALER 0x08C
86 #define MEC_TIMER_CTRL 0x098
87 #define MEC_SFSR 0x0A0
88 #define MEC_FFAR 0x0A4
89 #define MEC_ERSR 0x0B0
96 #define MEC_UARTA 0x0E0
97 #define MEC_UARTB 0x0E4
98 #define MEC_UART_CTRL 0x0E8
99 #define SIM_LOAD 0x0F0
101 /* Memory exception causes */
105 #define WATCH_EXC 0xa
106 #define BREAK_EXC 0xb
108 /* Size of UART buffers (bytes) */
111 /* Number of simulator ticks between flushing the UARTS. */
112 /* For good performance, keep above 1000 */
113 #define UART_FLUSH_TIME 3000
115 /* MEC timer control register bits */
120 #define TCR_TCRCR 0x100
121 #define TCR_TCRCL 0x200
122 #define TCR_TCRSE 0x400
123 #define TCR_TCRSL 0x800
125 /* New uart defines */
126 #define UART_TX_TIME 1000
127 #define UART_RX_TIME 1000
129 #define UARTA_SRE 0x2
130 #define UARTA_HRE 0x4
131 #define UARTA_OR 0x40
132 #define UARTA_CLR 0x80
133 #define UARTB_DR 0x10000
134 #define UARTB_SRE 0x20000
135 #define UARTB_HRE 0x40000
136 #define UARTB_OR 0x400000
137 #define UARTB_CLR 0x800000
139 #define UART_DR 0x100
140 #define UART_TSE 0x200
141 #define UART_THE 0x400
145 static char fname
[256];
146 static int32 find
= 0;
147 static uint32 mec_ssa
[2]; /* Write protection start address */
148 static uint32 mec_sea
[2]; /* Write protection end address */
149 static uint32 mec_wpr
[2]; /* Write protection control fields */
150 static uint32 mec_sfsr
;
151 static uint32 mec_ffar
;
152 static uint32 mec_ipr
;
153 static uint32 mec_imr
;
154 static uint32 mec_isr
;
155 static uint32 mec_icr
;
156 static uint32 mec_ifr
;
157 static uint32 mec_mcr
; /* MEC control register */
158 static uint32 mec_memcfg
; /* Memory control register */
159 static uint32 mec_wcr
; /* MEC waitstate register */
160 static uint32 mec_iocr
; /* MEC IO control register */
161 static uint32 posted_irq
;
162 static uint32 mec_ersr
; /* MEC error and status register */
163 static uint32 mec_tcr
; /* MEC test comtrol register */
165 static uint32 rtc_counter
;
166 static uint32 rtc_reload
;
167 static uint32 rtc_scaler
;
168 static uint32 rtc_scaler_start
;
169 static uint32 rtc_enabled
;
170 static uint32 rtc_cr
;
171 static uint32 rtc_se
;
173 static uint32 gpt_counter
;
174 static uint32 gpt_reload
;
175 static uint32 gpt_scaler
;
176 static uint32 gpt_scaler_start
;
177 static uint32 gpt_enabled
;
178 static uint32 gpt_cr
;
179 static uint32 gpt_se
;
181 static uint32 wdog_scaler
;
182 static uint32 wdog_counter
;
183 static uint32 wdog_rst_delay
;
184 static uint32 wdog_rston
;
187 init
, disabled
, enabled
, stopped
190 static enum wdog_type wdog_status
;
193 /* ROM size 1024 Kbyte */
194 #define ROM_SZ 0x100000
195 #define ROM_MASK 0x0fffff
197 /* RAM size 4 Mbyte */
198 #define RAM_START 0x02000000
199 #define RAM_END 0x02400000
200 #define RAM_MASK 0x003fffff
202 /* SPARClite boards all seem to have RAM at the same place. */
203 #define RAM_START_SLITE 0x40000000
204 #define RAM_END_SLITE 0x40400000
205 #define RAM_MASK_SLITE 0x003fffff
207 /* Memory support variables */
209 static uint32 mem_ramr_ws
; /* RAM read waitstates */
210 static uint32 mem_ramw_ws
; /* RAM write waitstates */
211 static uint32 mem_romr_ws
; /* ROM read waitstates */
212 static uint32 mem_romw_ws
; /* ROM write waitstates */
213 static uint32 mem_ramstart
; /* RAM start */
214 static uint32 mem_ramend
; /* RAM end */
215 static uint32 mem_rammask
; /* RAM address mask */
216 static uint32 mem_ramsz
; /* RAM size */
217 static uint32 mem_romsz
; /* ROM size */
218 static uint32 mem_accprot
; /* RAM write protection enabled */
219 static uint32 mem_blockprot
; /* RAM block write protection enabled */
221 static unsigned char romb
[ROM_SZ
];
222 static unsigned char ramb
[RAM_END
- RAM_START
];
225 /* UART support variables */
227 static int32 fd1
, fd2
; /* file descriptor for input file */
228 static int32 Ucontrol
; /* UART status register */
229 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
230 static int32 anum
, aind
= 0;
231 static int32 bnum
, bind
= 0;
232 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
233 static unsigned wnuma
;
234 static unsigned wnumb
;
235 static FILE *f1in
, *f1out
, *f2in
, *f2out
;
236 static struct termios ioc1
, ioc2
, iocold1
, iocold2
;
237 static int f1open
= 0, f2open
= 0;
239 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
240 static uint32 uart_stat_reg
;
241 static uint32 uarta_data
, uartb_data
;
248 /* Forward declarations */
250 static void decode_ersr (void);
252 static void iucomperr (void);
254 static void mecparerror (void);
255 static void decode_memcfg (void);
256 static void decode_wcr (void);
257 static void decode_mcr (void);
258 static void close_port (void);
259 static void mec_reset (void);
260 static void mec_intack (int32 level
);
261 static void chk_irq (void);
262 static void mec_irq (int32 level
);
263 static void set_sfsr (uint32 fault
, uint32 addr
,
264 uint32 asi
, uint32 read
);
265 static int32
mec_read (uint32 addr
, uint32 asi
, uint32
*data
);
266 static int mec_write (uint32 addr
, uint32 data
);
267 static void port_init (void);
268 static uint32
read_uart (uint32 addr
);
269 static void write_uart (uint32 addr
, uint32 data
);
270 static void flush_uart (void);
271 static void uarta_tx (void);
272 static void uartb_tx (void);
273 static void uart_rx (caddr_t arg
);
274 static void uart_intr (caddr_t arg
);
275 static void uart_irq_start (void);
276 static void wdog_intr (caddr_t arg
);
277 static void wdog_start (void);
278 static void rtc_intr (caddr_t arg
);
279 static void rtc_start (void);
280 static uint32
rtc_counter_read (void);
281 static void rtc_scaler_set (uint32 val
);
282 static void rtc_reload_set (uint32 val
);
283 static void gpt_intr (caddr_t arg
);
284 static void gpt_start (void);
285 static uint32
gpt_counter_read (void);
286 static void gpt_scaler_set (uint32 val
);
287 static void gpt_reload_set (uint32 val
);
288 static void timer_ctrl (uint32 val
);
289 static unsigned char *
290 get_mem_ptr (uint32 addr
, uint32 size
);
291 static void store_bytes (unsigned char *mem
, uint32 waddr
,
292 uint32
*data
, int sz
, int32
*ws
);
305 /* Power-on reset init */
318 if (mec_ersr
& 0x01) {
319 if (!(mec_mcr
& 0x20)) {
320 if (mec_mcr
& 0x40) {
324 printf("Error manager reset - IU in error mode\n");
329 printf("Error manager halt - IU in error mode\n");
334 if (mec_ersr
& 0x04) {
335 if (!(mec_mcr
& 0x200)) {
336 if (mec_mcr
& 0x400) {
340 printf("Error manager reset - IU comparison error\n");
345 printf("Error manager halt - IU comparison error\n");
350 if (mec_ersr
& 0x20) {
351 if (!(mec_mcr
& 0x2000)) {
352 if (mec_mcr
& 0x4000) {
356 printf("Error manager reset - MEC hardware error\n");
361 printf("Error manager halt - MEC hardware error\n");
385 /* IU error mode manager */
397 /* Check memory settings */
402 if (rom8
) mec_memcfg
&= ~0x20000;
403 else mec_memcfg
|= 0x20000;
405 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
406 mem_romsz
= (128 * 1024) << ((mec_memcfg
>> 18) & 7);
408 if (sparclite_board
) {
409 mem_ramstart
= RAM_START_SLITE
;
410 mem_ramend
= RAM_END_SLITE
;
411 mem_rammask
= RAM_MASK_SLITE
;
414 mem_ramstart
= RAM_START
;
415 mem_ramend
= RAM_END
;
416 mem_rammask
= RAM_MASK
;
419 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
420 mem_ramstart
, mem_ramsz
>> 10, mem_romsz
>> 10);
426 mem_ramr_ws
= mec_wcr
& 3;
427 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
428 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
430 if (mem_romr_ws
> 0 ) mem_romr_ws
--;
431 mem_romr_ws
= 5 + (4*mem_romr_ws
);
433 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
435 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
436 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
442 mem_accprot
= (mec_wpr
[0] | mec_wpr
[1]);
443 mem_blockprot
= (mec_mcr
>> 3) & 1;
444 if (sis_verbose
&& mem_accprot
)
445 printf("Memory block write protection enabled\n");
446 if (mec_mcr
& 0x08000) {
450 if (sis_verbose
&& (mec_mcr
& 2))
451 printf("Software reset enabled\n");
452 if (sis_verbose
&& (mec_mcr
& 1))
453 printf("Power-down mode enabled\n");
456 /* Flush ports when simulator stops */
467 sim_stop(SIM_DESC sd
)
476 if (f1open
&& f1in
!= stdin
)
478 if (f2open
&& f2in
!= stdin
)
494 for (i
= 0; i
< 2; i
++)
495 mec_ssa
[i
] = mec_sea
[i
] = mec_wpr
[i
] = 0;
496 mec_mcr
= 0x01350014;
505 mec_memcfg
= 0x10000;
507 mec_ersr
= 0; /* MEC error and status register */
508 mec_tcr
= 0; /* MEC test comtrol register */
516 anum
= aind
= bnum
= bind
= 0;
518 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
519 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
521 rtc_counter
= 0xffffffff;
522 rtc_reload
= 0xffffffff;
528 gpt_counter
= 0xffffffff;
529 gpt_reload
= 0xffffffff;
536 wdog_rst_delay
= 255;
537 wdog_counter
= 0xffff;
556 printf("interrupt %d acknowledged\n", level
);
557 irq_test
= mec_tcr
& 0x80000;
558 if ((irq_test
) && (mec_ifr
& (1 << level
)))
559 mec_ifr
&= ~(1 << level
);
561 mec_ipr
&= ~(1 << level
);
573 if (mec_tcr
& 0x80000) itmp
= mec_ifr
;
575 itmp
= ((mec_ipr
| itmp
) & ~mec_imr
) & 0x0fffe;
578 for (i
= 15; i
> 0; i
--) {
579 if (((itmp
>> i
) & 1) != 0) {
580 if ((sis_verbose
) && (i
> old_irl
))
581 printf("IU irl: %d\n", i
);
583 set_int(i
, mec_intack
, i
);
594 mec_ipr
|= (1 << level
);
599 set_sfsr(fault
, addr
, asi
, read
)
605 if ((asi
== 0xa) || (asi
== 0xb)) {
607 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
608 mec_sfsr
|= ((mec_sfsr
& 1) ^ 1) | (mec_sfsr
& 1);
621 mec_read(addr
, asi
, data
)
627 switch (addr
& 0x0ff) {
629 case MEC_MCR
: /* 0x00 */
633 case MEC_MEMCFG
: /* 0x10 */
638 *data
= mec_iocr
; /* 0x14 */
641 case MEC_SSA1
: /* 0x20 */
642 *data
= mec_ssa
[0] | (mec_wpr
[0] << 23);
644 case MEC_SEA1
: /* 0x24 */
647 case MEC_SSA2
: /* 0x28 */
648 *data
= mec_ssa
[1] | (mec_wpr
[1] << 23);
650 case MEC_SEA2
: /* 0x2c */
654 case MEC_ISR
: /* 0x44 */
658 case MEC_IPR
: /* 0x48 */
662 case MEC_IMR
: /* 0x4c */
666 case MEC_IFR
: /* 0x54 */
670 case MEC_RTC_COUNTER
: /* 0x80 */
671 *data
= rtc_counter_read();
673 case MEC_RTC_SCALER
: /* 0x84 */
675 *data
= rtc_scaler
- (now() - rtc_scaler_start
);
680 case MEC_GPT_COUNTER
: /* 0x88 */
681 *data
= gpt_counter_read();
684 case MEC_GPT_SCALER
: /* 0x8c */
686 *data
= gpt_scaler
- (now() - gpt_scaler_start
);
692 case MEC_SFSR
: /* 0xA0 */
696 case MEC_FFAR
: /* 0xA4 */
703 strcpy(fname
, "simload");
704 find
= bfd_load(fname
);
712 case MEC_ERSR
: /* 0xB0 */
716 case MEC_TCR
: /* 0xD0 */
720 case MEC_UARTA
: /* 0xE0 */
721 case MEC_UARTB
: /* 0xE4 */
723 set_sfsr(MEC_ACC
, addr
, asi
, 1);
726 *data
= read_uart(addr
);
729 case MEC_UART_CTRL
: /* 0xE8 */
731 *data
= read_uart(addr
);
734 case 0xF4: /* simulator RAM size in bytes */
738 case 0xF8: /* simulator ROM size in bytes */
743 set_sfsr(MEC_ACC
, addr
, asi
, 1);
751 mec_write(addr
, data
)
756 printf("MEC write a: %08x, d: %08x\n",addr
,data
);
757 switch (addr
& 0x0ff) {
762 if (mec_mcr
& 0x08000) mecparerror();
770 printf(" Software reset issued\n");
776 if (mec_iocr
& 0xC0C0C0C0) mecparerror();
779 case MEC_SSA1
: /* 0x20 */
780 if (data
& 0xFE000000) mecparerror();
781 mec_ssa
[0] = data
& 0x7fffff;
782 mec_wpr
[0] = (data
>> 23) & 0x03;
783 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
784 if (sis_verbose
&& mec_wpr
[0])
785 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
786 mec_ssa
[0] << 2, mec_sea
[0] << 2);
788 case MEC_SEA1
: /* 0x24 */
789 if (data
& 0xFF800000) mecparerror();
790 mec_sea
[0] = data
& 0x7fffff;
792 case MEC_SSA2
: /* 0x28 */
793 if (data
& 0xFE000000) mecparerror();
794 mec_ssa
[1] = data
& 0x7fffff;
795 mec_wpr
[1] = (data
>> 23) & 0x03;
796 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
797 if (sis_verbose
&& mec_wpr
[1])
798 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
799 mec_ssa
[1] << 2, mec_sea
[1] << 2);
801 case MEC_SEA2
: /* 0x2c */
802 if (data
& 0xFF800000) mecparerror();
803 mec_sea
[1] = data
& 0x7fffff;
808 if (data
& 0xFFFFFF00) mecparerror();
810 if (data
& 0xFF00FF00) mecparerror();
811 write_uart(addr
, data
);
815 gpt_reload_set(data
);
819 if (data
& 0xFFFF0000) mecparerror();
820 gpt_scaler_set(data
);
824 if (data
& 0xFFFFF0F0) mecparerror();
829 rtc_reload_set(data
);
833 if (data
& 0xFFFFFF00) mecparerror();
834 rtc_scaler_set(data
);
837 case MEC_SFSR
: /* 0xA0 */
838 if (data
& 0xFFFF0880) mecparerror();
843 if (data
& 0xFFFFE000) mecparerror();
847 case MEC_IMR
: /* 0x4c */
849 if (data
& 0xFFFF8001) mecparerror();
850 mec_imr
= data
& 0x7ffe;
854 case MEC_ICR
: /* 0x50 */
856 if (data
& 0xFFFF0001) mecparerror();
857 mec_ipr
&= ~data
& 0x0fffe;
861 case MEC_IFR
: /* 0x54 */
863 if (mec_tcr
& 0x080000) {
864 if (data
& 0xFFFF0001) mecparerror();
865 mec_ifr
= data
& 0xfffe;
870 fname
[find
++] = (char) data
;
874 case MEC_MEMCFG
: /* 0x10 */
875 if (data
& 0xC0E08000) mecparerror();
878 if (mec_memcfg
& 0xc0e08000)
882 case MEC_WCR
: /* 0x18 */
887 case MEC_ERSR
: /* 0xB0 */
888 if (mec_tcr
& 0x100000)
889 if (data
& 0xFFFFEFC0) mecparerror();
890 mec_ersr
= data
& 0x103f;
893 case MEC_TCR
: /* 0xD0 */
894 if (data
& 0xFFE1FFC0) mecparerror();
895 mec_tcr
= data
& 0x1e003f;
898 case MEC_WDOG
: /* 0x60 */
899 wdog_scaler
= (data
>> 16) & 0x0ff;
900 wdog_counter
= data
& 0x0ffff;
901 wdog_rst_delay
= data
>> 24;
903 if (wdog_status
== stopped
)
905 wdog_status
= enabled
;
908 case MEC_TRAPD
: /* 0x64 */
909 if (wdog_status
== init
) {
910 wdog_status
= disabled
;
912 printf("Watchdog disabled\n");
922 set_sfsr(MEC_ACC
, addr
, 0xb, 0);
932 static int ifd1
= -1, ifd2
= -1, ofd1
= -1, ofd2
= -1;
938 return; /* do nothing */
940 tcsetattr(0, TCSANOW
, &ioc1
);
942 tcsetattr(0, TCSANOW
, &ioc2
);
949 return; /* do nothing */
951 tcsetattr(0, TCSANOW
, &iocold1
);
953 tcsetattr(0, TCSANOW
, &iocold2
);
956 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
958 ? (0) /* no bytes read, no delay */ \
959 : read( _fd_, _buf_, _len_ ) )
977 if (uart_dev1
[0] != 0)
978 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NONBLOCK
)) < 0) {
979 printf("Warning, couldn't open output device %s\n", uart_dev1
);
982 printf("serial port A on %s\n", uart_dev1
);
983 f1in
= f1out
= fdopen(fd1
, "r+");
987 if (f1in
) ifd1
= fileno(f1in
);
990 printf("serial port A on stdin/stdout\n");
992 tcgetattr(ifd1
, &ioc1
);
994 ioc1
.c_lflag
&= ~(ICANON
| ECHO
);
996 ioc1
.c_cc
[VTIME
] = 0;
1002 ofd1
= fileno(f1out
);
1003 if (!dumbio
&& ofd1
== 1) setbuf(f1out
, NULL
);
1006 if (uart_dev2
[0] != 0)
1007 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NONBLOCK
)) < 0) {
1008 printf("Warning, couldn't open output device %s\n", uart_dev2
);
1011 printf("serial port B on %s\n", uart_dev2
);
1012 f2in
= f2out
= fdopen(fd2
, "r+");
1013 setbuf(f2out
, NULL
);
1016 if (f2in
) ifd2
= fileno(f2in
);
1019 printf("serial port B on stdin/stdout\n");
1021 tcgetattr(ifd2
, &ioc2
);
1023 ioc2
.c_lflag
&= ~(ICANON
| ECHO
);
1024 ioc2
.c_cc
[VMIN
] = 0;
1025 ioc2
.c_cc
[VTIME
] = 0;
1031 ofd2
= fileno(f2out
);
1032 if (!dumbio
&& ofd2
== 1) setbuf(f2out
, NULL
);
1047 switch (addr
& 0xff) {
1049 case 0xE0: /* UART 1 */
1054 if ((aind
+ 1) < anum
)
1056 return (0x700 | (uint32
) aq
[aind
++]);
1059 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1063 if ((aind
+ 1) < anum
)
1065 return (0x700 | (uint32
) aq
[aind
++]);
1067 return (0x600 | (uint32
) aq
[aind
]);
1073 uarta_data
&= ~UART_DR
;
1074 uart_stat_reg
&= ~UARTA_DR
;
1082 case 0xE4: /* UART 2 */
1086 if ((bind
+ 1) < bnum
)
1088 return (0x700 | (uint32
) bq
[bind
++]);
1091 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1095 if ((bind
+ 1) < bnum
)
1097 return (0x700 | (uint32
) bq
[bind
++]);
1099 return (0x600 | (uint32
) bq
[bind
]);
1105 uartb_data
&= ~UART_DR
;
1106 uart_stat_reg
&= ~UARTB_DR
;
1114 case 0xE8: /* UART status register */
1120 Ucontrol
|= 0x00000001;
1123 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1126 Ucontrol
|= 0x00000001;
1132 Ucontrol
|= 0x00010000;
1135 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1138 Ucontrol
|= 0x00010000;
1144 Ucontrol
|= 0x00060006;
1147 return uart_stat_reg
;
1155 printf("Read from unimplemented MEC register (%x)\n", addr
);
1162 write_uart(addr
, data
)
1168 c
= (unsigned char) data
;
1169 switch (addr
& 0xff) {
1171 case 0xE0: /* UART A */
1174 if (wnuma
< UARTBUF
)
1178 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1184 if (uart_stat_reg
& UARTA_SRE
) {
1186 uart_stat_reg
&= ~UARTA_SRE
;
1187 event(uarta_tx
, 0, UART_TX_TIME
);
1190 uart_stat_reg
&= ~UARTA_HRE
;
1195 case 0xE4: /* UART B */
1198 if (wnumb
< UARTBUF
)
1202 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1208 if (uart_stat_reg
& UARTB_SRE
) {
1210 uart_stat_reg
&= ~UARTB_SRE
;
1211 event(uartb_tx
, 0, UART_TX_TIME
);
1214 uart_stat_reg
&= ~UARTB_HRE
;
1218 case 0xE8: /* UART status register */
1220 if (data
& UARTA_CLR
) {
1221 uart_stat_reg
&= 0xFFFF0000;
1222 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
1224 if (data
& UARTB_CLR
) {
1225 uart_stat_reg
&= 0x0000FFFF;
1226 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
1232 printf("Write to unimplemented MEC register (%x)\n", addr
);
1240 while (wnuma
&& f1open
)
1241 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1242 while (wnumb
&& f2open
)
1243 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1252 while (f1open
&& fwrite(&uarta_sreg
, 1, 1, f1out
) != 1);
1253 if (uart_stat_reg
& UARTA_HRE
) {
1254 uart_stat_reg
|= UARTA_SRE
;
1256 uarta_sreg
= uarta_hreg
;
1257 uart_stat_reg
|= UARTA_HRE
;
1258 event(uarta_tx
, 0, UART_TX_TIME
);
1266 while (f2open
&& fwrite(&uartb_sreg
, 1, 1, f2out
) != 1);
1267 if (uart_stat_reg
& UARTB_HRE
) {
1268 uart_stat_reg
|= UARTB_SRE
;
1270 uartb_sreg
= uartb_hreg
;
1271 uart_stat_reg
|= UARTB_HRE
;
1272 event(uartb_tx
, 0, UART_TX_TIME
);
1287 rsize
= DO_STDIO_READ(ifd1
, &rxd
, 1);
1289 uarta_data
= UART_DR
| rxd
;
1290 if (uart_stat_reg
& UARTA_HRE
)
1291 uarta_data
|= UART_THE
;
1292 if (uart_stat_reg
& UARTA_SRE
)
1293 uarta_data
|= UART_TSE
;
1294 if (uart_stat_reg
& UARTA_DR
) {
1295 uart_stat_reg
|= UARTA_OR
;
1296 mec_irq(7); /* UART error interrupt */
1298 uart_stat_reg
|= UARTA_DR
;
1303 rsize
= DO_STDIO_READ(ifd2
, &rxd
, 1);
1305 uartb_data
= UART_DR
| rxd
;
1306 if (uart_stat_reg
& UARTB_HRE
)
1307 uartb_data
|= UART_THE
;
1308 if (uart_stat_reg
& UARTB_SRE
)
1309 uartb_data
|= UART_TSE
;
1310 if (uart_stat_reg
& UARTB_DR
) {
1311 uart_stat_reg
|= UARTB_OR
;
1312 mec_irq(7); /* UART error interrupt */
1314 uart_stat_reg
|= UARTB_DR
;
1317 event(uart_rx
, 0, UART_RX_TIME
);
1324 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1325 flush_uart(); /* Flush UART ports */
1326 event(uart_intr
, 0, UART_FLUSH_TIME
);
1334 event(uart_intr
, 0, UART_FLUSH_TIME
);
1337 event(uart_rx
, 0, UART_RX_TIME
);
1348 if (wdog_status
== disabled
) {
1349 wdog_status
= stopped
;
1354 event(wdog_intr
, 0, wdog_scaler
+ 1);
1357 printf("Watchdog reset!\n");
1363 wdog_counter
= wdog_rst_delay
;
1364 event(wdog_intr
, 0, wdog_scaler
+ 1);
1373 event(wdog_intr
, 0, wdog_scaler
+ 1);
1375 printf("Watchdog started, scaler = %d, counter = %d\n",
1376 wdog_scaler
, wdog_counter
);
1387 if (rtc_counter
== 0) {
1391 rtc_counter
= rtc_reload
;
1397 event(rtc_intr
, 0, rtc_scaler
+ 1);
1398 rtc_scaler_start
= now();
1402 printf("RTC stopped\n\r");
1411 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1412 event(rtc_intr
, 0, rtc_scaler
+ 1);
1413 rtc_scaler_start
= now();
1427 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1441 if (gpt_counter
== 0) {
1444 gpt_counter
= gpt_reload
;
1450 event(gpt_intr
, 0, gpt_scaler
+ 1);
1451 gpt_scaler_start
= now();
1455 printf("GPT stopped\n\r");
1464 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1465 event(gpt_intr
, 0, gpt_scaler
+ 1);
1466 gpt_scaler_start
= now();
1480 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1495 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1496 if (val
& TCR_TCRCL
) {
1497 rtc_counter
= rtc_reload
;
1499 if (val
& TCR_TCRSL
) {
1501 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1502 if (rtc_se
&& (rtc_enabled
== 0))
1505 gpt_cr
= (val
& TCR_GACR
);
1506 if (val
& TCR_GACL
) {
1507 gpt_counter
= gpt_reload
;
1509 if (val
& TCR_GACL
) {
1511 gpt_se
= (val
& TCR_GASE
) >> 2;
1512 if (gpt_se
&& (gpt_enabled
== 0))
1516 /* Store data in host byte order. MEM points to the beginning of the
1517 emulated memory; WADDR contains the index the emulated memory,
1518 DATA points to words in host byte order to be stored. SZ contains log(2)
1519 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1520 2 (one word), or 3 (two words); WS should return the number of
1524 store_bytes (unsigned char *mem
, uint32 waddr
, uint32
*data
, int32 sz
,
1530 mem
[waddr
] = *data
& 0x0ff;
1531 *ws
= mem_ramw_ws
+ 3;
1534 #ifdef HOST_LITTLE_ENDIAN
1537 memcpy (&mem
[waddr
], data
, 2);
1538 *ws
= mem_ramw_ws
+ 3;
1541 memcpy (&mem
[waddr
], data
, 4);
1545 memcpy (&mem
[waddr
], data
, 8);
1546 *ws
= 2 * mem_ramw_ws
+ STD_WS
;
1552 /* Memory emulation */
1555 memory_iread (uint32 addr
, uint32
*data
, int32
*ws
)
1558 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1559 memcpy (data
, &ramb
[addr
& mem_rammask
& ~3], 4);
1562 } else if (addr
< mem_romsz
) {
1563 memcpy (data
, &romb
[addr
& ~3], 4);
1569 printf ("Memory exception at %x (illegal address)\n", addr
);
1570 if (sregs
.psr
& 0x080)
1574 set_sfsr (UIMP_ACC
, addr
, asi
, 1);
1580 memory_read(asi
, addr
, data
, sz
, ws
)
1592 printf("Inserted MEC error %d\n",errmec
);
1593 set_sfsr(errmec
, addr
, asi
, 1);
1594 if (errmec
== 5) mecparerror();
1595 if (errmec
== 6) iucomperr();
1601 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1602 memcpy (data
, &ramb
[addr
& mem_rammask
& ~3], 4);
1605 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1606 mexc
= mec_read(addr
, asi
, data
);
1608 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1618 if ((addr
< 0x100000) ||
1619 ((addr
>= 0x80000000) && (addr
< 0x80100000))) {
1620 memcpy (data
, &romb
[addr
& ROM_MASK
& ~3], 4);
1623 } else if ((addr
>= 0x10000000) &&
1624 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1625 (mec_iocr
& 0x10)) {
1630 } else if (addr
< mem_romsz
) {
1631 memcpy (data
, &romb
[addr
& ~3], 4);
1635 } else if (addr
< mem_romsz
) {
1636 memcpy (data
, &romb
[addr
& ~3], 4);
1644 printf ("Memory exception at %x (illegal address)\n", addr
);
1645 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1651 memory_write(asi
, addr
, data
, sz
, ws
)
1669 printf("Inserted MEC error %d\n",errmec
);
1670 set_sfsr(errmec
, addr
, asi
, 0);
1671 if (errmec
== 5) mecparerror();
1672 if (errmec
== 6) iucomperr();
1678 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1681 waddr
= (addr
& 0x7fffff) >> 2;
1682 for (i
= 0; i
< 2; i
++)
1684 (((asi
== 0xa) && (mec_wpr
[i
] & 1)) ||
1685 ((asi
== 0xb) && (mec_wpr
[i
] & 2))) &&
1686 ((waddr
>= mec_ssa
[i
]) && ((waddr
| (sz
== 3)) < mec_sea
[i
]));
1688 if (((mem_blockprot
) && (wphit
[0] || wphit
[1])) ||
1689 ((!mem_blockprot
) &&
1690 !((mec_wpr
[0] && wphit
[0]) || (mec_wpr
[1] && wphit
[1]))
1693 printf("Memory access protection error at 0x%08x\n", addr
);
1694 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1699 waddr
= addr
& mem_rammask
;
1700 store_bytes (ramb
, waddr
, data
, sz
, ws
);
1702 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1703 if ((sz
!= 2) || (asi
!= 0xb)) {
1704 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1708 mexc
= mec_write(addr
, *data
);
1710 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1721 ((addr
< 0x100000) || ((addr
>= 0x80000000) && (addr
< 0x80100000)))) {
1723 *ws
= sz
== 3 ? 8 : 4;
1724 store_bytes (romb
, addr
, data
, sz
, ws
);
1726 } else if ((addr
>= 0x10000000) &&
1727 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1728 (mec_iocr
& 0x10)) {
1729 erareg
= *data
& 0x0e;
1733 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1734 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1735 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1737 *ws
= mem_romw_ws
+ 1;
1739 *ws
+= mem_romw_ws
+ STD_WS
;
1740 store_bytes (romb
, addr
, data
, sz
, ws
);
1744 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1745 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1746 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1748 *ws
= mem_romw_ws
+ 1;
1750 *ws
+= mem_romw_ws
+ STD_WS
;
1751 store_bytes (romb
, addr
, data
, sz
, ws
);
1759 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1763 static unsigned char *
1764 get_mem_ptr(addr
, size
)
1768 if ((addr
+ size
) < ROM_SZ
) {
1770 } else if ((addr
>= mem_ramstart
) && ((addr
+ size
) < mem_ramend
)) {
1771 return &ramb
[addr
& mem_rammask
];
1775 else if ((era
) && ((addr
<0x100000) ||
1776 ((addr
>= (unsigned) 0x80000000) && ((addr
+ size
) < (unsigned) 0x80100000)))) {
1777 return &romb
[addr
& ROM_MASK
];
1785 sis_memory_write(addr
, data
, length
)
1787 const unsigned char *data
;
1792 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1795 memcpy(mem
, data
, length
);
1800 sis_memory_read(addr
, data
, length
)
1807 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1810 memcpy(data
, mem
, length
);
1814 extern struct pstate sregs
;
1819 mec_write(MEC_WCR
, 0); /* zero waitstates */
1820 mec_write(MEC_TRAPD
, 0); /* turn off watch-dog */
1821 mec_write(MEC_RTC_SCALER
, sregs
.freq
- 1); /* generate 1 MHz RTC tick */
1822 mec_write(MEC_MEMCFG
, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1824 sregs
.psr
= 0x110010e0;
1825 sregs
.r
[30] = RAM_END
;
1826 sregs
.r
[14] = sregs
.r
[30] - 96 * 4;
1827 mec_mcr
|= 1; /* power-down enabled */
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