2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
22 /* The control space devices */
25 #include <sys/types.h>
29 #include <sys/fcntl.h>
34 #include "sim-config.h"
37 extern int32 sis_verbose
;
38 extern int32 sparclite
, sparclite_board
;
39 extern int rom8
,wrp
,uben
;
40 extern char uart_dev1
[], uart_dev2
[];
42 int dumbio
= 0; /* normal, smart, terminal oriented IO by default */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
48 /* Memory exception waitstates */
51 /* ERC32 always adds one waitstate during RAM std */
58 /* The target's byte order is big-endian by default until we load a
59 little-endian program. */
61 int current_target_byte_order
= BIG_ENDIAN
;
63 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
66 /* MEC register addresses */
70 #define MEC_PWDR 0x008
71 #define MEC_MEMCFG 0x010
72 #define MEC_IOCR 0x014
75 #define MEC_MAR0 0x020
76 #define MEC_MAR1 0x024
78 #define MEC_SSA1 0x020
79 #define MEC_SEA1 0x024
80 #define MEC_SSA2 0x028
81 #define MEC_SEA2 0x02C
87 #define MEC_WDOG 0x060
88 #define MEC_TRAPD 0x064
89 #define MEC_RTC_COUNTER 0x080
90 #define MEC_RTC_RELOAD 0x080
91 #define MEC_RTC_SCALER 0x084
92 #define MEC_GPT_COUNTER 0x088
93 #define MEC_GPT_RELOAD 0x088
94 #define MEC_GPT_SCALER 0x08C
95 #define MEC_TIMER_CTRL 0x098
96 #define MEC_SFSR 0x0A0
97 #define MEC_FFAR 0x0A4
98 #define MEC_ERSR 0x0B0
100 #define MEC_TCR 0x0D0
102 #define MEC_BRK 0x0C4
103 #define MEC_WPR 0x0C8
105 #define MEC_UARTA 0x0E0
106 #define MEC_UARTB 0x0E4
107 #define MEC_UART_CTRL 0x0E8
108 #define SIM_LOAD 0x0F0
110 /* Memory exception causes */
114 #define WATCH_EXC 0xa
115 #define BREAK_EXC 0xb
117 /* Size of UART buffers (bytes) */
120 /* Number of simulator ticks between flushing the UARTS. */
121 /* For good performance, keep above 1000 */
122 #define UART_FLUSH_TIME 3000
124 /* MEC timer control register bits */
129 #define TCR_TCRCR 0x100
130 #define TCR_TCRCL 0x200
131 #define TCR_TCRSE 0x400
132 #define TCR_TCRSL 0x800
134 /* New uart defines */
135 #define UART_TX_TIME 1000
136 #define UART_RX_TIME 1000
138 #define UARTA_SRE 0x2
139 #define UARTA_HRE 0x4
140 #define UARTA_OR 0x40
141 #define UARTA_CLR 0x80
142 #define UARTB_DR 0x10000
143 #define UARTB_SRE 0x20000
144 #define UARTB_HRE 0x40000
145 #define UARTB_OR 0x400000
146 #define UARTB_CLR 0x800000
148 #define UART_DR 0x100
149 #define UART_TSE 0x200
150 #define UART_THE 0x400
154 static char fname
[256];
155 static int32 find
= 0;
156 static uint32 mec_ssa
[2]; /* Write protection start address */
157 static uint32 mec_sea
[2]; /* Write protection end address */
158 static uint32 mec_wpr
[2]; /* Write protection control fields */
159 static uint32 mec_sfsr
;
160 static uint32 mec_ffar
;
161 static uint32 mec_ipr
;
162 static uint32 mec_imr
;
163 static uint32 mec_isr
;
164 static uint32 mec_icr
;
165 static uint32 mec_ifr
;
166 static uint32 mec_mcr
; /* MEC control register */
167 static uint32 mec_memcfg
; /* Memory control register */
168 static uint32 mec_wcr
; /* MEC waitstate register */
169 static uint32 mec_iocr
; /* MEC IO control register */
170 static uint32 posted_irq
;
171 static uint32 mec_ersr
; /* MEC error and status register */
172 static uint32 mec_tcr
; /* MEC test comtrol register */
174 static uint32 rtc_counter
;
175 static uint32 rtc_reload
;
176 static uint32 rtc_scaler
;
177 static uint32 rtc_scaler_start
;
178 static uint32 rtc_enabled
;
179 static uint32 rtc_cr
;
180 static uint32 rtc_se
;
182 static uint32 gpt_counter
;
183 static uint32 gpt_reload
;
184 static uint32 gpt_scaler
;
185 static uint32 gpt_scaler_start
;
186 static uint32 gpt_enabled
;
187 static uint32 gpt_cr
;
188 static uint32 gpt_se
;
190 static uint32 wdog_scaler
;
191 static uint32 wdog_counter
;
192 static uint32 wdog_rst_delay
;
193 static uint32 wdog_rston
;
196 init
, disabled
, enabled
, stopped
199 static enum wdog_type wdog_status
;
202 /* ROM size 1024 Kbyte */
203 #define ROM_SZ 0x100000
204 #define ROM_MASK 0x0fffff
206 /* RAM size 4 Mbyte */
207 #define RAM_START 0x02000000
208 #define RAM_END 0x02400000
209 #define RAM_MASK 0x003fffff
211 /* SPARClite boards all seem to have RAM at the same place. */
212 #define RAM_START_SLITE 0x40000000
213 #define RAM_END_SLITE 0x40400000
214 #define RAM_MASK_SLITE 0x003fffff
216 /* Memory support variables */
218 static uint32 mem_ramr_ws
; /* RAM read waitstates */
219 static uint32 mem_ramw_ws
; /* RAM write waitstates */
220 static uint32 mem_romr_ws
; /* ROM read waitstates */
221 static uint32 mem_romw_ws
; /* ROM write waitstates */
222 static uint32 mem_ramstart
; /* RAM start */
223 static uint32 mem_ramend
; /* RAM end */
224 static uint32 mem_rammask
; /* RAM address mask */
225 static uint32 mem_ramsz
; /* RAM size */
226 static uint32 mem_romsz
; /* ROM size */
227 static uint32 mem_accprot
; /* RAM write protection enabled */
228 static uint32 mem_blockprot
; /* RAM block write protection enabled */
230 static unsigned char romb
[ROM_SZ
];
231 static unsigned char ramb
[RAM_END
- RAM_START
];
234 /* UART support variables */
236 static int32 fd1
, fd2
; /* file descriptor for input file */
237 static int32 Ucontrol
; /* UART status register */
238 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
239 static int32 anum
, aind
= 0;
240 static int32 bnum
, bind
= 0;
241 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
242 static unsigned wnuma
;
243 static unsigned wnumb
;
244 static FILE *f1in
, *f1out
, *f2in
, *f2out
;
245 static struct termios ioc1
, ioc2
, iocold1
, iocold2
;
246 static int f1open
= 0, f2open
= 0;
248 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
249 static uint32 uart_stat_reg
;
250 static uint32 uarta_data
, uartb_data
;
257 /* Forward declarations */
259 static void decode_ersr (void);
261 static void iucomperr (void);
263 static void mecparerror (void);
264 static void decode_memcfg (void);
265 static void decode_wcr (void);
266 static void decode_mcr (void);
267 static void close_port (void);
268 static void mec_reset (void);
269 static void mec_intack (int32 level
);
270 static void chk_irq (void);
271 static void mec_irq (int32 level
);
272 static void set_sfsr (uint32 fault
, uint32 addr
,
273 uint32 asi
, uint32 read
);
274 static int32
mec_read (uint32 addr
, uint32 asi
, uint32
*data
);
275 static int mec_write (uint32 addr
, uint32 data
);
276 static void port_init (void);
277 static uint32
read_uart (uint32 addr
);
278 static void write_uart (uint32 addr
, uint32 data
);
279 static void flush_uart (void);
280 static void uarta_tx (void);
281 static void uartb_tx (void);
282 static void uart_rx (caddr_t arg
);
283 static void uart_intr (caddr_t arg
);
284 static void uart_irq_start (void);
285 static void wdog_intr (caddr_t arg
);
286 static void wdog_start (void);
287 static void rtc_intr (caddr_t arg
);
288 static void rtc_start (void);
289 static uint32
rtc_counter_read (void);
290 static void rtc_scaler_set (uint32 val
);
291 static void rtc_reload_set (uint32 val
);
292 static void gpt_intr (caddr_t arg
);
293 static void gpt_start (void);
294 static uint32
gpt_counter_read (void);
295 static void gpt_scaler_set (uint32 val
);
296 static void gpt_reload_set (uint32 val
);
297 static void timer_ctrl (uint32 val
);
298 static unsigned char *
299 get_mem_ptr (uint32 addr
, uint32 size
);
301 static void fetch_bytes (int asi
, unsigned char *mem
,
302 uint32
*data
, int sz
);
304 static void store_bytes (unsigned char *mem
, uint32
*data
, int sz
);
317 /* Power-on reset init */
330 if (mec_ersr
& 0x01) {
331 if (!(mec_mcr
& 0x20)) {
332 if (mec_mcr
& 0x40) {
336 printf("Error manager reset - IU in error mode\n");
341 printf("Error manager halt - IU in error mode\n");
346 if (mec_ersr
& 0x04) {
347 if (!(mec_mcr
& 0x200)) {
348 if (mec_mcr
& 0x400) {
352 printf("Error manager reset - IU comparison error\n");
357 printf("Error manager halt - IU comparison error\n");
362 if (mec_ersr
& 0x20) {
363 if (!(mec_mcr
& 0x2000)) {
364 if (mec_mcr
& 0x4000) {
368 printf("Error manager reset - MEC hardware error\n");
373 printf("Error manager halt - MEC hardware error\n");
397 /* IU error mode manager */
409 /* Check memory settings */
414 if (rom8
) mec_memcfg
&= ~0x20000;
415 else mec_memcfg
|= 0x20000;
417 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
418 mem_romsz
= (128 * 1024) << ((mec_memcfg
>> 18) & 7);
420 if (sparclite_board
) {
421 mem_ramstart
= RAM_START_SLITE
;
422 mem_ramend
= RAM_END_SLITE
;
423 mem_rammask
= RAM_MASK_SLITE
;
426 mem_ramstart
= RAM_START
;
427 mem_ramend
= RAM_END
;
428 mem_rammask
= RAM_MASK
;
431 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
432 mem_ramstart
, mem_ramsz
>> 10, mem_romsz
>> 10);
438 mem_ramr_ws
= mec_wcr
& 3;
439 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
440 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
442 if (mem_romr_ws
> 0 ) mem_romr_ws
--;
443 mem_romr_ws
= 5 + (4*mem_romr_ws
);
445 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
447 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
448 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
454 mem_accprot
= (mec_wpr
[0] | mec_wpr
[1]);
455 mem_blockprot
= (mec_mcr
>> 3) & 1;
456 if (sis_verbose
&& mem_accprot
)
457 printf("Memory block write protection enabled\n");
458 if (mec_mcr
& 0x08000) {
462 if (sis_verbose
&& (mec_mcr
& 2))
463 printf("Software reset enabled\n");
464 if (sis_verbose
&& (mec_mcr
& 1))
465 printf("Power-down mode enabled\n");
468 /* Flush ports when simulator stops */
479 sim_stop(SIM_DESC sd
)
488 if (f1open
&& f1in
!= stdin
)
490 if (f2open
&& f2in
!= stdin
)
506 for (i
= 0; i
< 2; i
++)
507 mec_ssa
[i
] = mec_sea
[i
] = mec_wpr
[i
] = 0;
508 mec_mcr
= 0x01350014;
517 mec_memcfg
= 0x10000;
519 mec_ersr
= 0; /* MEC error and status register */
520 mec_tcr
= 0; /* MEC test comtrol register */
528 anum
= aind
= bnum
= bind
= 0;
530 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
531 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
533 rtc_counter
= 0xffffffff;
534 rtc_reload
= 0xffffffff;
540 gpt_counter
= 0xffffffff;
541 gpt_reload
= 0xffffffff;
548 wdog_rst_delay
= 255;
549 wdog_counter
= 0xffff;
568 printf("interrupt %d acknowledged\n", level
);
569 irq_test
= mec_tcr
& 0x80000;
570 if ((irq_test
) && (mec_ifr
& (1 << level
)))
571 mec_ifr
&= ~(1 << level
);
573 mec_ipr
&= ~(1 << level
);
585 if (mec_tcr
& 0x80000) itmp
= mec_ifr
;
587 itmp
= ((mec_ipr
| itmp
) & ~mec_imr
) & 0x0fffe;
590 for (i
= 15; i
> 0; i
--) {
591 if (((itmp
>> i
) & 1) != 0) {
592 if ((sis_verbose
) && (i
> old_irl
))
593 printf("IU irl: %d\n", i
);
595 set_int(i
, mec_intack
, i
);
606 mec_ipr
|= (1 << level
);
611 set_sfsr(fault
, addr
, asi
, read
)
617 if ((asi
== 0xa) || (asi
== 0xb)) {
619 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
620 mec_sfsr
|= ((mec_sfsr
& 1) ^ 1) | (mec_sfsr
& 1);
633 mec_read(addr
, asi
, data
)
639 switch (addr
& 0x0ff) {
641 case MEC_MCR
: /* 0x00 */
645 case MEC_MEMCFG
: /* 0x10 */
650 *data
= mec_iocr
; /* 0x14 */
653 case MEC_SSA1
: /* 0x20 */
654 *data
= mec_ssa
[0] | (mec_wpr
[0] << 23);
656 case MEC_SEA1
: /* 0x24 */
659 case MEC_SSA2
: /* 0x28 */
660 *data
= mec_ssa
[1] | (mec_wpr
[1] << 23);
662 case MEC_SEA2
: /* 0x2c */
666 case MEC_ISR
: /* 0x44 */
670 case MEC_IPR
: /* 0x48 */
674 case MEC_IMR
: /* 0x4c */
678 case MEC_IFR
: /* 0x54 */
682 case MEC_RTC_COUNTER
: /* 0x80 */
683 *data
= rtc_counter_read();
685 case MEC_RTC_SCALER
: /* 0x84 */
687 *data
= rtc_scaler
- (now() - rtc_scaler_start
);
692 case MEC_GPT_COUNTER
: /* 0x88 */
693 *data
= gpt_counter_read();
696 case MEC_GPT_SCALER
: /* 0x8c */
698 *data
= gpt_scaler
- (now() - gpt_scaler_start
);
704 case MEC_SFSR
: /* 0xA0 */
708 case MEC_FFAR
: /* 0xA4 */
715 strcpy(fname
, "simload");
716 find
= bfd_load(fname
);
724 case MEC_ERSR
: /* 0xB0 */
728 case MEC_TCR
: /* 0xD0 */
732 case MEC_UARTA
: /* 0xE0 */
733 case MEC_UARTB
: /* 0xE4 */
735 set_sfsr(MEC_ACC
, addr
, asi
, 1);
738 *data
= read_uart(addr
);
741 case MEC_UART_CTRL
: /* 0xE8 */
743 *data
= read_uart(addr
);
746 case 0xF4: /* simulator RAM size in bytes */
750 case 0xF8: /* simulator ROM size in bytes */
755 set_sfsr(MEC_ACC
, addr
, asi
, 1);
763 mec_write(addr
, data
)
768 printf("MEC write a: %08x, d: %08x\n",addr
,data
);
769 switch (addr
& 0x0ff) {
774 if (mec_mcr
& 0x08000) mecparerror();
782 printf(" Software reset issued\n");
788 if (mec_iocr
& 0xC0C0C0C0) mecparerror();
791 case MEC_SSA1
: /* 0x20 */
792 if (data
& 0xFE000000) mecparerror();
793 mec_ssa
[0] = data
& 0x7fffff;
794 mec_wpr
[0] = (data
>> 23) & 0x03;
795 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
796 if (sis_verbose
&& mec_wpr
[0])
797 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
798 mec_ssa
[0] << 2, mec_sea
[0] << 2);
800 case MEC_SEA1
: /* 0x24 */
801 if (data
& 0xFF800000) mecparerror();
802 mec_sea
[0] = data
& 0x7fffff;
804 case MEC_SSA2
: /* 0x28 */
805 if (data
& 0xFE000000) mecparerror();
806 mec_ssa
[1] = data
& 0x7fffff;
807 mec_wpr
[1] = (data
>> 23) & 0x03;
808 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
809 if (sis_verbose
&& mec_wpr
[1])
810 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
811 mec_ssa
[1] << 2, mec_sea
[1] << 2);
813 case MEC_SEA2
: /* 0x2c */
814 if (data
& 0xFF800000) mecparerror();
815 mec_sea
[1] = data
& 0x7fffff;
820 if (data
& 0xFFFFFF00) mecparerror();
822 if (data
& 0xFF00FF00) mecparerror();
823 write_uart(addr
, data
);
827 gpt_reload_set(data
);
831 if (data
& 0xFFFF0000) mecparerror();
832 gpt_scaler_set(data
);
836 if (data
& 0xFFFFF0F0) mecparerror();
841 rtc_reload_set(data
);
845 if (data
& 0xFFFFFF00) mecparerror();
846 rtc_scaler_set(data
);
849 case MEC_SFSR
: /* 0xA0 */
850 if (data
& 0xFFFF0880) mecparerror();
855 if (data
& 0xFFFFE000) mecparerror();
859 case MEC_IMR
: /* 0x4c */
861 if (data
& 0xFFFF8001) mecparerror();
862 mec_imr
= data
& 0x7ffe;
866 case MEC_ICR
: /* 0x50 */
868 if (data
& 0xFFFF0001) mecparerror();
869 mec_ipr
&= ~data
& 0x0fffe;
873 case MEC_IFR
: /* 0x54 */
875 if (mec_tcr
& 0x080000) {
876 if (data
& 0xFFFF0001) mecparerror();
877 mec_ifr
= data
& 0xfffe;
882 fname
[find
++] = (char) data
;
886 case MEC_MEMCFG
: /* 0x10 */
887 if (data
& 0xC0E08000) mecparerror();
890 if (mec_memcfg
& 0xc0e08000)
894 case MEC_WCR
: /* 0x18 */
899 case MEC_ERSR
: /* 0xB0 */
900 if (mec_tcr
& 0x100000)
901 if (data
& 0xFFFFEFC0) mecparerror();
902 mec_ersr
= data
& 0x103f;
905 case MEC_TCR
: /* 0xD0 */
906 if (data
& 0xFFE1FFC0) mecparerror();
907 mec_tcr
= data
& 0x1e003f;
910 case MEC_WDOG
: /* 0x60 */
911 wdog_scaler
= (data
>> 16) & 0x0ff;
912 wdog_counter
= data
& 0x0ffff;
913 wdog_rst_delay
= data
>> 24;
915 if (wdog_status
== stopped
)
917 wdog_status
= enabled
;
920 case MEC_TRAPD
: /* 0x64 */
921 if (wdog_status
== init
) {
922 wdog_status
= disabled
;
924 printf("Watchdog disabled\n");
934 set_sfsr(MEC_ACC
, addr
, 0xb, 0);
944 static int ifd1
= -1, ifd2
= -1, ofd1
= -1, ofd2
= -1;
950 return; /* do nothing */
952 tcsetattr(0, TCSANOW
, &ioc1
);
954 tcsetattr(0, TCSANOW
, &ioc2
);
961 return; /* do nothing */
963 tcsetattr(0, TCSANOW
, &iocold1
);
965 tcsetattr(0, TCSANOW
, &iocold2
);
968 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
970 ? (0) /* no bytes read, no delay */ \
971 : read( _fd_, _buf_, _len_ ) )
989 if (uart_dev1
[0] != 0)
990 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NONBLOCK
)) < 0) {
991 printf("Warning, couldn't open output device %s\n", uart_dev1
);
994 printf("serial port A on %s\n", uart_dev1
);
995 f1in
= f1out
= fdopen(fd1
, "r+");
999 if (f1in
) ifd1
= fileno(f1in
);
1002 printf("serial port A on stdin/stdout\n");
1004 tcgetattr(ifd1
, &ioc1
);
1006 ioc1
.c_lflag
&= ~(ICANON
| ECHO
);
1007 ioc1
.c_cc
[VMIN
] = 0;
1008 ioc1
.c_cc
[VTIME
] = 0;
1014 ofd1
= fileno(f1out
);
1015 if (!dumbio
&& ofd1
== 1) setbuf(f1out
, NULL
);
1018 if (uart_dev2
[0] != 0)
1019 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NONBLOCK
)) < 0) {
1020 printf("Warning, couldn't open output device %s\n", uart_dev2
);
1023 printf("serial port B on %s\n", uart_dev2
);
1024 f2in
= f2out
= fdopen(fd2
, "r+");
1025 setbuf(f2out
, NULL
);
1028 if (f2in
) ifd2
= fileno(f2in
);
1031 printf("serial port B on stdin/stdout\n");
1033 tcgetattr(ifd2
, &ioc2
);
1035 ioc2
.c_lflag
&= ~(ICANON
| ECHO
);
1036 ioc2
.c_cc
[VMIN
] = 0;
1037 ioc2
.c_cc
[VTIME
] = 0;
1043 ofd2
= fileno(f2out
);
1044 if (!dumbio
&& ofd2
== 1) setbuf(f2out
, NULL
);
1059 switch (addr
& 0xff) {
1061 case 0xE0: /* UART 1 */
1066 if ((aind
+ 1) < anum
)
1068 return (0x700 | (uint32
) aq
[aind
++]);
1071 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1075 if ((aind
+ 1) < anum
)
1077 return (0x700 | (uint32
) aq
[aind
++]);
1079 return (0x600 | (uint32
) aq
[aind
]);
1085 uarta_data
&= ~UART_DR
;
1086 uart_stat_reg
&= ~UARTA_DR
;
1094 case 0xE4: /* UART 2 */
1098 if ((bind
+ 1) < bnum
)
1100 return (0x700 | (uint32
) bq
[bind
++]);
1103 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1107 if ((bind
+ 1) < bnum
)
1109 return (0x700 | (uint32
) bq
[bind
++]);
1111 return (0x600 | (uint32
) bq
[bind
]);
1117 uartb_data
&= ~UART_DR
;
1118 uart_stat_reg
&= ~UARTB_DR
;
1126 case 0xE8: /* UART status register */
1132 Ucontrol
|= 0x00000001;
1135 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1138 Ucontrol
|= 0x00000001;
1144 Ucontrol
|= 0x00010000;
1147 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1150 Ucontrol
|= 0x00010000;
1156 Ucontrol
|= 0x00060006;
1159 return (uart_stat_reg
);
1167 printf("Read from unimplemented MEC register (%x)\n", addr
);
1174 write_uart(addr
, data
)
1180 c
= (unsigned char) data
;
1181 switch (addr
& 0xff) {
1183 case 0xE0: /* UART A */
1186 if (wnuma
< UARTBUF
)
1190 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1196 if (uart_stat_reg
& UARTA_SRE
) {
1198 uart_stat_reg
&= ~UARTA_SRE
;
1199 event(uarta_tx
, 0, UART_TX_TIME
);
1202 uart_stat_reg
&= ~UARTA_HRE
;
1207 case 0xE4: /* UART B */
1210 if (wnumb
< UARTBUF
)
1214 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1220 if (uart_stat_reg
& UARTB_SRE
) {
1222 uart_stat_reg
&= ~UARTB_SRE
;
1223 event(uartb_tx
, 0, UART_TX_TIME
);
1226 uart_stat_reg
&= ~UARTB_HRE
;
1230 case 0xE8: /* UART status register */
1232 if (data
& UARTA_CLR
) {
1233 uart_stat_reg
&= 0xFFFF0000;
1234 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
1236 if (data
& UARTB_CLR
) {
1237 uart_stat_reg
&= 0x0000FFFF;
1238 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
1244 printf("Write to unimplemented MEC register (%x)\n", addr
);
1252 while (wnuma
&& f1open
)
1253 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1254 while (wnumb
&& f2open
)
1255 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1264 while (f1open
&& fwrite(&uarta_sreg
, 1, 1, f1out
) != 1);
1265 if (uart_stat_reg
& UARTA_HRE
) {
1266 uart_stat_reg
|= UARTA_SRE
;
1268 uarta_sreg
= uarta_hreg
;
1269 uart_stat_reg
|= UARTA_HRE
;
1270 event(uarta_tx
, 0, UART_TX_TIME
);
1278 while (f2open
&& fwrite(&uartb_sreg
, 1, 1, f2out
) != 1);
1279 if (uart_stat_reg
& UARTB_HRE
) {
1280 uart_stat_reg
|= UARTB_SRE
;
1282 uartb_sreg
= uartb_hreg
;
1283 uart_stat_reg
|= UARTB_HRE
;
1284 event(uartb_tx
, 0, UART_TX_TIME
);
1299 rsize
= DO_STDIO_READ(ifd1
, &rxd
, 1);
1301 uarta_data
= UART_DR
| rxd
;
1302 if (uart_stat_reg
& UARTA_HRE
)
1303 uarta_data
|= UART_THE
;
1304 if (uart_stat_reg
& UARTA_SRE
)
1305 uarta_data
|= UART_TSE
;
1306 if (uart_stat_reg
& UARTA_DR
) {
1307 uart_stat_reg
|= UARTA_OR
;
1308 mec_irq(7); /* UART error interrupt */
1310 uart_stat_reg
|= UARTA_DR
;
1315 rsize
= DO_STDIO_READ(ifd2
, &rxd
, 1);
1317 uartb_data
= UART_DR
| rxd
;
1318 if (uart_stat_reg
& UARTB_HRE
)
1319 uartb_data
|= UART_THE
;
1320 if (uart_stat_reg
& UARTB_SRE
)
1321 uartb_data
|= UART_TSE
;
1322 if (uart_stat_reg
& UARTB_DR
) {
1323 uart_stat_reg
|= UARTB_OR
;
1324 mec_irq(7); /* UART error interrupt */
1326 uart_stat_reg
|= UARTB_DR
;
1329 event(uart_rx
, 0, UART_RX_TIME
);
1336 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1337 flush_uart(); /* Flush UART ports */
1338 event(uart_intr
, 0, UART_FLUSH_TIME
);
1346 event(uart_intr
, 0, UART_FLUSH_TIME
);
1349 event(uart_rx
, 0, UART_RX_TIME
);
1360 if (wdog_status
== disabled
) {
1361 wdog_status
= stopped
;
1366 event(wdog_intr
, 0, wdog_scaler
+ 1);
1369 printf("Watchdog reset!\n");
1375 wdog_counter
= wdog_rst_delay
;
1376 event(wdog_intr
, 0, wdog_scaler
+ 1);
1385 event(wdog_intr
, 0, wdog_scaler
+ 1);
1387 printf("Watchdog started, scaler = %d, counter = %d\n",
1388 wdog_scaler
, wdog_counter
);
1399 if (rtc_counter
== 0) {
1403 rtc_counter
= rtc_reload
;
1409 event(rtc_intr
, 0, rtc_scaler
+ 1);
1410 rtc_scaler_start
= now();
1414 printf("RTC stopped\n\r");
1423 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1424 event(rtc_intr
, 0, rtc_scaler
+ 1);
1425 rtc_scaler_start
= now();
1432 return (rtc_counter
);
1439 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1453 if (gpt_counter
== 0) {
1456 gpt_counter
= gpt_reload
;
1462 event(gpt_intr
, 0, gpt_scaler
+ 1);
1463 gpt_scaler_start
= now();
1467 printf("GPT stopped\n\r");
1476 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1477 event(gpt_intr
, 0, gpt_scaler
+ 1);
1478 gpt_scaler_start
= now();
1485 return (gpt_counter
);
1492 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1507 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1508 if (val
& TCR_TCRCL
) {
1509 rtc_counter
= rtc_reload
;
1511 if (val
& TCR_TCRSL
) {
1513 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1514 if (rtc_se
&& (rtc_enabled
== 0))
1517 gpt_cr
= (val
& TCR_GACR
);
1518 if (val
& TCR_GACL
) {
1519 gpt_counter
= gpt_reload
;
1521 if (val
& TCR_GACL
) {
1523 gpt_se
= (val
& TCR_GASE
) >> 2;
1524 if (gpt_se
&& (gpt_enabled
== 0))
1529 /* Retrieve data from target memory. MEM points to location from which
1530 to read the data; DATA points to words where retrieved data will be
1531 stored in host byte order. SZ contains log(2) of the number of bytes
1532 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1533 or 3 (two words). */
1536 fetch_bytes (asi
, mem
, data
, sz
)
1542 if (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
1543 || asi
== 8 || asi
== 9) {
1546 data
[1] = (((uint32
) mem
[7]) & 0xff) |
1547 ((((uint32
) mem
[6]) & 0xff) << 8) |
1548 ((((uint32
) mem
[5]) & 0xff) << 16) |
1549 ((((uint32
) mem
[4]) & 0xff) << 24);
1550 /* Fall through to 2 */
1552 data
[0] = (((uint32
) mem
[3]) & 0xff) |
1553 ((((uint32
) mem
[2]) & 0xff) << 8) |
1554 ((((uint32
) mem
[1]) & 0xff) << 16) |
1555 ((((uint32
) mem
[0]) & 0xff) << 24);
1558 data
[0] = (((uint32
) mem
[1]) & 0xff) |
1559 ((((uint32
) mem
[0]) & 0xff) << 8);
1562 data
[0] = mem
[0] & 0xff;
1569 data
[1] = ((((uint32
) mem
[7]) & 0xff) << 24) |
1570 ((((uint32
) mem
[6]) & 0xff) << 16) |
1571 ((((uint32
) mem
[5]) & 0xff) << 8) |
1572 (((uint32
) mem
[4]) & 0xff);
1573 /* Fall through to 4 */
1575 data
[0] = ((((uint32
) mem
[3]) & 0xff) << 24) |
1576 ((((uint32
) mem
[2]) & 0xff) << 16) |
1577 ((((uint32
) mem
[1]) & 0xff) << 8) |
1578 (((uint32
) mem
[0]) & 0xff);
1581 data
[0] = ((((uint32
) mem
[1]) & 0xff) << 8) |
1582 (((uint32
) mem
[0]) & 0xff);
1585 data
[0] = mem
[0] & 0xff;
1592 /* Store data in target byte order. MEM points to location to store data;
1593 DATA points to words in host byte order to be stored. SZ contains log(2)
1594 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1595 2 (one word), or 3 (two words). */
1598 store_bytes (mem
, data
, sz
)
1603 if (CURRENT_TARGET_BYTE_ORDER
== LITTLE_ENDIAN
) {
1606 mem
[7] = (data
[1] >> 24) & 0xff;
1607 mem
[6] = (data
[1] >> 16) & 0xff;
1608 mem
[5] = (data
[1] >> 8) & 0xff;
1609 mem
[4] = data
[1] & 0xff;
1610 /* Fall through to 2 */
1612 mem
[3] = (data
[0] >> 24) & 0xff;
1613 mem
[2] = (data
[0] >> 16) & 0xff;
1614 /* Fall through to 1 */
1616 mem
[1] = (data
[0] >> 8) & 0xff;
1617 /* Fall through to 0 */
1619 mem
[0] = data
[0] & 0xff;
1625 mem
[7] = data
[1] & 0xff;
1626 mem
[6] = (data
[1] >> 8) & 0xff;
1627 mem
[5] = (data
[1] >> 16) & 0xff;
1628 mem
[4] = (data
[1] >> 24) & 0xff;
1629 /* Fall through to 2 */
1631 mem
[3] = data
[0] & 0xff;
1632 mem
[2] = (data
[0] >> 8) & 0xff;
1633 mem
[1] = (data
[0] >> 16) & 0xff;
1634 mem
[0] = (data
[0] >> 24) & 0xff;
1637 mem
[1] = data
[0] & 0xff;
1638 mem
[0] = (data
[0] >> 8) & 0xff;
1641 mem
[0] = data
[0] & 0xff;
1649 /* Memory emulation */
1652 memory_read(asi
, addr
, data
, sz
, ws
)
1664 printf("Inserted MEC error %d\n",errmec
);
1665 set_sfsr(errmec
, addr
, asi
, 1);
1666 if (errmec
== 5) mecparerror();
1667 if (errmec
== 6) iucomperr();
1673 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1674 fetch_bytes (asi
, &ramb
[addr
& mem_rammask
], data
, sz
);
1677 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1678 mexc
= mec_read(addr
, asi
, data
);
1680 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1690 if ((addr
< 0x100000) ||
1691 ((addr
>= 0x80000000) && (addr
< 0x80100000))) {
1692 fetch_bytes (asi
, &romb
[addr
& ROM_MASK
], data
, sz
);
1695 } else if ((addr
>= 0x10000000) &&
1696 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1697 (mec_iocr
& 0x10)) {
1702 } else if (addr
< mem_romsz
) {
1703 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1708 } else if (addr
< mem_romsz
) {
1709 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1716 printf("Memory exception at %x (illegal address)\n", addr
);
1717 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1723 memory_write(asi
, addr
, data
, sz
, ws
)
1741 printf("Inserted MEC error %d\n",errmec
);
1742 set_sfsr(errmec
, addr
, asi
, 0);
1743 if (errmec
== 5) mecparerror();
1744 if (errmec
== 6) iucomperr();
1750 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1753 waddr
= (addr
& 0x7fffff) >> 2;
1754 for (i
= 0; i
< 2; i
++)
1756 (((asi
== 0xa) && (mec_wpr
[i
] & 1)) ||
1757 ((asi
== 0xb) && (mec_wpr
[i
] & 2))) &&
1758 ((waddr
>= mec_ssa
[i
]) && ((waddr
| (sz
== 3)) < mec_sea
[i
]));
1760 if (((mem_blockprot
) && (wphit
[0] || wphit
[1])) ||
1761 ((!mem_blockprot
) &&
1762 !((mec_wpr
[0] && wphit
[0]) || (mec_wpr
[1] && wphit
[1]))
1765 printf("Memory access protection error at 0x%08x\n", addr
);
1766 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1772 store_bytes (&ramb
[addr
& mem_rammask
], data
, sz
);
1777 *ws
= mem_ramw_ws
+ 3;
1783 *ws
= 2 * mem_ramw_ws
+ STD_WS
;
1787 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1788 if ((sz
!= 2) || (asi
!= 0xb)) {
1789 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1793 mexc
= mec_write(addr
, *data
);
1795 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1806 ((addr
< 0x100000) || ((addr
>= 0x80000000) && (addr
< 0x80100000)))) {
1808 *ws
= sz
== 3 ? 8 : 4;
1809 store_bytes (&romb
[addr
], data
, sz
);
1811 } else if ((addr
>= 0x10000000) &&
1812 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1813 (mec_iocr
& 0x10)) {
1814 erareg
= *data
& 0x0e;
1818 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1819 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1820 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1822 *ws
= mem_romw_ws
+ 1;
1824 *ws
+= mem_romw_ws
+ STD_WS
;
1825 store_bytes (&romb
[addr
], data
, sz
);
1829 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1830 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1831 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1833 *ws
= mem_romw_ws
+ 1;
1835 *ws
+= mem_romw_ws
+ STD_WS
;
1836 store_bytes (&romb
[addr
], data
, sz
);
1844 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1848 static unsigned char *
1849 get_mem_ptr(addr
, size
)
1853 if ((addr
+ size
) < ROM_SZ
) {
1854 return (&romb
[addr
]);
1855 } else if ((addr
>= mem_ramstart
) && ((addr
+ size
) < mem_ramend
)) {
1856 return (&ramb
[addr
& mem_rammask
]);
1860 else if ((era
) && ((addr
<0x100000) ||
1861 ((addr
>= (unsigned) 0x80000000) && ((addr
+ size
) < (unsigned) 0x80100000)))) {
1862 return (&romb
[addr
& ROM_MASK
]);
1866 return ((char *) -1);
1870 sis_memory_write(addr
, data
, length
)
1872 const unsigned char *data
;
1877 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1880 memcpy(mem
, data
, length
);
1885 sis_memory_read(addr
, data
, length
)
1892 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1895 memcpy(data
, mem
, length
);
1899 extern struct pstate sregs
;
1904 mec_write(MEC_WCR
, 0); /* zero waitstates */
1905 mec_write(MEC_TRAPD
, 0); /* turn off watch-dog */
1906 mec_write(MEC_RTC_SCALER
, sregs
.freq
- 1); /* generate 1 MHz RTC tick */
1907 mec_write(MEC_MEMCFG
, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1909 sregs
.psr
= 0x110010e0;
1910 sregs
.r
[30] = RAM_END
;
1911 sregs
.r
[14] = sregs
.r
[30] - 96 * 4;
1912 mec_mcr
|= 1; /* power-down enabled */