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[sim] Update old contact info in GPL license notices
[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
1 /*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 */
21
22 /* The control space devices */
23
24 #include "config.h"
25 #include <sys/types.h>
26 #include <stdio.h>
27 #include <string.h>
28 #include <termios.h>
29 #include <sys/fcntl.h>
30 #include <sys/file.h>
31 #include <unistd.h>
32 #include "sis.h"
33 #include "end.h"
34 #include "sim-config.h"
35
36 extern int ctrl_c;
37 extern int32 sis_verbose;
38 extern int32 sparclite, sparclite_board;
39 extern int rom8,wrp,uben;
40 extern char uart_dev1[], uart_dev2[];
41
42 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
43
44 /* MEC registers */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
47
48 /* Memory exception waitstates */
49 #define MEM_EX_WS 1
50
51 /* ERC32 always adds one waitstate during RAM std */
52 #define STD_WS 1
53
54 #ifdef ERRINJ
55 extern int errmec;
56 #endif
57
58 /* The target's byte order is big-endian by default until we load a
59 little-endian program. */
60
61 int current_target_byte_order = BIG_ENDIAN;
62
63 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
64 #define MOK 0
65
66 /* MEC register addresses */
67
68 #define MEC_MCR 0x000
69 #define MEC_SFR 0x004
70 #define MEC_PWDR 0x008
71 #define MEC_MEMCFG 0x010
72 #define MEC_IOCR 0x014
73 #define MEC_WCR 0x018
74
75 #define MEC_MAR0 0x020
76 #define MEC_MAR1 0x024
77
78 #define MEC_SSA1 0x020
79 #define MEC_SEA1 0x024
80 #define MEC_SSA2 0x028
81 #define MEC_SEA2 0x02C
82 #define MEC_ISR 0x044
83 #define MEC_IPR 0x048
84 #define MEC_IMR 0x04C
85 #define MEC_ICR 0x050
86 #define MEC_IFR 0x054
87 #define MEC_WDOG 0x060
88 #define MEC_TRAPD 0x064
89 #define MEC_RTC_COUNTER 0x080
90 #define MEC_RTC_RELOAD 0x080
91 #define MEC_RTC_SCALER 0x084
92 #define MEC_GPT_COUNTER 0x088
93 #define MEC_GPT_RELOAD 0x088
94 #define MEC_GPT_SCALER 0x08C
95 #define MEC_TIMER_CTRL 0x098
96 #define MEC_SFSR 0x0A0
97 #define MEC_FFAR 0x0A4
98 #define MEC_ERSR 0x0B0
99 #define MEC_DBG 0x0C0
100 #define MEC_TCR 0x0D0
101
102 #define MEC_BRK 0x0C4
103 #define MEC_WPR 0x0C8
104
105 #define MEC_UARTA 0x0E0
106 #define MEC_UARTB 0x0E4
107 #define MEC_UART_CTRL 0x0E8
108 #define SIM_LOAD 0x0F0
109
110 /* Memory exception causes */
111 #define PROT_EXC 0x3
112 #define UIMP_ACC 0x4
113 #define MEC_ACC 0x6
114 #define WATCH_EXC 0xa
115 #define BREAK_EXC 0xb
116
117 /* Size of UART buffers (bytes) */
118 #define UARTBUF 1024
119
120 /* Number of simulator ticks between flushing the UARTS. */
121 /* For good performance, keep above 1000 */
122 #define UART_FLUSH_TIME 3000
123
124 /* MEC timer control register bits */
125 #define TCR_GACR 1
126 #define TCR_GACL 2
127 #define TCR_GASE 4
128 #define TCR_GASL 8
129 #define TCR_TCRCR 0x100
130 #define TCR_TCRCL 0x200
131 #define TCR_TCRSE 0x400
132 #define TCR_TCRSL 0x800
133
134 /* New uart defines */
135 #define UART_TX_TIME 1000
136 #define UART_RX_TIME 1000
137 #define UARTA_DR 0x1
138 #define UARTA_SRE 0x2
139 #define UARTA_HRE 0x4
140 #define UARTA_OR 0x40
141 #define UARTA_CLR 0x80
142 #define UARTB_DR 0x10000
143 #define UARTB_SRE 0x20000
144 #define UARTB_HRE 0x40000
145 #define UARTB_OR 0x400000
146 #define UARTB_CLR 0x800000
147
148 #define UART_DR 0x100
149 #define UART_TSE 0x200
150 #define UART_THE 0x400
151
152 /* MEC registers */
153
154 static char fname[256];
155 static int32 find = 0;
156 static uint32 mec_ssa[2]; /* Write protection start address */
157 static uint32 mec_sea[2]; /* Write protection end address */
158 static uint32 mec_wpr[2]; /* Write protection control fields */
159 static uint32 mec_sfsr;
160 static uint32 mec_ffar;
161 static uint32 mec_ipr;
162 static uint32 mec_imr;
163 static uint32 mec_isr;
164 static uint32 mec_icr;
165 static uint32 mec_ifr;
166 static uint32 mec_mcr; /* MEC control register */
167 static uint32 mec_memcfg; /* Memory control register */
168 static uint32 mec_wcr; /* MEC waitstate register */
169 static uint32 mec_iocr; /* MEC IO control register */
170 static uint32 posted_irq;
171 static uint32 mec_ersr; /* MEC error and status register */
172 static uint32 mec_tcr; /* MEC test comtrol register */
173
174 static uint32 rtc_counter;
175 static uint32 rtc_reload;
176 static uint32 rtc_scaler;
177 static uint32 rtc_scaler_start;
178 static uint32 rtc_enabled;
179 static uint32 rtc_cr;
180 static uint32 rtc_se;
181
182 static uint32 gpt_counter;
183 static uint32 gpt_reload;
184 static uint32 gpt_scaler;
185 static uint32 gpt_scaler_start;
186 static uint32 gpt_enabled;
187 static uint32 gpt_cr;
188 static uint32 gpt_se;
189
190 static uint32 wdog_scaler;
191 static uint32 wdog_counter;
192 static uint32 wdog_rst_delay;
193 static uint32 wdog_rston;
194
195 enum wdog_type {
196 init, disabled, enabled, stopped
197 };
198
199 static enum wdog_type wdog_status;
200
201
202 /* ROM size 1024 Kbyte */
203 #define ROM_SZ 0x100000
204 #define ROM_MASK 0x0fffff
205
206 /* RAM size 4 Mbyte */
207 #define RAM_START 0x02000000
208 #define RAM_END 0x02400000
209 #define RAM_MASK 0x003fffff
210
211 /* SPARClite boards all seem to have RAM at the same place. */
212 #define RAM_START_SLITE 0x40000000
213 #define RAM_END_SLITE 0x40400000
214 #define RAM_MASK_SLITE 0x003fffff
215
216 /* Memory support variables */
217
218 static uint32 mem_ramr_ws; /* RAM read waitstates */
219 static uint32 mem_ramw_ws; /* RAM write waitstates */
220 static uint32 mem_romr_ws; /* ROM read waitstates */
221 static uint32 mem_romw_ws; /* ROM write waitstates */
222 static uint32 mem_ramstart; /* RAM start */
223 static uint32 mem_ramend; /* RAM end */
224 static uint32 mem_rammask; /* RAM address mask */
225 static uint32 mem_ramsz; /* RAM size */
226 static uint32 mem_romsz; /* ROM size */
227 static uint32 mem_accprot; /* RAM write protection enabled */
228 static uint32 mem_blockprot; /* RAM block write protection enabled */
229
230 static unsigned char romb[ROM_SZ];
231 static unsigned char ramb[RAM_END - RAM_START];
232
233
234 /* UART support variables */
235
236 static int32 fd1, fd2; /* file descriptor for input file */
237 static int32 Ucontrol; /* UART status register */
238 static unsigned char aq[UARTBUF], bq[UARTBUF];
239 static int32 anum, aind = 0;
240 static int32 bnum, bind = 0;
241 static char wbufa[UARTBUF], wbufb[UARTBUF];
242 static unsigned wnuma;
243 static unsigned wnumb;
244 static FILE *f1in, *f1out, *f2in, *f2out;
245 static struct termios ioc1, ioc2, iocold1, iocold2;
246 static int f1open = 0, f2open = 0;
247
248 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
249 static uint32 uart_stat_reg;
250 static uint32 uarta_data, uartb_data;
251
252 #ifdef ERA
253 int era = 0;
254 int erareg;
255 #endif
256
257 /* Forward declarations */
258
259 static void decode_ersr PARAMS ((void));
260 #ifdef ERRINJ
261 static void iucomperr PARAMS ((void));
262 #endif
263 static void mecparerror PARAMS ((void));
264 static void decode_memcfg PARAMS ((void));
265 static void decode_wcr PARAMS ((void));
266 static void decode_mcr PARAMS ((void));
267 static void close_port PARAMS ((void));
268 static void mec_reset PARAMS ((void));
269 static void mec_intack PARAMS ((int32 level));
270 static void chk_irq PARAMS ((void));
271 static void mec_irq PARAMS ((int32 level));
272 static void set_sfsr PARAMS ((uint32 fault, uint32 addr,
273 uint32 asi, uint32 read));
274 static int32 mec_read PARAMS ((uint32 addr, uint32 asi, uint32 *data));
275 static int mec_write PARAMS ((uint32 addr, uint32 data));
276 static void port_init PARAMS ((void));
277 static uint32 read_uart PARAMS ((uint32 addr));
278 static void write_uart PARAMS ((uint32 addr, uint32 data));
279 static void flush_uart PARAMS ((void));
280 static void uarta_tx PARAMS ((void));
281 static void uartb_tx PARAMS ((void));
282 static void uart_rx PARAMS ((caddr_t arg));
283 static void uart_intr PARAMS ((caddr_t arg));
284 static void uart_irq_start PARAMS ((void));
285 static void wdog_intr PARAMS ((caddr_t arg));
286 static void wdog_start PARAMS ((void));
287 static void rtc_intr PARAMS ((caddr_t arg));
288 static void rtc_start PARAMS ((void));
289 static uint32 rtc_counter_read PARAMS ((void));
290 static void rtc_scaler_set PARAMS ((uint32 val));
291 static void rtc_reload_set PARAMS ((uint32 val));
292 static void gpt_intr PARAMS ((caddr_t arg));
293 static void gpt_start PARAMS ((void));
294 static uint32 gpt_counter_read PARAMS ((void));
295 static void gpt_scaler_set PARAMS ((uint32 val));
296 static void gpt_reload_set PARAMS ((uint32 val));
297 static void timer_ctrl PARAMS ((uint32 val));
298 static unsigned char *
299 get_mem_ptr PARAMS ((uint32 addr, uint32 size));
300
301 static void fetch_bytes PARAMS ((int asi, unsigned char *mem,
302 uint32 *data, int sz));
303
304 static void store_bytes PARAMS ((unsigned char *mem, uint32 *data, int sz));
305
306 extern int ext_irl;
307
308
309 /* One-time init */
310
311 void
312 init_sim()
313 {
314 port_init();
315 }
316
317 /* Power-on reset init */
318
319 void
320 reset()
321 {
322 mec_reset();
323 uart_irq_start();
324 wdog_start();
325 }
326
327 static void
328 decode_ersr()
329 {
330 if (mec_ersr & 0x01) {
331 if (!(mec_mcr & 0x20)) {
332 if (mec_mcr & 0x40) {
333 sys_reset();
334 mec_ersr = 0x8000;
335 if (sis_verbose)
336 printf("Error manager reset - IU in error mode\n");
337 } else {
338 sys_halt();
339 mec_ersr |= 0x2000;
340 if (sis_verbose)
341 printf("Error manager halt - IU in error mode\n");
342 }
343 } else
344 mec_irq(1);
345 }
346 if (mec_ersr & 0x04) {
347 if (!(mec_mcr & 0x200)) {
348 if (mec_mcr & 0x400) {
349 sys_reset();
350 mec_ersr = 0x8000;
351 if (sis_verbose)
352 printf("Error manager reset - IU comparison error\n");
353 } else {
354 sys_halt();
355 mec_ersr |= 0x2000;
356 if (sis_verbose)
357 printf("Error manager halt - IU comparison error\n");
358 }
359 } else
360 mec_irq(1);
361 }
362 if (mec_ersr & 0x20) {
363 if (!(mec_mcr & 0x2000)) {
364 if (mec_mcr & 0x4000) {
365 sys_reset();
366 mec_ersr = 0x8000;
367 if (sis_verbose)
368 printf("Error manager reset - MEC hardware error\n");
369 } else {
370 sys_halt();
371 mec_ersr |= 0x2000;
372 if (sis_verbose)
373 printf("Error manager halt - MEC hardware error\n");
374 }
375 } else
376 mec_irq(1);
377 }
378 }
379
380 #ifdef ERRINJ
381 static void
382 iucomperr()
383 {
384 mec_ersr |= 0x04;
385 decode_ersr();
386 }
387 #endif
388
389 static void
390 mecparerror()
391 {
392 mec_ersr |= 0x20;
393 decode_ersr();
394 }
395
396
397 /* IU error mode manager */
398
399 void
400 error_mode(pc)
401 uint32 pc;
402 {
403
404 mec_ersr |= 0x1;
405 decode_ersr();
406 }
407
408
409 /* Check memory settings */
410
411 static void
412 decode_memcfg()
413 {
414 if (rom8) mec_memcfg &= ~0x20000;
415 else mec_memcfg |= 0x20000;
416
417 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
418 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
419
420 if (sparclite_board) {
421 mem_ramstart = RAM_START_SLITE;
422 mem_ramend = RAM_END_SLITE;
423 mem_rammask = RAM_MASK_SLITE;
424 }
425 else {
426 mem_ramstart = RAM_START;
427 mem_ramend = RAM_END;
428 mem_rammask = RAM_MASK;
429 }
430 if (sis_verbose)
431 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
432 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
433 }
434
435 static void
436 decode_wcr()
437 {
438 mem_ramr_ws = mec_wcr & 3;
439 mem_ramw_ws = (mec_wcr >> 2) & 3;
440 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
441 if (rom8) {
442 if (mem_romr_ws > 0 ) mem_romr_ws--;
443 mem_romr_ws = 5 + (4*mem_romr_ws);
444 }
445 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
446 if (sis_verbose)
447 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
448 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
449 }
450
451 static void
452 decode_mcr()
453 {
454 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
455 mem_blockprot = (mec_mcr >> 3) & 1;
456 if (sis_verbose && mem_accprot)
457 printf("Memory block write protection enabled\n");
458 if (mec_mcr & 0x08000) {
459 mec_ersr |= 0x20;
460 decode_ersr();
461 }
462 if (sis_verbose && (mec_mcr & 2))
463 printf("Software reset enabled\n");
464 if (sis_verbose && (mec_mcr & 1))
465 printf("Power-down mode enabled\n");
466 }
467
468 /* Flush ports when simulator stops */
469
470 void
471 sim_halt()
472 {
473 #ifdef FAST_UART
474 flush_uart();
475 #endif
476 }
477
478 int
479 sim_stop(SIM_DESC sd)
480 {
481 ctrl_c = 1;
482 return 1;
483 }
484
485 static void
486 close_port()
487 {
488 if (f1open && f1in != stdin)
489 fclose(f1in);
490 if (f2open && f2in != stdin)
491 fclose(f2in);
492 }
493
494 void
495 exit_sim()
496 {
497 close_port();
498 }
499
500 static void
501 mec_reset()
502 {
503 int i;
504
505 find = 0;
506 for (i = 0; i < 2; i++)
507 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
508 mec_mcr = 0x01350014;
509 mec_iocr = 0;
510 mec_sfsr = 0x078;
511 mec_ffar = 0;
512 mec_ipr = 0;
513 mec_imr = 0x7ffe;
514 mec_isr = 0;
515 mec_icr = 0;
516 mec_ifr = 0;
517 mec_memcfg = 0x10000;
518 mec_wcr = -1;
519 mec_ersr = 0; /* MEC error and status register */
520 mec_tcr = 0; /* MEC test comtrol register */
521
522 decode_memcfg();
523 decode_wcr();
524 decode_mcr();
525
526 posted_irq = 0;
527 wnuma = wnumb = 0;
528 anum = aind = bnum = bind = 0;
529
530 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
531 uarta_data = uartb_data = UART_THE | UART_TSE;
532
533 rtc_counter = 0xffffffff;
534 rtc_reload = 0xffffffff;
535 rtc_scaler = 0xff;
536 rtc_enabled = 0;
537 rtc_cr = 0;
538 rtc_se = 0;
539
540 gpt_counter = 0xffffffff;
541 gpt_reload = 0xffffffff;
542 gpt_scaler = 0xffff;
543 gpt_enabled = 0;
544 gpt_cr = 0;
545 gpt_se = 0;
546
547 wdog_scaler = 255;
548 wdog_rst_delay = 255;
549 wdog_counter = 0xffff;
550 wdog_rston = 0;
551 wdog_status = init;
552
553 #ifdef ERA
554 erareg = 0;
555 #endif
556
557 }
558
559
560
561 static void
562 mec_intack(level)
563 int32 level;
564 {
565 int irq_test;
566
567 if (sis_verbose)
568 printf("interrupt %d acknowledged\n", level);
569 irq_test = mec_tcr & 0x80000;
570 if ((irq_test) && (mec_ifr & (1 << level)))
571 mec_ifr &= ~(1 << level);
572 else
573 mec_ipr &= ~(1 << level);
574 chk_irq();
575 }
576
577 static void
578 chk_irq()
579 {
580 int32 i;
581 uint32 itmp;
582 int old_irl;
583
584 old_irl = ext_irl;
585 if (mec_tcr & 0x80000) itmp = mec_ifr;
586 else itmp = 0;
587 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
588 ext_irl = 0;
589 if (itmp != 0) {
590 for (i = 15; i > 0; i--) {
591 if (((itmp >> i) & 1) != 0) {
592 if ((sis_verbose) && (i > old_irl))
593 printf("IU irl: %d\n", i);
594 ext_irl = i;
595 set_int(i, mec_intack, i);
596 break;
597 }
598 }
599 }
600 }
601
602 static void
603 mec_irq(level)
604 int32 level;
605 {
606 mec_ipr |= (1 << level);
607 chk_irq();
608 }
609
610 static void
611 set_sfsr(fault, addr, asi, read)
612 uint32 fault;
613 uint32 addr;
614 uint32 asi;
615 uint32 read;
616 {
617 if ((asi == 0xa) || (asi == 0xb)) {
618 mec_ffar = addr;
619 mec_sfsr = (fault << 3) | (!read << 15);
620 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
621 switch (asi) {
622 case 0xa:
623 mec_sfsr |= 0x0004;
624 break;
625 case 0xb:
626 mec_sfsr |= 0x1004;
627 break;
628 }
629 }
630 }
631
632 static int32
633 mec_read(addr, asi, data)
634 uint32 addr;
635 uint32 asi;
636 uint32 *data;
637 {
638
639 switch (addr & 0x0ff) {
640
641 case MEC_MCR: /* 0x00 */
642 *data = mec_mcr;
643 break;
644
645 case MEC_MEMCFG: /* 0x10 */
646 *data = mec_memcfg;
647 break;
648
649 case MEC_IOCR:
650 *data = mec_iocr; /* 0x14 */
651 break;
652
653 case MEC_SSA1: /* 0x20 */
654 *data = mec_ssa[0] | (mec_wpr[0] << 23);
655 break;
656 case MEC_SEA1: /* 0x24 */
657 *data = mec_sea[0];
658 break;
659 case MEC_SSA2: /* 0x28 */
660 *data = mec_ssa[1] | (mec_wpr[1] << 23);
661 break;
662 case MEC_SEA2: /* 0x2c */
663 *data = mec_sea[1];
664 break;
665
666 case MEC_ISR: /* 0x44 */
667 *data = mec_isr;
668 break;
669
670 case MEC_IPR: /* 0x48 */
671 *data = mec_ipr;
672 break;
673
674 case MEC_IMR: /* 0x4c */
675 *data = mec_imr;
676 break;
677
678 case MEC_IFR: /* 0x54 */
679 *data = mec_ifr;
680 break;
681
682 case MEC_RTC_COUNTER: /* 0x80 */
683 *data = rtc_counter_read();
684 break;
685 case MEC_RTC_SCALER: /* 0x84 */
686 if (rtc_enabled)
687 *data = rtc_scaler - (now() - rtc_scaler_start);
688 else
689 *data = rtc_scaler;
690 break;
691
692 case MEC_GPT_COUNTER: /* 0x88 */
693 *data = gpt_counter_read();
694 break;
695
696 case MEC_GPT_SCALER: /* 0x8c */
697 if (rtc_enabled)
698 *data = gpt_scaler - (now() - gpt_scaler_start);
699 else
700 *data = gpt_scaler;
701 break;
702
703
704 case MEC_SFSR: /* 0xA0 */
705 *data = mec_sfsr;
706 break;
707
708 case MEC_FFAR: /* 0xA4 */
709 *data = mec_ffar;
710 break;
711
712 case SIM_LOAD:
713 fname[find] = 0;
714 if (find == 0)
715 strcpy(fname, "simload");
716 find = bfd_load(fname);
717 if (find == -1)
718 *data = 0;
719 else
720 *data = 1;
721 find = 0;
722 break;
723
724 case MEC_ERSR: /* 0xB0 */
725 *data = mec_ersr;
726 break;
727
728 case MEC_TCR: /* 0xD0 */
729 *data = mec_tcr;
730 break;
731
732 case MEC_UARTA: /* 0xE0 */
733 case MEC_UARTB: /* 0xE4 */
734 if (asi != 0xb) {
735 set_sfsr(MEC_ACC, addr, asi, 1);
736 return (1);
737 }
738 *data = read_uart(addr);
739 break;
740
741 case MEC_UART_CTRL: /* 0xE8 */
742
743 *data = read_uart(addr);
744 break;
745
746 default:
747 set_sfsr(MEC_ACC, addr, asi, 1);
748 return (1);
749 break;
750 }
751 return (MOK);
752 }
753
754 static int
755 mec_write(addr, data)
756 uint32 addr;
757 uint32 data;
758 {
759 if (sis_verbose > 1)
760 printf("MEC write a: %08x, d: %08x\n",addr,data);
761 switch (addr & 0x0ff) {
762
763 case MEC_MCR:
764 mec_mcr = data;
765 decode_mcr();
766 if (mec_mcr & 0x08000) mecparerror();
767 break;
768
769 case MEC_SFR:
770 if (mec_mcr & 0x2) {
771 sys_reset();
772 mec_ersr = 0x4000;
773 if (sis_verbose)
774 printf(" Software reset issued\n");
775 }
776 break;
777
778 case MEC_IOCR:
779 mec_iocr = data;
780 if (mec_iocr & 0xC0C0C0C0) mecparerror();
781 break;
782
783 case MEC_SSA1: /* 0x20 */
784 if (data & 0xFE000000) mecparerror();
785 mec_ssa[0] = data & 0x7fffff;
786 mec_wpr[0] = (data >> 23) & 0x03;
787 mem_accprot = mec_wpr[0] || mec_wpr[1];
788 if (sis_verbose && mec_wpr[0])
789 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
790 mec_ssa[0] << 2, mec_sea[0] << 2);
791 break;
792 case MEC_SEA1: /* 0x24 */
793 if (data & 0xFF800000) mecparerror();
794 mec_sea[0] = data & 0x7fffff;
795 break;
796 case MEC_SSA2: /* 0x28 */
797 if (data & 0xFE000000) mecparerror();
798 mec_ssa[1] = data & 0x7fffff;
799 mec_wpr[1] = (data >> 23) & 0x03;
800 mem_accprot = mec_wpr[0] || mec_wpr[1];
801 if (sis_verbose && mec_wpr[1])
802 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
803 mec_ssa[1] << 2, mec_sea[1] << 2);
804 break;
805 case MEC_SEA2: /* 0x2c */
806 if (data & 0xFF800000) mecparerror();
807 mec_sea[1] = data & 0x7fffff;
808 break;
809
810 case MEC_UARTA:
811 case MEC_UARTB:
812 if (data & 0xFFFFFF00) mecparerror();
813 case MEC_UART_CTRL:
814 if (data & 0xFF00FF00) mecparerror();
815 write_uart(addr, data);
816 break;
817
818 case MEC_GPT_RELOAD:
819 gpt_reload_set(data);
820 break;
821
822 case MEC_GPT_SCALER:
823 if (data & 0xFFFF0000) mecparerror();
824 gpt_scaler_set(data);
825 break;
826
827 case MEC_TIMER_CTRL:
828 if (data & 0xFFFFF0F0) mecparerror();
829 timer_ctrl(data);
830 break;
831
832 case MEC_RTC_RELOAD:
833 rtc_reload_set(data);
834 break;
835
836 case MEC_RTC_SCALER:
837 if (data & 0xFFFFFF00) mecparerror();
838 rtc_scaler_set(data);
839 break;
840
841 case MEC_SFSR: /* 0xA0 */
842 if (data & 0xFFFF0880) mecparerror();
843 mec_sfsr = 0x78;
844 break;
845
846 case MEC_ISR:
847 if (data & 0xFFFFE000) mecparerror();
848 mec_isr = data;
849 break;
850
851 case MEC_IMR: /* 0x4c */
852
853 if (data & 0xFFFF8001) mecparerror();
854 mec_imr = data & 0x7ffe;
855 chk_irq();
856 break;
857
858 case MEC_ICR: /* 0x50 */
859
860 if (data & 0xFFFF0001) mecparerror();
861 mec_ipr &= ~data & 0x0fffe;
862 chk_irq();
863 break;
864
865 case MEC_IFR: /* 0x54 */
866
867 if (mec_tcr & 0x080000) {
868 if (data & 0xFFFF0001) mecparerror();
869 mec_ifr = data & 0xfffe;
870 chk_irq();
871 }
872 break;
873 case SIM_LOAD:
874 fname[find++] = (char) data;
875 break;
876
877
878 case MEC_MEMCFG: /* 0x10 */
879 if (data & 0xC0E08000) mecparerror();
880 mec_memcfg = data;
881 decode_memcfg();
882 if (mec_memcfg & 0xc0e08000)
883 mecparerror();
884 break;
885
886 case MEC_WCR: /* 0x18 */
887 mec_wcr = data;
888 decode_wcr();
889 break;
890
891 case MEC_ERSR: /* 0xB0 */
892 if (mec_tcr & 0x100000)
893 if (data & 0xFFFFEFC0) mecparerror();
894 mec_ersr = data & 0x103f;
895 break;
896
897 case MEC_TCR: /* 0xD0 */
898 if (data & 0xFFE1FFC0) mecparerror();
899 mec_tcr = data & 0x1e003f;
900 break;
901
902 case MEC_WDOG: /* 0x60 */
903 wdog_scaler = (data >> 16) & 0x0ff;
904 wdog_counter = data & 0x0ffff;
905 wdog_rst_delay = data >> 24;
906 wdog_rston = 0;
907 if (wdog_status == stopped)
908 wdog_start();
909 wdog_status = enabled;
910 break;
911
912 case MEC_TRAPD: /* 0x64 */
913 if (wdog_status == init) {
914 wdog_status = disabled;
915 if (sis_verbose)
916 printf("Watchdog disabled\n");
917 }
918 break;
919
920 case MEC_PWDR:
921 if (mec_mcr & 1)
922 wait_for_irq();
923 break;
924
925 default:
926 set_sfsr(MEC_ACC, addr, 0xb, 0);
927 return (1);
928 break;
929 }
930 return (MOK);
931 }
932
933
934 /* MEC UARTS */
935
936 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
937
938 void
939 init_stdio()
940 {
941 if (dumbio)
942 return; /* do nothing */
943 if (!ifd1)
944 tcsetattr(0, TCSANOW, &ioc1);
945 if (!ifd2)
946 tcsetattr(0, TCSANOW, &ioc2);
947 }
948
949 void
950 restore_stdio()
951 {
952 if (dumbio)
953 return; /* do nothing */
954 if (!ifd1)
955 tcsetattr(0, TCSANOW, &iocold1);
956 if (!ifd2)
957 tcsetattr(0, TCSANOW, &iocold2);
958 }
959
960 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
961 ( dumbio \
962 ? (0) /* no bytes read, no delay */ \
963 : read( _fd_, _buf_, _len_ ) )
964
965
966 static void
967 port_init()
968 {
969
970 if (uben) {
971 f2in = stdin;
972 f1in = NULL;
973 f2out = stdout;
974 f1out = NULL;
975 } else {
976 f1in = stdin;
977 f2in = NULL;
978 f1out = stdout;
979 f2out = NULL;
980 }
981 if (uart_dev1[0] != 0)
982 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
983 printf("Warning, couldn't open output device %s\n", uart_dev1);
984 } else {
985 if (sis_verbose)
986 printf("serial port A on %s\n", uart_dev1);
987 f1in = f1out = fdopen(fd1, "r+");
988 setbuf(f1out, NULL);
989 f1open = 1;
990 }
991 if (f1in) ifd1 = fileno(f1in);
992 if (ifd1 == 0) {
993 if (sis_verbose)
994 printf("serial port A on stdin/stdout\n");
995 if (!dumbio) {
996 tcgetattr(ifd1, &ioc1);
997 iocold1 = ioc1;
998 ioc1.c_lflag &= ~(ICANON | ECHO);
999 ioc1.c_cc[VMIN] = 0;
1000 ioc1.c_cc[VTIME] = 0;
1001 }
1002 f1open = 1;
1003 }
1004
1005 if (f1out) {
1006 ofd1 = fileno(f1out);
1007 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1008 }
1009
1010 if (uart_dev2[0] != 0)
1011 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1012 printf("Warning, couldn't open output device %s\n", uart_dev2);
1013 } else {
1014 if (sis_verbose)
1015 printf("serial port B on %s\n", uart_dev2);
1016 f2in = f2out = fdopen(fd2, "r+");
1017 setbuf(f2out, NULL);
1018 f2open = 1;
1019 }
1020 if (f2in) ifd2 = fileno(f2in);
1021 if (ifd2 == 0) {
1022 if (sis_verbose)
1023 printf("serial port B on stdin/stdout\n");
1024 if (!dumbio) {
1025 tcgetattr(ifd2, &ioc2);
1026 iocold2 = ioc2;
1027 ioc2.c_lflag &= ~(ICANON | ECHO);
1028 ioc2.c_cc[VMIN] = 0;
1029 ioc2.c_cc[VTIME] = 0;
1030 }
1031 f2open = 1;
1032 }
1033
1034 if (f2out) {
1035 ofd2 = fileno(f2out);
1036 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1037 }
1038
1039 wnuma = wnumb = 0;
1040
1041 }
1042
1043 static uint32
1044 read_uart(addr)
1045 uint32 addr;
1046 {
1047
1048 unsigned tmp;
1049
1050 tmp = 0;
1051 switch (addr & 0xff) {
1052
1053 case 0xE0: /* UART 1 */
1054 #ifndef _WIN32
1055 #ifdef FAST_UART
1056
1057 if (aind < anum) {
1058 if ((aind + 1) < anum)
1059 mec_irq(4);
1060 return (0x700 | (uint32) aq[aind++]);
1061 } else {
1062 if (f1open) {
1063 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1064 }
1065 if (anum > 0) {
1066 aind = 0;
1067 if ((aind + 1) < anum)
1068 mec_irq(4);
1069 return (0x700 | (uint32) aq[aind++]);
1070 } else {
1071 return (0x600 | (uint32) aq[aind]);
1072 }
1073
1074 }
1075 #else
1076 tmp = uarta_data;
1077 uarta_data &= ~UART_DR;
1078 uart_stat_reg &= ~UARTA_DR;
1079 return tmp;
1080 #endif
1081 #else
1082 return(0);
1083 #endif
1084 break;
1085
1086 case 0xE4: /* UART 2 */
1087 #ifndef _WIN32
1088 #ifdef FAST_UART
1089 if (bind < bnum) {
1090 if ((bind + 1) < bnum)
1091 mec_irq(5);
1092 return (0x700 | (uint32) bq[bind++]);
1093 } else {
1094 if (f2open) {
1095 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1096 }
1097 if (bnum > 0) {
1098 bind = 0;
1099 if ((bind + 1) < bnum)
1100 mec_irq(5);
1101 return (0x700 | (uint32) bq[bind++]);
1102 } else {
1103 return (0x600 | (uint32) bq[bind]);
1104 }
1105
1106 }
1107 #else
1108 tmp = uartb_data;
1109 uartb_data &= ~UART_DR;
1110 uart_stat_reg &= ~UARTB_DR;
1111 return tmp;
1112 #endif
1113 #else
1114 return(0);
1115 #endif
1116 break;
1117
1118 case 0xE8: /* UART status register */
1119 #ifndef _WIN32
1120 #ifdef FAST_UART
1121
1122 Ucontrol = 0;
1123 if (aind < anum) {
1124 Ucontrol |= 0x00000001;
1125 } else {
1126 if (f1open) {
1127 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1128 }
1129 if (anum > 0) {
1130 Ucontrol |= 0x00000001;
1131 aind = 0;
1132 mec_irq(4);
1133 }
1134 }
1135 if (bind < bnum) {
1136 Ucontrol |= 0x00010000;
1137 } else {
1138 if (f2open) {
1139 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1140 }
1141 if (bnum > 0) {
1142 Ucontrol |= 0x00010000;
1143 bind = 0;
1144 mec_irq(5);
1145 }
1146 }
1147
1148 Ucontrol |= 0x00060006;
1149 return (Ucontrol);
1150 #else
1151 return (uart_stat_reg);
1152 #endif
1153 #else
1154 return(0x00060006);
1155 #endif
1156 break;
1157 default:
1158 if (sis_verbose)
1159 printf("Read from unimplemented MEC register (%x)\n", addr);
1160
1161 }
1162 return (0);
1163 }
1164
1165 static void
1166 write_uart(addr, data)
1167 uint32 addr;
1168 uint32 data;
1169 {
1170 unsigned char c;
1171
1172 c = (unsigned char) data;
1173 switch (addr & 0xff) {
1174
1175 case 0xE0: /* UART A */
1176 #ifdef FAST_UART
1177 if (f1open) {
1178 if (wnuma < UARTBUF)
1179 wbufa[wnuma++] = c;
1180 else {
1181 while (wnuma)
1182 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1183 wbufa[wnuma++] = c;
1184 }
1185 }
1186 mec_irq(4);
1187 #else
1188 if (uart_stat_reg & UARTA_SRE) {
1189 uarta_sreg = c;
1190 uart_stat_reg &= ~UARTA_SRE;
1191 event(uarta_tx, 0, UART_TX_TIME);
1192 } else {
1193 uarta_hreg = c;
1194 uart_stat_reg &= ~UARTA_HRE;
1195 }
1196 #endif
1197 break;
1198
1199 case 0xE4: /* UART B */
1200 #ifdef FAST_UART
1201 if (f2open) {
1202 if (wnumb < UARTBUF)
1203 wbufb[wnumb++] = c;
1204 else {
1205 while (wnumb)
1206 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1207 wbufb[wnumb++] = c;
1208 }
1209 }
1210 mec_irq(5);
1211 #else
1212 if (uart_stat_reg & UARTB_SRE) {
1213 uartb_sreg = c;
1214 uart_stat_reg &= ~UARTB_SRE;
1215 event(uartb_tx, 0, UART_TX_TIME);
1216 } else {
1217 uartb_hreg = c;
1218 uart_stat_reg &= ~UARTB_HRE;
1219 }
1220 #endif
1221 break;
1222 case 0xE8: /* UART status register */
1223 #ifndef FAST_UART
1224 if (data & UARTA_CLR) {
1225 uart_stat_reg &= 0xFFFF0000;
1226 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1227 }
1228 if (data & UARTB_CLR) {
1229 uart_stat_reg &= 0x0000FFFF;
1230 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1231 }
1232 #endif
1233 break;
1234 default:
1235 if (sis_verbose)
1236 printf("Write to unimplemented MEC register (%x)\n", addr);
1237
1238 }
1239 }
1240
1241 static void
1242 flush_uart()
1243 {
1244 while (wnuma && f1open)
1245 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1246 while (wnumb && f2open)
1247 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1248 }
1249
1250
1251
1252 static void
1253 uarta_tx()
1254 {
1255
1256 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1257 if (uart_stat_reg & UARTA_HRE) {
1258 uart_stat_reg |= UARTA_SRE;
1259 } else {
1260 uarta_sreg = uarta_hreg;
1261 uart_stat_reg |= UARTA_HRE;
1262 event(uarta_tx, 0, UART_TX_TIME);
1263 }
1264 mec_irq(4);
1265 }
1266
1267 static void
1268 uartb_tx()
1269 {
1270 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1271 if (uart_stat_reg & UARTB_HRE) {
1272 uart_stat_reg |= UARTB_SRE;
1273 } else {
1274 uartb_sreg = uartb_hreg;
1275 uart_stat_reg |= UARTB_HRE;
1276 event(uartb_tx, 0, UART_TX_TIME);
1277 }
1278 mec_irq(5);
1279 }
1280
1281 static void
1282 uart_rx(arg)
1283 caddr_t arg;
1284 {
1285 int32 rsize;
1286 char rxd;
1287
1288
1289 rsize = 0;
1290 if (f1open)
1291 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1292 if (rsize > 0) {
1293 uarta_data = UART_DR | rxd;
1294 if (uart_stat_reg & UARTA_HRE)
1295 uarta_data |= UART_THE;
1296 if (uart_stat_reg & UARTA_SRE)
1297 uarta_data |= UART_TSE;
1298 if (uart_stat_reg & UARTA_DR) {
1299 uart_stat_reg |= UARTA_OR;
1300 mec_irq(7); /* UART error interrupt */
1301 }
1302 uart_stat_reg |= UARTA_DR;
1303 mec_irq(4);
1304 }
1305 rsize = 0;
1306 if (f2open)
1307 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1308 if (rsize) {
1309 uartb_data = UART_DR | rxd;
1310 if (uart_stat_reg & UARTB_HRE)
1311 uartb_data |= UART_THE;
1312 if (uart_stat_reg & UARTB_SRE)
1313 uartb_data |= UART_TSE;
1314 if (uart_stat_reg & UARTB_DR) {
1315 uart_stat_reg |= UARTB_OR;
1316 mec_irq(7); /* UART error interrupt */
1317 }
1318 uart_stat_reg |= UARTB_DR;
1319 mec_irq(5);
1320 }
1321 event(uart_rx, 0, UART_RX_TIME);
1322 }
1323
1324 static void
1325 uart_intr(arg)
1326 caddr_t arg;
1327 {
1328 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1329 flush_uart(); /* Flush UART ports */
1330 event(uart_intr, 0, UART_FLUSH_TIME);
1331 }
1332
1333
1334 static void
1335 uart_irq_start()
1336 {
1337 #ifdef FAST_UART
1338 event(uart_intr, 0, UART_FLUSH_TIME);
1339 #else
1340 #ifndef _WIN32
1341 event(uart_rx, 0, UART_RX_TIME);
1342 #endif
1343 #endif
1344 }
1345
1346 /* Watch-dog */
1347
1348 static void
1349 wdog_intr(arg)
1350 caddr_t arg;
1351 {
1352 if (wdog_status == disabled) {
1353 wdog_status = stopped;
1354 } else {
1355
1356 if (wdog_counter) {
1357 wdog_counter--;
1358 event(wdog_intr, 0, wdog_scaler + 1);
1359 } else {
1360 if (wdog_rston) {
1361 printf("Watchdog reset!\n");
1362 sys_reset();
1363 mec_ersr = 0xC000;
1364 } else {
1365 mec_irq(15);
1366 wdog_rston = 1;
1367 wdog_counter = wdog_rst_delay;
1368 event(wdog_intr, 0, wdog_scaler + 1);
1369 }
1370 }
1371 }
1372 }
1373
1374 static void
1375 wdog_start()
1376 {
1377 event(wdog_intr, 0, wdog_scaler + 1);
1378 if (sis_verbose)
1379 printf("Watchdog started, scaler = %d, counter = %d\n",
1380 wdog_scaler, wdog_counter);
1381 }
1382
1383
1384 /* MEC timers */
1385
1386
1387 static void
1388 rtc_intr(arg)
1389 caddr_t arg;
1390 {
1391 if (rtc_counter == 0) {
1392
1393 mec_irq(13);
1394 if (rtc_cr)
1395 rtc_counter = rtc_reload;
1396 else
1397 rtc_se = 0;
1398 } else
1399 rtc_counter -= 1;
1400 if (rtc_se) {
1401 event(rtc_intr, 0, rtc_scaler + 1);
1402 rtc_scaler_start = now();
1403 rtc_enabled = 1;
1404 } else {
1405 if (sis_verbose)
1406 printf("RTC stopped\n\r");
1407 rtc_enabled = 0;
1408 }
1409 }
1410
1411 static void
1412 rtc_start()
1413 {
1414 if (sis_verbose)
1415 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1416 event(rtc_intr, 0, rtc_scaler + 1);
1417 rtc_scaler_start = now();
1418 rtc_enabled = 1;
1419 }
1420
1421 static uint32
1422 rtc_counter_read()
1423 {
1424 return (rtc_counter);
1425 }
1426
1427 static void
1428 rtc_scaler_set(val)
1429 uint32 val;
1430 {
1431 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1432 }
1433
1434 static void
1435 rtc_reload_set(val)
1436 uint32 val;
1437 {
1438 rtc_reload = val;
1439 }
1440
1441 static void
1442 gpt_intr(arg)
1443 caddr_t arg;
1444 {
1445 if (gpt_counter == 0) {
1446 mec_irq(12);
1447 if (gpt_cr)
1448 gpt_counter = gpt_reload;
1449 else
1450 gpt_se = 0;
1451 } else
1452 gpt_counter -= 1;
1453 if (gpt_se) {
1454 event(gpt_intr, 0, gpt_scaler + 1);
1455 gpt_scaler_start = now();
1456 gpt_enabled = 1;
1457 } else {
1458 if (sis_verbose)
1459 printf("GPT stopped\n\r");
1460 gpt_enabled = 0;
1461 }
1462 }
1463
1464 static void
1465 gpt_start()
1466 {
1467 if (sis_verbose)
1468 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1469 event(gpt_intr, 0, gpt_scaler + 1);
1470 gpt_scaler_start = now();
1471 gpt_enabled = 1;
1472 }
1473
1474 static uint32
1475 gpt_counter_read()
1476 {
1477 return (gpt_counter);
1478 }
1479
1480 static void
1481 gpt_scaler_set(val)
1482 uint32 val;
1483 {
1484 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1485 }
1486
1487 static void
1488 gpt_reload_set(val)
1489 uint32 val;
1490 {
1491 gpt_reload = val;
1492 }
1493
1494 static void
1495 timer_ctrl(val)
1496 uint32 val;
1497 {
1498
1499 rtc_cr = ((val & TCR_TCRCR) != 0);
1500 if (val & TCR_TCRCL) {
1501 rtc_counter = rtc_reload;
1502 }
1503 if (val & TCR_TCRSL) {
1504 }
1505 rtc_se = ((val & TCR_TCRSE) != 0);
1506 if (rtc_se && (rtc_enabled == 0))
1507 rtc_start();
1508
1509 gpt_cr = (val & TCR_GACR);
1510 if (val & TCR_GACL) {
1511 gpt_counter = gpt_reload;
1512 }
1513 if (val & TCR_GACL) {
1514 }
1515 gpt_se = (val & TCR_GASE) >> 2;
1516 if (gpt_se && (gpt_enabled == 0))
1517 gpt_start();
1518 }
1519
1520
1521 /* Retrieve data from target memory. MEM points to location from which
1522 to read the data; DATA points to words where retrieved data will be
1523 stored in host byte order. SZ contains log(2) of the number of bytes
1524 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1525 or 3 (two words). */
1526
1527 static void
1528 fetch_bytes (asi, mem, data, sz)
1529 int asi;
1530 unsigned char *mem;
1531 uint32 *data;
1532 int sz;
1533 {
1534 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1535 || asi == 8 || asi == 9) {
1536 switch (sz) {
1537 case 3:
1538 data[1] = (((uint32) mem[7]) & 0xff) |
1539 ((((uint32) mem[6]) & 0xff) << 8) |
1540 ((((uint32) mem[5]) & 0xff) << 16) |
1541 ((((uint32) mem[4]) & 0xff) << 24);
1542 /* Fall through to 2 */
1543 case 2:
1544 data[0] = (((uint32) mem[3]) & 0xff) |
1545 ((((uint32) mem[2]) & 0xff) << 8) |
1546 ((((uint32) mem[1]) & 0xff) << 16) |
1547 ((((uint32) mem[0]) & 0xff) << 24);
1548 break;
1549 case 1:
1550 data[0] = (((uint32) mem[1]) & 0xff) |
1551 ((((uint32) mem[0]) & 0xff) << 8);
1552 break;
1553 case 0:
1554 data[0] = mem[0] & 0xff;
1555 break;
1556
1557 }
1558 } else {
1559 switch (sz) {
1560 case 3:
1561 data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1562 ((((uint32) mem[6]) & 0xff) << 16) |
1563 ((((uint32) mem[5]) & 0xff) << 8) |
1564 (((uint32) mem[4]) & 0xff);
1565 /* Fall through to 4 */
1566 case 2:
1567 data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1568 ((((uint32) mem[2]) & 0xff) << 16) |
1569 ((((uint32) mem[1]) & 0xff) << 8) |
1570 (((uint32) mem[0]) & 0xff);
1571 break;
1572 case 1:
1573 data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
1574 (((uint32) mem[0]) & 0xff);
1575 break;
1576 case 0:
1577 data[0] = mem[0] & 0xff;
1578 break;
1579 }
1580 }
1581 }
1582
1583
1584 /* Store data in target byte order. MEM points to location to store data;
1585 DATA points to words in host byte order to be stored. SZ contains log(2)
1586 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1587 2 (one word), or 3 (two words). */
1588
1589 static void
1590 store_bytes (mem, data, sz)
1591 unsigned char *mem;
1592 uint32 *data;
1593 int sz;
1594 {
1595 if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1596 switch (sz) {
1597 case 3:
1598 mem[7] = (data[1] >> 24) & 0xff;
1599 mem[6] = (data[1] >> 16) & 0xff;
1600 mem[5] = (data[1] >> 8) & 0xff;
1601 mem[4] = data[1] & 0xff;
1602 /* Fall through to 2 */
1603 case 2:
1604 mem[3] = (data[0] >> 24) & 0xff;
1605 mem[2] = (data[0] >> 16) & 0xff;
1606 /* Fall through to 1 */
1607 case 1:
1608 mem[1] = (data[0] >> 8) & 0xff;
1609 /* Fall through to 0 */
1610 case 0:
1611 mem[0] = data[0] & 0xff;
1612 break;
1613 }
1614 } else {
1615 switch (sz) {
1616 case 3:
1617 mem[7] = data[1] & 0xff;
1618 mem[6] = (data[1] >> 8) & 0xff;
1619 mem[5] = (data[1] >> 16) & 0xff;
1620 mem[4] = (data[1] >> 24) & 0xff;
1621 /* Fall through to 2 */
1622 case 2:
1623 mem[3] = data[0] & 0xff;
1624 mem[2] = (data[0] >> 8) & 0xff;
1625 mem[1] = (data[0] >> 16) & 0xff;
1626 mem[0] = (data[0] >> 24) & 0xff;
1627 break;
1628 case 1:
1629 mem[1] = data[0] & 0xff;
1630 mem[0] = (data[0] >> 8) & 0xff;
1631 break;
1632 case 0:
1633 mem[0] = data[0] & 0xff;
1634 break;
1635
1636 }
1637 }
1638 }
1639
1640
1641 /* Memory emulation */
1642
1643 int
1644 memory_read(asi, addr, data, sz, ws)
1645 int32 asi;
1646 uint32 addr;
1647 uint32 *data;
1648 int32 sz;
1649 int32 *ws;
1650 {
1651 int32 mexc;
1652
1653 #ifdef ERRINJ
1654 if (errmec) {
1655 if (sis_verbose)
1656 printf("Inserted MEC error %d\n",errmec);
1657 set_sfsr(errmec, addr, asi, 1);
1658 if (errmec == 5) mecparerror();
1659 if (errmec == 6) iucomperr();
1660 errmec = 0;
1661 return(1);
1662 }
1663 #endif
1664
1665 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1666 fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1667 *ws = mem_ramr_ws;
1668 return (0);
1669 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1670 mexc = mec_read(addr, asi, data);
1671 if (mexc) {
1672 set_sfsr(MEC_ACC, addr, asi, 1);
1673 *ws = MEM_EX_WS;
1674 } else {
1675 *ws = 0;
1676 }
1677 return (mexc);
1678
1679 #ifdef ERA
1680
1681 } else if (era) {
1682 if ((addr < 0x100000) ||
1683 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1684 fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1685 *ws = 4;
1686 return (0);
1687 } else if ((addr >= 0x10000000) &&
1688 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1689 (mec_iocr & 0x10)) {
1690 *data = erareg;
1691 return (0);
1692 }
1693
1694 } else if (addr < mem_romsz) {
1695 fetch_bytes (asi, &romb[addr], data, sz);
1696 *ws = mem_romr_ws;
1697 return (0);
1698
1699 #else
1700 } else if (addr < mem_romsz) {
1701 fetch_bytes (asi, &romb[addr], data, sz);
1702 *ws = mem_romr_ws;
1703 return (0);
1704 #endif
1705
1706 }
1707
1708 printf("Memory exception at %x (illegal address)\n", addr);
1709 set_sfsr(UIMP_ACC, addr, asi, 1);
1710 *ws = MEM_EX_WS;
1711 return (1);
1712 }
1713
1714 int
1715 memory_write(asi, addr, data, sz, ws)
1716 int32 asi;
1717 uint32 addr;
1718 uint32 *data;
1719 int32 sz;
1720 int32 *ws;
1721 {
1722 uint32 byte_addr;
1723 uint32 byte_mask;
1724 uint32 waddr;
1725 uint32 *ram;
1726 int32 mexc;
1727 int i;
1728 int wphit[2];
1729
1730 #ifdef ERRINJ
1731 if (errmec) {
1732 if (sis_verbose)
1733 printf("Inserted MEC error %d\n",errmec);
1734 set_sfsr(errmec, addr, asi, 0);
1735 if (errmec == 5) mecparerror();
1736 if (errmec == 6) iucomperr();
1737 errmec = 0;
1738 return(1);
1739 }
1740 #endif
1741
1742 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1743 if (mem_accprot) {
1744
1745 waddr = (addr & 0x7fffff) >> 2;
1746 for (i = 0; i < 2; i++)
1747 wphit[i] =
1748 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1749 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1750 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1751
1752 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1753 ((!mem_blockprot) &&
1754 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1755 )) {
1756 if (sis_verbose)
1757 printf("Memory access protection error at 0x%08x\n", addr);
1758 set_sfsr(PROT_EXC, addr, asi, 0);
1759 *ws = MEM_EX_WS;
1760 return (1);
1761 }
1762 }
1763
1764 store_bytes (&ramb[addr & mem_rammask], data, sz);
1765
1766 switch (sz) {
1767 case 0:
1768 case 1:
1769 *ws = mem_ramw_ws + 3;
1770 break;
1771 case 2:
1772 *ws = mem_ramw_ws;
1773 break;
1774 case 3:
1775 *ws = 2 * mem_ramw_ws + STD_WS;
1776 break;
1777 }
1778 return (0);
1779 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1780 if ((sz != 2) || (asi != 0xb)) {
1781 set_sfsr(MEC_ACC, addr, asi, 0);
1782 *ws = MEM_EX_WS;
1783 return (1);
1784 }
1785 mexc = mec_write(addr, *data);
1786 if (mexc) {
1787 set_sfsr(MEC_ACC, addr, asi, 0);
1788 *ws = MEM_EX_WS;
1789 } else {
1790 *ws = 0;
1791 }
1792 return (mexc);
1793
1794 #ifdef ERA
1795
1796 } else if (era) {
1797 if ((erareg & 2) &&
1798 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1799 addr &= ROM_MASK;
1800 *ws = sz == 3 ? 8 : 4;
1801 store_bytes (&romb[addr], data, sz);
1802 return (0);
1803 } else if ((addr >= 0x10000000) &&
1804 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1805 (mec_iocr & 0x10)) {
1806 erareg = *data & 0x0e;
1807 return (0);
1808 }
1809
1810 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1811 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1812 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1813
1814 *ws = mem_romw_ws + 1;
1815 if (sz == 3)
1816 *ws += mem_romw_ws + STD_WS;
1817 store_bytes (&romb[addr], data, sz);
1818 return (0);
1819
1820 #else
1821 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1822 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1823 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1824
1825 *ws = mem_romw_ws + 1;
1826 if (sz == 3)
1827 *ws += mem_romw_ws + STD_WS;
1828 store_bytes (&romb[addr], data, sz);
1829 return (0);
1830
1831 #endif
1832
1833 }
1834
1835 *ws = MEM_EX_WS;
1836 set_sfsr(UIMP_ACC, addr, asi, 0);
1837 return (1);
1838 }
1839
1840 static unsigned char *
1841 get_mem_ptr(addr, size)
1842 uint32 addr;
1843 uint32 size;
1844 {
1845 if ((addr + size) < ROM_SZ) {
1846 return (&romb[addr]);
1847 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1848 return (&ramb[addr & mem_rammask]);
1849 }
1850
1851 #ifdef ERA
1852 else if ((era) && ((addr <0x100000) ||
1853 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1854 return (&romb[addr & ROM_MASK]);
1855 }
1856 #endif
1857
1858 return ((char *) -1);
1859 }
1860
1861 int
1862 sis_memory_write(addr, data, length)
1863 uint32 addr;
1864 const unsigned char *data;
1865 uint32 length;
1866 {
1867 char *mem;
1868
1869 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1870 return (0);
1871
1872 memcpy(mem, data, length);
1873 return (length);
1874 }
1875
1876 int
1877 sis_memory_read(addr, data, length)
1878 uint32 addr;
1879 char *data;
1880 uint32 length;
1881 {
1882 char *mem;
1883
1884 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1885 return (0);
1886
1887 memcpy(data, mem, length);
1888 return (length);
1889 }
GDB Binutils - Deliverables
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