2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
22 /* The control space devices */
25 #include <sys/types.h>
29 #include <sys/fcntl.h>
33 #include "sim-config.h"
36 extern int32 sis_verbose
;
37 extern int32 sparclite
, sparclite_board
;
38 extern int rom8
,wrp
,uben
;
39 extern char uart_dev1
[], uart_dev2
[];
41 int dumbio
= 0; /* normal, smart, terminal oriented IO by default */
44 #define MEC_START 0x01f80000
45 #define MEC_END 0x01f80100
47 /* Memory exception waitstates */
50 /* ERC32 always adds one waitstate during RAM std */
57 /* The target's byte order is big-endian by default until we load a
58 little-endian program. */
60 int current_target_byte_order
= BIG_ENDIAN
;
62 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
65 /* MEC register addresses */
69 #define MEC_PWDR 0x008
70 #define MEC_MEMCFG 0x010
71 #define MEC_IOCR 0x014
74 #define MEC_MAR0 0x020
75 #define MEC_MAR1 0x024
77 #define MEC_SSA1 0x020
78 #define MEC_SEA1 0x024
79 #define MEC_SSA2 0x028
80 #define MEC_SEA2 0x02C
86 #define MEC_WDOG 0x060
87 #define MEC_TRAPD 0x064
88 #define MEC_RTC_COUNTER 0x080
89 #define MEC_RTC_RELOAD 0x080
90 #define MEC_RTC_SCALER 0x084
91 #define MEC_GPT_COUNTER 0x088
92 #define MEC_GPT_RELOAD 0x088
93 #define MEC_GPT_SCALER 0x08C
94 #define MEC_TIMER_CTRL 0x098
95 #define MEC_SFSR 0x0A0
96 #define MEC_FFAR 0x0A4
97 #define MEC_ERSR 0x0B0
101 #define MEC_BRK 0x0C4
102 #define MEC_WPR 0x0C8
104 #define MEC_UARTA 0x0E0
105 #define MEC_UARTB 0x0E4
106 #define MEC_UART_CTRL 0x0E8
107 #define SIM_LOAD 0x0F0
109 /* Memory exception causes */
113 #define WATCH_EXC 0xa
114 #define BREAK_EXC 0xb
116 /* Size of UART buffers (bytes) */
119 /* Number of simulator ticks between flushing the UARTS. */
120 /* For good performance, keep above 1000 */
121 #define UART_FLUSH_TIME 3000
123 /* MEC timer control register bits */
128 #define TCR_TCRCR 0x100
129 #define TCR_TCRCL 0x200
130 #define TCR_TCRSE 0x400
131 #define TCR_TCRSL 0x800
133 /* New uart defines */
134 #define UART_TX_TIME 1000
135 #define UART_RX_TIME 1000
137 #define UARTA_SRE 0x2
138 #define UARTA_HRE 0x4
139 #define UARTA_OR 0x40
140 #define UARTA_CLR 0x80
141 #define UARTB_DR 0x10000
142 #define UARTB_SRE 0x20000
143 #define UARTB_HRE 0x40000
144 #define UARTB_OR 0x400000
145 #define UARTB_CLR 0x800000
147 #define UART_DR 0x100
148 #define UART_TSE 0x200
149 #define UART_THE 0x400
153 static char fname
[256];
154 static int32 find
= 0;
155 static uint32 mec_ssa
[2]; /* Write protection start address */
156 static uint32 mec_sea
[2]; /* Write protection end address */
157 static uint32 mec_wpr
[2]; /* Write protection control fields */
158 static uint32 mec_sfsr
;
159 static uint32 mec_ffar
;
160 static uint32 mec_ipr
;
161 static uint32 mec_imr
;
162 static uint32 mec_isr
;
163 static uint32 mec_icr
;
164 static uint32 mec_ifr
;
165 static uint32 mec_mcr
; /* MEC control register */
166 static uint32 mec_memcfg
; /* Memory control register */
167 static uint32 mec_wcr
; /* MEC waitstate register */
168 static uint32 mec_iocr
; /* MEC IO control register */
169 static uint32 posted_irq
;
170 static uint32 mec_ersr
; /* MEC error and status register */
171 static uint32 mec_tcr
; /* MEC test comtrol register */
173 static uint32 rtc_counter
;
174 static uint32 rtc_reload
;
175 static uint32 rtc_scaler
;
176 static uint32 rtc_scaler_start
;
177 static uint32 rtc_enabled
;
178 static uint32 rtc_cr
;
179 static uint32 rtc_se
;
181 static uint32 gpt_counter
;
182 static uint32 gpt_reload
;
183 static uint32 gpt_scaler
;
184 static uint32 gpt_scaler_start
;
185 static uint32 gpt_enabled
;
186 static uint32 gpt_cr
;
187 static uint32 gpt_se
;
189 static uint32 wdog_scaler
;
190 static uint32 wdog_counter
;
191 static uint32 wdog_rst_delay
;
192 static uint32 wdog_rston
;
195 init
, disabled
, enabled
, stopped
198 static enum wdog_type wdog_status
;
201 /* ROM size 1024 Kbyte */
202 #define ROM_SZ 0x100000
203 #define ROM_MASK 0x0fffff
205 /* RAM size 4 Mbyte */
206 #define RAM_START 0x02000000
207 #define RAM_END 0x02400000
208 #define RAM_MASK 0x003fffff
210 /* SPARClite boards all seem to have RAM at the same place. */
211 #define RAM_START_SLITE 0x40000000
212 #define RAM_END_SLITE 0x40400000
213 #define RAM_MASK_SLITE 0x003fffff
215 /* Memory support variables */
217 static uint32 mem_ramr_ws
; /* RAM read waitstates */
218 static uint32 mem_ramw_ws
; /* RAM write waitstates */
219 static uint32 mem_romr_ws
; /* ROM read waitstates */
220 static uint32 mem_romw_ws
; /* ROM write waitstates */
221 static uint32 mem_ramstart
; /* RAM start */
222 static uint32 mem_ramend
; /* RAM end */
223 static uint32 mem_rammask
; /* RAM address mask */
224 static uint32 mem_ramsz
; /* RAM size */
225 static uint32 mem_romsz
; /* ROM size */
226 static uint32 mem_accprot
; /* RAM write protection enabled */
227 static uint32 mem_blockprot
; /* RAM block write protection enabled */
229 static unsigned char romb
[ROM_SZ
];
230 static unsigned char ramb
[RAM_END
- RAM_START
];
233 /* UART support variables */
235 static int32 fd1
, fd2
; /* file descriptor for input file */
236 static int32 Ucontrol
; /* UART status register */
237 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
238 static int32 anum
, aind
= 0;
239 static int32 bnum
, bind
= 0;
240 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
241 static unsigned wnuma
;
242 static unsigned wnumb
;
243 static FILE *f1in
, *f1out
, *f2in
, *f2out
;
244 static struct termios ioc1
, ioc2
, iocold1
, iocold2
;
245 static int f1open
= 0, f2open
= 0;
247 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
248 static uint32 uart_stat_reg
;
249 static uint32 uarta_data
, uartb_data
;
256 /* Forward declarations */
258 static void decode_ersr (void);
260 static void iucomperr (void);
262 static void mecparerror (void);
263 static void decode_memcfg (void);
264 static void decode_wcr (void);
265 static void decode_mcr (void);
266 static void close_port (void);
267 static void mec_reset (void);
268 static void mec_intack (int32 level
);
269 static void chk_irq (void);
270 static void mec_irq (int32 level
);
271 static void set_sfsr (uint32 fault
, uint32 addr
,
272 uint32 asi
, uint32 read
);
273 static int32
mec_read (uint32 addr
, uint32 asi
, uint32
*data
);
274 static int mec_write (uint32 addr
, uint32 data
);
275 static void port_init (void);
276 static uint32
read_uart (uint32 addr
);
277 static void write_uart (uint32 addr
, uint32 data
);
278 static void flush_uart (void);
279 static void uarta_tx (void);
280 static void uartb_tx (void);
281 static void uart_rx (caddr_t arg
);
282 static void uart_intr (caddr_t arg
);
283 static void uart_irq_start (void);
284 static void wdog_intr (caddr_t arg
);
285 static void wdog_start (void);
286 static void rtc_intr (caddr_t arg
);
287 static void rtc_start (void);
288 static uint32
rtc_counter_read (void);
289 static void rtc_scaler_set (uint32 val
);
290 static void rtc_reload_set (uint32 val
);
291 static void gpt_intr (caddr_t arg
);
292 static void gpt_start (void);
293 static uint32
gpt_counter_read (void);
294 static void gpt_scaler_set (uint32 val
);
295 static void gpt_reload_set (uint32 val
);
296 static void timer_ctrl (uint32 val
);
297 static unsigned char *
298 get_mem_ptr (uint32 addr
, uint32 size
);
300 static void fetch_bytes (int asi
, unsigned char *mem
,
301 uint32
*data
, int sz
);
303 static void store_bytes (unsigned char *mem
, uint32
*data
, int sz
);
316 /* Power-on reset init */
329 if (mec_ersr
& 0x01) {
330 if (!(mec_mcr
& 0x20)) {
331 if (mec_mcr
& 0x40) {
335 printf("Error manager reset - IU in error mode\n");
340 printf("Error manager halt - IU in error mode\n");
345 if (mec_ersr
& 0x04) {
346 if (!(mec_mcr
& 0x200)) {
347 if (mec_mcr
& 0x400) {
351 printf("Error manager reset - IU comparison error\n");
356 printf("Error manager halt - IU comparison error\n");
361 if (mec_ersr
& 0x20) {
362 if (!(mec_mcr
& 0x2000)) {
363 if (mec_mcr
& 0x4000) {
367 printf("Error manager reset - MEC hardware error\n");
372 printf("Error manager halt - MEC hardware error\n");
396 /* IU error mode manager */
408 /* Check memory settings */
413 if (rom8
) mec_memcfg
&= ~0x20000;
414 else mec_memcfg
|= 0x20000;
416 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
417 mem_romsz
= (128 * 1024) << ((mec_memcfg
>> 18) & 7);
419 if (sparclite_board
) {
420 mem_ramstart
= RAM_START_SLITE
;
421 mem_ramend
= RAM_END_SLITE
;
422 mem_rammask
= RAM_MASK_SLITE
;
425 mem_ramstart
= RAM_START
;
426 mem_ramend
= RAM_END
;
427 mem_rammask
= RAM_MASK
;
430 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
431 mem_ramstart
, mem_ramsz
>> 10, mem_romsz
>> 10);
437 mem_ramr_ws
= mec_wcr
& 3;
438 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
439 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
441 if (mem_romr_ws
> 0 ) mem_romr_ws
--;
442 mem_romr_ws
= 5 + (4*mem_romr_ws
);
444 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
446 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
447 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
453 mem_accprot
= (mec_wpr
[0] | mec_wpr
[1]);
454 mem_blockprot
= (mec_mcr
>> 3) & 1;
455 if (sis_verbose
&& mem_accprot
)
456 printf("Memory block write protection enabled\n");
457 if (mec_mcr
& 0x08000) {
461 if (sis_verbose
&& (mec_mcr
& 2))
462 printf("Software reset enabled\n");
463 if (sis_verbose
&& (mec_mcr
& 1))
464 printf("Power-down mode enabled\n");
467 /* Flush ports when simulator stops */
478 sim_stop(SIM_DESC sd
)
487 if (f1open
&& f1in
!= stdin
)
489 if (f2open
&& f2in
!= stdin
)
505 for (i
= 0; i
< 2; i
++)
506 mec_ssa
[i
] = mec_sea
[i
] = mec_wpr
[i
] = 0;
507 mec_mcr
= 0x01350014;
516 mec_memcfg
= 0x10000;
518 mec_ersr
= 0; /* MEC error and status register */
519 mec_tcr
= 0; /* MEC test comtrol register */
527 anum
= aind
= bnum
= bind
= 0;
529 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
530 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
532 rtc_counter
= 0xffffffff;
533 rtc_reload
= 0xffffffff;
539 gpt_counter
= 0xffffffff;
540 gpt_reload
= 0xffffffff;
547 wdog_rst_delay
= 255;
548 wdog_counter
= 0xffff;
567 printf("interrupt %d acknowledged\n", level
);
568 irq_test
= mec_tcr
& 0x80000;
569 if ((irq_test
) && (mec_ifr
& (1 << level
)))
570 mec_ifr
&= ~(1 << level
);
572 mec_ipr
&= ~(1 << level
);
584 if (mec_tcr
& 0x80000) itmp
= mec_ifr
;
586 itmp
= ((mec_ipr
| itmp
) & ~mec_imr
) & 0x0fffe;
589 for (i
= 15; i
> 0; i
--) {
590 if (((itmp
>> i
) & 1) != 0) {
591 if ((sis_verbose
) && (i
> old_irl
))
592 printf("IU irl: %d\n", i
);
594 set_int(i
, mec_intack
, i
);
605 mec_ipr
|= (1 << level
);
610 set_sfsr(fault
, addr
, asi
, read
)
616 if ((asi
== 0xa) || (asi
== 0xb)) {
618 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
619 mec_sfsr
|= ((mec_sfsr
& 1) ^ 1) | (mec_sfsr
& 1);
632 mec_read(addr
, asi
, data
)
638 switch (addr
& 0x0ff) {
640 case MEC_MCR
: /* 0x00 */
644 case MEC_MEMCFG
: /* 0x10 */
649 *data
= mec_iocr
; /* 0x14 */
652 case MEC_SSA1
: /* 0x20 */
653 *data
= mec_ssa
[0] | (mec_wpr
[0] << 23);
655 case MEC_SEA1
: /* 0x24 */
658 case MEC_SSA2
: /* 0x28 */
659 *data
= mec_ssa
[1] | (mec_wpr
[1] << 23);
661 case MEC_SEA2
: /* 0x2c */
665 case MEC_ISR
: /* 0x44 */
669 case MEC_IPR
: /* 0x48 */
673 case MEC_IMR
: /* 0x4c */
677 case MEC_IFR
: /* 0x54 */
681 case MEC_RTC_COUNTER
: /* 0x80 */
682 *data
= rtc_counter_read();
684 case MEC_RTC_SCALER
: /* 0x84 */
686 *data
= rtc_scaler
- (now() - rtc_scaler_start
);
691 case MEC_GPT_COUNTER
: /* 0x88 */
692 *data
= gpt_counter_read();
695 case MEC_GPT_SCALER
: /* 0x8c */
697 *data
= gpt_scaler
- (now() - gpt_scaler_start
);
703 case MEC_SFSR
: /* 0xA0 */
707 case MEC_FFAR
: /* 0xA4 */
714 strcpy(fname
, "simload");
715 find
= bfd_load(fname
);
723 case MEC_ERSR
: /* 0xB0 */
727 case MEC_TCR
: /* 0xD0 */
731 case MEC_UARTA
: /* 0xE0 */
732 case MEC_UARTB
: /* 0xE4 */
734 set_sfsr(MEC_ACC
, addr
, asi
, 1);
737 *data
= read_uart(addr
);
740 case MEC_UART_CTRL
: /* 0xE8 */
742 *data
= read_uart(addr
);
745 case 0xF4: /* simulator RAM size in bytes */
749 case 0xF8: /* simulator ROM size in bytes */
754 set_sfsr(MEC_ACC
, addr
, asi
, 1);
762 mec_write(addr
, data
)
767 printf("MEC write a: %08x, d: %08x\n",addr
,data
);
768 switch (addr
& 0x0ff) {
773 if (mec_mcr
& 0x08000) mecparerror();
781 printf(" Software reset issued\n");
787 if (mec_iocr
& 0xC0C0C0C0) mecparerror();
790 case MEC_SSA1
: /* 0x20 */
791 if (data
& 0xFE000000) mecparerror();
792 mec_ssa
[0] = data
& 0x7fffff;
793 mec_wpr
[0] = (data
>> 23) & 0x03;
794 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
795 if (sis_verbose
&& mec_wpr
[0])
796 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
797 mec_ssa
[0] << 2, mec_sea
[0] << 2);
799 case MEC_SEA1
: /* 0x24 */
800 if (data
& 0xFF800000) mecparerror();
801 mec_sea
[0] = data
& 0x7fffff;
803 case MEC_SSA2
: /* 0x28 */
804 if (data
& 0xFE000000) mecparerror();
805 mec_ssa
[1] = data
& 0x7fffff;
806 mec_wpr
[1] = (data
>> 23) & 0x03;
807 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
808 if (sis_verbose
&& mec_wpr
[1])
809 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
810 mec_ssa
[1] << 2, mec_sea
[1] << 2);
812 case MEC_SEA2
: /* 0x2c */
813 if (data
& 0xFF800000) mecparerror();
814 mec_sea
[1] = data
& 0x7fffff;
819 if (data
& 0xFFFFFF00) mecparerror();
821 if (data
& 0xFF00FF00) mecparerror();
822 write_uart(addr
, data
);
826 gpt_reload_set(data
);
830 if (data
& 0xFFFF0000) mecparerror();
831 gpt_scaler_set(data
);
835 if (data
& 0xFFFFF0F0) mecparerror();
840 rtc_reload_set(data
);
844 if (data
& 0xFFFFFF00) mecparerror();
845 rtc_scaler_set(data
);
848 case MEC_SFSR
: /* 0xA0 */
849 if (data
& 0xFFFF0880) mecparerror();
854 if (data
& 0xFFFFE000) mecparerror();
858 case MEC_IMR
: /* 0x4c */
860 if (data
& 0xFFFF8001) mecparerror();
861 mec_imr
= data
& 0x7ffe;
865 case MEC_ICR
: /* 0x50 */
867 if (data
& 0xFFFF0001) mecparerror();
868 mec_ipr
&= ~data
& 0x0fffe;
872 case MEC_IFR
: /* 0x54 */
874 if (mec_tcr
& 0x080000) {
875 if (data
& 0xFFFF0001) mecparerror();
876 mec_ifr
= data
& 0xfffe;
881 fname
[find
++] = (char) data
;
885 case MEC_MEMCFG
: /* 0x10 */
886 if (data
& 0xC0E08000) mecparerror();
889 if (mec_memcfg
& 0xc0e08000)
893 case MEC_WCR
: /* 0x18 */
898 case MEC_ERSR
: /* 0xB0 */
899 if (mec_tcr
& 0x100000)
900 if (data
& 0xFFFFEFC0) mecparerror();
901 mec_ersr
= data
& 0x103f;
904 case MEC_TCR
: /* 0xD0 */
905 if (data
& 0xFFE1FFC0) mecparerror();
906 mec_tcr
= data
& 0x1e003f;
909 case MEC_WDOG
: /* 0x60 */
910 wdog_scaler
= (data
>> 16) & 0x0ff;
911 wdog_counter
= data
& 0x0ffff;
912 wdog_rst_delay
= data
>> 24;
914 if (wdog_status
== stopped
)
916 wdog_status
= enabled
;
919 case MEC_TRAPD
: /* 0x64 */
920 if (wdog_status
== init
) {
921 wdog_status
= disabled
;
923 printf("Watchdog disabled\n");
933 set_sfsr(MEC_ACC
, addr
, 0xb, 0);
943 static int ifd1
= -1, ifd2
= -1, ofd1
= -1, ofd2
= -1;
949 return; /* do nothing */
951 tcsetattr(0, TCSANOW
, &ioc1
);
953 tcsetattr(0, TCSANOW
, &ioc2
);
960 return; /* do nothing */
962 tcsetattr(0, TCSANOW
, &iocold1
);
964 tcsetattr(0, TCSANOW
, &iocold2
);
967 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
969 ? (0) /* no bytes read, no delay */ \
970 : read( _fd_, _buf_, _len_ ) )
988 if (uart_dev1
[0] != 0)
989 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NONBLOCK
)) < 0) {
990 printf("Warning, couldn't open output device %s\n", uart_dev1
);
993 printf("serial port A on %s\n", uart_dev1
);
994 f1in
= f1out
= fdopen(fd1
, "r+");
998 if (f1in
) ifd1
= fileno(f1in
);
1001 printf("serial port A on stdin/stdout\n");
1003 tcgetattr(ifd1
, &ioc1
);
1005 ioc1
.c_lflag
&= ~(ICANON
| ECHO
);
1006 ioc1
.c_cc
[VMIN
] = 0;
1007 ioc1
.c_cc
[VTIME
] = 0;
1013 ofd1
= fileno(f1out
);
1014 if (!dumbio
&& ofd1
== 1) setbuf(f1out
, NULL
);
1017 if (uart_dev2
[0] != 0)
1018 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NONBLOCK
)) < 0) {
1019 printf("Warning, couldn't open output device %s\n", uart_dev2
);
1022 printf("serial port B on %s\n", uart_dev2
);
1023 f2in
= f2out
= fdopen(fd2
, "r+");
1024 setbuf(f2out
, NULL
);
1027 if (f2in
) ifd2
= fileno(f2in
);
1030 printf("serial port B on stdin/stdout\n");
1032 tcgetattr(ifd2
, &ioc2
);
1034 ioc2
.c_lflag
&= ~(ICANON
| ECHO
);
1035 ioc2
.c_cc
[VMIN
] = 0;
1036 ioc2
.c_cc
[VTIME
] = 0;
1042 ofd2
= fileno(f2out
);
1043 if (!dumbio
&& ofd2
== 1) setbuf(f2out
, NULL
);
1058 switch (addr
& 0xff) {
1060 case 0xE0: /* UART 1 */
1065 if ((aind
+ 1) < anum
)
1067 return (0x700 | (uint32
) aq
[aind
++]);
1070 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1074 if ((aind
+ 1) < anum
)
1076 return (0x700 | (uint32
) aq
[aind
++]);
1078 return (0x600 | (uint32
) aq
[aind
]);
1084 uarta_data
&= ~UART_DR
;
1085 uart_stat_reg
&= ~UARTA_DR
;
1093 case 0xE4: /* UART 2 */
1097 if ((bind
+ 1) < bnum
)
1099 return (0x700 | (uint32
) bq
[bind
++]);
1102 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1106 if ((bind
+ 1) < bnum
)
1108 return (0x700 | (uint32
) bq
[bind
++]);
1110 return (0x600 | (uint32
) bq
[bind
]);
1116 uartb_data
&= ~UART_DR
;
1117 uart_stat_reg
&= ~UARTB_DR
;
1125 case 0xE8: /* UART status register */
1131 Ucontrol
|= 0x00000001;
1134 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1137 Ucontrol
|= 0x00000001;
1143 Ucontrol
|= 0x00010000;
1146 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1149 Ucontrol
|= 0x00010000;
1155 Ucontrol
|= 0x00060006;
1158 return (uart_stat_reg
);
1166 printf("Read from unimplemented MEC register (%x)\n", addr
);
1173 write_uart(addr
, data
)
1179 c
= (unsigned char) data
;
1180 switch (addr
& 0xff) {
1182 case 0xE0: /* UART A */
1185 if (wnuma
< UARTBUF
)
1189 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1195 if (uart_stat_reg
& UARTA_SRE
) {
1197 uart_stat_reg
&= ~UARTA_SRE
;
1198 event(uarta_tx
, 0, UART_TX_TIME
);
1201 uart_stat_reg
&= ~UARTA_HRE
;
1206 case 0xE4: /* UART B */
1209 if (wnumb
< UARTBUF
)
1213 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1219 if (uart_stat_reg
& UARTB_SRE
) {
1221 uart_stat_reg
&= ~UARTB_SRE
;
1222 event(uartb_tx
, 0, UART_TX_TIME
);
1225 uart_stat_reg
&= ~UARTB_HRE
;
1229 case 0xE8: /* UART status register */
1231 if (data
& UARTA_CLR
) {
1232 uart_stat_reg
&= 0xFFFF0000;
1233 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
1235 if (data
& UARTB_CLR
) {
1236 uart_stat_reg
&= 0x0000FFFF;
1237 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
1243 printf("Write to unimplemented MEC register (%x)\n", addr
);
1251 while (wnuma
&& f1open
)
1252 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1253 while (wnumb
&& f2open
)
1254 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1263 while (f1open
&& fwrite(&uarta_sreg
, 1, 1, f1out
) != 1);
1264 if (uart_stat_reg
& UARTA_HRE
) {
1265 uart_stat_reg
|= UARTA_SRE
;
1267 uarta_sreg
= uarta_hreg
;
1268 uart_stat_reg
|= UARTA_HRE
;
1269 event(uarta_tx
, 0, UART_TX_TIME
);
1277 while (f2open
&& fwrite(&uartb_sreg
, 1, 1, f2out
) != 1);
1278 if (uart_stat_reg
& UARTB_HRE
) {
1279 uart_stat_reg
|= UARTB_SRE
;
1281 uartb_sreg
= uartb_hreg
;
1282 uart_stat_reg
|= UARTB_HRE
;
1283 event(uartb_tx
, 0, UART_TX_TIME
);
1298 rsize
= DO_STDIO_READ(ifd1
, &rxd
, 1);
1300 uarta_data
= UART_DR
| rxd
;
1301 if (uart_stat_reg
& UARTA_HRE
)
1302 uarta_data
|= UART_THE
;
1303 if (uart_stat_reg
& UARTA_SRE
)
1304 uarta_data
|= UART_TSE
;
1305 if (uart_stat_reg
& UARTA_DR
) {
1306 uart_stat_reg
|= UARTA_OR
;
1307 mec_irq(7); /* UART error interrupt */
1309 uart_stat_reg
|= UARTA_DR
;
1314 rsize
= DO_STDIO_READ(ifd2
, &rxd
, 1);
1316 uartb_data
= UART_DR
| rxd
;
1317 if (uart_stat_reg
& UARTB_HRE
)
1318 uartb_data
|= UART_THE
;
1319 if (uart_stat_reg
& UARTB_SRE
)
1320 uartb_data
|= UART_TSE
;
1321 if (uart_stat_reg
& UARTB_DR
) {
1322 uart_stat_reg
|= UARTB_OR
;
1323 mec_irq(7); /* UART error interrupt */
1325 uart_stat_reg
|= UARTB_DR
;
1328 event(uart_rx
, 0, UART_RX_TIME
);
1335 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1336 flush_uart(); /* Flush UART ports */
1337 event(uart_intr
, 0, UART_FLUSH_TIME
);
1345 event(uart_intr
, 0, UART_FLUSH_TIME
);
1348 event(uart_rx
, 0, UART_RX_TIME
);
1359 if (wdog_status
== disabled
) {
1360 wdog_status
= stopped
;
1365 event(wdog_intr
, 0, wdog_scaler
+ 1);
1368 printf("Watchdog reset!\n");
1374 wdog_counter
= wdog_rst_delay
;
1375 event(wdog_intr
, 0, wdog_scaler
+ 1);
1384 event(wdog_intr
, 0, wdog_scaler
+ 1);
1386 printf("Watchdog started, scaler = %d, counter = %d\n",
1387 wdog_scaler
, wdog_counter
);
1398 if (rtc_counter
== 0) {
1402 rtc_counter
= rtc_reload
;
1408 event(rtc_intr
, 0, rtc_scaler
+ 1);
1409 rtc_scaler_start
= now();
1413 printf("RTC stopped\n\r");
1422 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1423 event(rtc_intr
, 0, rtc_scaler
+ 1);
1424 rtc_scaler_start
= now();
1431 return (rtc_counter
);
1438 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1452 if (gpt_counter
== 0) {
1455 gpt_counter
= gpt_reload
;
1461 event(gpt_intr
, 0, gpt_scaler
+ 1);
1462 gpt_scaler_start
= now();
1466 printf("GPT stopped\n\r");
1475 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1476 event(gpt_intr
, 0, gpt_scaler
+ 1);
1477 gpt_scaler_start
= now();
1484 return (gpt_counter
);
1491 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1506 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1507 if (val
& TCR_TCRCL
) {
1508 rtc_counter
= rtc_reload
;
1510 if (val
& TCR_TCRSL
) {
1512 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1513 if (rtc_se
&& (rtc_enabled
== 0))
1516 gpt_cr
= (val
& TCR_GACR
);
1517 if (val
& TCR_GACL
) {
1518 gpt_counter
= gpt_reload
;
1520 if (val
& TCR_GACL
) {
1522 gpt_se
= (val
& TCR_GASE
) >> 2;
1523 if (gpt_se
&& (gpt_enabled
== 0))
1528 /* Retrieve data from target memory. MEM points to location from which
1529 to read the data; DATA points to words where retrieved data will be
1530 stored in host byte order. SZ contains log(2) of the number of bytes
1531 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1532 or 3 (two words). */
1535 fetch_bytes (asi
, mem
, data
, sz
)
1541 if (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
1542 || asi
== 8 || asi
== 9) {
1545 data
[1] = (((uint32
) mem
[7]) & 0xff) |
1546 ((((uint32
) mem
[6]) & 0xff) << 8) |
1547 ((((uint32
) mem
[5]) & 0xff) << 16) |
1548 ((((uint32
) mem
[4]) & 0xff) << 24);
1549 /* Fall through to 2 */
1551 data
[0] = (((uint32
) mem
[3]) & 0xff) |
1552 ((((uint32
) mem
[2]) & 0xff) << 8) |
1553 ((((uint32
) mem
[1]) & 0xff) << 16) |
1554 ((((uint32
) mem
[0]) & 0xff) << 24);
1557 data
[0] = (((uint32
) mem
[1]) & 0xff) |
1558 ((((uint32
) mem
[0]) & 0xff) << 8);
1561 data
[0] = mem
[0] & 0xff;
1568 data
[1] = ((((uint32
) mem
[7]) & 0xff) << 24) |
1569 ((((uint32
) mem
[6]) & 0xff) << 16) |
1570 ((((uint32
) mem
[5]) & 0xff) << 8) |
1571 (((uint32
) mem
[4]) & 0xff);
1572 /* Fall through to 4 */
1574 data
[0] = ((((uint32
) mem
[3]) & 0xff) << 24) |
1575 ((((uint32
) mem
[2]) & 0xff) << 16) |
1576 ((((uint32
) mem
[1]) & 0xff) << 8) |
1577 (((uint32
) mem
[0]) & 0xff);
1580 data
[0] = ((((uint32
) mem
[1]) & 0xff) << 8) |
1581 (((uint32
) mem
[0]) & 0xff);
1584 data
[0] = mem
[0] & 0xff;
1591 /* Store data in target byte order. MEM points to location to store data;
1592 DATA points to words in host byte order to be stored. SZ contains log(2)
1593 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1594 2 (one word), or 3 (two words). */
1597 store_bytes (mem
, data
, sz
)
1602 if (CURRENT_TARGET_BYTE_ORDER
== LITTLE_ENDIAN
) {
1605 mem
[7] = (data
[1] >> 24) & 0xff;
1606 mem
[6] = (data
[1] >> 16) & 0xff;
1607 mem
[5] = (data
[1] >> 8) & 0xff;
1608 mem
[4] = data
[1] & 0xff;
1609 /* Fall through to 2 */
1611 mem
[3] = (data
[0] >> 24) & 0xff;
1612 mem
[2] = (data
[0] >> 16) & 0xff;
1613 /* Fall through to 1 */
1615 mem
[1] = (data
[0] >> 8) & 0xff;
1616 /* Fall through to 0 */
1618 mem
[0] = data
[0] & 0xff;
1624 mem
[7] = data
[1] & 0xff;
1625 mem
[6] = (data
[1] >> 8) & 0xff;
1626 mem
[5] = (data
[1] >> 16) & 0xff;
1627 mem
[4] = (data
[1] >> 24) & 0xff;
1628 /* Fall through to 2 */
1630 mem
[3] = data
[0] & 0xff;
1631 mem
[2] = (data
[0] >> 8) & 0xff;
1632 mem
[1] = (data
[0] >> 16) & 0xff;
1633 mem
[0] = (data
[0] >> 24) & 0xff;
1636 mem
[1] = data
[0] & 0xff;
1637 mem
[0] = (data
[0] >> 8) & 0xff;
1640 mem
[0] = data
[0] & 0xff;
1648 /* Memory emulation */
1651 memory_read(asi
, addr
, data
, sz
, ws
)
1663 printf("Inserted MEC error %d\n",errmec
);
1664 set_sfsr(errmec
, addr
, asi
, 1);
1665 if (errmec
== 5) mecparerror();
1666 if (errmec
== 6) iucomperr();
1672 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1673 fetch_bytes (asi
, &ramb
[addr
& mem_rammask
], data
, sz
);
1676 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1677 mexc
= mec_read(addr
, asi
, data
);
1679 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1689 if ((addr
< 0x100000) ||
1690 ((addr
>= 0x80000000) && (addr
< 0x80100000))) {
1691 fetch_bytes (asi
, &romb
[addr
& ROM_MASK
], data
, sz
);
1694 } else if ((addr
>= 0x10000000) &&
1695 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1696 (mec_iocr
& 0x10)) {
1701 } else if (addr
< mem_romsz
) {
1702 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1707 } else if (addr
< mem_romsz
) {
1708 fetch_bytes (asi
, &romb
[addr
], data
, sz
);
1715 printf("Memory exception at %x (illegal address)\n", addr
);
1716 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1722 memory_write(asi
, addr
, data
, sz
, ws
)
1740 printf("Inserted MEC error %d\n",errmec
);
1741 set_sfsr(errmec
, addr
, asi
, 0);
1742 if (errmec
== 5) mecparerror();
1743 if (errmec
== 6) iucomperr();
1749 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1752 waddr
= (addr
& 0x7fffff) >> 2;
1753 for (i
= 0; i
< 2; i
++)
1755 (((asi
== 0xa) && (mec_wpr
[i
] & 1)) ||
1756 ((asi
== 0xb) && (mec_wpr
[i
] & 2))) &&
1757 ((waddr
>= mec_ssa
[i
]) && ((waddr
| (sz
== 3)) < mec_sea
[i
]));
1759 if (((mem_blockprot
) && (wphit
[0] || wphit
[1])) ||
1760 ((!mem_blockprot
) &&
1761 !((mec_wpr
[0] && wphit
[0]) || (mec_wpr
[1] && wphit
[1]))
1764 printf("Memory access protection error at 0x%08x\n", addr
);
1765 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1771 store_bytes (&ramb
[addr
& mem_rammask
], data
, sz
);
1776 *ws
= mem_ramw_ws
+ 3;
1782 *ws
= 2 * mem_ramw_ws
+ STD_WS
;
1786 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1787 if ((sz
!= 2) || (asi
!= 0xb)) {
1788 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1792 mexc
= mec_write(addr
, *data
);
1794 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1805 ((addr
< 0x100000) || ((addr
>= 0x80000000) && (addr
< 0x80100000)))) {
1807 *ws
= sz
== 3 ? 8 : 4;
1808 store_bytes (&romb
[addr
], data
, sz
);
1810 } else if ((addr
>= 0x10000000) &&
1811 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1812 (mec_iocr
& 0x10)) {
1813 erareg
= *data
& 0x0e;
1817 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1818 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1819 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1821 *ws
= mem_romw_ws
+ 1;
1823 *ws
+= mem_romw_ws
+ STD_WS
;
1824 store_bytes (&romb
[addr
], data
, sz
);
1828 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1829 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1830 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1832 *ws
= mem_romw_ws
+ 1;
1834 *ws
+= mem_romw_ws
+ STD_WS
;
1835 store_bytes (&romb
[addr
], data
, sz
);
1843 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1847 static unsigned char *
1848 get_mem_ptr(addr
, size
)
1852 if ((addr
+ size
) < ROM_SZ
) {
1853 return (&romb
[addr
]);
1854 } else if ((addr
>= mem_ramstart
) && ((addr
+ size
) < mem_ramend
)) {
1855 return (&ramb
[addr
& mem_rammask
]);
1859 else if ((era
) && ((addr
<0x100000) ||
1860 ((addr
>= (unsigned) 0x80000000) && ((addr
+ size
) < (unsigned) 0x80100000)))) {
1861 return (&romb
[addr
& ROM_MASK
]);
1865 return ((char *) -1);
1869 sis_memory_write(addr
, data
, length
)
1871 const unsigned char *data
;
1876 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1879 memcpy(mem
, data
, length
);
1884 sis_memory_read(addr
, data
, length
)
1891 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1894 memcpy(data
, mem
, length
);
1898 extern struct pstate sregs
;
1903 mec_write(MEC_WCR
, 0); /* zero waitstates */
1904 mec_write(MEC_TRAPD
, 0); /* turn off watch-dog */
1905 mec_write(MEC_RTC_SCALER
, sregs
.freq
- 1); /* generate 1 MHz RTC tick */
1906 mec_write(MEC_MEMCFG
, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1908 sregs
.psr
= 0x110010e0;
1909 sregs
.r
[30] = RAM_END
;
1910 sregs
.r
[14] = sregs
.r
[30] - 96 * 4;
1911 mec_mcr
|= 1; /* power-down enabled */