1b8f0fc76cfe89c2f4b5b08cee8c8108b3e79000
2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
21 * This file implements the interface between the host and the simulated
22 * FPU. IEEE trap handling is done as follows:
23 * 1. In the host, all IEEE traps are masked
24 * 2. After each simulated FPU instruction, check if any exception occured
25 * by reading the exception bits from the host FPU status register
27 * 3. Propagate any exceptions to the simulated FSR.
28 * 4. Clear host exception bits
31 * This can also be done using ieee_flags() library routine on sun.
37 /* Forward declarations */
39 extern uint32 _get_sw
PARAMS ((void));
40 extern uint32 _get_cw
PARAMS ((void));
41 static void __setfpucw
PARAMS ((unsigned short fpu_control
));
43 /* This host dependent routine should return the accrued exceptions */
48 return ((_get_fsr_raw() >> 5) & 0x1F);
52 accx
= _get_sw() & 0x3f;
53 accx
= ((accx
& 1) << 4) | ((accx
& 2) >> 1) | ((accx
& 4) >> 1) |
54 (accx
& 8) | ((accx
& 16) >> 2) | ((accx
& 32) >> 5);
58 #warning no fpu trap support for this target
63 /* How to clear the accrued exceptions */
68 set_fsr((_get_fsr_raw() & ~0x3e0));
76 #warning no fpu trap support for this target
80 /* How to map SPARC FSR onto the host */
86 _set_fsr_raw(fsr
& ~0x0f800000);
88 void __setfpucw(unsigned short fpu_control
);
106 rawfsr
|= (fsr
<< 10) | 0x3ff;
109 #warning no fpu trap support for this target
114 /* Host dependent support functions */
122 " .global __set_fsr_raw,_set_fsr_raw\n"
125 " save %sp,-104,%sp\n"
127 " ld [%fp+68], %fsr\n"
133 " .global __get_fsr_raw\n"
134 " .global _get_fsr_raw\n"
137 " save %sp,-104,%sp\n"
138 " st %fsr,[%fp+68]\n"
139 " ld [%fp+68], %i0\n"
151 ".globl _get_sw,__get_sw\n"
163 ".globl _get_cw,__get_cw\n"
170 " movw -2(%ebp),%eax\n"
180 #warning no fpu trap support for this target
184 /* #if defined _WIN32 || defined __GO32__ */
185 /* This is so floating exception handling works on NT
186 These definitions are from the linux fpu_control.h, which
191 - rounding to nearest
192 - exceptions on overflow, zero divide and NaN
194 #define _FPU_DEFAULT 0x1372
195 #define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
198 __setfpucw(unsigned short fpu_control
)
200 volatile unsigned short cw
;
202 /* If user supplied _fpu_control, use it ! */
206 fpu_control
= _FPU_DEFAULT
;
208 /* Get Control Word */
209 __asm__
volatile ("fnstcw %0" : "=m" (cw
) : );
213 cw
= cw
| (fpu_control
& ~_FPU_RESERVED
);
216 __asm__
volatile ("fldcw %0" :: "m" (cw
));
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