2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
21 * This file implements the interface between the host and the simulated
22 * FPU. IEEE trap handling is done as follows:
23 * 1. In the host, all IEEE traps are masked
24 * 2. After each simulated FPU instruction, check if any exception occured
25 * by reading the exception bits from the host FPU status register
27 * 3. Propagate any exceptions to the simulated FSR.
28 * 4. Clear host exception bits
37 /* This routine should return the accrued exceptions */
43 fexc
= fetestexcept (FE_ALL_EXCEPT
);
45 if (fexc
& FE_INEXACT
)
47 if (fexc
& FE_DIVBYZERO
)
49 if (fexc
& FE_UNDERFLOW
)
51 if (fexc
& FE_OVERFLOW
)
53 if (fexc
& FE_INVALID
)
58 /* How to clear the accrued exceptions */
62 feclearexcept (FE_ALL_EXCEPT
);
65 /* How to map SPARC FSR onto the host */
75 fround
= FE_TONEAREST
;
78 fround
= FE_TOWARDZERO
;
This page took 0.147313 seconds and 5 git commands to generate.