1 /* CPU family header for fr30bf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 1
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* coprocessor registers */
49 #define GET_H_CR(a1) CPU (h_cr)[a1]
50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51 /* dedicated registers */
53 #define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index)
54 #define SET_H_DR(index, x) \
56 fr30bf_h_dr_set_handler (current_cpu, (index), (x));\
58 /* processor status */
60 #define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
63 fr30bf_h_ps_set_handler (current_cpu, (x));\
65 /* General Register 13 explicitly required */
67 #define GET_H_R13() CPU (h_r13)
68 #define SET_H_R13(x) (CPU (h_r13) = (x))
69 /* General Register 14 explicitly required */
71 #define GET_H_R14() CPU (h_r14)
72 #define SET_H_R14(x) (CPU (h_r14) = (x))
73 /* General Register 15 explicitly required */
75 #define GET_H_R15() CPU (h_r15)
76 #define SET_H_R15(x) (CPU (h_r15) = (x))
79 #define GET_H_NBIT() CPU (h_nbit)
80 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
83 #define GET_H_ZBIT() CPU (h_zbit)
84 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
87 #define GET_H_VBIT() CPU (h_vbit)
88 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
91 #define GET_H_CBIT() CPU (h_cbit)
92 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
93 /* interrupt enable bit */
95 #define GET_H_IBIT() CPU (h_ibit)
96 #define SET_H_IBIT(x) (CPU (h_ibit) = (x))
99 #define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
100 #define SET_H_SBIT(x) \
102 fr30bf_h_sbit_set_handler (current_cpu, (x));\
106 #define GET_H_TBIT() CPU (h_tbit)
107 #define SET_H_TBIT(x) (CPU (h_tbit) = (x))
110 #define GET_H_D0BIT() CPU (h_d0bit)
111 #define SET_H_D0BIT(x) (CPU (h_d0bit) = (x))
114 #define GET_H_D1BIT() CPU (h_d1bit)
115 #define SET_H_D1BIT(x) (CPU (h_d1bit) = (x))
116 /* condition code bits */
118 #define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
119 #define SET_H_CCR(x) \
121 fr30bf_h_ccr_set_handler (current_cpu, (x));\
123 /* system condition bits */
125 #define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
126 #define SET_H_SCR(x) \
128 fr30bf_h_scr_set_handler (current_cpu, (x));\
130 /* interrupt level mask */
132 #define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
133 #define SET_H_ILM(x) \
135 fr30bf_h_ilm_set_handler (current_cpu, (x));\
138 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
141 /* Cover fns for register access. */
142 USI
fr30bf_h_pc_get (SIM_CPU
*);
143 void fr30bf_h_pc_set (SIM_CPU
*, USI
);
144 SI
fr30bf_h_gr_get (SIM_CPU
*, UINT
);
145 void fr30bf_h_gr_set (SIM_CPU
*, UINT
, SI
);
146 SI
fr30bf_h_cr_get (SIM_CPU
*, UINT
);
147 void fr30bf_h_cr_set (SIM_CPU
*, UINT
, SI
);
148 SI
fr30bf_h_dr_get (SIM_CPU
*, UINT
);
149 void fr30bf_h_dr_set (SIM_CPU
*, UINT
, SI
);
150 USI
fr30bf_h_ps_get (SIM_CPU
*);
151 void fr30bf_h_ps_set (SIM_CPU
*, USI
);
152 SI
fr30bf_h_r13_get (SIM_CPU
*);
153 void fr30bf_h_r13_set (SIM_CPU
*, SI
);
154 SI
fr30bf_h_r14_get (SIM_CPU
*);
155 void fr30bf_h_r14_set (SIM_CPU
*, SI
);
156 SI
fr30bf_h_r15_get (SIM_CPU
*);
157 void fr30bf_h_r15_set (SIM_CPU
*, SI
);
158 BI
fr30bf_h_nbit_get (SIM_CPU
*);
159 void fr30bf_h_nbit_set (SIM_CPU
*, BI
);
160 BI
fr30bf_h_zbit_get (SIM_CPU
*);
161 void fr30bf_h_zbit_set (SIM_CPU
*, BI
);
162 BI
fr30bf_h_vbit_get (SIM_CPU
*);
163 void fr30bf_h_vbit_set (SIM_CPU
*, BI
);
164 BI
fr30bf_h_cbit_get (SIM_CPU
*);
165 void fr30bf_h_cbit_set (SIM_CPU
*, BI
);
166 BI
fr30bf_h_ibit_get (SIM_CPU
*);
167 void fr30bf_h_ibit_set (SIM_CPU
*, BI
);
168 BI
fr30bf_h_sbit_get (SIM_CPU
*);
169 void fr30bf_h_sbit_set (SIM_CPU
*, BI
);
170 BI
fr30bf_h_tbit_get (SIM_CPU
*);
171 void fr30bf_h_tbit_set (SIM_CPU
*, BI
);
172 BI
fr30bf_h_d0bit_get (SIM_CPU
*);
173 void fr30bf_h_d0bit_set (SIM_CPU
*, BI
);
174 BI
fr30bf_h_d1bit_get (SIM_CPU
*);
175 void fr30bf_h_d1bit_set (SIM_CPU
*, BI
);
176 UQI
fr30bf_h_ccr_get (SIM_CPU
*);
177 void fr30bf_h_ccr_set (SIM_CPU
*, UQI
);
178 UQI
fr30bf_h_scr_get (SIM_CPU
*);
179 void fr30bf_h_scr_set (SIM_CPU
*, UQI
);
180 UQI
fr30bf_h_ilm_get (SIM_CPU
*);
181 void fr30bf_h_ilm_set (SIM_CPU
*, UQI
);
183 /* These must be hand-written. */
184 extern CPUREG_FETCH_FN fr30bf_fetch_register
;
185 extern CPUREG_STORE_FN fr30bf_store_register
;
189 UINT load_regs_pending
;
192 /* Instruction argument buffer. */
195 struct { /* no operands */
209 unsigned char in_h_gr_SI_15
;
210 unsigned char out_h_gr_SI_15
;
214 unsigned char in_h_gr_SI_15
;
215 unsigned char out_h_gr_SI_15
;
219 unsigned char in_h_gr_SI_13
;
220 unsigned char out_h_gr_SI_13
;
224 unsigned char in_h_gr_SI_13
;
225 unsigned char out_h_gr_SI_13
;
229 unsigned char in_h_gr_SI_13
;
230 unsigned char out_h_gr_SI_13
;
234 unsigned char in_h_gr_SI_15
;
235 unsigned char out_h_gr_SI_15
;
247 unsigned char out_Ri
;
253 unsigned char out_Ri
;
259 unsigned char out_Ri
;
265 unsigned char out_Ri
;
269 unsigned char in_h_gr_SI_14
;
270 unsigned char in_h_gr_SI_15
;
271 unsigned char out_h_gr_SI_14
;
272 unsigned char out_h_gr_SI_15
;
278 unsigned char in_h_gr_SI_15
;
279 unsigned char out_h_gr_SI_15
;
286 unsigned char in_h_gr_SI_15
;
293 unsigned char in_h_gr_SI_14
;
300 unsigned char in_h_gr_SI_14
;
307 unsigned char in_h_gr_SI_14
;
312 unsigned char in_h_gr_SI_15
;
313 unsigned char out_Ri
;
314 unsigned char out_h_gr_SI_15
;
320 unsigned char in_h_gr_SI_15
;
321 unsigned char out_Ri
;
327 unsigned char in_h_gr_SI_14
;
328 unsigned char out_Ri
;
334 unsigned char in_h_gr_SI_14
;
335 unsigned char out_Ri
;
341 unsigned char in_h_gr_SI_14
;
342 unsigned char out_Ri
;
349 unsigned char out_Ri
;
356 unsigned char out_Ri
;
365 unsigned char in_h_gr_SI_13
;
373 unsigned char in_h_gr_SI_13
;
374 unsigned char out_Ri
;
383 unsigned char out_Ri
;
386 UINT f_reglist_hi_st
;
387 unsigned char in_h_gr_SI_10
;
388 unsigned char in_h_gr_SI_11
;
389 unsigned char in_h_gr_SI_12
;
390 unsigned char in_h_gr_SI_13
;
391 unsigned char in_h_gr_SI_14
;
392 unsigned char in_h_gr_SI_15
;
393 unsigned char in_h_gr_SI_8
;
394 unsigned char in_h_gr_SI_9
;
395 unsigned char out_h_gr_SI_15
;
398 UINT f_reglist_hi_ld
;
399 unsigned char in_h_gr_SI_15
;
400 unsigned char out_h_gr_SI_10
;
401 unsigned char out_h_gr_SI_11
;
402 unsigned char out_h_gr_SI_12
;
403 unsigned char out_h_gr_SI_13
;
404 unsigned char out_h_gr_SI_14
;
405 unsigned char out_h_gr_SI_15
;
406 unsigned char out_h_gr_SI_8
;
407 unsigned char out_h_gr_SI_9
;
410 UINT f_reglist_low_st
;
411 unsigned char in_h_gr_SI_0
;
412 unsigned char in_h_gr_SI_1
;
413 unsigned char in_h_gr_SI_15
;
414 unsigned char in_h_gr_SI_2
;
415 unsigned char in_h_gr_SI_3
;
416 unsigned char in_h_gr_SI_4
;
417 unsigned char in_h_gr_SI_5
;
418 unsigned char in_h_gr_SI_6
;
419 unsigned char in_h_gr_SI_7
;
420 unsigned char out_h_gr_SI_15
;
423 UINT f_reglist_low_ld
;
424 unsigned char in_h_gr_SI_15
;
425 unsigned char out_h_gr_SI_0
;
426 unsigned char out_h_gr_SI_1
;
427 unsigned char out_h_gr_SI_15
;
428 unsigned char out_h_gr_SI_2
;
429 unsigned char out_h_gr_SI_3
;
430 unsigned char out_h_gr_SI_4
;
431 unsigned char out_h_gr_SI_5
;
432 unsigned char out_h_gr_SI_6
;
433 unsigned char out_h_gr_SI_7
;
436 /* Writeback handler. */
438 /* Pointer to argbuf entry for insn whose results need writing back. */
439 const struct argbuf
*abuf
;
441 /* x-before handler */
443 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
446 /* x-after handler */
450 /* This entry is used to terminate each pbb. */
452 /* Number of insns in pbb. */
454 /* Next pbb to execute. */
456 SCACHE
*branch_target
;
461 /* The ARGBUF struct. */
463 /* These are the baseclass definitions. */
468 /* ??? Temporary hack for skip insns. */
471 /* cpu specific data follows */
474 union sem_fields fields
;
479 ??? SCACHE used to contain more than just argbuf. We could delete the
480 type entirely and always just use ARGBUF, but for future concerns and as
481 a level of abstraction it is left in. */
484 struct argbuf argbuf
;
487 /* Macros to simplify extraction, reading and semantic code.
488 These define and assign the local vars that contain the insn's fields. */
490 #define EXTRACT_IFMT_EMPTY_VARS \
492 #define EXTRACT_IFMT_EMPTY_CODE \
495 #define EXTRACT_IFMT_ADD_VARS \
501 #define EXTRACT_IFMT_ADD_CODE \
503 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
504 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
505 f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
506 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
508 #define EXTRACT_IFMT_ADDI_VARS \
514 #define EXTRACT_IFMT_ADDI_CODE \
516 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
517 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
518 f_u4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
519 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
521 #define EXTRACT_IFMT_ADD2_VARS \
527 #define EXTRACT_IFMT_ADD2_CODE \
529 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
530 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
531 f_m4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
532 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
534 #define EXTRACT_IFMT_DIV0S_VARS \
540 #define EXTRACT_IFMT_DIV0S_CODE \
542 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
543 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
544 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
545 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
547 #define EXTRACT_IFMT_DIV3_VARS \
553 #define EXTRACT_IFMT_DIV3_CODE \
555 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
556 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
557 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
558 f_op4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
560 #define EXTRACT_IFMT_LDI8_VARS \
565 #define EXTRACT_IFMT_LDI8_CODE \
567 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
568 f_i8 = EXTRACT_MSB0_UINT (insn, 16, 4, 8); \
569 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
571 #define EXTRACT_IFMT_LDI20_VARS \
578 /* Contents of trailing part of insn. */ \
581 #define EXTRACT_IFMT_LDI20_CODE \
583 word_1 = GETIMEMUHI (current_cpu, pc + 2); \
584 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
585 f_i20_4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
586 f_i20_16 = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 0)); \
588 f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
590 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
591 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
593 #define EXTRACT_IFMT_LDI32_VARS \
599 /* Contents of trailing part of insn. */ \
603 #define EXTRACT_IFMT_LDI32_CODE \
605 word_1 = GETIMEMUHI (current_cpu, pc + 2); \
606 word_2 = GETIMEMUHI (current_cpu, pc + 4); \
607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_i32 = (0|(EXTRACT_MSB0_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 16)); \
609 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
610 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
611 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
613 #define EXTRACT_IFMT_LDR14_VARS \
618 #define EXTRACT_IFMT_LDR14_CODE \
620 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
621 f_disp10 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (2)); \
622 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
624 #define EXTRACT_IFMT_LDR14UH_VARS \
629 #define EXTRACT_IFMT_LDR14UH_CODE \
631 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
632 f_disp9 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (1)); \
633 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
635 #define EXTRACT_IFMT_LDR14UB_VARS \
640 #define EXTRACT_IFMT_LDR14UB_CODE \
642 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
643 f_disp8 = EXTRACT_MSB0_INT (insn, 16, 4, 8); \
644 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
646 #define EXTRACT_IFMT_LDR15_VARS \
652 #define EXTRACT_IFMT_LDR15_CODE \
654 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
655 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
656 f_udisp6 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) << (2)); \
657 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
659 #define EXTRACT_IFMT_LDR15DR_VARS \
665 #define EXTRACT_IFMT_LDR15DR_CODE \
667 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
668 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
669 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
670 f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
672 #define EXTRACT_IFMT_MOVDR_VARS \
678 #define EXTRACT_IFMT_MOVDR_CODE \
680 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
681 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
682 f_Rs1 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
683 f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
685 #define EXTRACT_IFMT_CALL_VARS \
690 #define EXTRACT_IFMT_CALL_CODE \
692 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
693 f_op5 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
694 f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
696 #define EXTRACT_IFMT_INT_VARS \
701 #define EXTRACT_IFMT_INT_CODE \
703 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
704 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
705 f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
707 #define EXTRACT_IFMT_BRAD_VARS \
712 #define EXTRACT_IFMT_BRAD_CODE \
714 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
715 f_cc = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
716 f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
718 #define EXTRACT_IFMT_DMOVR13_VARS \
723 #define EXTRACT_IFMT_DMOVR13_CODE \
725 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
726 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
727 f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
729 #define EXTRACT_IFMT_DMOVR13H_VARS \
734 #define EXTRACT_IFMT_DMOVR13H_CODE \
736 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
737 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
738 f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
740 #define EXTRACT_IFMT_DMOVR13B_VARS \
745 #define EXTRACT_IFMT_DMOVR13B_CODE \
747 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
748 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
749 f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
751 #define EXTRACT_IFMT_COPOP_VARS \
759 /* Contents of trailing part of insn. */ \
762 #define EXTRACT_IFMT_COPOP_CODE \
764 word_1 = GETIMEMUHI (current_cpu, pc + 2); \
765 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
766 f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
767 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
768 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
769 f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
770 f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
771 f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
773 #define EXTRACT_IFMT_COPLD_VARS \
781 /* Contents of trailing part of insn. */ \
784 #define EXTRACT_IFMT_COPLD_CODE \
786 word_1 = GETIMEMUHI (current_cpu, pc + 2); \
787 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
788 f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
789 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
790 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
791 f_Rjc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
792 f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
793 f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
795 #define EXTRACT_IFMT_COPST_VARS \
803 /* Contents of trailing part of insn. */ \
806 #define EXTRACT_IFMT_COPST_CODE \
808 word_1 = GETIMEMUHI (current_cpu, pc + 2); \
809 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
810 f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
811 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
812 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
813 f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
814 f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
815 f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
817 #define EXTRACT_IFMT_ADDSP_VARS \
822 #define EXTRACT_IFMT_ADDSP_CODE \
824 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
825 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
826 f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); \
828 #define EXTRACT_IFMT_LDM0_VARS \
831 UINT f_reglist_low_ld; \
833 #define EXTRACT_IFMT_LDM0_CODE \
835 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
836 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
837 f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
839 #define EXTRACT_IFMT_LDM1_VARS \
842 UINT f_reglist_hi_ld; \
844 #define EXTRACT_IFMT_LDM1_CODE \
846 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
847 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
848 f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
850 #define EXTRACT_IFMT_STM0_VARS \
853 UINT f_reglist_low_st; \
855 #define EXTRACT_IFMT_STM0_CODE \
857 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
858 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
859 f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
861 #define EXTRACT_IFMT_STM1_VARS \
864 UINT f_reglist_hi_st; \
866 #define EXTRACT_IFMT_STM1_CODE \
868 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
869 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
870 f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
872 #define EXTRACT_IFMT_ENTER_VARS \
877 #define EXTRACT_IFMT_ENTER_CODE \
879 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
880 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
881 f_u10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
883 /* Collection of various things for the trace handler to use. */
885 typedef struct trace_record
{
890 #endif /* CPU_FR30BF_H */