1 /* fr30 simulator support code
2 Copyright (C) 1998, 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #define WANT_CPU_FR30BF
28 /* Convert gdb dedicated register number to actual dr reg number. */
31 decode_gdb_dr_regnum (int gdb_regnum
)
35 case TBR_REGNUM
: return H_DR_TBR
;
36 case RP_REGNUM
: return H_DR_RP
;
37 case SSP_REGNUM
: return H_DR_SSP
;
38 case USP_REGNUM
: return H_DR_USP
;
39 case MDH_REGNUM
: return H_DR_MDH
;
40 case MDL_REGNUM
: return H_DR_MDL
;
45 /* The contents of BUF are in target byte order. */
48 fr30bf_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
51 SETTWI (buf
, fr30bf_h_gr_get (current_cpu
, rn
));
56 SETTWI (buf
, fr30bf_h_pc_get (current_cpu
));
59 SETTWI (buf
, fr30bf_h_ps_get (current_cpu
));
67 SETTWI (buf
, fr30bf_h_dr_get (current_cpu
,
68 decode_gdb_dr_regnum (rn
)));
77 /* The contents of BUF are in target byte order. */
80 fr30bf_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
83 fr30bf_h_gr_set (current_cpu
, rn
, GETTWI (buf
));
88 fr30bf_h_pc_set (current_cpu
, GETTWI (buf
));
91 fr30bf_h_ps_set (current_cpu
, GETTWI (buf
));
99 fr30bf_h_dr_set (current_cpu
,
100 decode_gdb_dr_regnum (rn
),
110 /* Cover fns to access the ccr bits. */
113 fr30bf_h_sbit_get_handler (SIM_CPU
*current_cpu
)
119 fr30bf_h_sbit_set_handler (SIM_CPU
*current_cpu
, BI newval
)
121 int old_sbit
= CPU (h_sbit
);
122 int new_sbit
= (newval
!= 0);
124 CPU (h_sbit
) = new_sbit
;
126 /* When switching stack modes, update the registers. */
127 if (old_sbit
!= new_sbit
)
131 /* Switching user -> system. */
132 CPU (h_dr
[H_DR_USP
]) = CPU (h_gr
[H_GR_SP
]);
133 CPU (h_gr
[H_GR_SP
]) = CPU (h_dr
[H_DR_SSP
]);
137 /* Switching system -> user. */
138 CPU (h_dr
[H_DR_SSP
]) = CPU (h_gr
[H_GR_SP
]);
139 CPU (h_gr
[H_GR_SP
]) = CPU (h_dr
[H_DR_USP
]);
143 /* TODO: r15 interlock */
146 /* Cover fns to access the ccr bits. */
149 fr30bf_h_ccr_get_handler (SIM_CPU
*current_cpu
)
151 int ccr
= ( (GET_H_CBIT () << 0)
152 | (GET_H_VBIT () << 1)
153 | (GET_H_ZBIT () << 2)
154 | (GET_H_NBIT () << 3)
155 | (GET_H_IBIT () << 4)
156 | (GET_H_SBIT () << 5));
162 fr30bf_h_ccr_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
164 int ccr
= newval
& 0x3f;
166 SET_H_CBIT ((ccr
& 1) != 0);
167 SET_H_VBIT ((ccr
& 2) != 0);
168 SET_H_ZBIT ((ccr
& 4) != 0);
169 SET_H_NBIT ((ccr
& 8) != 0);
170 SET_H_IBIT ((ccr
& 0x10) != 0);
171 SET_H_SBIT ((ccr
& 0x20) != 0);
174 /* Cover fns to access the scr bits. */
177 fr30bf_h_scr_get_handler (SIM_CPU
*current_cpu
)
179 int scr
= ( (GET_H_TBIT () << 0)
180 | (GET_H_D0BIT () << 1)
181 | (GET_H_D1BIT () << 2));
186 fr30bf_h_scr_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
188 int scr
= newval
& 7;
190 SET_H_TBIT ((scr
& 1) != 0);
191 SET_H_D0BIT ((scr
& 2) != 0);
192 SET_H_D1BIT ((scr
& 4) != 0);
195 /* Cover fns to access the ilm bits. */
198 fr30bf_h_ilm_get_handler (SIM_CPU
*current_cpu
)
204 fr30bf_h_ilm_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
206 int ilm
= newval
& 0x1f;
207 int current_ilm
= CPU (h_ilm
);
209 /* We can only set new ilm values < 16 if the current ilm is < 16. Otherwise
210 we add 16 to the value we are given. */
211 if (current_ilm
>= 16 && ilm
< 16)
217 /* Cover fns to access the ps register. */
220 fr30bf_h_ps_get_handler (SIM_CPU
*current_cpu
)
222 int ccr
= GET_H_CCR ();
223 int scr
= GET_H_SCR ();
224 int ilm
= GET_H_ILM ();
226 return ccr
| (scr
<< 8) | (ilm
<< 16);
230 fr30bf_h_ps_set_handler (SIM_CPU
*current_cpu
, USI newval
)
232 int ccr
= newval
& 0xff;
233 int scr
= (newval
>> 8) & 7;
234 int ilm
= (newval
>> 16) & 0x1f;
241 /* Cover fns to access the dedicated registers. */
244 fr30bf_h_dr_get_handler (SIM_CPU
*current_cpu
, UINT dr
)
250 return GET_H_GR (H_GR_SP
);
252 return CPU (h_dr
[H_DR_SSP
]);
255 return GET_H_GR (H_GR_SP
);
257 return CPU (h_dr
[H_DR_USP
]);
262 return CPU (h_dr
[dr
]);
268 fr30bf_h_dr_set_handler (SIM_CPU
*current_cpu
, UINT dr
, SI newval
)
274 SET_H_GR (H_GR_SP
, newval
);
276 CPU (h_dr
[H_DR_SSP
]) = newval
;
280 SET_H_GR (H_GR_SP
, newval
);
282 CPU (h_dr
[H_DR_USP
]) = newval
;
288 CPU (h_dr
[dr
]) = newval
;
293 #if WITH_PROFILE_MODEL_P
295 /* FIXME: Some of these should be inline or macros. Later. */
297 /* Initialize cycle counting for an insn.
298 FIRST_P is non-zero if this is the first insn in a set of parallel
302 fr30bf_model_insn_before (SIM_CPU
*cpu
, int first_p
)
304 MODEL_FR30_1_DATA
*d
= CPU_MODEL_DATA (cpu
);
305 d
->load_regs_pending
= 0;
308 /* Record the cycles computed for an insn.
309 LAST_P is non-zero if this is the last insn in a set of parallel insns,
310 and we update the total cycle count.
311 CYCLES is the cycle count of the insn. */
314 fr30bf_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
316 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
317 MODEL_FR30_1_DATA
*d
= CPU_MODEL_DATA (cpu
);
319 PROFILE_MODEL_TOTAL_CYCLES (p
) += cycles
;
320 PROFILE_MODEL_CUR_INSN_CYCLES (p
) = cycles
;
321 d
->load_regs
= d
->load_regs_pending
;
325 check_load_stall (SIM_CPU
*cpu
, int regno
)
327 const MODEL_FR30_1_DATA
*d
= CPU_MODEL_DATA (cpu
);
328 UINT load_regs
= d
->load_regs
;
331 && (load_regs
& (1 << regno
)) != 0)
333 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
334 ++ PROFILE_MODEL_LOAD_STALL_CYCLES (p
);
335 if (TRACE_INSN_P (cpu
))
336 cgen_trace_printf (cpu
, " ; Load stall.");
344 fr30bf_model_fr30_1_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
345 int unit_num
, int referenced
,
346 INT in_Ri
, INT in_Rj
, INT out_Ri
)
348 int cycles
= idesc
->timing
->units
[unit_num
].done
;
349 cycles
+= check_load_stall (cpu
, in_Ri
);
350 cycles
+= check_load_stall (cpu
, in_Rj
);
355 fr30bf_model_fr30_1_u_cti (SIM_CPU
*cpu
, const IDESC
*idesc
,
356 int unit_num
, int referenced
,
359 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
360 /* (1 << 1): The pc is the 2nd element in inputs, outputs.
361 ??? can be cleaned up */
362 int taken_p
= (referenced
& (1 << 1)) != 0;
363 int cycles
= idesc
->timing
->units
[unit_num
].done
;
364 int delay_slot_p
= CGEN_ATTR_VALUE (NULL
, idesc
->attrs
, CGEN_INSN_DELAY_SLOT
);
366 cycles
+= check_load_stall (cpu
, in_Ri
);
369 /* ??? Handling cti's without delay slots this way will run afoul of
370 accurate system simulation. Later. */
374 ++PROFILE_MODEL_CTI_STALL_CYCLES (p
);
376 ++PROFILE_MODEL_TAKEN_COUNT (p
);
379 ++PROFILE_MODEL_UNTAKEN_COUNT (p
);
385 fr30bf_model_fr30_1_u_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
386 int unit_num
, int referenced
,
387 INT in_Rj
, INT out_Ri
)
389 MODEL_FR30_1_DATA
*d
= CPU_MODEL_DATA (cpu
);
390 int cycles
= idesc
->timing
->units
[unit_num
].done
;
391 d
->load_regs_pending
|= 1 << out_Ri
;
392 cycles
+= check_load_stall (cpu
, in_Rj
);
397 fr30bf_model_fr30_1_u_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
398 int unit_num
, int referenced
,
399 INT in_Ri
, INT in_Rj
)
401 int cycles
= idesc
->timing
->units
[unit_num
].done
;
402 cycles
+= check_load_stall (cpu
, in_Ri
);
403 cycles
+= check_load_stall (cpu
, in_Rj
);
408 fr30bf_model_fr30_1_u_ldm (SIM_CPU
*cpu
, const IDESC
*idesc
,
409 int unit_num
, int referenced
,
412 return idesc
->timing
->units
[unit_num
].done
;
416 fr30bf_model_fr30_1_u_stm (SIM_CPU
*cpu
, const IDESC
*idesc
,
417 int unit_num
, int referenced
,
420 return idesc
->timing
->units
[unit_num
].done
;
423 #endif /* WITH_PROFILE_MODEL_P */
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