sim/frv/frv-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
   3    Contributed by Red Hat
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef FRV_SIM_H
  22 #define FRV_SIM_H
  23
  24 #include "sim-options.h"
  25
  26 /* Not defined in the cgen cpu file for access restriction purposes.  */
  27 #define H_SPR_ACC4   1412
  28 #define H_SPR_ACC63  1471
  29 #define H_SPR_ACCG4  1476
  30 #define H_SPR_ACCG63 1535
  31
  32 /* gdb register numbers.  */
  33 #define GR_REGNUM_MAX   63
  34 #define FR_REGNUM_MAX  127
  35 #define PC_REGNUM      128
  36 #define SPR_REGNUM_MIN 129
  37 #define SPR_REGNUM_MAX (SPR_REGNUM_MIN + 4096 - 1)
  38
  39 /* Initialization of the frv cpu.  */
  40 void frv_initialize (SIM_CPU *, SIM_DESC);
  41 void frv_term (SIM_DESC);
  42 void frv_power_on_reset (SIM_CPU *);
  43 void frv_hardware_reset (SIM_CPU *);
  44 void frv_software_reset (SIM_CPU *);
  45
  46 /* The reset register.  See FRV LSI section 10.3.1  */
  47 #define RSTR_ADDRESS        0xfeff0500
  48 #define RSTR_INITIAL_VALUE  0x00000400
  49 #define RSTR_HARDWARE_RESET 0x00000200
  50 #define RSTR_SOFTWARE_RESET 0x00000100
  51
  52 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
  53 #define GET_RSTR_SR(rstr) (((rstr)     ) & 1)
  54
  55 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
  56 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
  57
  58 #define CLEAR_RSTR_P(rstr)  ((rstr) &= ~(1 << 10))
  59 #define CLEAR_RSTR_H(rstr)  ((rstr) &= ~(1 <<  9))
  60 #define CLEAR_RSTR_S(rstr)  ((rstr) &= ~(1 <<  8))
  61 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 <<  1))
  62 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
  63
  64 /* Cutomized hardware get/set functions.  */
  65 extern USI  frvbf_h_spr_get_handler (SIM_CPU *, UINT);
  66 extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
  67 extern USI  frvbf_h_gr_get_handler (SIM_CPU *, UINT);
  68 extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
  69 extern UHI  frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
  70 extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
  71 extern UHI  frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
  72 extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
  73 extern DI   frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
  74 extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
  75 extern SF   frvbf_h_fr_get_handler (SIM_CPU *, UINT);
  76 extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
  77 extern DF   frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
  78 extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
  79 extern USI  frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
  80 extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
  81 extern DI   frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
  82 extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
  83 extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
  84 extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
  85 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
  86 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
  87
  88 extern USI  spr_psr_get_handler (SIM_CPU *);
  89 extern void spr_psr_set_handler (SIM_CPU *, USI);
  90 extern USI  spr_tbr_get_handler (SIM_CPU *);
  91 extern void spr_tbr_set_handler (SIM_CPU *, USI);
  92 extern USI  spr_bpsr_get_handler (SIM_CPU *);
  93 extern void spr_bpsr_set_handler (SIM_CPU *, USI);
  94 extern USI  spr_ccr_get_handler (SIM_CPU *);
  95 extern void spr_ccr_set_handler (SIM_CPU *, USI);
  96 extern void spr_cccr_set_handler (SIM_CPU *, USI);
  97 extern USI  spr_cccr_get_handler (SIM_CPU *);
  98 extern USI  spr_isr_get_handler (SIM_CPU *);
  99 extern void spr_isr_set_handler (SIM_CPU *, USI);
 100 extern USI  spr_sr_get_handler (SIM_CPU *, UINT);
 101 extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
 102
 103 extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
 104
 105 extern QI frvbf_set_icc_for_shift_left  (SIM_CPU *, SI, SI, QI);
 106 extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
 107
 108 /* Insn semantics.  */
 109 extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
 110 extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
 111 extern SI   frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
 112 extern SI   frvbf_iacc_cut (SIM_CPU *, DI, SI);
 113
 114 extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
 115
 116 extern SI   frvbf_scan_result (SIM_CPU *, SI);
 117 extern SI   frvbf_cut (SIM_CPU *, SI, SI, SI);
 118 extern SI   frvbf_media_cut (SIM_CPU *, DI, SI);
 119 extern SI   frvbf_media_cut_ss (SIM_CPU *, DI, SI);
 120 extern void frvbf_media_cop (SIM_CPU *, int);
 121 extern UQI  frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
 122
 123 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
 124 extern int  frvbf_write_next_vliw_addr_to_LR;
 125
 126 extern void frvbf_set_ne_index (SIM_CPU *, int);
 127 extern void frvbf_force_update (SIM_CPU *);
 128 \f
 129 #define GETTWI GETTSI
 130 #define SETTWI SETTSI
 131 #define LEUINT LEUSI
 132 \f
 133 /* Hardware/device support.
 134    ??? Will eventually want to move device stuff to config files.  */
 135
 136 /* Support for the MCCR register (Cache Control Register) is needed in order
 137    for overlays to work correctly with the scache: cached instructions need
 138    to be flushed when the instruction space is changed at runtime.  */
 139
 140 /* These were just copied from another port and are necessary to build, but
 141    but don't appear to be used.  */
 142 #define MCCR_ADDR 0xffffffff
 143 #define MCCR_CP 0x80
 144 /* not supported */
 145 #define MCCR_CM0 2
 146 #define MCCR_CM1 1
 147
 148 /* sim_core_attach device argument.  */
 149 extern device frv_devices;
 150
 151 /* FIXME: Temporary, until device support ready.  */
 152 struct _device { int foo; };
 153
 154 /* maintain the address of the start of the previous VLIW insn sequence.  */
 155 extern IADDR previous_vliw_pc;
 156 extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
 157
 158 /* Hardware status.  */
 159 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
 160 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
 161
 162 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
 163 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
 164 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
 165
 166 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
 167 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
 168 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
 169
 170 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
 171 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
 172 #define GET_HSR0_SA(hsr0)  (((hsr0) >> 12) & 1)
 173 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
 174 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
 175 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
 176 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
 177 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
 178 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
 179
 180 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
 181 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
 182 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >>  1) & 1)
 183 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >>  8) & 7)
 184 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
 185
 186 void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
 187 void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
 188 void frvbf_insn_cache_unlock (SIM_CPU *, SI);
 189 void frvbf_data_cache_unlock (SIM_CPU *, SI);
 190 void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
 191 void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
 192 void frvbf_data_cache_flush (SIM_CPU *, SI, int);
 193
 194 /* FR-V Interrupt classes.
 195    These are declared in order of increasing priority.  */
 196 enum frv_interrupt_class
 197 {
 198   FRV_EXTERNAL_INTERRUPT,
 199   FRV_SOFTWARE_INTERRUPT,
 200   FRV_PROGRAM_INTERRUPT,
 201   FRV_BREAK_INTERRUPT,
 202   FRV_RESET_INTERRUPT,
 203   NUM_FRV_INTERRUPT_CLASSES
 204 };
 205
 206 /* FR-V Interrupt kinds.
 207    These are declared in order of increasing priority.  */
 208 enum frv_interrupt_kind
 209 {
 210   /* External interrupts */
 211   FRV_INTERRUPT_LEVEL_1,
 212   FRV_INTERRUPT_LEVEL_2,
 213   FRV_INTERRUPT_LEVEL_3,
 214   FRV_INTERRUPT_LEVEL_4,
 215   FRV_INTERRUPT_LEVEL_5,
 216   FRV_INTERRUPT_LEVEL_6,
 217   FRV_INTERRUPT_LEVEL_7,
 218   FRV_INTERRUPT_LEVEL_8,
 219   FRV_INTERRUPT_LEVEL_9,
 220   FRV_INTERRUPT_LEVEL_10,
 221   FRV_INTERRUPT_LEVEL_11,
 222   FRV_INTERRUPT_LEVEL_12,
 223   FRV_INTERRUPT_LEVEL_13,
 224   FRV_INTERRUPT_LEVEL_14,
 225   FRV_INTERRUPT_LEVEL_15,
 226   /* Software interrupt */
 227   FRV_TRAP_INSTRUCTION,
 228   /* Program interrupts */
 229   FRV_COMMIT_EXCEPTION,
 230   FRV_DIVISION_EXCEPTION,
 231   FRV_DATA_STORE_ERROR,
 232   FRV_DATA_ACCESS_EXCEPTION,
 233   FRV_DATA_ACCESS_MMU_MISS,
 234   FRV_DATA_ACCESS_ERROR,
 235   FRV_MP_EXCEPTION,
 236   FRV_FP_EXCEPTION,
 237   FRV_MEM_ADDRESS_NOT_ALIGNED,
 238   FRV_REGISTER_EXCEPTION,
 239   FRV_MP_DISABLED,
 240   FRV_FP_DISABLED,
 241   FRV_PRIVILEGED_INSTRUCTION,
 242   FRV_ILLEGAL_INSTRUCTION,
 243   FRV_INSTRUCTION_ACCESS_EXCEPTION,
 244   FRV_INSTRUCTION_ACCESS_ERROR,
 245   FRV_INSTRUCTION_ACCESS_MMU_MISS,
 246   FRV_COMPOUND_EXCEPTION,
 247   /* Break interrupt */
 248   FRV_BREAK_EXCEPTION,
 249   /* Reset interrupt */
 250   FRV_RESET,
 251   NUM_FRV_INTERRUPT_KINDS
 252 };
 253
 254 /* FRV interrupt exception codes */
 255 enum frv_ec
 256 {
 257   FRV_EC_DATA_STORE_ERROR             = 0x00,
 258   FRV_EC_INSTRUCTION_ACCESS_MMU_MISS  = 0x01,
 259   FRV_EC_INSTRUCTION_ACCESS_ERROR     = 0x02,
 260   FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
 261   FRV_EC_PRIVILEGED_INSTRUCTION       = 0x04,
 262   FRV_EC_ILLEGAL_INSTRUCTION          = 0x05,
 263   FRV_EC_FP_DISABLED                  = 0x06,
 264   FRV_EC_MP_DISABLED                  = 0x07,
 265   FRV_EC_MEM_ADDRESS_NOT_ALIGNED      = 0x0b,
 266   FRV_EC_REGISTER_EXCEPTION           = 0x0c,
 267   FRV_EC_FP_EXCEPTION                 = 0x0d,
 268   FRV_EC_MP_EXCEPTION                 = 0x0e,
 269   FRV_EC_DATA_ACCESS_ERROR            = 0x10,
 270   FRV_EC_DATA_ACCESS_MMU_MISS         = 0x11,
 271   FRV_EC_DATA_ACCESS_EXCEPTION        = 0x12,
 272   FRV_EC_DIVISION_EXCEPTION           = 0x13,
 273   FRV_EC_COMMIT_EXCEPTION             = 0x14,
 274   FRV_EC_NOT_EXECUTED                 = 0x1f,
 275   FRV_EC_INTERRUPT_LEVEL_1            = FRV_EC_NOT_EXECUTED,
 276   FRV_EC_INTERRUPT_LEVEL_2            = FRV_EC_NOT_EXECUTED,
 277   FRV_EC_INTERRUPT_LEVEL_3            = FRV_EC_NOT_EXECUTED,
 278   FRV_EC_INTERRUPT_LEVEL_4            = FRV_EC_NOT_EXECUTED,
 279   FRV_EC_INTERRUPT_LEVEL_5            = FRV_EC_NOT_EXECUTED,
 280   FRV_EC_INTERRUPT_LEVEL_6            = FRV_EC_NOT_EXECUTED,
 281   FRV_EC_INTERRUPT_LEVEL_7            = FRV_EC_NOT_EXECUTED,
 282   FRV_EC_INTERRUPT_LEVEL_8            = FRV_EC_NOT_EXECUTED,
 283   FRV_EC_INTERRUPT_LEVEL_9            = FRV_EC_NOT_EXECUTED,
 284   FRV_EC_INTERRUPT_LEVEL_10           = FRV_EC_NOT_EXECUTED,
 285   FRV_EC_INTERRUPT_LEVEL_11           = FRV_EC_NOT_EXECUTED,
 286   FRV_EC_INTERRUPT_LEVEL_12           = FRV_EC_NOT_EXECUTED,
 287   FRV_EC_INTERRUPT_LEVEL_13           = FRV_EC_NOT_EXECUTED,
 288   FRV_EC_INTERRUPT_LEVEL_14           = FRV_EC_NOT_EXECUTED,
 289   FRV_EC_INTERRUPT_LEVEL_15           = FRV_EC_NOT_EXECUTED,
 290   FRV_EC_TRAP_INSTRUCTION             = FRV_EC_NOT_EXECUTED,
 291   FRV_EC_COMPOUND_EXCEPTION           = FRV_EC_NOT_EXECUTED,
 292   FRV_EC_BREAK_EXCEPTION              = FRV_EC_NOT_EXECUTED,
 293   FRV_EC_RESET                        = FRV_EC_NOT_EXECUTED
 294 };
 295
 296 /* FR-V Interrupt.
 297    This struct contains enough information to describe a particular interrupt
 298    occurance.  */
 299 struct frv_interrupt
 300 {
 301   enum frv_interrupt_kind  kind;
 302   enum frv_ec              ec;
 303   enum frv_interrupt_class iclass;
 304   unsigned char deferred;
 305   unsigned char precise;
 306   unsigned char handler_offset;
 307 };
 308
 309 /* FR-V Interrupt table.
 310    Describes the interrupts supported by the FR-V.  */
 311 extern struct frv_interrupt frv_interrupt_table[];
 312
 313 /* FR-V Interrupt State.
 314    Interrupts are queued during execution of parallel insns and the interupt(s)
 315    to be handled determined by analysing the queue after each VLIW insn.  */
 316 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now.  */
 317
 318 /* register_exception codes */
 319 enum frv_rec
 320 {
 321   FRV_REC_UNIMPLEMENTED = 0,
 322   FRV_REC_UNALIGNED     = 1
 323 };
 324
 325 /* instruction_access_exception codes */
 326 enum frv_iaec
 327 {
 328   FRV_IAEC_PROTECT_VIOLATION = 1
 329 };
 330
 331 /* data_access_exception codes */
 332 enum frv_daec
 333 {
 334   FRV_DAEC_PROTECT_VIOLATION = 1
 335 };
 336
 337 /* division_exception ISR codes */
 338 enum frv_dtt
 339 {
 340   FRV_DTT_NO_EXCEPTION     = 0,
 341   FRV_DTT_DIVISION_BY_ZERO = 1,
 342   FRV_DTT_OVERFLOW         = 2,
 343   FRV_DTT_BOTH             = 3
 344 };
 345
 346 /* data written during an insn causing an interrupt */
 347 struct frv_data_written
 348 {
 349   USI words[4]; /* Actual data in words */
 350   int length;   /* length of data written */
 351 };
 352
 353 /* fp_exception info */
 354 /* Trap codes for FSR0 and FQ registers.  */
 355 enum frv_fsr_traps
 356 {
 357   FSR_INVALID_OPERATION = 0x20,
 358   FSR_OVERFLOW          = 0x10,
 359   FSR_UNDERFLOW         = 0x08,
 360   FSR_DIVISION_BY_ZERO  = 0x04,
 361   FSR_INEXACT           = 0x02,
 362   FSR_DENORMAL_INPUT    = 0x01,
 363   FSR_NO_EXCEPTION      = 0
 364 };
 365
 366 /* Floating point trap types for FSR.  */
 367 enum frv_fsr_ftt
 368 {
 369   FTT_NONE               = 0,
 370   FTT_IEEE_754_EXCEPTION = 1,
 371   FTT_UNIMPLEMENTED_FPOP = 3,
 372   FTT_SEQUENCE_ERROR     = 4,
 373   FTT_INVALID_FR         = 6,
 374   FTT_DENORMAL_INPUT     = 7
 375 };
 376
 377 struct frv_fp_exception_info
 378 {
 379   enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
 380   enum frv_fsr_ftt   ftt;      /* floating point trap type */
 381 };
 382
 383 struct frv_interrupt_queue_element
 384 {
 385   enum frv_interrupt_kind kind;      /* kind of interrupt */
 386   IADDR                   vpc;       /* address of insn causing interrupt */
 387   int                     slot;      /* VLIW slot containing the insn.  */
 388   USI                     eaddress;  /* address of data access */
 389   union {
 390     enum frv_rec  rec;               /* register exception code */
 391     enum frv_iaec iaec;              /* insn access exception code */
 392     enum frv_daec daec;              /* data access exception code */
 393     enum frv_dtt  dtt;               /* division exception code */
 394     struct frv_fp_exception_info fp_info;
 395     struct frv_data_written data_written;
 396   } u;
 397 };
 398
 399 struct frv_interrupt_timer
 400 {
 401   int enabled;
 402   unsigned value;
 403   unsigned current;
 404   enum frv_interrupt_kind interrupt;
 405 };
 406
 407 struct frv_interrupt_state
 408 {
 409   /* The interrupt queue */
 410   struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
 411   int queue_index;
 412
 413   /* interrupt queue element causing imprecise interrupt.  */
 414   struct frv_interrupt_queue_element *imprecise_interrupt;
 415
 416   /* interrupt timer.  */
 417   struct frv_interrupt_timer timer;
 418
 419   /* The last data written stored as an array of words.  */
 420   struct frv_data_written data_written;
 421
 422   /* The vliw slot of the insn causing the interrupt.  */
 423   int slot;
 424
 425   /* target register index for non excepting insns.  */
 426 #define NE_NOFLAG (-1)
 427   int ne_index;
 428
 429   /* Accumulated NE flags for non excepting floating point insns.  */
 430   SI f_ne_flags[2];
 431 };
 432
 433 extern struct frv_interrupt_state frv_interrupt_state;
 434
 435 /* Macros to manipulate the PSR.  */
 436 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
 437
 438 #define SET_PSR_ET(psr, et) (           \
 439   (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
 440 )
 441
 442 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
 443
 444 #define SET_PSR_S(psr, s) (                          \
 445   (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
 446 )
 447
 448 /* Macros to handle the ISR register.  */
 449 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
 450 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
 451
 452 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
 453
 454 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
 455 #define SET_ISR_DTT(isr, dtt) (                        \
 456   (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
 457 )
 458
 459 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
 460
 461 #define GET_ISR_EMAM(isr) ((isr) & 1)
 462
 463 /* Macros to handle exception status registers.
 464    Get and set the hardware directly, since we may be getting/setting fields
 465    which are not accessible to the user.  */
 466 #define GET_ESR(index) \
 467   (CPU (h_spr[H_SPR_ESR0 + (index)]))
 468 #define SET_ESR(index, esr) \
 469   (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
 470
 471 #define SET_ESR_VALID(esr) ((esr) |= 1)
 472 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
 473
 474 #define SET_ESR_EC(esr, ec) (                           \
 475   (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 476 )
 477
 478 #define SET_ESR_REC(esr, rec) (                        \
 479   (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
 480 )
 481
 482 #define SET_ESR_IAEC(esr, iaec) (                       \
 483   (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
 484 )
 485
 486 #define SET_ESR_DAEC(esr, daec) (                       \
 487   (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
 488 )
 489
 490 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
 491 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
 492
 493 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
 494 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
 495 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
 496
 497 #define GET_ESR_EDN(esr) ( \
 498   ((esr) >> 13) & 0xf      \
 499 )
 500 #define SET_ESR_EDN(esr, edn) (                       \
 501   (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
 502 )
 503
 504 #define SET_EPCR(index, address) \
 505   (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
 506
 507 #define SET_EAR(index, address) \
 508   (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
 509
 510 #define SET_EDR(index, edr) \
 511   (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
 512
 513 #define GET_ESFR(index) \
 514   (CPU (h_spr[H_SPR_ESFR0 + (index)]))
 515 #define SET_ESFR(index, esfr) \
 516   (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
 517
 518 #define GET_ESFR_FLAG(findex) ( \
 519   (findex) > 31 ? \
 520     ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
 521     : \
 522     ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
 523 )
 524 #define SET_ESFR_FLAG(findex) ( \
 525   (findex) > 31 ? \
 526     (CPU (h_spr[H_SPR_ESFR0]) = \
 527       (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
 528     ) : \
 529     (CPU (h_spr[H_SPR_ESFR1]) = \
 530       (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
 531     ) \
 532 )
 533
 534 /* The FSR registers.
 535    Get and set the hardware directly, since we may be getting/setting fields
 536    which are not accessible to the user.  */
 537 #define GET_FSR(index) \
 538   (CPU (h_spr[H_SPR_FSR0 + (index)]))
 539 #define SET_FSR(index, fsr) \
 540   (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
 541
 542 #define GET_FSR_TEM(fsr) ( \
 543   ((fsr) >> 24) & 0x3f     \
 544 )
 545
 546 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
 547 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
 548
 549 #define SET_FSR_FTT(fsr, ftt) (                          \
 550   (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
 551 )
 552
 553 #define GET_FSR_AEXC(fsr) ( \
 554   ((fsr) >> 10) & 0x3f      \
 555 )
 556 #define SET_FSR_AEXC(fsr, aexc) (                          \
 557   (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
 558 )
 559
 560 /* SIMD instruction exception codes for FQ.  */
 561 enum frv_sie
 562 {
 563   SIE_NIL   = 0,
 564   SIE_FRi   = 1,
 565   SIE_FRi_1 = 2
 566 };
 567
 568 /* MIV field of FQ.  */
 569 enum frv_miv
 570 {
 571   MIV_FLOAT = 0,
 572   MIV_MEDIA = 1
 573 };
 574
 575 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
 576    index here refers to the low order 32 bit element.
 577    Get and set the hardware directly, since we may be getting/setting fields
 578    which are not accessible to the user.  */
 579 #define GET_FQ(index) \
 580   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
 581 #define SET_FQ(index, fq) \
 582   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
 583
 584 #define SET_FQ_MIV(fq, miv) (                          \
 585   (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
 586 )
 587
 588 #define SET_FQ_SIE(fq, sie) (                          \
 589   (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
 590 )
 591
 592 #define SET_FQ_FTT(fq, ftt) (                        \
 593   (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
 594 )
 595
 596 #define SET_FQ_CEXC(fq, cexc) (                         \
 597   (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
 598 )
 599
 600 #define GET_FQ_VALID(fq) ((fq) & 1)
 601 #define SET_FQ_VALID(fq) ((fq) |= 1)
 602
 603 #define SET_FQ_OPC(index, insn) \
 604   (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
 605
 606 /* mp_exception support.  */
 607 /* Media trap types for MSR.  */
 608 enum frv_msr_mtt
 609 {
 610   MTT_NONE                = 0,
 611   MTT_OVERFLOW            = 1,
 612   MTT_ACC_NOT_ALIGNED     = 2,
 613   MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
 614   MTT_CR_NOT_ALIGNED      = 3,
 615   MTT_UNIMPLEMENTED_MPOP  = 5,
 616   MTT_INVALID_FR          = 6
 617 };
 618
 619 /* Media status registers.
 620    Get and set the hardware directly, since we may be getting/setting fields
 621    which are not accessible to the user.  */
 622 #define GET_MSR(index) \
 623   (CPU (h_spr[H_SPR_MSR0 + (index)]))
 624 #define SET_MSR(index, msr) \
 625   (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
 626
 627 #define GET_MSR_AOVF(msr) ((msr) & 1)
 628 #define SET_MSR_AOVF(msr) ((msr) |=  1)
 629
 630 #define GET_MSR_OVF(msr) ( \
 631   ((msr) >> 1) & 0x1       \
 632 )
 633 #define SET_MSR_OVF(msr) ( \
 634   (msr) |= (1 << 1)        \
 635 )
 636 #define CLEAR_MSR_OVF(msr) ( \
 637   (msr) &= ~(1 << 1)         \
 638 )
 639
 640 #define OR_MSR_SIE(msr, sie) (  \
 641   (msr) |= (((sie) & 0xf) << 2) \
 642 )
 643 #define CLEAR_MSR_SIE(msr) ( \
 644   (msr) &= ~(0xf << 2)       \
 645 )
 646
 647 #define GET_MSR_MTT(msr) ( \
 648   ((msr) >> 12) & 0x7      \
 649 )
 650 #define SET_MSR_MTT(msr, mtt) (                          \
 651   (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
 652 )
 653 #define GET_MSR_EMCI(msr) ( \
 654   ((msr) >> 24) & 0x1       \
 655 )
 656 #define GET_MSR_MPEM(msr) ( \
 657   ((msr) >> 27) & 0x1        \
 658 )
 659 #define GET_MSR_SRDAV(msr) ( \
 660   ((msr) >> 28) & 0x1        \
 661 )
 662 #define GET_MSR_RDAV(msr) ( \
 663   ((msr) >> 29) & 0x1       \
 664 )
 665 #define GET_MSR_RD(msr) ( \
 666   ((msr) >> 30) & 0x3     \
 667 )
 668
 669 void frvbf_media_register_not_aligned (SIM_CPU *);
 670 void frvbf_media_acc_not_aligned (SIM_CPU *);
 671 void frvbf_media_cr_not_aligned (SIM_CPU *);
 672 void frvbf_media_overflow (SIM_CPU *, int);
 673
 674 /* Functions for queuing and processing interrupts.  */
 675 struct frv_interrupt_queue_element *
 676 frv_queue_break_interrupt (SIM_CPU *);
 677
 678 struct frv_interrupt_queue_element *
 679 frv_queue_software_interrupt (SIM_CPU *, SI);
 680
 681 struct frv_interrupt_queue_element *
 682 frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 683
 684 struct frv_interrupt_queue_element *
 685 frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 686
 687 struct frv_interrupt_queue_element *
 688 frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 689
 690 struct frv_interrupt_queue_element *
 691 frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 692
 693 struct frv_interrupt_queue_element *
 694 frv_queue_float_disabled_interrupt (SIM_CPU *);
 695
 696 struct frv_interrupt_queue_element *
 697 frv_queue_media_disabled_interrupt (SIM_CPU *);
 698
 699 struct frv_interrupt_queue_element *
 700 frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 701
 702 struct frv_interrupt_queue_element *
 703 frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
 704
 705 struct frv_interrupt_queue_element *
 706 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
 707
 708 struct frv_interrupt_queue_element *
 709 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
 710
 711 struct frv_interrupt_queue_element *
 712 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
 713
 714 struct frv_interrupt_queue_element *
 715 frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
 716
 717 struct frv_interrupt_queue_element *
 718 frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
 719
 720 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
 721
 722 struct frv_interrupt_queue_element *
 723 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 724
 725 void
 726 frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
 727
 728 void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
 729 void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
 730
 731 void frv_process_interrupts (SIM_CPU *);
 732
 733 void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
 734 void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
 735 void frv_program_interrupt (
 736   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 737 );
 738 void frv_software_interrupt (
 739   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 740 );
 741 void frv_external_interrupt (
 742   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 743 );
 744 void frv_program_or_software_interrupt (
 745   SIM_CPU *, struct frv_interrupt *, IADDR
 746 );
 747 void frv_clear_interrupt_classes (
 748   enum frv_interrupt_class, enum frv_interrupt_class
 749 );
 750
 751 void
 752 frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
 753
 754 /* Special purpose traps.  */
 755 #define TRAP_SYSCALL    0x80
 756 #define TRAP_BREAKPOINT 0x81
 757 #define TRAP_REGDUMP1   0x82
 758 #define TRAP_REGDUMP2   0x83
 759
 760 /* Handle the trap insns  */
 761 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
 762 void frv_mtrap (SIM_CPU *);
 763 /* Handle the break insn.  */
 764 void frv_break (SIM_CPU *);
 765 /* Handle the rett insn.  */
 766 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
 767
 768 /* Parallel write queue flags.  */
 769 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
 770
 771 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
 772
 773 /* Functions and macros for handling non-excepting instruction side effects.
 774    Get and set the hardware directly, since we may be getting/setting fields
 775    which are not accessible to the user.  */
 776 #define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
 777 #define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
 778 #define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
 779 #define GET_NECR_VALID(necr) (((necr)     ) & 1)
 780
 781 #define NO_NESR    (-1)
 782 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
 783    Architecture volume 1.  */
 784 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
 785 #define NESR_REGISTER_NOT_ALIGNED    0x1
 786 #define NESR_UQI_SIZE 0
 787 #define NESR_QI_SIZE  1
 788 #define NESR_UHI_SIZE 2
 789 #define NESR_HI_SIZE  3
 790 #define NESR_SI_SIZE  4
 791 #define NESR_DI_SIZE  5
 792 #define NESR_XI_SIZE  6
 793
 794 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
 795 #define SET_NESR(index, value) (                          \
 796   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
 797                          H_SPR_NESR0 + (index), (value)), \
 798   frvbf_force_update (current_cpu)                        \
 799 )
 800 #define GET_NESR_VALID(nesr) ((nesr) & 1)
 801 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
 802
 803 #define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))
 804
 805 #define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
 806 #define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
 807 #define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))
 808
 809 #define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
 810 #define SET_NESR_DRN(nesr, drn) (                            \
 811   (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
 812 )
 813
 814 #define SET_NESR_SIZE(nesr, data_size) (                         \
 815   (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
 816 )
 817
 818 #define SET_NESR_NEAN(nesr, index) (                           \
 819   (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
 820 )
 821
 822 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
 823 #define SET_NESR_DAEC(nesr, daec) (                   \
 824   (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
 825 )
 826
 827 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
 828 #define SET_NESR_REC(nesr, rec) (                    \
 829   (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
 830 )
 831
 832 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
 833 #define SET_NESR_EC(nesr, ec) (                       \
 834   (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 835 )
 836
 837 #define SET_NEEAR(index, address) ( \
 838   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
 839                          H_SPR_NEEAR0 + (index), (address)), \
 840   frvbf_force_update (current_cpu)                           \
 841 )
 842
 843 #define GET_NE_FLAGS(flags, NE_base) (   \
 844   (flags)[0] = GET_H_SPR ((NE_base)),    \
 845   (flags)[1] = GET_H_SPR ((NE_base) + 1) \
 846 )
 847 #define SET_NE_FLAGS(NE_base, flags) ( \
 848   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
 849                          (flags)[0]),                                  \
 850   frvbf_force_update (current_cpu),                                    \
 851   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
 852                          (flags)[1]),                                  \
 853   frvbf_force_update (current_cpu)                                     \
 854 )
 855
 856 #define GET_NE_FLAG(flags, index) (    \
 857   (index) > 31 ?                       \
 858     ((flags[0] >> ((index) - 32)) & 1) \
 859   :                                    \
 860     ((flags[1] >> (index)) & 1)        \
 861 )
 862 #define SET_NE_FLAG(flags, index) (       \
 863   (index) > 31 ?                          \
 864     ((flags)[0] |= (1 << ((index) - 32))) \
 865   :                                       \
 866     ((flags)[1] |= (1 << (index)))        \
 867 )
 868 #define CLEAR_NE_FLAG(flags, index) (      \
 869   (index) > 31 ?                           \
 870     ((flags)[0] &= ~(1 << ((index) - 32))) \
 871   :                                        \
 872     ((flags)[1] &= ~(1 << (index)))        \
 873 )
 874
 875 BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
 876 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
 877
 878 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
 879 void frvbf_commit (SIM_CPU *, SI, BI);
 880
 881 void frvbf_fpu_error (CGEN_FPU *, int);
 882
 883 void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
 884
 885 extern int insns_in_slot[];
 886
 887 #define COUNT_INSNS_IN_SLOT(slot) \
 888 {                                 \
 889   if (WITH_PROFILE_MODEL_P)       \
 890     ++insns_in_slot[slot];        \
 891 }
 892
 893 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
 894
 895 /* Multiple loads and stores.  */
 896 void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 897 void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 898 void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 899 void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 900 void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 901 void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 902
 903 /* Memory and cache support.  */
 904 QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
 905 UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
 906 HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
 907 UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
 908 SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
 909 SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
 910 DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
 911 DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);
 912
 913 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
 914
 915 void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
 916 void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
 917 void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
 918 void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
 919 void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
 920 void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
 921 void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
 922 void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);
 923
 924 void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
 925 void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
 926 void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
 927 void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
 928 void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
 929 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
 930
 931 void frv_set_write_queue_slot (SIM_CPU *current_cpu);
 932
 933 /* FRV specific options.  */
 934 extern const OPTION frv_options[];
 935
 936 #endif /* FRV_SIM_H */