sim/frv/frv-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1998, 1999, 2000, 2001, 2003, 2007
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat
   5
   6 This file is part of the GNU Simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License along
  19 with this program; if not, write to the Free Software Foundation, Inc.,
  20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef FRV_SIM_H
  23 #define FRV_SIM_H
  24
  25 #include "sim-options.h"
  26
  27 /* True if SPR is the number of accumulator or accumulator guard register.  */
  28 #define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
  29
  30 /* Initialization of the frv cpu.  */
  31 void frv_initialize (SIM_CPU *, SIM_DESC);
  32 void frv_term (SIM_DESC);
  33 void frv_power_on_reset (SIM_CPU *);
  34 void frv_hardware_reset (SIM_CPU *);
  35 void frv_software_reset (SIM_CPU *);
  36
  37 /* The reset register.  See FRV LSI section 10.3.1  */
  38 #define RSTR_ADDRESS        0xfeff0500
  39 #define RSTR_INITIAL_VALUE  0x00000400
  40 #define RSTR_HARDWARE_RESET 0x00000200
  41 #define RSTR_SOFTWARE_RESET 0x00000100
  42
  43 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
  44 #define GET_RSTR_SR(rstr) (((rstr)     ) & 1)
  45
  46 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
  47 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
  48
  49 #define CLEAR_RSTR_P(rstr)  ((rstr) &= ~(1 << 10))
  50 #define CLEAR_RSTR_H(rstr)  ((rstr) &= ~(1 <<  9))
  51 #define CLEAR_RSTR_S(rstr)  ((rstr) &= ~(1 <<  8))
  52 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 <<  1))
  53 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
  54
  55 /* Cutomized hardware get/set functions.  */
  56 extern USI  frvbf_h_spr_get_handler (SIM_CPU *, UINT);
  57 extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
  58 extern USI  frvbf_h_gr_get_handler (SIM_CPU *, UINT);
  59 extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
  60 extern UHI  frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
  61 extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
  62 extern UHI  frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
  63 extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
  64 extern DI   frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
  65 extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
  66 extern SF   frvbf_h_fr_get_handler (SIM_CPU *, UINT);
  67 extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
  68 extern DF   frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
  69 extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
  70 extern USI  frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
  71 extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
  72 extern DI   frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
  73 extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
  74 extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
  75 extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
  76 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
  77 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
  78
  79 extern USI  spr_psr_get_handler (SIM_CPU *);
  80 extern void spr_psr_set_handler (SIM_CPU *, USI);
  81 extern USI  spr_tbr_get_handler (SIM_CPU *);
  82 extern void spr_tbr_set_handler (SIM_CPU *, USI);
  83 extern USI  spr_bpsr_get_handler (SIM_CPU *);
  84 extern void spr_bpsr_set_handler (SIM_CPU *, USI);
  85 extern USI  spr_ccr_get_handler (SIM_CPU *);
  86 extern void spr_ccr_set_handler (SIM_CPU *, USI);
  87 extern void spr_cccr_set_handler (SIM_CPU *, USI);
  88 extern USI  spr_cccr_get_handler (SIM_CPU *);
  89 extern USI  spr_isr_get_handler (SIM_CPU *);
  90 extern void spr_isr_set_handler (SIM_CPU *, USI);
  91 extern USI  spr_sr_get_handler (SIM_CPU *, UINT);
  92 extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
  93
  94 extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
  95
  96 extern QI frvbf_set_icc_for_shift_left  (SIM_CPU *, SI, SI, QI);
  97 extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
  98
  99 /* Insn semantics.  */
 100 extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
 101 extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
 102 extern SI   frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
 103 extern SI   frvbf_iacc_cut (SIM_CPU *, DI, SI);
 104
 105 extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
 106
 107 extern SI   frvbf_scan_result (SIM_CPU *, SI);
 108 extern SI   frvbf_cut (SIM_CPU *, SI, SI, SI);
 109 extern SI   frvbf_media_cut (SIM_CPU *, DI, SI);
 110 extern SI   frvbf_media_cut_ss (SIM_CPU *, DI, SI);
 111 extern void frvbf_media_cop (SIM_CPU *, int);
 112 extern UQI  frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
 113
 114 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
 115 extern int  frvbf_write_next_vliw_addr_to_LR;
 116
 117 extern void frvbf_set_ne_index (SIM_CPU *, int);
 118 extern void frvbf_force_update (SIM_CPU *);
 119 \f
 120 #define GETTWI GETTSI
 121 #define SETTWI SETTSI
 122 #define LEUINT LEUSI
 123 \f
 124 /* Hardware/device support.
 125    ??? Will eventually want to move device stuff to config files.  */
 126
 127 /* Support for the MCCR register (Cache Control Register) is needed in order
 128    for overlays to work correctly with the scache: cached instructions need
 129    to be flushed when the instruction space is changed at runtime.  */
 130
 131 /* These were just copied from another port and are necessary to build, but
 132    but don't appear to be used.  */
 133 #define MCCR_ADDR 0xffffffff
 134 #define MCCR_CP 0x80
 135 /* not supported */
 136 #define MCCR_CM0 2
 137 #define MCCR_CM1 1
 138
 139 /* sim_core_attach device argument.  */
 140 extern device frv_devices;
 141
 142 /* FIXME: Temporary, until device support ready.  */
 143 struct _device { int foo; };
 144
 145 /* maintain the address of the start of the previous VLIW insn sequence.  */
 146 extern IADDR previous_vliw_pc;
 147 extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
 148
 149 /* Hardware status.  */
 150 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
 151 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
 152
 153 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
 154 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
 155 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
 156
 157 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
 158 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
 159 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
 160
 161 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
 162 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
 163 #define GET_HSR0_SA(hsr0)  (((hsr0) >> 12) & 1)
 164 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
 165 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
 166 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
 167 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
 168 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
 169 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
 170
 171 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
 172 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
 173 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >>  1) & 1)
 174 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >>  8) & 7)
 175 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
 176
 177 void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
 178 void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
 179 void frvbf_insn_cache_unlock (SIM_CPU *, SI);
 180 void frvbf_data_cache_unlock (SIM_CPU *, SI);
 181 void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
 182 void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
 183 void frvbf_data_cache_flush (SIM_CPU *, SI, int);
 184
 185 /* FR-V Interrupt classes.
 186    These are declared in order of increasing priority.  */
 187 enum frv_interrupt_class
 188 {
 189   FRV_EXTERNAL_INTERRUPT,
 190   FRV_SOFTWARE_INTERRUPT,
 191   FRV_PROGRAM_INTERRUPT,
 192   FRV_BREAK_INTERRUPT,
 193   FRV_RESET_INTERRUPT,
 194   NUM_FRV_INTERRUPT_CLASSES
 195 };
 196
 197 /* FR-V Interrupt kinds.
 198    These are declared in order of increasing priority.  */
 199 enum frv_interrupt_kind
 200 {
 201   /* External interrupts */
 202   FRV_INTERRUPT_LEVEL_1,
 203   FRV_INTERRUPT_LEVEL_2,
 204   FRV_INTERRUPT_LEVEL_3,
 205   FRV_INTERRUPT_LEVEL_4,
 206   FRV_INTERRUPT_LEVEL_5,
 207   FRV_INTERRUPT_LEVEL_6,
 208   FRV_INTERRUPT_LEVEL_7,
 209   FRV_INTERRUPT_LEVEL_8,
 210   FRV_INTERRUPT_LEVEL_9,
 211   FRV_INTERRUPT_LEVEL_10,
 212   FRV_INTERRUPT_LEVEL_11,
 213   FRV_INTERRUPT_LEVEL_12,
 214   FRV_INTERRUPT_LEVEL_13,
 215   FRV_INTERRUPT_LEVEL_14,
 216   FRV_INTERRUPT_LEVEL_15,
 217   /* Software interrupt */
 218   FRV_TRAP_INSTRUCTION,
 219   /* Program interrupts */
 220   FRV_COMMIT_EXCEPTION,
 221   FRV_DIVISION_EXCEPTION,
 222   FRV_DATA_STORE_ERROR,
 223   FRV_DATA_ACCESS_EXCEPTION,
 224   FRV_DATA_ACCESS_MMU_MISS,
 225   FRV_DATA_ACCESS_ERROR,
 226   FRV_MP_EXCEPTION,
 227   FRV_FP_EXCEPTION,
 228   FRV_MEM_ADDRESS_NOT_ALIGNED,
 229   FRV_REGISTER_EXCEPTION,
 230   FRV_MP_DISABLED,
 231   FRV_FP_DISABLED,
 232   FRV_PRIVILEGED_INSTRUCTION,
 233   FRV_ILLEGAL_INSTRUCTION,
 234   FRV_INSTRUCTION_ACCESS_EXCEPTION,
 235   FRV_INSTRUCTION_ACCESS_ERROR,
 236   FRV_INSTRUCTION_ACCESS_MMU_MISS,
 237   FRV_COMPOUND_EXCEPTION,
 238   /* Break interrupt */
 239   FRV_BREAK_EXCEPTION,
 240   /* Reset interrupt */
 241   FRV_RESET,
 242   NUM_FRV_INTERRUPT_KINDS
 243 };
 244
 245 /* FRV interrupt exception codes */
 246 enum frv_ec
 247 {
 248   FRV_EC_DATA_STORE_ERROR             = 0x00,
 249   FRV_EC_INSTRUCTION_ACCESS_MMU_MISS  = 0x01,
 250   FRV_EC_INSTRUCTION_ACCESS_ERROR     = 0x02,
 251   FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
 252   FRV_EC_PRIVILEGED_INSTRUCTION       = 0x04,
 253   FRV_EC_ILLEGAL_INSTRUCTION          = 0x05,
 254   FRV_EC_FP_DISABLED                  = 0x06,
 255   FRV_EC_MP_DISABLED                  = 0x07,
 256   FRV_EC_MEM_ADDRESS_NOT_ALIGNED      = 0x0b,
 257   FRV_EC_REGISTER_EXCEPTION           = 0x0c,
 258   FRV_EC_FP_EXCEPTION                 = 0x0d,
 259   FRV_EC_MP_EXCEPTION                 = 0x0e,
 260   FRV_EC_DATA_ACCESS_ERROR            = 0x10,
 261   FRV_EC_DATA_ACCESS_MMU_MISS         = 0x11,
 262   FRV_EC_DATA_ACCESS_EXCEPTION        = 0x12,
 263   FRV_EC_DIVISION_EXCEPTION           = 0x13,
 264   FRV_EC_COMMIT_EXCEPTION             = 0x14,
 265   FRV_EC_NOT_EXECUTED                 = 0x1f,
 266   FRV_EC_INTERRUPT_LEVEL_1            = FRV_EC_NOT_EXECUTED,
 267   FRV_EC_INTERRUPT_LEVEL_2            = FRV_EC_NOT_EXECUTED,
 268   FRV_EC_INTERRUPT_LEVEL_3            = FRV_EC_NOT_EXECUTED,
 269   FRV_EC_INTERRUPT_LEVEL_4            = FRV_EC_NOT_EXECUTED,
 270   FRV_EC_INTERRUPT_LEVEL_5            = FRV_EC_NOT_EXECUTED,
 271   FRV_EC_INTERRUPT_LEVEL_6            = FRV_EC_NOT_EXECUTED,
 272   FRV_EC_INTERRUPT_LEVEL_7            = FRV_EC_NOT_EXECUTED,
 273   FRV_EC_INTERRUPT_LEVEL_8            = FRV_EC_NOT_EXECUTED,
 274   FRV_EC_INTERRUPT_LEVEL_9            = FRV_EC_NOT_EXECUTED,
 275   FRV_EC_INTERRUPT_LEVEL_10           = FRV_EC_NOT_EXECUTED,
 276   FRV_EC_INTERRUPT_LEVEL_11           = FRV_EC_NOT_EXECUTED,
 277   FRV_EC_INTERRUPT_LEVEL_12           = FRV_EC_NOT_EXECUTED,
 278   FRV_EC_INTERRUPT_LEVEL_13           = FRV_EC_NOT_EXECUTED,
 279   FRV_EC_INTERRUPT_LEVEL_14           = FRV_EC_NOT_EXECUTED,
 280   FRV_EC_INTERRUPT_LEVEL_15           = FRV_EC_NOT_EXECUTED,
 281   FRV_EC_TRAP_INSTRUCTION             = FRV_EC_NOT_EXECUTED,
 282   FRV_EC_COMPOUND_EXCEPTION           = FRV_EC_NOT_EXECUTED,
 283   FRV_EC_BREAK_EXCEPTION              = FRV_EC_NOT_EXECUTED,
 284   FRV_EC_RESET                        = FRV_EC_NOT_EXECUTED
 285 };
 286
 287 /* FR-V Interrupt.
 288    This struct contains enough information to describe a particular interrupt
 289    occurance.  */
 290 struct frv_interrupt
 291 {
 292   enum frv_interrupt_kind  kind;
 293   enum frv_ec              ec;
 294   enum frv_interrupt_class iclass;
 295   unsigned char deferred;
 296   unsigned char precise;
 297   unsigned char handler_offset;
 298 };
 299
 300 /* FR-V Interrupt table.
 301    Describes the interrupts supported by the FR-V.  */
 302 extern struct frv_interrupt frv_interrupt_table[];
 303
 304 /* FR-V Interrupt State.
 305    Interrupts are queued during execution of parallel insns and the interupt(s)
 306    to be handled determined by analysing the queue after each VLIW insn.  */
 307 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now.  */
 308
 309 /* register_exception codes */
 310 enum frv_rec
 311 {
 312   FRV_REC_UNIMPLEMENTED = 0,
 313   FRV_REC_UNALIGNED     = 1
 314 };
 315
 316 /* instruction_access_exception codes */
 317 enum frv_iaec
 318 {
 319   FRV_IAEC_PROTECT_VIOLATION = 1
 320 };
 321
 322 /* data_access_exception codes */
 323 enum frv_daec
 324 {
 325   FRV_DAEC_PROTECT_VIOLATION = 1
 326 };
 327
 328 /* division_exception ISR codes */
 329 enum frv_dtt
 330 {
 331   FRV_DTT_NO_EXCEPTION     = 0,
 332   FRV_DTT_DIVISION_BY_ZERO = 1,
 333   FRV_DTT_OVERFLOW         = 2,
 334   FRV_DTT_BOTH             = 3
 335 };
 336
 337 /* data written during an insn causing an interrupt */
 338 struct frv_data_written
 339 {
 340   USI words[4]; /* Actual data in words */
 341   int length;   /* length of data written */
 342 };
 343
 344 /* fp_exception info */
 345 /* Trap codes for FSR0 and FQ registers.  */
 346 enum frv_fsr_traps
 347 {
 348   FSR_INVALID_OPERATION = 0x20,
 349   FSR_OVERFLOW          = 0x10,
 350   FSR_UNDERFLOW         = 0x08,
 351   FSR_DIVISION_BY_ZERO  = 0x04,
 352   FSR_INEXACT           = 0x02,
 353   FSR_DENORMAL_INPUT    = 0x01,
 354   FSR_NO_EXCEPTION      = 0
 355 };
 356
 357 /* Floating point trap types for FSR.  */
 358 enum frv_fsr_ftt
 359 {
 360   FTT_NONE               = 0,
 361   FTT_IEEE_754_EXCEPTION = 1,
 362   FTT_UNIMPLEMENTED_FPOP = 3,
 363   FTT_SEQUENCE_ERROR     = 4,
 364   FTT_INVALID_FR         = 6,
 365   FTT_DENORMAL_INPUT     = 7
 366 };
 367
 368 struct frv_fp_exception_info
 369 {
 370   enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
 371   enum frv_fsr_ftt   ftt;      /* floating point trap type */
 372 };
 373
 374 struct frv_interrupt_queue_element
 375 {
 376   enum frv_interrupt_kind kind;      /* kind of interrupt */
 377   IADDR                   vpc;       /* address of insn causing interrupt */
 378   int                     slot;      /* VLIW slot containing the insn.  */
 379   USI                     eaddress;  /* address of data access */
 380   union {
 381     enum frv_rec  rec;               /* register exception code */
 382     enum frv_iaec iaec;              /* insn access exception code */
 383     enum frv_daec daec;              /* data access exception code */
 384     enum frv_dtt  dtt;               /* division exception code */
 385     struct frv_fp_exception_info fp_info;
 386     struct frv_data_written data_written;
 387   } u;
 388 };
 389
 390 struct frv_interrupt_timer
 391 {
 392   int enabled;
 393   unsigned value;
 394   unsigned current;
 395   enum frv_interrupt_kind interrupt;
 396 };
 397
 398 struct frv_interrupt_state
 399 {
 400   /* The interrupt queue */
 401   struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
 402   int queue_index;
 403
 404   /* interrupt queue element causing imprecise interrupt.  */
 405   struct frv_interrupt_queue_element *imprecise_interrupt;
 406
 407   /* interrupt timer.  */
 408   struct frv_interrupt_timer timer;
 409
 410   /* The last data written stored as an array of words.  */
 411   struct frv_data_written data_written;
 412
 413   /* The vliw slot of the insn causing the interrupt.  */
 414   int slot;
 415
 416   /* target register index for non excepting insns.  */
 417 #define NE_NOFLAG (-1)
 418   int ne_index;
 419
 420   /* Accumulated NE flags for non excepting floating point insns.  */
 421   SI f_ne_flags[2];
 422 };
 423
 424 extern struct frv_interrupt_state frv_interrupt_state;
 425
 426 /* Macros to manipulate the PSR.  */
 427 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
 428
 429 #define SET_PSR_ET(psr, et) (           \
 430   (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
 431 )
 432
 433 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
 434
 435 #define SET_PSR_S(psr, s) (                          \
 436   (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
 437 )
 438
 439 /* Macros to handle the ISR register.  */
 440 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
 441 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
 442
 443 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
 444
 445 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
 446 #define SET_ISR_DTT(isr, dtt) (                        \
 447   (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
 448 )
 449
 450 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
 451
 452 #define GET_ISR_EMAM(isr) ((isr) & 1)
 453
 454 /* Macros to handle exception status registers.
 455    Get and set the hardware directly, since we may be getting/setting fields
 456    which are not accessible to the user.  */
 457 #define GET_ESR(index) \
 458   (CPU (h_spr[H_SPR_ESR0 + (index)]))
 459 #define SET_ESR(index, esr) \
 460   (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
 461
 462 #define SET_ESR_VALID(esr) ((esr) |= 1)
 463 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
 464
 465 #define SET_ESR_EC(esr, ec) (                           \
 466   (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 467 )
 468
 469 #define SET_ESR_REC(esr, rec) (                        \
 470   (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
 471 )
 472
 473 #define SET_ESR_IAEC(esr, iaec) (                       \
 474   (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
 475 )
 476
 477 #define SET_ESR_DAEC(esr, daec) (                       \
 478   (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
 479 )
 480
 481 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
 482 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
 483
 484 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
 485 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
 486 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
 487
 488 #define GET_ESR_EDN(esr) ( \
 489   ((esr) >> 13) & 0xf      \
 490 )
 491 #define SET_ESR_EDN(esr, edn) (                       \
 492   (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
 493 )
 494
 495 #define SET_EPCR(index, address) \
 496   (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
 497
 498 #define SET_EAR(index, address) \
 499   (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
 500
 501 #define SET_EDR(index, edr) \
 502   (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
 503
 504 #define GET_ESFR(index) \
 505   (CPU (h_spr[H_SPR_ESFR0 + (index)]))
 506 #define SET_ESFR(index, esfr) \
 507   (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
 508
 509 #define GET_ESFR_FLAG(findex) ( \
 510   (findex) > 31 ? \
 511     ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
 512     : \
 513     ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
 514 )
 515 #define SET_ESFR_FLAG(findex) ( \
 516   (findex) > 31 ? \
 517     (CPU (h_spr[H_SPR_ESFR0]) = \
 518       (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
 519     ) : \
 520     (CPU (h_spr[H_SPR_ESFR1]) = \
 521       (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
 522     ) \
 523 )
 524
 525 /* The FSR registers.
 526    Get and set the hardware directly, since we may be getting/setting fields
 527    which are not accessible to the user.  */
 528 #define GET_FSR(index) \
 529   (CPU (h_spr[H_SPR_FSR0 + (index)]))
 530 #define SET_FSR(index, fsr) \
 531   (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
 532
 533 #define GET_FSR_TEM(fsr) ( \
 534   ((fsr) >> 24) & 0x3f     \
 535 )
 536
 537 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
 538 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
 539
 540 #define SET_FSR_FTT(fsr, ftt) (                          \
 541   (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
 542 )
 543
 544 #define GET_FSR_AEXC(fsr) ( \
 545   ((fsr) >> 10) & 0x3f      \
 546 )
 547 #define SET_FSR_AEXC(fsr, aexc) (                          \
 548   (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
 549 )
 550
 551 /* SIMD instruction exception codes for FQ.  */
 552 enum frv_sie
 553 {
 554   SIE_NIL   = 0,
 555   SIE_FRi   = 1,
 556   SIE_FRi_1 = 2
 557 };
 558
 559 /* MIV field of FQ.  */
 560 enum frv_miv
 561 {
 562   MIV_FLOAT = 0,
 563   MIV_MEDIA = 1
 564 };
 565
 566 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
 567    index here refers to the low order 32 bit element.
 568    Get and set the hardware directly, since we may be getting/setting fields
 569    which are not accessible to the user.  */
 570 #define GET_FQ(index) \
 571   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
 572 #define SET_FQ(index, fq) \
 573   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
 574
 575 #define SET_FQ_MIV(fq, miv) (                          \
 576   (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
 577 )
 578
 579 #define SET_FQ_SIE(fq, sie) (                          \
 580   (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
 581 )
 582
 583 #define SET_FQ_FTT(fq, ftt) (                        \
 584   (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
 585 )
 586
 587 #define SET_FQ_CEXC(fq, cexc) (                         \
 588   (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
 589 )
 590
 591 #define GET_FQ_VALID(fq) ((fq) & 1)
 592 #define SET_FQ_VALID(fq) ((fq) |= 1)
 593
 594 #define SET_FQ_OPC(index, insn) \
 595   (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
 596
 597 /* mp_exception support.  */
 598 /* Media trap types for MSR.  */
 599 enum frv_msr_mtt
 600 {
 601   MTT_NONE                = 0,
 602   MTT_OVERFLOW            = 1,
 603   MTT_ACC_NOT_ALIGNED     = 2,
 604   MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
 605   MTT_CR_NOT_ALIGNED      = 3,
 606   MTT_UNIMPLEMENTED_MPOP  = 5,
 607   MTT_INVALID_FR          = 6
 608 };
 609
 610 /* Media status registers.
 611    Get and set the hardware directly, since we may be getting/setting fields
 612    which are not accessible to the user.  */
 613 #define GET_MSR(index) \
 614   (CPU (h_spr[H_SPR_MSR0 + (index)]))
 615 #define SET_MSR(index, msr) \
 616   (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
 617
 618 #define GET_MSR_AOVF(msr) ((msr) & 1)
 619 #define SET_MSR_AOVF(msr) ((msr) |=  1)
 620
 621 #define GET_MSR_OVF(msr) ( \
 622   ((msr) >> 1) & 0x1       \
 623 )
 624 #define SET_MSR_OVF(msr) ( \
 625   (msr) |= (1 << 1)        \
 626 )
 627 #define CLEAR_MSR_OVF(msr) ( \
 628   (msr) &= ~(1 << 1)         \
 629 )
 630
 631 #define OR_MSR_SIE(msr, sie) (  \
 632   (msr) |= (((sie) & 0xf) << 2) \
 633 )
 634 #define CLEAR_MSR_SIE(msr) ( \
 635   (msr) &= ~(0xf << 2)       \
 636 )
 637
 638 #define GET_MSR_MTT(msr) ( \
 639   ((msr) >> 12) & 0x7      \
 640 )
 641 #define SET_MSR_MTT(msr, mtt) (                          \
 642   (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
 643 )
 644 #define GET_MSR_EMCI(msr) ( \
 645   ((msr) >> 24) & 0x1       \
 646 )
 647 #define GET_MSR_MPEM(msr) ( \
 648   ((msr) >> 27) & 0x1        \
 649 )
 650 #define GET_MSR_SRDAV(msr) ( \
 651   ((msr) >> 28) & 0x1        \
 652 )
 653 #define GET_MSR_RDAV(msr) ( \
 654   ((msr) >> 29) & 0x1       \
 655 )
 656 #define GET_MSR_RD(msr) ( \
 657   ((msr) >> 30) & 0x3     \
 658 )
 659
 660 void frvbf_media_register_not_aligned (SIM_CPU *);
 661 void frvbf_media_acc_not_aligned (SIM_CPU *);
 662 void frvbf_media_cr_not_aligned (SIM_CPU *);
 663 void frvbf_media_overflow (SIM_CPU *, int);
 664
 665 /* Functions for queuing and processing interrupts.  */
 666 struct frv_interrupt_queue_element *
 667 frv_queue_break_interrupt (SIM_CPU *);
 668
 669 struct frv_interrupt_queue_element *
 670 frv_queue_software_interrupt (SIM_CPU *, SI);
 671
 672 struct frv_interrupt_queue_element *
 673 frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 674
 675 struct frv_interrupt_queue_element *
 676 frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 677
 678 struct frv_interrupt_queue_element *
 679 frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 680
 681 struct frv_interrupt_queue_element *
 682 frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 683
 684 struct frv_interrupt_queue_element *
 685 frv_queue_float_disabled_interrupt (SIM_CPU *);
 686
 687 struct frv_interrupt_queue_element *
 688 frv_queue_media_disabled_interrupt (SIM_CPU *);
 689
 690 struct frv_interrupt_queue_element *
 691 frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 692
 693 struct frv_interrupt_queue_element *
 694 frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
 695
 696 struct frv_interrupt_queue_element *
 697 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
 698
 699 struct frv_interrupt_queue_element *
 700 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
 701
 702 struct frv_interrupt_queue_element *
 703 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
 704
 705 struct frv_interrupt_queue_element *
 706 frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
 707
 708 struct frv_interrupt_queue_element *
 709 frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
 710
 711 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
 712
 713 struct frv_interrupt_queue_element *
 714 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 715
 716 void
 717 frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
 718
 719 void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
 720 void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
 721
 722 void frv_process_interrupts (SIM_CPU *);
 723
 724 void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
 725 void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
 726 void frv_program_interrupt (
 727   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 728 );
 729 void frv_software_interrupt (
 730   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 731 );
 732 void frv_external_interrupt (
 733   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 734 );
 735 void frv_program_or_software_interrupt (
 736   SIM_CPU *, struct frv_interrupt *, IADDR
 737 );
 738 void frv_clear_interrupt_classes (
 739   enum frv_interrupt_class, enum frv_interrupt_class
 740 );
 741
 742 void
 743 frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
 744
 745 /* Special purpose traps.  */
 746 #define TRAP_SYSCALL    0x80
 747 #define TRAP_BREAKPOINT 0x81
 748 #define TRAP_REGDUMP1   0x82
 749 #define TRAP_REGDUMP2   0x83
 750
 751 /* Handle the trap insns  */
 752 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
 753 void frv_mtrap (SIM_CPU *);
 754 /* Handle the break insn.  */
 755 void frv_break (SIM_CPU *);
 756 /* Handle the rett insn.  */
 757 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
 758
 759 /* Parallel write queue flags.  */
 760 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
 761
 762 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
 763
 764 /* Functions and macros for handling non-excepting instruction side effects.
 765    Get and set the hardware directly, since we may be getting/setting fields
 766    which are not accessible to the user.  */
 767 #define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
 768 #define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
 769 #define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
 770 #define GET_NECR_VALID(necr) (((necr)     ) & 1)
 771
 772 #define NO_NESR    (-1)
 773 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
 774    Architecture volume 1.  */
 775 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
 776 #define NESR_REGISTER_NOT_ALIGNED    0x1
 777 #define NESR_UQI_SIZE 0
 778 #define NESR_QI_SIZE  1
 779 #define NESR_UHI_SIZE 2
 780 #define NESR_HI_SIZE  3
 781 #define NESR_SI_SIZE  4
 782 #define NESR_DI_SIZE  5
 783 #define NESR_XI_SIZE  6
 784
 785 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
 786 #define SET_NESR(index, value) (                          \
 787   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
 788                          H_SPR_NESR0 + (index), (value)), \
 789   frvbf_force_update (current_cpu)                        \
 790 )
 791 #define GET_NESR_VALID(nesr) ((nesr) & 1)
 792 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
 793
 794 #define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))
 795
 796 #define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
 797 #define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
 798 #define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))
 799
 800 #define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
 801 #define SET_NESR_DRN(nesr, drn) (                            \
 802   (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
 803 )
 804
 805 #define SET_NESR_SIZE(nesr, data_size) (                         \
 806   (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
 807 )
 808
 809 #define SET_NESR_NEAN(nesr, index) (                           \
 810   (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
 811 )
 812
 813 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
 814 #define SET_NESR_DAEC(nesr, daec) (                   \
 815   (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
 816 )
 817
 818 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
 819 #define SET_NESR_REC(nesr, rec) (                    \
 820   (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
 821 )
 822
 823 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
 824 #define SET_NESR_EC(nesr, ec) (                       \
 825   (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 826 )
 827
 828 #define SET_NEEAR(index, address) ( \
 829   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
 830                          H_SPR_NEEAR0 + (index), (address)), \
 831   frvbf_force_update (current_cpu)                           \
 832 )
 833
 834 #define GET_NE_FLAGS(flags, NE_base) (   \
 835   (flags)[0] = GET_H_SPR ((NE_base)),    \
 836   (flags)[1] = GET_H_SPR ((NE_base) + 1) \
 837 )
 838 #define SET_NE_FLAGS(NE_base, flags) ( \
 839   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
 840                          (flags)[0]),                                  \
 841   frvbf_force_update (current_cpu),                                    \
 842   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
 843                          (flags)[1]),                                  \
 844   frvbf_force_update (current_cpu)                                     \
 845 )
 846
 847 #define GET_NE_FLAG(flags, index) (    \
 848   (index) > 31 ?                       \
 849     ((flags[0] >> ((index) - 32)) & 1) \
 850   :                                    \
 851     ((flags[1] >> (index)) & 1)        \
 852 )
 853 #define SET_NE_FLAG(flags, index) (       \
 854   (index) > 31 ?                          \
 855     ((flags)[0] |= (1 << ((index) - 32))) \
 856   :                                       \
 857     ((flags)[1] |= (1 << (index)))        \
 858 )
 859 #define CLEAR_NE_FLAG(flags, index) (      \
 860   (index) > 31 ?                           \
 861     ((flags)[0] &= ~(1 << ((index) - 32))) \
 862   :                                        \
 863     ((flags)[1] &= ~(1 << (index)))        \
 864 )
 865
 866 BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
 867 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
 868
 869 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
 870 void frvbf_commit (SIM_CPU *, SI, BI);
 871
 872 void frvbf_fpu_error (CGEN_FPU *, int);
 873
 874 void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
 875
 876 extern int insns_in_slot[];
 877
 878 #define COUNT_INSNS_IN_SLOT(slot) \
 879 {                                 \
 880   if (WITH_PROFILE_MODEL_P)       \
 881     ++insns_in_slot[slot];        \
 882 }
 883
 884 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
 885
 886 /* Multiple loads and stores.  */
 887 void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 888 void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 889 void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 890 void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
 891 void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
 892 void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
 893
 894 /* Memory and cache support.  */
 895 QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
 896 UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
 897 HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
 898 UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
 899 SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
 900 SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
 901 DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
 902 DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);
 903
 904 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
 905
 906 void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
 907 void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
 908 void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
 909 void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
 910 void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
 911 void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
 912 void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
 913 void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);
 914
 915 void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
 916 void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
 917 void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
 918 void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
 919 void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
 920 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
 921
 922 void frv_set_write_queue_slot (SIM_CPU *current_cpu);
 923
 924 /* FRV specific options.  */
 925 extern const OPTION frv_options[];
 926
 927 #endif /* FRV_SIM_H */