1 /* collection of junk waiting time to sort out
2 Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
5 This file is part of the GNU Simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "sim-options.h"
26 /* Not defined in the cgen cpu file for access restriction purposes. */
27 #define H_SPR_ACC4 1412
28 #define H_SPR_ACC63 1471
29 #define H_SPR_ACCG4 1476
30 #define H_SPR_ACCG63 1535
32 /* gdb register numbers. */
33 #define GR_REGNUM_MAX 63
34 #define FR_REGNUM_MAX 127
38 /* Initialization of the frv cpu. */
39 void frv_initialize (SIM_CPU
*, SIM_DESC
);
40 void frv_term (SIM_DESC
);
41 void frv_power_on_reset (SIM_CPU
*);
42 void frv_hardware_reset (SIM_CPU
*);
43 void frv_software_reset (SIM_CPU
*);
45 /* The reset register. See FRV LSI section 10.3.1 */
46 #define RSTR_ADDRESS 0xfeff0500
47 #define RSTR_INITIAL_VALUE 0x00000400
48 #define RSTR_HARDWARE_RESET 0x00000200
49 #define RSTR_SOFTWARE_RESET 0x00000100
51 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
52 #define GET_RSTR_SR(rstr) (((rstr) ) & 1)
54 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
55 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
57 #define CLEAR_RSTR_P(rstr) ((rstr) &= ~(1 << 10))
58 #define CLEAR_RSTR_H(rstr) ((rstr) &= ~(1 << 9))
59 #define CLEAR_RSTR_S(rstr) ((rstr) &= ~(1 << 8))
60 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 << 1))
61 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
63 /* Cutomized hardware get/set functions. */
64 extern USI
frvbf_h_spr_get_handler (SIM_CPU
*, UINT
);
65 extern void frvbf_h_spr_set_handler (SIM_CPU
*, UINT
, USI
);
66 extern USI
frvbf_h_gr_get_handler (SIM_CPU
*, UINT
);
67 extern void frvbf_h_gr_set_handler (SIM_CPU
*, UINT
, USI
);
68 extern UHI
frvbf_h_gr_hi_get_handler (SIM_CPU
*, UINT
);
69 extern void frvbf_h_gr_hi_set_handler (SIM_CPU
*, UINT
, UHI
);
70 extern UHI
frvbf_h_gr_lo_get_handler (SIM_CPU
*, UINT
);
71 extern void frvbf_h_gr_lo_set_handler (SIM_CPU
*, UINT
, UHI
);
72 extern DI
frvbf_h_gr_double_get_handler (SIM_CPU
*, UINT
);
73 extern void frvbf_h_gr_double_set_handler (SIM_CPU
*, UINT
, DI
);
74 extern SF
frvbf_h_fr_get_handler (SIM_CPU
*, UINT
);
75 extern void frvbf_h_fr_set_handler (SIM_CPU
*, UINT
, SF
);
76 extern DF
frvbf_h_fr_double_get_handler (SIM_CPU
*, UINT
);
77 extern void frvbf_h_fr_double_set_handler (SIM_CPU
*, UINT
, DF
);
78 extern USI
frvbf_h_fr_int_get_handler (SIM_CPU
*, UINT
);
79 extern void frvbf_h_fr_int_set_handler (SIM_CPU
*, UINT
, USI
);
80 extern DI
frvbf_h_cpr_double_get_handler (SIM_CPU
*, UINT
);
81 extern void frvbf_h_cpr_double_set_handler (SIM_CPU
*, UINT
, DI
);
82 extern void frvbf_h_gr_quad_set_handler (SIM_CPU
*, UINT
, SI
*);
83 extern void frvbf_h_fr_quad_set_handler (SIM_CPU
*, UINT
, SI
*);
84 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU
*, UINT
, SI
*);
85 extern void frvbf_h_psr_s_set_handler (SIM_CPU
*, BI
);
87 extern USI
spr_psr_get_handler (SIM_CPU
*);
88 extern void spr_psr_set_handler (SIM_CPU
*, USI
);
89 extern USI
spr_tbr_get_handler (SIM_CPU
*);
90 extern void spr_tbr_set_handler (SIM_CPU
*, USI
);
91 extern USI
spr_bpsr_get_handler (SIM_CPU
*);
92 extern void spr_bpsr_set_handler (SIM_CPU
*, USI
);
93 extern USI
spr_ccr_get_handler (SIM_CPU
*);
94 extern void spr_ccr_set_handler (SIM_CPU
*, USI
);
95 extern void spr_cccr_set_handler (SIM_CPU
*, USI
);
96 extern USI
spr_cccr_get_handler (SIM_CPU
*);
97 extern USI
spr_isr_get_handler (SIM_CPU
*);
98 extern void spr_isr_set_handler (SIM_CPU
*, USI
);
99 extern USI
spr_sr_get_handler (SIM_CPU
*, UINT
);
100 extern void spr_sr_set_handler (SIM_CPU
*, UINT
, USI
);
102 extern void frvbf_switch_supervisor_user_context (SIM_CPU
*);
104 extern QI
frvbf_set_icc_for_shift_left (SIM_CPU
*, SI
, SI
, QI
);
105 extern QI
frvbf_set_icc_for_shift_right (SIM_CPU
*, SI
, SI
, QI
);
107 /* Insn semantics. */
108 extern void frvbf_signed_integer_divide (SIM_CPU
*, SI
, SI
, int, int);
109 extern void frvbf_unsigned_integer_divide (SIM_CPU
*, USI
, USI
, int, int);
110 extern SI
frvbf_shift_left_arith_saturate (SIM_CPU
*, SI
, SI
);
111 extern SI
frvbf_iacc_cut (SIM_CPU
*, DI
, SI
);
113 extern void frvbf_clear_accumulators (SIM_CPU
*, SI
, int);
115 extern SI
frvbf_scan_result (SIM_CPU
*, SI
);
116 extern SI
frvbf_cut (SIM_CPU
*, SI
, SI
, SI
);
117 extern SI
frvbf_media_cut (SIM_CPU
*, DI
, SI
);
118 extern SI
frvbf_media_cut_ss (SIM_CPU
*, DI
, SI
);
119 extern void frvbf_media_cop (SIM_CPU
*, int);
120 extern UQI
frvbf_cr_logic (SIM_CPU
*, SI
, UQI
, UQI
);
122 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU
*, int);
123 extern int frvbf_write_next_vliw_addr_to_LR
;
125 extern void frvbf_set_ne_index (SIM_CPU
*, int);
126 extern void frvbf_force_update (SIM_CPU
*);
128 #define GETTWI GETTSI
129 #define SETTWI SETTSI
132 /* Hardware/device support.
133 ??? Will eventually want to move device stuff to config files. */
135 /* Support for the MCCR register (Cache Control Register) is needed in order
136 for overlays to work correctly with the scache: cached instructions need
137 to be flushed when the instruction space is changed at runtime. */
139 /* These were just copied from another port and are necessary to build, but
140 but don't appear to be used. */
141 #define MCCR_ADDR 0xffffffff
147 /* sim_core_attach device argument. */
148 extern device frv_devices
;
150 /* FIXME: Temporary, until device support ready. */
151 struct _device
{ int foo
; };
153 /* maintain the address of the start of the previous VLIW insn sequence. */
154 extern IADDR previous_vliw_pc
;
155 extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot
;
157 /* Hardware status. */
158 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
159 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
161 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
162 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
163 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
165 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
166 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
167 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
169 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
170 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
171 #define GET_HSR0_SA(hsr0) (((hsr0) >> 12) & 1)
172 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
173 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
174 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
175 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
176 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
177 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
179 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
180 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
181 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
182 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
183 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
185 void frvbf_insn_cache_preload (SIM_CPU
*, SI
, USI
, int);
186 void frvbf_data_cache_preload (SIM_CPU
*, SI
, USI
, int);
187 void frvbf_insn_cache_unlock (SIM_CPU
*, SI
);
188 void frvbf_data_cache_unlock (SIM_CPU
*, SI
);
189 void frvbf_insn_cache_invalidate (SIM_CPU
*, SI
, int);
190 void frvbf_data_cache_invalidate (SIM_CPU
*, SI
, int);
191 void frvbf_data_cache_flush (SIM_CPU
*, SI
, int);
193 /* FR-V Interrupt classes.
194 These are declared in order of increasing priority. */
195 enum frv_interrupt_class
197 FRV_EXTERNAL_INTERRUPT
,
198 FRV_SOFTWARE_INTERRUPT
,
199 FRV_PROGRAM_INTERRUPT
,
202 NUM_FRV_INTERRUPT_CLASSES
205 /* FR-V Interrupt kinds.
206 These are declared in order of increasing priority. */
207 enum frv_interrupt_kind
209 /* External interrupts */
210 FRV_INTERRUPT_LEVEL_1
,
211 FRV_INTERRUPT_LEVEL_2
,
212 FRV_INTERRUPT_LEVEL_3
,
213 FRV_INTERRUPT_LEVEL_4
,
214 FRV_INTERRUPT_LEVEL_5
,
215 FRV_INTERRUPT_LEVEL_6
,
216 FRV_INTERRUPT_LEVEL_7
,
217 FRV_INTERRUPT_LEVEL_8
,
218 FRV_INTERRUPT_LEVEL_9
,
219 FRV_INTERRUPT_LEVEL_10
,
220 FRV_INTERRUPT_LEVEL_11
,
221 FRV_INTERRUPT_LEVEL_12
,
222 FRV_INTERRUPT_LEVEL_13
,
223 FRV_INTERRUPT_LEVEL_14
,
224 FRV_INTERRUPT_LEVEL_15
,
225 /* Software interrupt */
226 FRV_TRAP_INSTRUCTION
,
227 /* Program interrupts */
228 FRV_COMMIT_EXCEPTION
,
229 FRV_DIVISION_EXCEPTION
,
230 FRV_DATA_STORE_ERROR
,
231 FRV_DATA_ACCESS_EXCEPTION
,
232 FRV_DATA_ACCESS_MMU_MISS
,
233 FRV_DATA_ACCESS_ERROR
,
236 FRV_MEM_ADDRESS_NOT_ALIGNED
,
237 FRV_REGISTER_EXCEPTION
,
240 FRV_PRIVILEGED_INSTRUCTION
,
241 FRV_ILLEGAL_INSTRUCTION
,
242 FRV_INSTRUCTION_ACCESS_EXCEPTION
,
243 FRV_INSTRUCTION_ACCESS_ERROR
,
244 FRV_INSTRUCTION_ACCESS_MMU_MISS
,
245 FRV_COMPOUND_EXCEPTION
,
246 /* Break interrupt */
248 /* Reset interrupt */
250 NUM_FRV_INTERRUPT_KINDS
253 /* FRV interrupt exception codes */
256 FRV_EC_DATA_STORE_ERROR
= 0x00,
257 FRV_EC_INSTRUCTION_ACCESS_MMU_MISS
= 0x01,
258 FRV_EC_INSTRUCTION_ACCESS_ERROR
= 0x02,
259 FRV_EC_INSTRUCTION_ACCESS_EXCEPTION
= 0x03,
260 FRV_EC_PRIVILEGED_INSTRUCTION
= 0x04,
261 FRV_EC_ILLEGAL_INSTRUCTION
= 0x05,
262 FRV_EC_FP_DISABLED
= 0x06,
263 FRV_EC_MP_DISABLED
= 0x07,
264 FRV_EC_MEM_ADDRESS_NOT_ALIGNED
= 0x0b,
265 FRV_EC_REGISTER_EXCEPTION
= 0x0c,
266 FRV_EC_FP_EXCEPTION
= 0x0d,
267 FRV_EC_MP_EXCEPTION
= 0x0e,
268 FRV_EC_DATA_ACCESS_ERROR
= 0x10,
269 FRV_EC_DATA_ACCESS_MMU_MISS
= 0x11,
270 FRV_EC_DATA_ACCESS_EXCEPTION
= 0x12,
271 FRV_EC_DIVISION_EXCEPTION
= 0x13,
272 FRV_EC_COMMIT_EXCEPTION
= 0x14,
273 FRV_EC_NOT_EXECUTED
= 0x1f,
274 FRV_EC_INTERRUPT_LEVEL_1
= FRV_EC_NOT_EXECUTED
,
275 FRV_EC_INTERRUPT_LEVEL_2
= FRV_EC_NOT_EXECUTED
,
276 FRV_EC_INTERRUPT_LEVEL_3
= FRV_EC_NOT_EXECUTED
,
277 FRV_EC_INTERRUPT_LEVEL_4
= FRV_EC_NOT_EXECUTED
,
278 FRV_EC_INTERRUPT_LEVEL_5
= FRV_EC_NOT_EXECUTED
,
279 FRV_EC_INTERRUPT_LEVEL_6
= FRV_EC_NOT_EXECUTED
,
280 FRV_EC_INTERRUPT_LEVEL_7
= FRV_EC_NOT_EXECUTED
,
281 FRV_EC_INTERRUPT_LEVEL_8
= FRV_EC_NOT_EXECUTED
,
282 FRV_EC_INTERRUPT_LEVEL_9
= FRV_EC_NOT_EXECUTED
,
283 FRV_EC_INTERRUPT_LEVEL_10
= FRV_EC_NOT_EXECUTED
,
284 FRV_EC_INTERRUPT_LEVEL_11
= FRV_EC_NOT_EXECUTED
,
285 FRV_EC_INTERRUPT_LEVEL_12
= FRV_EC_NOT_EXECUTED
,
286 FRV_EC_INTERRUPT_LEVEL_13
= FRV_EC_NOT_EXECUTED
,
287 FRV_EC_INTERRUPT_LEVEL_14
= FRV_EC_NOT_EXECUTED
,
288 FRV_EC_INTERRUPT_LEVEL_15
= FRV_EC_NOT_EXECUTED
,
289 FRV_EC_TRAP_INSTRUCTION
= FRV_EC_NOT_EXECUTED
,
290 FRV_EC_COMPOUND_EXCEPTION
= FRV_EC_NOT_EXECUTED
,
291 FRV_EC_BREAK_EXCEPTION
= FRV_EC_NOT_EXECUTED
,
292 FRV_EC_RESET
= FRV_EC_NOT_EXECUTED
296 This struct contains enough information to describe a particular interrupt
300 enum frv_interrupt_kind kind
;
302 enum frv_interrupt_class iclass
;
303 unsigned char deferred
;
304 unsigned char precise
;
305 unsigned char handler_offset
;
308 /* FR-V Interrupt table.
309 Describes the interrupts supported by the FR-V. */
310 extern struct frv_interrupt frv_interrupt_table
[];
312 /* FR-V Interrupt State.
313 Interrupts are queued during execution of parallel insns and the interupt(s)
314 to be handled determined by analysing the queue after each VLIW insn. */
315 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */
317 /* register_exception codes */
320 FRV_REC_UNIMPLEMENTED
= 0,
321 FRV_REC_UNALIGNED
= 1
324 /* instruction_access_exception codes */
327 FRV_IAEC_PROTECT_VIOLATION
= 1
330 /* data_access_exception codes */
333 FRV_DAEC_PROTECT_VIOLATION
= 1
336 /* division_exception ISR codes */
339 FRV_DTT_NO_EXCEPTION
= 0,
340 FRV_DTT_DIVISION_BY_ZERO
= 1,
341 FRV_DTT_OVERFLOW
= 2,
345 /* data written during an insn causing an interrupt */
346 struct frv_data_written
348 USI words
[4]; /* Actual data in words */
349 int length
; /* length of data written */
352 /* fp_exception info */
353 /* Trap codes for FSR0 and FQ registers. */
356 FSR_INVALID_OPERATION
= 0x20,
358 FSR_UNDERFLOW
= 0x08,
359 FSR_DIVISION_BY_ZERO
= 0x04,
361 FSR_DENORMAL_INPUT
= 0x01,
365 /* Floating point trap types for FSR. */
369 FTT_IEEE_754_EXCEPTION
= 1,
370 FTT_UNIMPLEMENTED_FPOP
= 3,
371 FTT_SEQUENCE_ERROR
= 4,
373 FTT_DENORMAL_INPUT
= 7
376 struct frv_fp_exception_info
378 enum frv_fsr_traps fsr_mask
; /* interrupt code for FSR */
379 enum frv_fsr_ftt ftt
; /* floating point trap type */
382 struct frv_interrupt_queue_element
384 enum frv_interrupt_kind kind
; /* kind of interrupt */
385 IADDR vpc
; /* address of insn causing interrupt */
386 int slot
; /* VLIW slot containing the insn. */
387 USI eaddress
; /* address of data access */
389 enum frv_rec rec
; /* register exception code */
390 enum frv_iaec iaec
; /* insn access exception code */
391 enum frv_daec daec
; /* data access exception code */
392 enum frv_dtt dtt
; /* division exception code */
393 struct frv_fp_exception_info fp_info
;
394 struct frv_data_written data_written
;
398 struct frv_interrupt_timer
403 enum frv_interrupt_kind interrupt
;
406 struct frv_interrupt_state
408 /* The interrupt queue */
409 struct frv_interrupt_queue_element queue
[FRV_INTERRUPT_QUEUE_SIZE
];
412 /* interrupt queue element causing imprecise interrupt. */
413 struct frv_interrupt_queue_element
*imprecise_interrupt
;
415 /* interrupt timer. */
416 struct frv_interrupt_timer timer
;
418 /* The last data written stored as an array of words. */
419 struct frv_data_written data_written
;
421 /* The vliw slot of the insn causing the interrupt. */
424 /* target register index for non excepting insns. */
425 #define NE_NOFLAG (-1)
428 /* Accumulated NE flags for non excepting floating point insns. */
432 extern struct frv_interrupt_state frv_interrupt_state
;
434 /* Macros to manipulate the PSR. */
435 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
437 #define SET_PSR_ET(psr, et) ( \
438 (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
441 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
443 #define SET_PSR_S(psr, s) ( \
444 (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
447 /* Macros to handle the ISR register. */
448 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
449 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
451 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
453 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
454 #define SET_ISR_DTT(isr, dtt) ( \
455 (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
458 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
460 #define GET_ISR_EMAM(isr) ((isr) & 1)
462 /* Macros to handle exception status registers.
463 Get and set the hardware directly, since we may be getting/setting fields
464 which are not accessible to the user. */
465 #define GET_ESR(index) \
466 (CPU (h_spr[H_SPR_ESR0 + (index)]))
467 #define SET_ESR(index, esr) \
468 (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
470 #define SET_ESR_VALID(esr) ((esr) |= 1)
471 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
473 #define SET_ESR_EC(esr, ec) ( \
474 (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
477 #define SET_ESR_REC(esr, rec) ( \
478 (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
481 #define SET_ESR_IAEC(esr, iaec) ( \
482 (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
485 #define SET_ESR_DAEC(esr, daec) ( \
486 (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
489 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
490 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
492 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
493 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
494 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
496 #define GET_ESR_EDN(esr) ( \
497 ((esr) >> 13) & 0xf \
499 #define SET_ESR_EDN(esr, edn) ( \
500 (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
503 #define SET_EPCR(index, address) \
504 (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
506 #define SET_EAR(index, address) \
507 (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
509 #define SET_EDR(index, edr) \
510 (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
512 #define GET_ESFR(index) \
513 (CPU (h_spr[H_SPR_ESFR0 + (index)]))
514 #define SET_ESFR(index, esfr) \
515 (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
517 #define GET_ESFR_FLAG(findex) ( \
519 ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
521 ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
523 #define SET_ESFR_FLAG(findex) ( \
525 (CPU (h_spr[H_SPR_ESFR0]) = \
526 (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
528 (CPU (h_spr[H_SPR_ESFR1]) = \
529 (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
533 /* The FSR registers.
534 Get and set the hardware directly, since we may be getting/setting fields
535 which are not accessible to the user. */
536 #define GET_FSR(index) \
537 (CPU (h_spr[H_SPR_FSR0 + (index)]))
538 #define SET_FSR(index, fsr) \
539 (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
541 #define GET_FSR_TEM(fsr) ( \
542 ((fsr) >> 24) & 0x3f \
545 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
546 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
548 #define SET_FSR_FTT(fsr, ftt) ( \
549 (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
552 #define GET_FSR_AEXC(fsr) ( \
553 ((fsr) >> 10) & 0x3f \
555 #define SET_FSR_AEXC(fsr, aexc) ( \
556 (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
559 /* SIMD instruction exception codes for FQ. */
567 /* MIV field of FQ. */
574 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
575 index here refers to the low order 32 bit element.
576 Get and set the hardware directly, since we may be getting/setting fields
577 which are not accessible to the user. */
578 #define GET_FQ(index) \
579 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
580 #define SET_FQ(index, fq) \
581 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
583 #define SET_FQ_MIV(fq, miv) ( \
584 (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
587 #define SET_FQ_SIE(fq, sie) ( \
588 (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
591 #define SET_FQ_FTT(fq, ftt) ( \
592 (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
595 #define SET_FQ_CEXC(fq, cexc) ( \
596 (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
599 #define GET_FQ_VALID(fq) ((fq) & 1)
600 #define SET_FQ_VALID(fq) ((fq) |= 1)
602 #define SET_FQ_OPC(index, insn) \
603 (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
605 /* mp_exception support. */
606 /* Media trap types for MSR. */
611 MTT_ACC_NOT_ALIGNED
= 2,
612 MTT_ACC_NOT_IMPLEMENTED
= 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED. */
613 MTT_CR_NOT_ALIGNED
= 3,
614 MTT_UNIMPLEMENTED_MPOP
= 5,
618 /* Media status registers.
619 Get and set the hardware directly, since we may be getting/setting fields
620 which are not accessible to the user. */
621 #define GET_MSR(index) \
622 (CPU (h_spr[H_SPR_MSR0 + (index)]))
623 #define SET_MSR(index, msr) \
624 (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
626 #define GET_MSR_AOVF(msr) ((msr) & 1)
627 #define SET_MSR_AOVF(msr) ((msr) |= 1)
629 #define GET_MSR_OVF(msr) ( \
632 #define SET_MSR_OVF(msr) ( \
635 #define CLEAR_MSR_OVF(msr) ( \
639 #define OR_MSR_SIE(msr, sie) ( \
640 (msr) |= (((sie) & 0xf) << 2) \
642 #define CLEAR_MSR_SIE(msr) ( \
643 (msr) &= ~(0xf << 2) \
646 #define GET_MSR_MTT(msr) ( \
647 ((msr) >> 12) & 0x7 \
649 #define SET_MSR_MTT(msr, mtt) ( \
650 (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
652 #define GET_MSR_EMCI(msr) ( \
653 ((msr) >> 24) & 0x1 \
655 #define GET_MSR_MPEM(msr) ( \
656 ((msr) >> 27) & 0x1 \
658 #define GET_MSR_SRDAV(msr) ( \
659 ((msr) >> 28) & 0x1 \
661 #define GET_MSR_RDAV(msr) ( \
662 ((msr) >> 29) & 0x1 \
664 #define GET_MSR_RD(msr) ( \
665 ((msr) >> 30) & 0x3 \
668 void frvbf_media_register_not_aligned (SIM_CPU
*);
669 void frvbf_media_acc_not_aligned (SIM_CPU
*);
670 void frvbf_media_cr_not_aligned (SIM_CPU
*);
671 void frvbf_media_overflow (SIM_CPU
*, int);
673 /* Functions for queuing and processing interrupts. */
674 struct frv_interrupt_queue_element
*
675 frv_queue_break_interrupt (SIM_CPU
*);
677 struct frv_interrupt_queue_element
*
678 frv_queue_software_interrupt (SIM_CPU
*, SI
);
680 struct frv_interrupt_queue_element
*
681 frv_queue_program_interrupt (SIM_CPU
*, enum frv_interrupt_kind
);
683 struct frv_interrupt_queue_element
*
684 frv_queue_external_interrupt (SIM_CPU
*, enum frv_interrupt_kind
);
686 struct frv_interrupt_queue_element
*
687 frv_queue_illegal_instruction_interrupt (SIM_CPU
*, const CGEN_INSN
*);
689 struct frv_interrupt_queue_element
*
690 frv_queue_privileged_instruction_interrupt (SIM_CPU
*, const CGEN_INSN
*);
692 struct frv_interrupt_queue_element
*
693 frv_queue_float_disabled_interrupt (SIM_CPU
*);
695 struct frv_interrupt_queue_element
*
696 frv_queue_media_disabled_interrupt (SIM_CPU
*);
698 struct frv_interrupt_queue_element
*
699 frv_queue_non_implemented_instruction_interrupt (SIM_CPU
*, const CGEN_INSN
*);
701 struct frv_interrupt_queue_element
*
702 frv_queue_register_exception_interrupt (SIM_CPU
*, enum frv_rec
);
704 struct frv_interrupt_queue_element
*
705 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU
*, USI
);
707 struct frv_interrupt_queue_element
*
708 frv_queue_data_access_error_interrupt (SIM_CPU
*, USI
);
710 struct frv_interrupt_queue_element
*
711 frv_queue_instruction_access_error_interrupt (SIM_CPU
*);
713 struct frv_interrupt_queue_element
*
714 frv_queue_instruction_access_exception_interrupt (SIM_CPU
*);
716 struct frv_interrupt_queue_element
*
717 frv_queue_fp_exception_interrupt (SIM_CPU
*, struct frv_fp_exception_info
*);
719 enum frv_dtt
frvbf_division_exception (SIM_CPU
*, enum frv_dtt
, int, int);
721 struct frv_interrupt_queue_element
*
722 frv_queue_interrupt (SIM_CPU
*, enum frv_interrupt_kind
);
725 frv_set_interrupt_queue_slot (SIM_CPU
*, struct frv_interrupt_queue_element
*);
727 void frv_set_mp_exception_registers (SIM_CPU
*, enum frv_msr_mtt
, int);
728 void frv_detect_insn_access_interrupts (SIM_CPU
*, SCACHE
*);
730 void frv_process_interrupts (SIM_CPU
*);
732 void frv_break_interrupt (SIM_CPU
*, struct frv_interrupt
*, IADDR
);
733 void frv_non_operating_interrupt (SIM_CPU
*, enum frv_interrupt_kind
, IADDR
);
734 void frv_program_interrupt (
735 SIM_CPU
*, struct frv_interrupt_queue_element
*, IADDR
737 void frv_software_interrupt (
738 SIM_CPU
*, struct frv_interrupt_queue_element
*, IADDR
740 void frv_external_interrupt (
741 SIM_CPU
*, struct frv_interrupt_queue_element
*, IADDR
743 void frv_program_or_software_interrupt (
744 SIM_CPU
*, struct frv_interrupt
*, IADDR
746 void frv_clear_interrupt_classes (
747 enum frv_interrupt_class
, enum frv_interrupt_class
751 frv_save_data_written_for_interrupts (SIM_CPU
*, CGEN_WRITE_QUEUE_ELEMENT
*);
753 /* Special purpose traps. */
754 #define TRAP_SYSCALL 0x80
755 #define TRAP_BREAKPOINT 0x81
756 #define TRAP_REGDUMP1 0x82
757 #define TRAP_REGDUMP2 0x83
759 /* Handle the trap insns */
760 void frv_itrap (SIM_CPU
*, PCADDR
, USI
, int);
761 void frv_mtrap (SIM_CPU
*);
762 /* Handle the break insn. */
763 void frv_break (SIM_CPU
*);
764 /* Handle the rett insn. */
765 USI
frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
);
767 /* Parallel write queue flags. */
768 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
770 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
772 /* Functions and macros for handling non-excepting instruction side effects.
773 Get and set the hardware directly, since we may be getting/setting fields
774 which are not accessible to the user. */
775 #define GET_NECR() (GET_H_SPR (H_SPR_NECR))
776 #define GET_NECR_ELOS(necr) (((necr) >> 6) & 1)
777 #define GET_NECR_NEN(necr) (((necr) >> 1) & 0x1f)
778 #define GET_NECR_VALID(necr) (((necr) ) & 1)
781 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
782 Architecture volume 1. */
783 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
784 #define NESR_REGISTER_NOT_ALIGNED 0x1
785 #define NESR_UQI_SIZE 0
786 #define NESR_QI_SIZE 1
787 #define NESR_UHI_SIZE 2
788 #define NESR_HI_SIZE 3
789 #define NESR_SI_SIZE 4
790 #define NESR_DI_SIZE 5
791 #define NESR_XI_SIZE 6
793 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
794 #define SET_NESR(index, value) ( \
795 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
796 H_SPR_NESR0 + (index), (value)), \
797 frvbf_force_update (current_cpu) \
799 #define GET_NESR_VALID(nesr) ((nesr) & 1)
800 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
802 #define SET_NESR_EAV(nesr) ((nesr) |= (1 << 31))
804 #define GET_NESR_FR(nesr) (((nesr) >> 30) & 1)
805 #define SET_NESR_FR(nesr) ((nesr) |= (1 << 30))
806 #define CLEAR_NESR_FR(nesr) ((nesr) &= ~(1 << 30))
808 #define GET_NESR_DRN(nesr) (((nesr) >> 24) & 0x3f)
809 #define SET_NESR_DRN(nesr, drn) ( \
810 (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
813 #define SET_NESR_SIZE(nesr, data_size) ( \
814 (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
817 #define SET_NESR_NEAN(nesr, index) ( \
818 (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
821 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
822 #define SET_NESR_DAEC(nesr, daec) ( \
823 (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
826 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
827 #define SET_NESR_REC(nesr, rec) ( \
828 (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
831 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
832 #define SET_NESR_EC(nesr, ec) ( \
833 (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
836 #define SET_NEEAR(index, address) ( \
837 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
838 H_SPR_NEEAR0 + (index), (address)), \
839 frvbf_force_update (current_cpu) \
842 #define GET_NE_FLAGS(flags, NE_base) ( \
843 (flags)[0] = GET_H_SPR ((NE_base)), \
844 (flags)[1] = GET_H_SPR ((NE_base) + 1) \
846 #define SET_NE_FLAGS(NE_base, flags) ( \
847 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base), \
849 frvbf_force_update (current_cpu), \
850 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1, \
852 frvbf_force_update (current_cpu) \
855 #define GET_NE_FLAG(flags, index) ( \
857 ((flags[0] >> ((index) - 32)) & 1) \
859 ((flags[1] >> (index)) & 1) \
861 #define SET_NE_FLAG(flags, index) ( \
863 ((flags)[0] |= (1 << ((index) - 32))) \
865 ((flags)[1] |= (1 << (index))) \
867 #define CLEAR_NE_FLAG(flags, index) ( \
869 ((flags)[0] &= ~(1 << ((index) - 32))) \
871 ((flags)[1] &= ~(1 << (index))) \
874 BI
frvbf_check_non_excepting_load (SIM_CPU
*, SI
, SI
, SI
, SI
, QI
, BI
);
875 void frvbf_check_recovering_store (SIM_CPU
*, PCADDR
, SI
, int, int);
877 void frvbf_clear_ne_flags (SIM_CPU
*, SI
, BI
);
878 void frvbf_commit (SIM_CPU
*, SI
, BI
);
880 void frvbf_fpu_error (CGEN_FPU
*, int);
882 void frv_vliw_setup_insn (SIM_CPU
*, const CGEN_INSN
*);
884 extern int insns_in_slot
[];
886 #define COUNT_INSNS_IN_SLOT(slot) \
888 if (WITH_PROFILE_MODEL_P) \
889 ++insns_in_slot[slot]; \
892 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
894 /* Multiple loads and stores. */
895 void frvbf_load_multiple_GR (SIM_CPU
*, PCADDR
, SI
, SI
, int);
896 void frvbf_load_multiple_FRint (SIM_CPU
*, PCADDR
, SI
, SI
, int);
897 void frvbf_load_multiple_CPR (SIM_CPU
*, PCADDR
, SI
, SI
, int);
898 void frvbf_store_multiple_GR (SIM_CPU
*, PCADDR
, SI
, SI
, int);
899 void frvbf_store_multiple_FRint (SIM_CPU
*, PCADDR
, SI
, SI
, int);
900 void frvbf_store_multiple_CPR (SIM_CPU
*, PCADDR
, SI
, SI
, int);
902 /* Memory and cache support. */
903 QI
frvbf_read_mem_QI (SIM_CPU
*, IADDR
, SI
);
904 UQI
frvbf_read_mem_UQI (SIM_CPU
*, IADDR
, SI
);
905 HI
frvbf_read_mem_HI (SIM_CPU
*, IADDR
, SI
);
906 UHI
frvbf_read_mem_UHI (SIM_CPU
*, IADDR
, SI
);
907 SI
frvbf_read_mem_SI (SIM_CPU
*, IADDR
, SI
);
908 SI
frvbf_read_mem_WI (SIM_CPU
*, IADDR
, SI
);
909 DI
frvbf_read_mem_DI (SIM_CPU
*, IADDR
, SI
);
910 DF
frvbf_read_mem_DF (SIM_CPU
*, IADDR
, SI
);
912 USI
frvbf_read_imem_USI (SIM_CPU
*, PCADDR
);
914 void frvbf_write_mem_QI (SIM_CPU
*, IADDR
, SI
, QI
);
915 void frvbf_write_mem_UQI (SIM_CPU
*, IADDR
, SI
, UQI
);
916 void frvbf_write_mem_HI (SIM_CPU
*, IADDR
, SI
, HI
);
917 void frvbf_write_mem_UHI (SIM_CPU
*, IADDR
, SI
, UHI
);
918 void frvbf_write_mem_SI (SIM_CPU
*, IADDR
, SI
, SI
);
919 void frvbf_write_mem_WI (SIM_CPU
*, IADDR
, SI
, SI
);
920 void frvbf_write_mem_DI (SIM_CPU
*, IADDR
, SI
, DI
);
921 void frvbf_write_mem_DF (SIM_CPU
*, IADDR
, SI
, DF
);
923 void frvbf_mem_set_QI (SIM_CPU
*, IADDR
, SI
, QI
);
924 void frvbf_mem_set_HI (SIM_CPU
*, IADDR
, SI
, HI
);
925 void frvbf_mem_set_SI (SIM_CPU
*, IADDR
, SI
, SI
);
926 void frvbf_mem_set_DI (SIM_CPU
*, IADDR
, SI
, DI
);
927 void frvbf_mem_set_DF (SIM_CPU
*, IADDR
, SI
, DF
);
928 void frvbf_mem_set_XI (SIM_CPU
*, IADDR
, SI
, SI
*);
930 void frv_set_write_queue_slot (SIM_CPU
*current_cpu
);
932 /* FRV specific options. */
933 extern const OPTION frv_options
[];
935 #endif /* FRV_SIM_H */