1 /* frv simulator support code
2 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #define WANT_CPU_FRVBF
27 #include "cgen-engine.h"
32 /* Maintain a flag in order to know when to write the address of the next
33 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL
35 int frvbf_write_next_vliw_addr_to_LR
;
37 /* The contents of BUF are in target byte order. */
39 frvbf_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
41 if (rn
<= GR_REGNUM_MAX
)
42 SETTSI (buf
, GET_H_GR (rn
));
43 else if (rn
<= FR_REGNUM_MAX
)
44 SETTSI (buf
, GET_H_FR (rn
- GR_REGNUM_MAX
- 1));
45 else if (rn
== PC_REGNUM
)
46 SETTSI (buf
, GET_H_PC ());
47 else if (rn
== LR_REGNUM
)
48 SETTSI (buf
, GET_H_SPR (H_SPR_LR
));
50 SETTSI (buf
, 0xdeadbeef);
55 /* The contents of BUF are in target byte order. */
58 frvbf_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
60 if (rn
<= GR_REGNUM_MAX
)
61 SET_H_GR (rn
, GETTSI (buf
));
62 else if (rn
<= FR_REGNUM_MAX
)
63 SET_H_FR (rn
- GR_REGNUM_MAX
- 1, GETTSI (buf
));
64 else if (rn
== PC_REGNUM
)
65 SET_H_PC (GETTSI (buf
));
66 else if (rn
== LR_REGNUM
)
67 SET_H_SPR (H_SPR_LR
, GETTSI (buf
));
72 /* Cover fns to access the general registers. */
74 frvbf_h_gr_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
76 frv_check_gr_access (current_cpu
, gr
);
77 return CPU (h_gr
[gr
]);
81 frvbf_h_gr_set_handler (SIM_CPU
*current_cpu
, UINT gr
, USI newval
)
83 frv_check_gr_access (current_cpu
, gr
);
86 return; /* Storing into gr0 has no effect. */
88 CPU (h_gr
[gr
]) = newval
;
91 /* Cover fns to access the floating point registers. */
93 frvbf_h_fr_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
95 frv_check_fr_access (current_cpu
, fr
);
96 return CPU (h_fr
[fr
]);
100 frvbf_h_fr_set_handler (SIM_CPU
*current_cpu
, UINT fr
, SF newval
)
102 frv_check_fr_access (current_cpu
, fr
);
103 CPU (h_fr
[fr
]) = newval
;
106 /* Cover fns to access the general registers as double words. */
108 check_register_alignment (SIM_CPU
*current_cpu
, UINT reg
, int align_mask
)
110 if (reg
& align_mask
)
112 SIM_DESC sd
= CPU_STATE (current_cpu
);
113 switch (STATE_ARCHITECTURE (sd
)->mach
)
116 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
118 case bfd_mach_frvtomcat
:
121 frv_queue_register_exception_interrupt (current_cpu
,
135 check_fr_register_alignment (SIM_CPU
*current_cpu
, UINT reg
, int align_mask
)
137 if (reg
& align_mask
)
139 SIM_DESC sd
= CPU_STATE (current_cpu
);
140 switch (STATE_ARCHITECTURE (sd
)->mach
)
143 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
145 case bfd_mach_frvtomcat
:
149 struct frv_fp_exception_info fp_info
= {
150 FSR_NO_EXCEPTION
, FTT_INVALID_FR
152 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);
166 check_memory_alignment (SIM_CPU
*current_cpu
, SI address
, int align_mask
)
168 if (address
& align_mask
)
170 SIM_DESC sd
= CPU_STATE (current_cpu
);
171 switch (STATE_ARCHITECTURE (sd
)->mach
)
174 frv_queue_data_access_error_interrupt (current_cpu
, address
);
176 case bfd_mach_frvtomcat
:
179 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, address
);
185 address
&= ~align_mask
;
192 frvbf_h_gr_double_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
197 return 0; /* gr0 is always 0. */
199 /* Check the register alignment. */
200 gr
= check_register_alignment (current_cpu
, gr
, 1);
202 value
= GET_H_GR (gr
);
204 value
|= (USI
) GET_H_GR (gr
+ 1);
209 frvbf_h_gr_double_set_handler (SIM_CPU
*current_cpu
, UINT gr
, DI newval
)
212 return; /* Storing into gr0 has no effect. */
214 /* Check the register alignment. */
215 gr
= check_register_alignment (current_cpu
, gr
, 1);
217 SET_H_GR (gr
, (newval
>> 32) & 0xffffffff);
218 SET_H_GR (gr
+ 1, (newval
) & 0xffffffff);
221 /* Cover fns to access the floating point register as double words. */
223 frvbf_h_fr_double_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
230 /* Check the register alignment. */
231 fr
= check_fr_register_alignment (current_cpu
, fr
, 1);
233 if (CURRENT_HOST_BYTE_ORDER
== LITTLE_ENDIAN
)
235 value
.as_sf
[1] = GET_H_FR (fr
);
236 value
.as_sf
[0] = GET_H_FR (fr
+ 1);
240 value
.as_sf
[0] = GET_H_FR (fr
);
241 value
.as_sf
[1] = GET_H_FR (fr
+ 1);
248 frvbf_h_fr_double_set_handler (SIM_CPU
*current_cpu
, UINT fr
, DF newval
)
255 /* Check the register alignment. */
256 fr
= check_fr_register_alignment (current_cpu
, fr
, 1);
258 value
.as_df
= newval
;
259 if (CURRENT_HOST_BYTE_ORDER
== LITTLE_ENDIAN
)
261 SET_H_FR (fr
, value
.as_sf
[1]);
262 SET_H_FR (fr
+ 1, value
.as_sf
[0]);
266 SET_H_FR (fr
, value
.as_sf
[0]);
267 SET_H_FR (fr
+ 1, value
.as_sf
[1]);
271 /* Cover fns to access the floating point register as integer words. */
273 frvbf_h_fr_int_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
280 value
.as_sf
= GET_H_FR (fr
);
285 frvbf_h_fr_int_set_handler (SIM_CPU
*current_cpu
, UINT fr
, USI newval
)
292 value
.as_usi
= newval
;
293 SET_H_FR (fr
, value
.as_sf
);
296 /* Cover fns to access the coprocessor registers as double words. */
298 frvbf_h_cpr_double_get_handler (SIM_CPU
*current_cpu
, UINT cpr
)
302 /* Check the register alignment. */
303 cpr
= check_register_alignment (current_cpu
, cpr
, 1);
305 value
= GET_H_CPR (cpr
);
307 value
|= (USI
) GET_H_CPR (cpr
+ 1);
312 frvbf_h_cpr_double_set_handler (SIM_CPU
*current_cpu
, UINT cpr
, DI newval
)
314 /* Check the register alignment. */
315 cpr
= check_register_alignment (current_cpu
, cpr
, 1);
317 SET_H_CPR (cpr
, (newval
>> 32) & 0xffffffff);
318 SET_H_CPR (cpr
+ 1, (newval
) & 0xffffffff);
321 /* Cover fns to write registers as quad words. */
323 frvbf_h_gr_quad_set_handler (SIM_CPU
*current_cpu
, UINT gr
, SI
*newval
)
326 return; /* Storing into gr0 has no effect. */
328 /* Check the register alignment. */
329 gr
= check_register_alignment (current_cpu
, gr
, 3);
331 SET_H_GR (gr
, newval
[0]);
332 SET_H_GR (gr
+ 1, newval
[1]);
333 SET_H_GR (gr
+ 2, newval
[2]);
334 SET_H_GR (gr
+ 3, newval
[3]);
338 frvbf_h_fr_quad_set_handler (SIM_CPU
*current_cpu
, UINT fr
, SI
*newval
)
340 /* Check the register alignment. */
341 fr
= check_fr_register_alignment (current_cpu
, fr
, 3);
343 SET_H_FR (fr
, newval
[0]);
344 SET_H_FR (fr
+ 1, newval
[1]);
345 SET_H_FR (fr
+ 2, newval
[2]);
346 SET_H_FR (fr
+ 3, newval
[3]);
350 frvbf_h_cpr_quad_set_handler (SIM_CPU
*current_cpu
, UINT cpr
, SI
*newval
)
352 /* Check the register alignment. */
353 cpr
= check_register_alignment (current_cpu
, cpr
, 3);
355 SET_H_CPR (cpr
, newval
[0]);
356 SET_H_CPR (cpr
+ 1, newval
[1]);
357 SET_H_CPR (cpr
+ 2, newval
[2]);
358 SET_H_CPR (cpr
+ 3, newval
[3]);
361 /* Cover fns to access the special purpose registers. */
363 frvbf_h_spr_get_handler (SIM_CPU
*current_cpu
, UINT spr
)
365 /* Check access restrictions. */
366 frv_check_spr_read_access (current_cpu
, spr
);
371 return spr_psr_get_handler (current_cpu
);
373 return spr_tbr_get_handler (current_cpu
);
375 return spr_bpsr_get_handler (current_cpu
);
377 return spr_ccr_get_handler (current_cpu
);
379 return spr_cccr_get_handler (current_cpu
);
384 return spr_sr_get_handler (current_cpu
, spr
);
387 return CPU (h_spr
[spr
]);
393 frvbf_h_spr_set_handler (SIM_CPU
*current_cpu
, UINT spr
, USI newval
)
395 FRV_REGISTER_CONTROL
*control
;
399 /* Check access restrictions. */
400 frv_check_spr_write_access (current_cpu
, spr
);
402 /* Only set those fields which are writeable. */
403 control
= CPU_REGISTER_CONTROL (current_cpu
);
404 mask
= control
->spr
[spr
].read_only_mask
;
405 oldval
= GET_H_SPR (spr
);
407 newval
= (newval
& ~mask
) | (oldval
& mask
);
409 /* Some registers are represented by individual components which are
410 referenced more often than the register itself. */
414 spr_psr_set_handler (current_cpu
, newval
);
417 spr_tbr_set_handler (current_cpu
, newval
);
420 spr_bpsr_set_handler (current_cpu
, newval
);
423 spr_ccr_set_handler (current_cpu
, newval
);
426 spr_cccr_set_handler (current_cpu
, newval
);
432 spr_sr_set_handler (current_cpu
, spr
, newval
);
435 CPU (h_spr
[spr
]) = newval
;
440 /* Cover fns to access the gr_hi and gr_lo registers. */
442 frvbf_h_gr_hi_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
444 return (GET_H_GR(gr
) >> 16) & 0xffff;
448 frvbf_h_gr_hi_set_handler (SIM_CPU
*current_cpu
, UINT gr
, UHI newval
)
450 USI value
= (GET_H_GR (gr
) & 0xffff) | (newval
<< 16);
451 SET_H_GR (gr
, value
);
455 frvbf_h_gr_lo_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
457 return GET_H_GR(gr
) & 0xffff;
461 frvbf_h_gr_lo_set_handler (SIM_CPU
*current_cpu
, UINT gr
, UHI newval
)
463 USI value
= (GET_H_GR (gr
) & 0xffff0000) | (newval
& 0xffff);
464 SET_H_GR (gr
, value
);
467 /* Cover fns to access the tbr bits. */
469 spr_tbr_get_handler (SIM_CPU
*current_cpu
)
471 int tbr
= ((GET_H_TBR_TBA () & 0xfffff) << 12) |
472 ((GET_H_TBR_TT () & 0xff) << 4);
478 spr_tbr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
482 SET_H_TBR_TBA ((tbr
>> 12) & 0xfffff) ;
483 SET_H_TBR_TT ((tbr
>> 4) & 0xff) ;
486 /* Cover fns to access the bpsr bits. */
488 spr_bpsr_get_handler (SIM_CPU
*current_cpu
)
490 int bpsr
= ((GET_H_BPSR_BS () & 0x1) << 12) |
491 ((GET_H_BPSR_BET () & 0x1) );
497 spr_bpsr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
501 SET_H_BPSR_BS ((bpsr
>> 12) & 1);
502 SET_H_BPSR_BET ((bpsr
) & 1);
505 /* Cover fns to access the psr bits. */
507 spr_psr_get_handler (SIM_CPU
*current_cpu
)
509 int psr
= ((GET_H_PSR_IMPLE () & 0xf) << 28) |
510 ((GET_H_PSR_VER () & 0xf) << 24) |
511 ((GET_H_PSR_ICE () & 0x1) << 16) |
512 ((GET_H_PSR_NEM () & 0x1) << 14) |
513 ((GET_H_PSR_CM () & 0x1) << 13) |
514 ((GET_H_PSR_BE () & 0x1) << 12) |
515 ((GET_H_PSR_ESR () & 0x1) << 11) |
516 ((GET_H_PSR_EF () & 0x1) << 8) |
517 ((GET_H_PSR_EM () & 0x1) << 7) |
518 ((GET_H_PSR_PIL () & 0xf) << 3) |
519 ((GET_H_PSR_S () & 0x1) << 2) |
520 ((GET_H_PSR_PS () & 0x1) << 1) |
521 ((GET_H_PSR_ET () & 0x1) );
527 spr_psr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
529 /* The handler for PSR.S references the value of PSR.ESR, so set PSR.S
531 SET_H_PSR_S ((newval
>> 2) & 1);
533 SET_H_PSR_IMPLE ((newval
>> 28) & 0xf);
534 SET_H_PSR_VER ((newval
>> 24) & 0xf);
535 SET_H_PSR_ICE ((newval
>> 16) & 1);
536 SET_H_PSR_NEM ((newval
>> 14) & 1);
537 SET_H_PSR_CM ((newval
>> 13) & 1);
538 SET_H_PSR_BE ((newval
>> 12) & 1);
539 SET_H_PSR_ESR ((newval
>> 11) & 1);
540 SET_H_PSR_EF ((newval
>> 8) & 1);
541 SET_H_PSR_EM ((newval
>> 7) & 1);
542 SET_H_PSR_PIL ((newval
>> 3) & 0xf);
543 SET_H_PSR_PS ((newval
>> 1) & 1);
544 SET_H_PSR_ET ((newval
) & 1);
548 frvbf_h_psr_s_set_handler (SIM_CPU
*current_cpu
, BI newval
)
550 /* If switching from user to supervisor mode, or vice-versa, then switch
551 the supervisor/user context. */
552 int psr_s
= GET_H_PSR_S ();
553 if (psr_s
!= (newval
& 1))
555 frvbf_switch_supervisor_user_context (current_cpu
);
556 CPU (h_psr_s
) = newval
& 1;
560 /* Cover fns to access the ccr bits. */
562 spr_ccr_get_handler (SIM_CPU
*current_cpu
)
564 int ccr
= ((GET_H_ICCR (H_ICCR_ICC3
) & 0xf) << 28) |
565 ((GET_H_ICCR (H_ICCR_ICC2
) & 0xf) << 24) |
566 ((GET_H_ICCR (H_ICCR_ICC1
) & 0xf) << 20) |
567 ((GET_H_ICCR (H_ICCR_ICC0
) & 0xf) << 16) |
568 ((GET_H_FCCR (H_FCCR_FCC3
) & 0xf) << 12) |
569 ((GET_H_FCCR (H_FCCR_FCC2
) & 0xf) << 8) |
570 ((GET_H_FCCR (H_FCCR_FCC1
) & 0xf) << 4) |
571 ((GET_H_FCCR (H_FCCR_FCC0
) & 0xf) );
577 spr_ccr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
581 SET_H_ICCR (H_ICCR_ICC3
, (newval
>> 28) & 0xf);
582 SET_H_ICCR (H_ICCR_ICC2
, (newval
>> 24) & 0xf);
583 SET_H_ICCR (H_ICCR_ICC1
, (newval
>> 20) & 0xf);
584 SET_H_ICCR (H_ICCR_ICC0
, (newval
>> 16) & 0xf);
585 SET_H_FCCR (H_FCCR_FCC3
, (newval
>> 12) & 0xf);
586 SET_H_FCCR (H_FCCR_FCC2
, (newval
>> 8) & 0xf);
587 SET_H_FCCR (H_FCCR_FCC1
, (newval
>> 4) & 0xf);
588 SET_H_FCCR (H_FCCR_FCC0
, (newval
) & 0xf);
592 frvbf_set_icc_for_shift_right (
593 SIM_CPU
*current_cpu
, SI value
, SI shift
, QI icc
596 /* Set the C flag of the given icc to the logical OR of the bits shifted
598 int mask
= (1 << shift
) - 1;
599 if ((value
& mask
) != 0)
606 frvbf_set_icc_for_shift_left (
607 SIM_CPU
*current_cpu
, SI value
, SI shift
, QI icc
610 /* Set the V flag of the given icc to the logical OR of the bits shifted
612 int mask
= ((1 << shift
) - 1) << (32 - shift
);
613 if ((value
& mask
) != 0)
619 /* Cover fns to access the cccr bits. */
621 spr_cccr_get_handler (SIM_CPU
*current_cpu
)
623 int cccr
= ((GET_H_CCCR (H_CCCR_CC7
) & 0x3) << 14) |
624 ((GET_H_CCCR (H_CCCR_CC6
) & 0x3) << 12) |
625 ((GET_H_CCCR (H_CCCR_CC5
) & 0x3) << 10) |
626 ((GET_H_CCCR (H_CCCR_CC4
) & 0x3) << 8) |
627 ((GET_H_CCCR (H_CCCR_CC3
) & 0x3) << 6) |
628 ((GET_H_CCCR (H_CCCR_CC2
) & 0x3) << 4) |
629 ((GET_H_CCCR (H_CCCR_CC1
) & 0x3) << 2) |
630 ((GET_H_CCCR (H_CCCR_CC0
) & 0x3) );
636 spr_cccr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
640 SET_H_CCCR (H_CCCR_CC7
, (newval
>> 14) & 0x3);
641 SET_H_CCCR (H_CCCR_CC6
, (newval
>> 12) & 0x3);
642 SET_H_CCCR (H_CCCR_CC5
, (newval
>> 10) & 0x3);
643 SET_H_CCCR (H_CCCR_CC4
, (newval
>> 8) & 0x3);
644 SET_H_CCCR (H_CCCR_CC3
, (newval
>> 6) & 0x3);
645 SET_H_CCCR (H_CCCR_CC2
, (newval
>> 4) & 0x3);
646 SET_H_CCCR (H_CCCR_CC1
, (newval
>> 2) & 0x3);
647 SET_H_CCCR (H_CCCR_CC0
, (newval
) & 0x3);
650 /* Cover fns to access the sr bits. */
652 spr_sr_get_handler (SIM_CPU
*current_cpu
, UINT spr
)
654 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
655 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
656 int psr_esr
= GET_H_PSR_ESR ();
658 return GET_H_GR (4 + (spr
- H_SPR_SR0
));
660 return CPU (h_spr
[spr
]);
664 spr_sr_set_handler (SIM_CPU
*current_cpu
, UINT spr
, USI newval
)
666 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
667 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
668 int psr_esr
= GET_H_PSR_ESR ();
670 SET_H_GR (4 + (spr
- H_SPR_SR0
), newval
);
672 CPU (h_spr
[spr
]) = newval
;
675 /* Switch SR0-SR4 with GR4-GR7 if PSR.ESR is set. */
677 frvbf_switch_supervisor_user_context (SIM_CPU
*current_cpu
)
679 if (GET_H_PSR_ESR ())
681 /* We need to be in supervisor mode to swap the registers. Access the
682 PSR.S directly in order to avoid recursive context switches. */
684 int save_psr_s
= CPU (h_psr_s
);
686 for (i
= 0; i
< 4; ++i
)
689 int spr
= i
+ H_SPR_SR0
;
690 SI tmp
= GET_H_SPR (spr
);
691 SET_H_SPR (spr
, GET_H_GR (gr
));
694 CPU (h_psr_s
) = save_psr_s
;
698 /* Handle load/store of quad registers. */
700 frvbf_load_quad_GR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
705 /* Check memory alignment */
706 address
= check_memory_alignment (current_cpu
, address
, 0xf);
708 /* If we need to count cycles, then the cache operation will be
709 initiated from the model profiling functions.
710 See frvbf_model_.... */
713 CPU_LOAD_ADDRESS (current_cpu
) = address
;
714 CPU_LOAD_LENGTH (current_cpu
) = 16;
718 for (i
= 0; i
< 4; ++i
)
720 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
723 sim_queue_fn_xi_write (current_cpu
, frvbf_h_gr_quad_set_handler
, targ_ix
,
729 frvbf_store_quad_GR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
735 /* Check register and memory alignment. */
736 src_ix
= check_register_alignment (current_cpu
, src_ix
, 3);
737 address
= check_memory_alignment (current_cpu
, address
, 0xf);
739 for (i
= 0; i
< 4; ++i
)
741 /* GR0 is always 0. */
745 value
[i
] = GET_H_GR (src_ix
+ i
);
748 if (GET_HSR0_DCE (hsr0
))
749 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
751 sim_queue_mem_xi_write (current_cpu
, address
, value
);
755 frvbf_load_quad_FRint (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
760 /* Check memory alignment */
761 address
= check_memory_alignment (current_cpu
, address
, 0xf);
763 /* If we need to count cycles, then the cache operation will be
764 initiated from the model profiling functions.
765 See frvbf_model_.... */
768 CPU_LOAD_ADDRESS (current_cpu
) = address
;
769 CPU_LOAD_LENGTH (current_cpu
) = 16;
773 for (i
= 0; i
< 4; ++i
)
775 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
778 sim_queue_fn_xi_write (current_cpu
, frvbf_h_fr_quad_set_handler
, targ_ix
,
784 frvbf_store_quad_FRint (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
790 /* Check register and memory alignment. */
791 src_ix
= check_fr_register_alignment (current_cpu
, src_ix
, 3);
792 address
= check_memory_alignment (current_cpu
, address
, 0xf);
794 for (i
= 0; i
< 4; ++i
)
795 value
[i
] = GET_H_FR (src_ix
+ i
);
798 if (GET_HSR0_DCE (hsr0
))
799 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
801 sim_queue_mem_xi_write (current_cpu
, address
, value
);
805 frvbf_load_quad_CPR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
810 /* Check memory alignment */
811 address
= check_memory_alignment (current_cpu
, address
, 0xf);
813 /* If we need to count cycles, then the cache operation will be
814 initiated from the model profiling functions.
815 See frvbf_model_.... */
818 CPU_LOAD_ADDRESS (current_cpu
) = address
;
819 CPU_LOAD_LENGTH (current_cpu
) = 16;
823 for (i
= 0; i
< 4; ++i
)
825 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
828 sim_queue_fn_xi_write (current_cpu
, frvbf_h_cpr_quad_set_handler
, targ_ix
,
834 frvbf_store_quad_CPR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
840 /* Check register and memory alignment. */
841 src_ix
= check_register_alignment (current_cpu
, src_ix
, 3);
842 address
= check_memory_alignment (current_cpu
, address
, 0xf);
844 for (i
= 0; i
< 4; ++i
)
845 value
[i
] = GET_H_CPR (src_ix
+ i
);
848 if (GET_HSR0_DCE (hsr0
))
849 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
851 sim_queue_mem_xi_write (current_cpu
, address
, value
);
855 frvbf_signed_integer_divide (
856 SIM_CPU
*current_cpu
, SI arg1
, SI arg2
, int target_index
, int non_excepting
859 enum frv_dtt dtt
= FRV_DTT_NO_EXCEPTION
;
860 if (arg1
== 0x80000000 && arg2
== -1)
862 /* 0x80000000/(-1) must result in 0x7fffffff when ISR.EDE is set
863 otherwise it may result in 0x7fffffff (sparc compatibility) or
864 0x80000000 (C language compatibility). */
866 dtt
= FRV_DTT_OVERFLOW
;
869 if (GET_ISR_EDE (isr
))
870 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
873 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
875 frvbf_force_update (current_cpu
); /* Force update of target register. */
878 dtt
= FRV_DTT_DIVISION_BY_ZERO
;
880 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
883 /* Check for exceptions. */
884 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
885 dtt
= frvbf_division_exception (current_cpu
, dtt
, target_index
,
887 if (non_excepting
&& dtt
== FRV_DTT_NO_EXCEPTION
)
889 /* Non excepting instruction. Clear the NE flag for the target
892 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
893 CLEAR_NE_FLAG (NE_flags
, target_index
);
894 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
899 frvbf_unsigned_integer_divide (
900 SIM_CPU
*current_cpu
, USI arg1
, USI arg2
, int target_index
, int non_excepting
904 frvbf_division_exception (current_cpu
, FRV_DTT_DIVISION_BY_ZERO
,
905 target_index
, non_excepting
);
908 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
912 /* Non excepting instruction. Clear the NE flag for the target
915 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
916 CLEAR_NE_FLAG (NE_flags
, target_index
);
917 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
922 /* Clear accumulators. */
924 frvbf_clear_accumulators (SIM_CPU
*current_cpu
, SI acc_ix
, int A
)
926 SIM_DESC sd
= CPU_STATE (current_cpu
);
928 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr500
) ? 8 :
929 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
) ? 4 :
932 if (A
== 0 || acc_ix
!= 0) /* Clear 1 accumuator? */
934 /* This instruction is a nop if the referenced accumulator is not
936 if (acc_ix
< acc_num
)
937 sim_queue_fn_di_write (current_cpu
, frvbf_h_acc40S_set
, acc_ix
, 0);
941 /* Clear all implemented accumulators. */
943 for (i
= 0; i
< acc_num
; ++i
)
944 sim_queue_fn_di_write (current_cpu
, frvbf_h_acc40S_set
, i
, 0);
948 /* Functions to aid insn semantics. */
950 /* Compute the result of the SCAN and SCANI insns after the shift and xor. */
952 frvbf_scan_result (SIM_CPU
*current_cpu
, SI value
)
960 /* Find the position of the first non-zero bit.
961 The loop will terminate since there is guaranteed to be at least one
963 mask
= 1 << (sizeof (mask
) * 8 - 1);
964 for (i
= 0; (value
& mask
) == 0; ++i
)
970 /* Compute the result of the cut insns. */
972 frvbf_cut (SIM_CPU
*current_cpu
, SI reg1
, SI reg2
, SI cut_point
)
977 result
= reg1
<< cut_point
;
978 result
|= (reg2
>> (32 - cut_point
)) & ((1 << cut_point
) - 1);
981 result
= reg2
<< (cut_point
- 32);
986 /* Compute the result of the cut insns. */
988 frvbf_media_cut (SIM_CPU
*current_cpu
, DI acc
, SI cut_point
)
990 /* The cut point is the lower 6 bits (signed) of what we are passed. */
991 cut_point
= cut_point
<< 26 >> 26;
993 /* The cut_point is relative to bit 40 of 64 bits. */
995 return (acc
<< (cut_point
+ 24)) >> 32;
997 /* Extend the sign bit (bit 40) for negative cuts. */
998 if (cut_point
== -32)
999 return (acc
<< 24) >> 63; /* Special case for full shiftout. */
1001 return (acc
<< 24) >> (32 + -cut_point
);
1004 /* Compute the result of the cut insns. */
1006 frvbf_media_cut_ss (SIM_CPU
*current_cpu
, DI acc
, SI cut_point
)
1008 /* The cut point is the lower 6 bits (signed) of what we are passed. */
1009 cut_point
= cut_point
<< 26 >> 26;
1013 /* The cut_point is relative to bit 40 of 64 bits. */
1014 DI shifted
= acc
<< (cut_point
+ 24);
1015 DI unshifted
= shifted
>> (cut_point
+ 24);
1017 /* The result will be saturated if significant bits are shifted out. */
1018 if (unshifted
!= acc
)
1026 /* The result will not be saturated, so use the code for the normal cut. */
1027 return frvbf_media_cut (current_cpu
, acc
, cut_point
);
1030 /* Simulate the media custom insns. */
1032 frvbf_media_cop (SIM_CPU
*current_cpu
, int cop_num
)
1034 /* The semantics of the insn are a nop, since it is implementation defined.
1035 We do need to check whether it's implemented and set up for MTRAP
1037 USI msr0
= GET_MSR (0);
1038 if (GET_MSR_EMCI (msr0
) == 0)
1040 /* no interrupt queued at this time. */
1041 frv_set_mp_exception_registers (current_cpu
, MTT_UNIMPLEMENTED_MPOP
, 0);
1045 /* Simulate the media average (MAVEH) insn. */
1047 do_media_average (SIM_CPU
*current_cpu
, HI arg1
, HI arg2
)
1049 SIM_DESC sd
= CPU_STATE (current_cpu
);
1050 SI sum
= (arg1
+ arg2
);
1051 HI result
= sum
>> 1;
1053 /* On fr400, check the rounding mode. On other machines rounding is always
1054 toward negative infinity and the result is already correctly rounded. */
1055 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
)
1057 /* Check whether rounding will be required. Rounding will be required
1058 if the sum is an odd number. */
1059 int rounding_value
= sum
& 1;
1062 USI msr0
= GET_MSR (0);
1063 /* Check MSR0.SRDAV to determine which bits control the rounding. */
1064 if (GET_MSR_SRDAV (msr0
))
1066 /* MSR0.RD controls rounding. */
1067 switch (GET_MSR_RD (msr0
))
1070 /* Round to nearest. */
1075 /* Round toward 0. */
1080 /* Round toward positive infinity. */
1084 /* Round toward negative infinity. The result is already
1085 correctly rounded. */
1094 /* MSR0.RDAV controls rounding. If set, round toward positive
1095 infinity. Otherwise the result is already rounded correctly
1096 toward negative infinity. */
1097 if (GET_MSR_RDAV (msr0
))
1107 frvbf_media_average (SIM_CPU
*current_cpu
, SI reg1
, SI reg2
)
1110 result
= do_media_average (current_cpu
, reg1
& 0xffff, reg2
& 0xffff);
1112 result
|= do_media_average (current_cpu
, (reg1
>> 16) & 0xffff,
1113 (reg2
>> 16) & 0xffff) << 16;
1117 /* Maintain a flag in order to know when to write the address of the next
1118 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL. */
1120 frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU
*current_cpu
, int value
)
1122 frvbf_write_next_vliw_addr_to_LR
= value
;
1126 frvbf_set_ne_index (SIM_CPU
*current_cpu
, int index
)
1130 /* Save the target register so interrupt processing can set its NE flag
1131 in the event of an exception. */
1132 frv_interrupt_state
.ne_index
= index
;
1134 /* Clear the NE flag of the target register. It will be reset if necessary
1135 in the event of an exception. */
1136 GET_NE_FLAGS (NE_flags
, H_SPR_FNER0
);
1137 CLEAR_NE_FLAG (NE_flags
, index
);
1138 SET_NE_FLAGS (H_SPR_FNER0
, NE_flags
);
1142 frvbf_force_update (SIM_CPU
*current_cpu
)
1144 CGEN_WRITE_QUEUE
*q
= CPU_WRITE_QUEUE (current_cpu
);
1145 int ix
= CGEN_WRITE_QUEUE_INDEX (q
);
1148 CGEN_WRITE_QUEUE_ELEMENT
*item
= CGEN_WRITE_QUEUE_ELEMENT (q
, ix
- 1);
1149 item
->flags
|= FRV_WRITE_QUEUE_FORCE_WRITE
;
1153 /* Condition code logic. */
1155 andcr
, orcr
, xorcr
, nandcr
, norcr
, andncr
, orncr
, nandncr
, norncr
,
1159 enum cr_result
{cr_undefined
, cr_undefined1
, cr_false
, cr_true
};
1161 static enum cr_result
1162 cr_logic
[num_cr_ops
][4][4] = {
1165 /* undefined undefined false true */
1166 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1167 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1168 /* false */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1169 /* true */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
}
1173 /* undefined undefined false true */
1174 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1175 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1176 /* false */ {cr_false
, cr_false
, cr_false
, cr_true
},
1177 /* true */ {cr_true
, cr_true
, cr_true
, cr_true
}
1181 /* undefined undefined false true */
1182 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1183 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1184 /* false */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1185 /* true */ {cr_true
, cr_true
, cr_true
, cr_false
}
1189 /* undefined undefined false true */
1190 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1191 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1192 /* false */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1193 /* true */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
}
1197 /* undefined undefined false true */
1198 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1199 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1200 /* false */ {cr_true
, cr_true
, cr_true
, cr_false
},
1201 /* true */ {cr_false
, cr_false
, cr_false
, cr_false
}
1205 /* undefined undefined false true */
1206 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1207 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1208 /* false */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1209 /* true */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
}
1213 /* undefined undefined false true */
1214 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1215 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1216 /* false */ {cr_true
, cr_true
, cr_true
, cr_true
},
1217 /* true */ {cr_false
, cr_false
, cr_false
, cr_true
}
1221 /* undefined undefined false true */
1222 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1223 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1224 /* false */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1225 /* true */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
}
1229 /* undefined undefined false true */
1230 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1231 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1232 /* false */ {cr_false
, cr_false
, cr_false
, cr_false
},
1233 /* true */ {cr_true
, cr_true
, cr_true
, cr_false
}
1238 frvbf_cr_logic (SIM_CPU
*current_cpu
, SI operation
, UQI arg1
, UQI arg2
)
1240 return cr_logic
[operation
][arg1
][arg2
];
1243 /* Cache Manipulation. */
1245 frvbf_insn_cache_preload (SIM_CPU
*current_cpu
, SI address
, USI length
, int lock
)
1247 /* If we need to count cycles, then the cache operation will be
1248 initiated from the model profiling functions.
1249 See frvbf_model_.... */
1250 int hsr0
= GET_HSR0 ();
1251 if (GET_HSR0_ICE (hsr0
))
1255 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1256 CPU_LOAD_LENGTH (current_cpu
) = length
;
1257 CPU_LOAD_LOCK (current_cpu
) = lock
;
1261 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1262 frv_cache_preload (cache
, address
, length
, lock
);
1268 frvbf_data_cache_preload (SIM_CPU
*current_cpu
, SI address
, USI length
, int lock
)
1270 /* If we need to count cycles, then the cache operation will be
1271 initiated from the model profiling functions.
1272 See frvbf_model_.... */
1273 int hsr0
= GET_HSR0 ();
1274 if (GET_HSR0_DCE (hsr0
))
1278 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1279 CPU_LOAD_LENGTH (current_cpu
) = length
;
1280 CPU_LOAD_LOCK (current_cpu
) = lock
;
1284 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1285 frv_cache_preload (cache
, address
, length
, lock
);
1291 frvbf_insn_cache_unlock (SIM_CPU
*current_cpu
, SI address
)
1293 /* If we need to count cycles, then the cache operation will be
1294 initiated from the model profiling functions.
1295 See frvbf_model_.... */
1296 int hsr0
= GET_HSR0 ();
1297 if (GET_HSR0_ICE (hsr0
))
1300 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1303 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1304 frv_cache_unlock (cache
, address
);
1310 frvbf_data_cache_unlock (SIM_CPU
*current_cpu
, SI address
)
1312 /* If we need to count cycles, then the cache operation will be
1313 initiated from the model profiling functions.
1314 See frvbf_model_.... */
1315 int hsr0
= GET_HSR0 ();
1316 if (GET_HSR0_DCE (hsr0
))
1319 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1322 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1323 frv_cache_unlock (cache
, address
);
1329 frvbf_insn_cache_invalidate (SIM_CPU
*current_cpu
, SI address
, int all
)
1331 /* Make sure the insn was specified properly. -1 will be passed for ALL
1332 for a icei with A=0. */
1335 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1339 /* If we need to count cycles, then the cache operation will be
1340 initiated from the model profiling functions.
1341 See frvbf_model_.... */
1344 /* Record the all-entries flag for use in profiling. */
1345 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1346 ps
->all_cache_entries
= all
;
1347 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1351 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1353 frv_cache_invalidate_all (cache
, 0/* flush? */);
1355 frv_cache_invalidate (cache
, address
, 0/* flush? */);
1360 frvbf_data_cache_invalidate (SIM_CPU
*current_cpu
, SI address
, int all
)
1362 /* Make sure the insn was specified properly. -1 will be passed for ALL
1363 for a dcei with A=0. */
1366 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1370 /* If we need to count cycles, then the cache operation will be
1371 initiated from the model profiling functions.
1372 See frvbf_model_.... */
1375 /* Record the all-entries flag for use in profiling. */
1376 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1377 ps
->all_cache_entries
= all
;
1378 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1382 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1384 frv_cache_invalidate_all (cache
, 0/* flush? */);
1386 frv_cache_invalidate (cache
, address
, 0/* flush? */);
1391 frvbf_data_cache_flush (SIM_CPU
*current_cpu
, SI address
, int all
)
1393 /* Make sure the insn was specified properly. -1 will be passed for ALL
1394 for a dcef with A=0. */
1397 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1401 /* If we need to count cycles, then the cache operation will be
1402 initiated from the model profiling functions.
1403 See frvbf_model_.... */
1406 /* Record the all-entries flag for use in profiling. */
1407 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1408 ps
->all_cache_entries
= all
;
1409 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1413 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1415 frv_cache_invalidate_all (cache
, 1/* flush? */);
1417 frv_cache_invalidate (cache
, address
, 1/* flush? */);