1 /* frv simulator support code
2 Copyright (C) 1998, 1999, 2000, 2001, 2003, 2004, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #define WANT_CPU_FRVBF
27 #include "cgen-engine.h"
30 #include "gdb/sim-frv.h"
33 /* Maintain a flag in order to know when to write the address of the next
34 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL
36 int frvbf_write_next_vliw_addr_to_LR
;
38 /* The contents of BUF are in target byte order. */
40 frvbf_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
42 if (SIM_FRV_GR0_REGNUM
<= rn
&& rn
<= SIM_FRV_GR63_REGNUM
)
44 int hi_available
, lo_available
;
45 int grn
= rn
- SIM_FRV_GR0_REGNUM
;
47 frv_gr_registers_available (current_cpu
, &hi_available
, &lo_available
);
49 if ((grn
< 32 && !lo_available
) || (grn
>= 32 && !hi_available
))
52 SETTSI (buf
, GET_H_GR (grn
));
54 else if (SIM_FRV_FR0_REGNUM
<= rn
&& rn
<= SIM_FRV_FR63_REGNUM
)
56 int hi_available
, lo_available
;
57 int frn
= rn
- SIM_FRV_FR0_REGNUM
;
59 frv_fr_registers_available (current_cpu
, &hi_available
, &lo_available
);
61 if ((frn
< 32 && !lo_available
) || (frn
>= 32 && !hi_available
))
64 SETTSI (buf
, GET_H_FR (frn
));
66 else if (rn
== SIM_FRV_PC_REGNUM
)
67 SETTSI (buf
, GET_H_PC ());
68 else if (SIM_FRV_SPR0_REGNUM
<= rn
&& rn
<= SIM_FRV_SPR4095_REGNUM
)
70 /* Make sure the register is implemented. */
71 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
72 int spr
= rn
- SIM_FRV_SPR0_REGNUM
;
73 if (! control
->spr
[spr
].implemented
)
75 SETTSI (buf
, GET_H_SPR (spr
));
79 SETTSI (buf
, 0xdeadbeef);
86 /* The contents of BUF are in target byte order. */
89 frvbf_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
91 if (SIM_FRV_GR0_REGNUM
<= rn
&& rn
<= SIM_FRV_GR63_REGNUM
)
93 int hi_available
, lo_available
;
94 int grn
= rn
- SIM_FRV_GR0_REGNUM
;
96 frv_gr_registers_available (current_cpu
, &hi_available
, &lo_available
);
98 if ((grn
< 32 && !lo_available
) || (grn
>= 32 && !hi_available
))
101 SET_H_GR (grn
, GETTSI (buf
));
103 else if (SIM_FRV_FR0_REGNUM
<= rn
&& rn
<= SIM_FRV_FR63_REGNUM
)
105 int hi_available
, lo_available
;
106 int frn
= rn
- SIM_FRV_FR0_REGNUM
;
108 frv_fr_registers_available (current_cpu
, &hi_available
, &lo_available
);
110 if ((frn
< 32 && !lo_available
) || (frn
>= 32 && !hi_available
))
113 SET_H_FR (frn
, GETTSI (buf
));
115 else if (rn
== SIM_FRV_PC_REGNUM
)
116 SET_H_PC (GETTSI (buf
));
117 else if (SIM_FRV_SPR0_REGNUM
<= rn
&& rn
<= SIM_FRV_SPR4095_REGNUM
)
119 /* Make sure the register is implemented. */
120 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
121 int spr
= rn
- SIM_FRV_SPR0_REGNUM
;
122 if (! control
->spr
[spr
].implemented
)
124 SET_H_SPR (spr
, GETTSI (buf
));
132 /* Cover fns to access the general registers. */
134 frvbf_h_gr_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
136 frv_check_gr_access (current_cpu
, gr
);
137 return CPU (h_gr
[gr
]);
141 frvbf_h_gr_set_handler (SIM_CPU
*current_cpu
, UINT gr
, USI newval
)
143 frv_check_gr_access (current_cpu
, gr
);
146 return; /* Storing into gr0 has no effect. */
148 CPU (h_gr
[gr
]) = newval
;
151 /* Cover fns to access the floating point registers. */
153 frvbf_h_fr_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
155 frv_check_fr_access (current_cpu
, fr
);
156 return CPU (h_fr
[fr
]);
160 frvbf_h_fr_set_handler (SIM_CPU
*current_cpu
, UINT fr
, SF newval
)
162 frv_check_fr_access (current_cpu
, fr
);
163 CPU (h_fr
[fr
]) = newval
;
166 /* Cover fns to access the general registers as double words. */
168 check_register_alignment (SIM_CPU
*current_cpu
, UINT reg
, int align_mask
)
170 if (reg
& align_mask
)
172 SIM_DESC sd
= CPU_STATE (current_cpu
);
173 switch (STATE_ARCHITECTURE (sd
)->mach
)
175 /* Note: there is a discrepancy between V2.2 of the FR400
176 instruction manual and the various FR4xx LSI specs.
177 The former claims that unaligned registers cause a
178 register_exception while the latter say it's an
179 illegal_instruction. The LSI specs appear to be
180 correct; in fact, the FR4xx series is not documented
181 as having a register_exception. */
185 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
187 case bfd_mach_frvtomcat
:
190 frv_queue_register_exception_interrupt (current_cpu
,
204 check_fr_register_alignment (SIM_CPU
*current_cpu
, UINT reg
, int align_mask
)
206 if (reg
& align_mask
)
208 SIM_DESC sd
= CPU_STATE (current_cpu
);
209 switch (STATE_ARCHITECTURE (sd
)->mach
)
211 /* See comment in check_register_alignment(). */
215 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
217 case bfd_mach_frvtomcat
:
221 struct frv_fp_exception_info fp_info
= {
222 FSR_NO_EXCEPTION
, FTT_INVALID_FR
224 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);
238 check_memory_alignment (SIM_CPU
*current_cpu
, SI address
, int align_mask
)
240 if (address
& align_mask
)
242 SIM_DESC sd
= CPU_STATE (current_cpu
);
243 switch (STATE_ARCHITECTURE (sd
)->mach
)
245 /* See comment in check_register_alignment(). */
248 frv_queue_data_access_error_interrupt (current_cpu
, address
);
250 case bfd_mach_frvtomcat
:
253 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, address
);
259 address
&= ~align_mask
;
266 frvbf_h_gr_double_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
271 return 0; /* gr0 is always 0. */
273 /* Check the register alignment. */
274 gr
= check_register_alignment (current_cpu
, gr
, 1);
276 value
= GET_H_GR (gr
);
278 value
|= (USI
) GET_H_GR (gr
+ 1);
283 frvbf_h_gr_double_set_handler (SIM_CPU
*current_cpu
, UINT gr
, DI newval
)
286 return; /* Storing into gr0 has no effect. */
288 /* Check the register alignment. */
289 gr
= check_register_alignment (current_cpu
, gr
, 1);
291 SET_H_GR (gr
, (newval
>> 32) & 0xffffffff);
292 SET_H_GR (gr
+ 1, (newval
) & 0xffffffff);
295 /* Cover fns to access the floating point register as double words. */
297 frvbf_h_fr_double_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
304 /* Check the register alignment. */
305 fr
= check_fr_register_alignment (current_cpu
, fr
, 1);
307 if (CURRENT_HOST_BYTE_ORDER
== LITTLE_ENDIAN
)
309 value
.as_sf
[1] = GET_H_FR (fr
);
310 value
.as_sf
[0] = GET_H_FR (fr
+ 1);
314 value
.as_sf
[0] = GET_H_FR (fr
);
315 value
.as_sf
[1] = GET_H_FR (fr
+ 1);
322 frvbf_h_fr_double_set_handler (SIM_CPU
*current_cpu
, UINT fr
, DF newval
)
329 /* Check the register alignment. */
330 fr
= check_fr_register_alignment (current_cpu
, fr
, 1);
332 value
.as_df
= newval
;
333 if (CURRENT_HOST_BYTE_ORDER
== LITTLE_ENDIAN
)
335 SET_H_FR (fr
, value
.as_sf
[1]);
336 SET_H_FR (fr
+ 1, value
.as_sf
[0]);
340 SET_H_FR (fr
, value
.as_sf
[0]);
341 SET_H_FR (fr
+ 1, value
.as_sf
[1]);
345 /* Cover fns to access the floating point register as integer words. */
347 frvbf_h_fr_int_get_handler (SIM_CPU
*current_cpu
, UINT fr
)
354 value
.as_sf
= GET_H_FR (fr
);
359 frvbf_h_fr_int_set_handler (SIM_CPU
*current_cpu
, UINT fr
, USI newval
)
366 value
.as_usi
= newval
;
367 SET_H_FR (fr
, value
.as_sf
);
370 /* Cover fns to access the coprocessor registers as double words. */
372 frvbf_h_cpr_double_get_handler (SIM_CPU
*current_cpu
, UINT cpr
)
376 /* Check the register alignment. */
377 cpr
= check_register_alignment (current_cpu
, cpr
, 1);
379 value
= GET_H_CPR (cpr
);
381 value
|= (USI
) GET_H_CPR (cpr
+ 1);
386 frvbf_h_cpr_double_set_handler (SIM_CPU
*current_cpu
, UINT cpr
, DI newval
)
388 /* Check the register alignment. */
389 cpr
= check_register_alignment (current_cpu
, cpr
, 1);
391 SET_H_CPR (cpr
, (newval
>> 32) & 0xffffffff);
392 SET_H_CPR (cpr
+ 1, (newval
) & 0xffffffff);
395 /* Cover fns to write registers as quad words. */
397 frvbf_h_gr_quad_set_handler (SIM_CPU
*current_cpu
, UINT gr
, SI
*newval
)
400 return; /* Storing into gr0 has no effect. */
402 /* Check the register alignment. */
403 gr
= check_register_alignment (current_cpu
, gr
, 3);
405 SET_H_GR (gr
, newval
[0]);
406 SET_H_GR (gr
+ 1, newval
[1]);
407 SET_H_GR (gr
+ 2, newval
[2]);
408 SET_H_GR (gr
+ 3, newval
[3]);
412 frvbf_h_fr_quad_set_handler (SIM_CPU
*current_cpu
, UINT fr
, SI
*newval
)
414 /* Check the register alignment. */
415 fr
= check_fr_register_alignment (current_cpu
, fr
, 3);
417 SET_H_FR (fr
, newval
[0]);
418 SET_H_FR (fr
+ 1, newval
[1]);
419 SET_H_FR (fr
+ 2, newval
[2]);
420 SET_H_FR (fr
+ 3, newval
[3]);
424 frvbf_h_cpr_quad_set_handler (SIM_CPU
*current_cpu
, UINT cpr
, SI
*newval
)
426 /* Check the register alignment. */
427 cpr
= check_register_alignment (current_cpu
, cpr
, 3);
429 SET_H_CPR (cpr
, newval
[0]);
430 SET_H_CPR (cpr
+ 1, newval
[1]);
431 SET_H_CPR (cpr
+ 2, newval
[2]);
432 SET_H_CPR (cpr
+ 3, newval
[3]);
435 /* Cover fns to access the special purpose registers. */
437 frvbf_h_spr_get_handler (SIM_CPU
*current_cpu
, UINT spr
)
439 /* Check access restrictions. */
440 frv_check_spr_read_access (current_cpu
, spr
);
445 return spr_psr_get_handler (current_cpu
);
447 return spr_tbr_get_handler (current_cpu
);
449 return spr_bpsr_get_handler (current_cpu
);
451 return spr_ccr_get_handler (current_cpu
);
453 return spr_cccr_get_handler (current_cpu
);
458 return spr_sr_get_handler (current_cpu
, spr
);
461 return CPU (h_spr
[spr
]);
467 frvbf_h_spr_set_handler (SIM_CPU
*current_cpu
, UINT spr
, USI newval
)
469 FRV_REGISTER_CONTROL
*control
;
473 /* Check access restrictions. */
474 frv_check_spr_write_access (current_cpu
, spr
);
476 /* Only set those fields which are writeable. */
477 control
= CPU_REGISTER_CONTROL (current_cpu
);
478 mask
= control
->spr
[spr
].read_only_mask
;
479 oldval
= GET_H_SPR (spr
);
481 newval
= (newval
& ~mask
) | (oldval
& mask
);
483 /* Some registers are represented by individual components which are
484 referenced more often than the register itself. */
488 spr_psr_set_handler (current_cpu
, newval
);
491 spr_tbr_set_handler (current_cpu
, newval
);
494 spr_bpsr_set_handler (current_cpu
, newval
);
497 spr_ccr_set_handler (current_cpu
, newval
);
500 spr_cccr_set_handler (current_cpu
, newval
);
506 spr_sr_set_handler (current_cpu
, spr
, newval
);
509 frv_cache_reconfigure (current_cpu
, CPU_INSN_CACHE (current_cpu
));
512 CPU (h_spr
[spr
]) = newval
;
517 /* Cover fns to access the gr_hi and gr_lo registers. */
519 frvbf_h_gr_hi_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
521 return (GET_H_GR(gr
) >> 16) & 0xffff;
525 frvbf_h_gr_hi_set_handler (SIM_CPU
*current_cpu
, UINT gr
, UHI newval
)
527 USI value
= (GET_H_GR (gr
) & 0xffff) | (newval
<< 16);
528 SET_H_GR (gr
, value
);
532 frvbf_h_gr_lo_get_handler (SIM_CPU
*current_cpu
, UINT gr
)
534 return GET_H_GR(gr
) & 0xffff;
538 frvbf_h_gr_lo_set_handler (SIM_CPU
*current_cpu
, UINT gr
, UHI newval
)
540 USI value
= (GET_H_GR (gr
) & 0xffff0000) | (newval
& 0xffff);
541 SET_H_GR (gr
, value
);
544 /* Cover fns to access the tbr bits. */
546 spr_tbr_get_handler (SIM_CPU
*current_cpu
)
548 int tbr
= ((GET_H_TBR_TBA () & 0xfffff) << 12) |
549 ((GET_H_TBR_TT () & 0xff) << 4);
555 spr_tbr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
559 SET_H_TBR_TBA ((tbr
>> 12) & 0xfffff) ;
560 SET_H_TBR_TT ((tbr
>> 4) & 0xff) ;
563 /* Cover fns to access the bpsr bits. */
565 spr_bpsr_get_handler (SIM_CPU
*current_cpu
)
567 int bpsr
= ((GET_H_BPSR_BS () & 0x1) << 12) |
568 ((GET_H_BPSR_BET () & 0x1) );
574 spr_bpsr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
578 SET_H_BPSR_BS ((bpsr
>> 12) & 1);
579 SET_H_BPSR_BET ((bpsr
) & 1);
582 /* Cover fns to access the psr bits. */
584 spr_psr_get_handler (SIM_CPU
*current_cpu
)
586 int psr
= ((GET_H_PSR_IMPLE () & 0xf) << 28) |
587 ((GET_H_PSR_VER () & 0xf) << 24) |
588 ((GET_H_PSR_ICE () & 0x1) << 16) |
589 ((GET_H_PSR_NEM () & 0x1) << 14) |
590 ((GET_H_PSR_CM () & 0x1) << 13) |
591 ((GET_H_PSR_BE () & 0x1) << 12) |
592 ((GET_H_PSR_ESR () & 0x1) << 11) |
593 ((GET_H_PSR_EF () & 0x1) << 8) |
594 ((GET_H_PSR_EM () & 0x1) << 7) |
595 ((GET_H_PSR_PIL () & 0xf) << 3) |
596 ((GET_H_PSR_S () & 0x1) << 2) |
597 ((GET_H_PSR_PS () & 0x1) << 1) |
598 ((GET_H_PSR_ET () & 0x1) );
604 spr_psr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
606 /* The handler for PSR.S references the value of PSR.ESR, so set PSR.S
608 SET_H_PSR_S ((newval
>> 2) & 1);
610 SET_H_PSR_IMPLE ((newval
>> 28) & 0xf);
611 SET_H_PSR_VER ((newval
>> 24) & 0xf);
612 SET_H_PSR_ICE ((newval
>> 16) & 1);
613 SET_H_PSR_NEM ((newval
>> 14) & 1);
614 SET_H_PSR_CM ((newval
>> 13) & 1);
615 SET_H_PSR_BE ((newval
>> 12) & 1);
616 SET_H_PSR_ESR ((newval
>> 11) & 1);
617 SET_H_PSR_EF ((newval
>> 8) & 1);
618 SET_H_PSR_EM ((newval
>> 7) & 1);
619 SET_H_PSR_PIL ((newval
>> 3) & 0xf);
620 SET_H_PSR_PS ((newval
>> 1) & 1);
621 SET_H_PSR_ET ((newval
) & 1);
625 frvbf_h_psr_s_set_handler (SIM_CPU
*current_cpu
, BI newval
)
627 /* If switching from user to supervisor mode, or vice-versa, then switch
628 the supervisor/user context. */
629 int psr_s
= GET_H_PSR_S ();
630 if (psr_s
!= (newval
& 1))
632 frvbf_switch_supervisor_user_context (current_cpu
);
633 CPU (h_psr_s
) = newval
& 1;
637 /* Cover fns to access the ccr bits. */
639 spr_ccr_get_handler (SIM_CPU
*current_cpu
)
641 int ccr
= ((GET_H_ICCR (H_ICCR_ICC3
) & 0xf) << 28) |
642 ((GET_H_ICCR (H_ICCR_ICC2
) & 0xf) << 24) |
643 ((GET_H_ICCR (H_ICCR_ICC1
) & 0xf) << 20) |
644 ((GET_H_ICCR (H_ICCR_ICC0
) & 0xf) << 16) |
645 ((GET_H_FCCR (H_FCCR_FCC3
) & 0xf) << 12) |
646 ((GET_H_FCCR (H_FCCR_FCC2
) & 0xf) << 8) |
647 ((GET_H_FCCR (H_FCCR_FCC1
) & 0xf) << 4) |
648 ((GET_H_FCCR (H_FCCR_FCC0
) & 0xf) );
654 spr_ccr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
658 SET_H_ICCR (H_ICCR_ICC3
, (newval
>> 28) & 0xf);
659 SET_H_ICCR (H_ICCR_ICC2
, (newval
>> 24) & 0xf);
660 SET_H_ICCR (H_ICCR_ICC1
, (newval
>> 20) & 0xf);
661 SET_H_ICCR (H_ICCR_ICC0
, (newval
>> 16) & 0xf);
662 SET_H_FCCR (H_FCCR_FCC3
, (newval
>> 12) & 0xf);
663 SET_H_FCCR (H_FCCR_FCC2
, (newval
>> 8) & 0xf);
664 SET_H_FCCR (H_FCCR_FCC1
, (newval
>> 4) & 0xf);
665 SET_H_FCCR (H_FCCR_FCC0
, (newval
) & 0xf);
669 frvbf_set_icc_for_shift_right (
670 SIM_CPU
*current_cpu
, SI value
, SI shift
, QI icc
673 /* Set the C flag of the given icc to the logical OR of the bits shifted
675 int mask
= (1 << shift
) - 1;
676 if ((value
& mask
) != 0)
683 frvbf_set_icc_for_shift_left (
684 SIM_CPU
*current_cpu
, SI value
, SI shift
, QI icc
687 /* Set the V flag of the given icc to the logical OR of the bits shifted
689 int mask
= ((1 << shift
) - 1) << (32 - shift
);
690 if ((value
& mask
) != 0)
696 /* Cover fns to access the cccr bits. */
698 spr_cccr_get_handler (SIM_CPU
*current_cpu
)
700 int cccr
= ((GET_H_CCCR (H_CCCR_CC7
) & 0x3) << 14) |
701 ((GET_H_CCCR (H_CCCR_CC6
) & 0x3) << 12) |
702 ((GET_H_CCCR (H_CCCR_CC5
) & 0x3) << 10) |
703 ((GET_H_CCCR (H_CCCR_CC4
) & 0x3) << 8) |
704 ((GET_H_CCCR (H_CCCR_CC3
) & 0x3) << 6) |
705 ((GET_H_CCCR (H_CCCR_CC2
) & 0x3) << 4) |
706 ((GET_H_CCCR (H_CCCR_CC1
) & 0x3) << 2) |
707 ((GET_H_CCCR (H_CCCR_CC0
) & 0x3) );
713 spr_cccr_set_handler (SIM_CPU
*current_cpu
, USI newval
)
717 SET_H_CCCR (H_CCCR_CC7
, (newval
>> 14) & 0x3);
718 SET_H_CCCR (H_CCCR_CC6
, (newval
>> 12) & 0x3);
719 SET_H_CCCR (H_CCCR_CC5
, (newval
>> 10) & 0x3);
720 SET_H_CCCR (H_CCCR_CC4
, (newval
>> 8) & 0x3);
721 SET_H_CCCR (H_CCCR_CC3
, (newval
>> 6) & 0x3);
722 SET_H_CCCR (H_CCCR_CC2
, (newval
>> 4) & 0x3);
723 SET_H_CCCR (H_CCCR_CC1
, (newval
>> 2) & 0x3);
724 SET_H_CCCR (H_CCCR_CC0
, (newval
) & 0x3);
727 /* Cover fns to access the sr bits. */
729 spr_sr_get_handler (SIM_CPU
*current_cpu
, UINT spr
)
731 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
732 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
733 int psr_esr
= GET_H_PSR_ESR ();
735 return GET_H_GR (4 + (spr
- H_SPR_SR0
));
737 return CPU (h_spr
[spr
]);
741 spr_sr_set_handler (SIM_CPU
*current_cpu
, UINT spr
, USI newval
)
743 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
744 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
745 int psr_esr
= GET_H_PSR_ESR ();
747 SET_H_GR (4 + (spr
- H_SPR_SR0
), newval
);
749 CPU (h_spr
[spr
]) = newval
;
752 /* Switch SR0-SR4 with GR4-GR7 if PSR.ESR is set. */
754 frvbf_switch_supervisor_user_context (SIM_CPU
*current_cpu
)
756 if (GET_H_PSR_ESR ())
758 /* We need to be in supervisor mode to swap the registers. Access the
759 PSR.S directly in order to avoid recursive context switches. */
761 int save_psr_s
= CPU (h_psr_s
);
763 for (i
= 0; i
< 4; ++i
)
766 int spr
= i
+ H_SPR_SR0
;
767 SI tmp
= GET_H_SPR (spr
);
768 SET_H_SPR (spr
, GET_H_GR (gr
));
771 CPU (h_psr_s
) = save_psr_s
;
775 /* Handle load/store of quad registers. */
777 frvbf_load_quad_GR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
782 /* Check memory alignment */
783 address
= check_memory_alignment (current_cpu
, address
, 0xf);
785 /* If we need to count cycles, then the cache operation will be
786 initiated from the model profiling functions.
787 See frvbf_model_.... */
790 CPU_LOAD_ADDRESS (current_cpu
) = address
;
791 CPU_LOAD_LENGTH (current_cpu
) = 16;
795 for (i
= 0; i
< 4; ++i
)
797 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
800 sim_queue_fn_xi_write (current_cpu
, frvbf_h_gr_quad_set_handler
, targ_ix
,
806 frvbf_store_quad_GR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
812 /* Check register and memory alignment. */
813 src_ix
= check_register_alignment (current_cpu
, src_ix
, 3);
814 address
= check_memory_alignment (current_cpu
, address
, 0xf);
816 for (i
= 0; i
< 4; ++i
)
818 /* GR0 is always 0. */
822 value
[i
] = GET_H_GR (src_ix
+ i
);
825 if (GET_HSR0_DCE (hsr0
))
826 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
828 sim_queue_mem_xi_write (current_cpu
, address
, value
);
832 frvbf_load_quad_FRint (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
837 /* Check memory alignment */
838 address
= check_memory_alignment (current_cpu
, address
, 0xf);
840 /* If we need to count cycles, then the cache operation will be
841 initiated from the model profiling functions.
842 See frvbf_model_.... */
845 CPU_LOAD_ADDRESS (current_cpu
) = address
;
846 CPU_LOAD_LENGTH (current_cpu
) = 16;
850 for (i
= 0; i
< 4; ++i
)
852 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
855 sim_queue_fn_xi_write (current_cpu
, frvbf_h_fr_quad_set_handler
, targ_ix
,
861 frvbf_store_quad_FRint (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
867 /* Check register and memory alignment. */
868 src_ix
= check_fr_register_alignment (current_cpu
, src_ix
, 3);
869 address
= check_memory_alignment (current_cpu
, address
, 0xf);
871 for (i
= 0; i
< 4; ++i
)
872 value
[i
] = GET_H_FR (src_ix
+ i
);
875 if (GET_HSR0_DCE (hsr0
))
876 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
878 sim_queue_mem_xi_write (current_cpu
, address
, value
);
882 frvbf_load_quad_CPR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI targ_ix
)
887 /* Check memory alignment */
888 address
= check_memory_alignment (current_cpu
, address
, 0xf);
890 /* If we need to count cycles, then the cache operation will be
891 initiated from the model profiling functions.
892 See frvbf_model_.... */
895 CPU_LOAD_ADDRESS (current_cpu
) = address
;
896 CPU_LOAD_LENGTH (current_cpu
) = 16;
900 for (i
= 0; i
< 4; ++i
)
902 value
[i
] = frvbf_read_mem_SI (current_cpu
, pc
, address
);
905 sim_queue_fn_xi_write (current_cpu
, frvbf_h_cpr_quad_set_handler
, targ_ix
,
911 frvbf_store_quad_CPR (SIM_CPU
*current_cpu
, PCADDR pc
, SI address
, SI src_ix
)
917 /* Check register and memory alignment. */
918 src_ix
= check_register_alignment (current_cpu
, src_ix
, 3);
919 address
= check_memory_alignment (current_cpu
, address
, 0xf);
921 for (i
= 0; i
< 4; ++i
)
922 value
[i
] = GET_H_CPR (src_ix
+ i
);
925 if (GET_HSR0_DCE (hsr0
))
926 sim_queue_fn_mem_xi_write (current_cpu
, frvbf_mem_set_XI
, address
, value
);
928 sim_queue_mem_xi_write (current_cpu
, address
, value
);
932 frvbf_signed_integer_divide (
933 SIM_CPU
*current_cpu
, SI arg1
, SI arg2
, int target_index
, int non_excepting
936 enum frv_dtt dtt
= FRV_DTT_NO_EXCEPTION
;
937 if (arg1
== 0x80000000 && arg2
== -1)
939 /* 0x80000000/(-1) must result in 0x7fffffff when ISR.EDE is set
940 otherwise it may result in 0x7fffffff (sparc compatibility) or
941 0x80000000 (C language compatibility). */
943 dtt
= FRV_DTT_OVERFLOW
;
946 if (GET_ISR_EDE (isr
))
947 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
950 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
952 frvbf_force_update (current_cpu
); /* Force update of target register. */
955 dtt
= FRV_DTT_DIVISION_BY_ZERO
;
957 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
960 /* Check for exceptions. */
961 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
962 dtt
= frvbf_division_exception (current_cpu
, dtt
, target_index
,
964 if (non_excepting
&& dtt
== FRV_DTT_NO_EXCEPTION
)
966 /* Non excepting instruction. Clear the NE flag for the target
969 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
970 CLEAR_NE_FLAG (NE_flags
, target_index
);
971 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
976 frvbf_unsigned_integer_divide (
977 SIM_CPU
*current_cpu
, USI arg1
, USI arg2
, int target_index
, int non_excepting
981 frvbf_division_exception (current_cpu
, FRV_DTT_DIVISION_BY_ZERO
,
982 target_index
, non_excepting
);
985 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, target_index
,
989 /* Non excepting instruction. Clear the NE flag for the target
992 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
993 CLEAR_NE_FLAG (NE_flags
, target_index
);
994 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
999 /* Clear accumulators. */
1001 frvbf_clear_accumulators (SIM_CPU
*current_cpu
, SI acc_ix
, int A
)
1003 SIM_DESC sd
= CPU_STATE (current_cpu
);
1005 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr500
) ? 7 :
1006 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr550
) ? 7 :
1007 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
) ? 11 :
1008 (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
) ? 3 :
1010 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1012 ps
->mclracc_acc
= acc_ix
;
1014 if (A
== 0 || acc_ix
!= 0) /* Clear 1 accumuator? */
1016 /* This instruction is a nop if the referenced accumulator is not
1018 if ((acc_ix
& acc_mask
) == acc_ix
)
1019 sim_queue_fn_di_write (current_cpu
, frvbf_h_acc40S_set
, acc_ix
, 0);
1023 /* Clear all implemented accumulators. */
1025 for (i
= 0; i
<= acc_mask
; ++i
)
1026 if ((i
& acc_mask
) == i
)
1027 sim_queue_fn_di_write (current_cpu
, frvbf_h_acc40S_set
, i
, 0);
1031 /* Functions to aid insn semantics. */
1033 /* Compute the result of the SCAN and SCANI insns after the shift and xor. */
1035 frvbf_scan_result (SIM_CPU
*current_cpu
, SI value
)
1043 /* Find the position of the first non-zero bit.
1044 The loop will terminate since there is guaranteed to be at least one
1046 mask
= 1 << (sizeof (mask
) * 8 - 1);
1047 for (i
= 0; (value
& mask
) == 0; ++i
)
1053 /* Compute the result of the cut insns. */
1055 frvbf_cut (SIM_CPU
*current_cpu
, SI reg1
, SI reg2
, SI cut_point
)
1061 result
= reg1
<< cut_point
;
1062 result
|= (reg2
>> (32 - cut_point
)) & ((1 << cut_point
) - 1);
1065 result
= reg2
<< (cut_point
- 32);
1070 /* Compute the result of the cut insns. */
1072 frvbf_media_cut (SIM_CPU
*current_cpu
, DI acc
, SI cut_point
)
1074 /* The cut point is the lower 6 bits (signed) of what we are passed. */
1075 cut_point
= cut_point
<< 26 >> 26;
1077 /* The cut_point is relative to bit 40 of 64 bits. */
1079 return (acc
<< (cut_point
+ 24)) >> 32;
1081 /* Extend the sign bit (bit 40) for negative cuts. */
1082 if (cut_point
== -32)
1083 return (acc
<< 24) >> 63; /* Special case for full shiftout. */
1085 return (acc
<< 24) >> (32 + -cut_point
);
1088 /* Compute the result of the cut insns. */
1090 frvbf_media_cut_ss (SIM_CPU
*current_cpu
, DI acc
, SI cut_point
)
1092 /* The cut point is the lower 6 bits (signed) of what we are passed. */
1093 cut_point
= cut_point
<< 26 >> 26;
1097 /* The cut_point is relative to bit 40 of 64 bits. */
1098 DI shifted
= acc
<< (cut_point
+ 24);
1099 DI unshifted
= shifted
>> (cut_point
+ 24);
1101 /* The result will be saturated if significant bits are shifted out. */
1102 if (unshifted
!= acc
)
1110 /* The result will not be saturated, so use the code for the normal cut. */
1111 return frvbf_media_cut (current_cpu
, acc
, cut_point
);
1114 /* Compute the result of int accumulator cut (SCUTSS). */
1116 frvbf_iacc_cut (SIM_CPU
*current_cpu
, DI acc
, SI cut_point
)
1120 /* The cut point is the lower 7 bits (signed) of what we are passed. */
1121 cut_point
= cut_point
<< 25 >> 25;
1123 /* Conceptually, the operation is on a 128-bit sign-extension of ACC.
1124 The top bit of the return value corresponds to bit (63 - CUT_POINT)
1125 of this 128-bit value.
1127 Since we can't deal with 128-bit values very easily, convert the
1128 operation into an equivalent 64-bit one. */
1131 /* Avoid an undefined shift operation. */
1132 if (cut_point
== -64)
1139 /* Get the shifted but unsaturated result. Set LOWER to the lowest
1140 32 bits of the result and UPPER to the result >> 31. */
1143 /* The cut loses the (32 - CUT_POINT) least significant bits.
1144 Round the result up if the most significant of these lost bits
1146 lower
= acc
>> (32 - cut_point
);
1147 if (lower
< 0x7fffffff)
1148 if (acc
& LSBIT64 (32 - cut_point
- 1))
1150 upper
= lower
>> 31;
1154 lower
= acc
<< (cut_point
- 32);
1155 upper
= acc
>> (63 - cut_point
);
1158 /* Saturate the result. */
1167 /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
1169 frvbf_shift_left_arith_saturate (SIM_CPU
*current_cpu
, SI arg1
, SI arg2
)
1173 /* FIXME: what to do with negative shift amt? */
1180 /* Signed shift by 31 or greater saturates by definition. */
1183 return (SI
) 0x7fffffff;
1185 return (SI
) 0x80000000;
1187 /* OK, arg2 is between 1 and 31. */
1188 neg_arg1
= (arg1
< 0);
1191 /* Check for sign bit change (saturation). */
1192 if (neg_arg1
&& (arg1
>= 0))
1193 return (SI
) 0x80000000;
1194 else if (!neg_arg1
&& (arg1
< 0))
1195 return (SI
) 0x7fffffff;
1196 } while (--arg2
> 0);
1201 /* Simulate the media custom insns. */
1203 frvbf_media_cop (SIM_CPU
*current_cpu
, int cop_num
)
1205 /* The semantics of the insn are a nop, since it is implementation defined.
1206 We do need to check whether it's implemented and set up for MTRAP
1208 USI msr0
= GET_MSR (0);
1209 if (GET_MSR_EMCI (msr0
) == 0)
1211 /* no interrupt queued at this time. */
1212 frv_set_mp_exception_registers (current_cpu
, MTT_UNIMPLEMENTED_MPOP
, 0);
1216 /* Simulate the media average (MAVEH) insn. */
1218 do_media_average (SIM_CPU
*current_cpu
, HI arg1
, HI arg2
)
1220 SIM_DESC sd
= CPU_STATE (current_cpu
);
1221 SI sum
= (arg1
+ arg2
);
1222 HI result
= sum
>> 1;
1225 /* On fr4xx and fr550, check the rounding mode. On other machines
1226 rounding is always toward negative infinity and the result is
1227 already correctly rounded. */
1228 switch (STATE_ARCHITECTURE (sd
)->mach
)
1230 /* Need to check rounding mode. */
1231 case bfd_mach_fr400
:
1232 case bfd_mach_fr450
:
1233 case bfd_mach_fr550
:
1234 /* Check whether rounding will be required. Rounding will be required
1235 if the sum is an odd number. */
1236 rounding_value
= sum
& 1;
1239 USI msr0
= GET_MSR (0);
1240 /* Check MSR0.SRDAV to determine which bits control the rounding. */
1241 if (GET_MSR_SRDAV (msr0
))
1243 /* MSR0.RD controls rounding. */
1244 switch (GET_MSR_RD (msr0
))
1247 /* Round to nearest. */
1252 /* Round toward 0. */
1257 /* Round toward positive infinity. */
1261 /* Round toward negative infinity. The result is already
1262 correctly rounded. */
1271 /* MSR0.RDAV controls rounding. If set, round toward positive
1272 infinity. Otherwise the result is already rounded correctly
1273 toward negative infinity. */
1274 if (GET_MSR_RDAV (msr0
))
1287 frvbf_media_average (SIM_CPU
*current_cpu
, SI reg1
, SI reg2
)
1290 result
= do_media_average (current_cpu
, reg1
& 0xffff, reg2
& 0xffff);
1292 result
|= do_media_average (current_cpu
, (reg1
>> 16) & 0xffff,
1293 (reg2
>> 16) & 0xffff) << 16;
1297 /* Maintain a flag in order to know when to write the address of the next
1298 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL. */
1300 frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU
*current_cpu
, int value
)
1302 frvbf_write_next_vliw_addr_to_LR
= value
;
1306 frvbf_set_ne_index (SIM_CPU
*current_cpu
, int index
)
1310 /* Save the target register so interrupt processing can set its NE flag
1311 in the event of an exception. */
1312 frv_interrupt_state
.ne_index
= index
;
1314 /* Clear the NE flag of the target register. It will be reset if necessary
1315 in the event of an exception. */
1316 GET_NE_FLAGS (NE_flags
, H_SPR_FNER0
);
1317 CLEAR_NE_FLAG (NE_flags
, index
);
1318 SET_NE_FLAGS (H_SPR_FNER0
, NE_flags
);
1322 frvbf_force_update (SIM_CPU
*current_cpu
)
1324 CGEN_WRITE_QUEUE
*q
= CPU_WRITE_QUEUE (current_cpu
);
1325 int ix
= CGEN_WRITE_QUEUE_INDEX (q
);
1328 CGEN_WRITE_QUEUE_ELEMENT
*item
= CGEN_WRITE_QUEUE_ELEMENT (q
, ix
- 1);
1329 item
->flags
|= FRV_WRITE_QUEUE_FORCE_WRITE
;
1333 /* Condition code logic. */
1335 andcr
, orcr
, xorcr
, nandcr
, norcr
, andncr
, orncr
, nandncr
, norncr
,
1339 enum cr_result
{cr_undefined
, cr_undefined1
, cr_false
, cr_true
};
1341 static enum cr_result
1342 cr_logic
[num_cr_ops
][4][4] = {
1345 /* undefined undefined false true */
1346 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1347 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1348 /* false */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1349 /* true */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
}
1353 /* undefined undefined false true */
1354 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1355 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1356 /* false */ {cr_false
, cr_false
, cr_false
, cr_true
},
1357 /* true */ {cr_true
, cr_true
, cr_true
, cr_true
}
1361 /* undefined undefined false true */
1362 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1363 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1364 /* false */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1365 /* true */ {cr_true
, cr_true
, cr_true
, cr_false
}
1369 /* undefined undefined false true */
1370 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1371 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1372 /* false */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1373 /* true */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
}
1377 /* undefined undefined false true */
1378 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1379 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1380 /* false */ {cr_true
, cr_true
, cr_true
, cr_false
},
1381 /* true */ {cr_false
, cr_false
, cr_false
, cr_false
}
1385 /* undefined undefined false true */
1386 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1387 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1388 /* false */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1389 /* true */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
}
1393 /* undefined undefined false true */
1394 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1395 /* undefined */ {cr_undefined
, cr_undefined
, cr_false
, cr_true
},
1396 /* false */ {cr_true
, cr_true
, cr_true
, cr_true
},
1397 /* true */ {cr_false
, cr_false
, cr_false
, cr_true
}
1401 /* undefined undefined false true */
1402 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1403 /* undefined */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
},
1404 /* false */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1405 /* true */ {cr_undefined
, cr_undefined
, cr_undefined
, cr_undefined
}
1409 /* undefined undefined false true */
1410 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1411 /* undefined */ {cr_undefined
, cr_undefined
, cr_true
, cr_false
},
1412 /* false */ {cr_false
, cr_false
, cr_false
, cr_false
},
1413 /* true */ {cr_true
, cr_true
, cr_true
, cr_false
}
1418 frvbf_cr_logic (SIM_CPU
*current_cpu
, SI operation
, UQI arg1
, UQI arg2
)
1420 return cr_logic
[operation
][arg1
][arg2
];
1423 /* Cache Manipulation. */
1425 frvbf_insn_cache_preload (SIM_CPU
*current_cpu
, SI address
, USI length
, int lock
)
1427 /* If we need to count cycles, then the cache operation will be
1428 initiated from the model profiling functions.
1429 See frvbf_model_.... */
1430 int hsr0
= GET_HSR0 ();
1431 if (GET_HSR0_ICE (hsr0
))
1435 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1436 CPU_LOAD_LENGTH (current_cpu
) = length
;
1437 CPU_LOAD_LOCK (current_cpu
) = lock
;
1441 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1442 frv_cache_preload (cache
, address
, length
, lock
);
1448 frvbf_data_cache_preload (SIM_CPU
*current_cpu
, SI address
, USI length
, int lock
)
1450 /* If we need to count cycles, then the cache operation will be
1451 initiated from the model profiling functions.
1452 See frvbf_model_.... */
1453 int hsr0
= GET_HSR0 ();
1454 if (GET_HSR0_DCE (hsr0
))
1458 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1459 CPU_LOAD_LENGTH (current_cpu
) = length
;
1460 CPU_LOAD_LOCK (current_cpu
) = lock
;
1464 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1465 frv_cache_preload (cache
, address
, length
, lock
);
1471 frvbf_insn_cache_unlock (SIM_CPU
*current_cpu
, SI address
)
1473 /* If we need to count cycles, then the cache operation will be
1474 initiated from the model profiling functions.
1475 See frvbf_model_.... */
1476 int hsr0
= GET_HSR0 ();
1477 if (GET_HSR0_ICE (hsr0
))
1480 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1483 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1484 frv_cache_unlock (cache
, address
);
1490 frvbf_data_cache_unlock (SIM_CPU
*current_cpu
, SI address
)
1492 /* If we need to count cycles, then the cache operation will be
1493 initiated from the model profiling functions.
1494 See frvbf_model_.... */
1495 int hsr0
= GET_HSR0 ();
1496 if (GET_HSR0_DCE (hsr0
))
1499 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1502 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1503 frv_cache_unlock (cache
, address
);
1509 frvbf_insn_cache_invalidate (SIM_CPU
*current_cpu
, SI address
, int all
)
1511 /* Make sure the insn was specified properly. -1 will be passed for ALL
1512 for a icei with A=0. */
1515 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1519 /* If we need to count cycles, then the cache operation will be
1520 initiated from the model profiling functions.
1521 See frvbf_model_.... */
1524 /* Record the all-entries flag for use in profiling. */
1525 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1526 ps
->all_cache_entries
= all
;
1527 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1531 FRV_CACHE
*cache
= CPU_INSN_CACHE (current_cpu
);
1533 frv_cache_invalidate_all (cache
, 0/* flush? */);
1535 frv_cache_invalidate (cache
, address
, 0/* flush? */);
1540 frvbf_data_cache_invalidate (SIM_CPU
*current_cpu
, SI address
, int all
)
1542 /* Make sure the insn was specified properly. -1 will be passed for ALL
1543 for a dcei with A=0. */
1546 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1550 /* If we need to count cycles, then the cache operation will be
1551 initiated from the model profiling functions.
1552 See frvbf_model_.... */
1555 /* Record the all-entries flag for use in profiling. */
1556 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1557 ps
->all_cache_entries
= all
;
1558 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1562 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1564 frv_cache_invalidate_all (cache
, 0/* flush? */);
1566 frv_cache_invalidate (cache
, address
, 0/* flush? */);
1571 frvbf_data_cache_flush (SIM_CPU
*current_cpu
, SI address
, int all
)
1573 /* Make sure the insn was specified properly. -1 will be passed for ALL
1574 for a dcef with A=0. */
1577 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
1581 /* If we need to count cycles, then the cache operation will be
1582 initiated from the model profiling functions.
1583 See frvbf_model_.... */
1586 /* Record the all-entries flag for use in profiling. */
1587 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
1588 ps
->all_cache_entries
= all
;
1589 CPU_LOAD_ADDRESS (current_cpu
) = address
;
1593 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
1595 frv_cache_invalidate_all (cache
, 1/* flush? */);
1597 frv_cache_invalidate (cache
, address
, 1/* flush? */);