1 # Simulator main loop for frv. -*- C -*-
2 # Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
3 # Contributed by Red Hat.
5 # This file is part of the GNU Simulators.
7 # This program is free software; you can redistribute it and/or modify
8 # it under the terms of the GNU General Public License as published by
9 # the Free Software Foundation; either version 2, or (at your option)
12 # This program is distributed in the hope that it will be useful,
13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License for more details.
17 # You should have received a copy of the GNU General Public License along
18 # with this program; if not, write to the Free Software Foundation, Inc.,
19 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 # /bin/sh mainloop.in command
28 # extract-{simple,scache,pbb}
29 # {full,fast}-exec-{simple,scache,pbb}
31 # A target need only provide a "full" version of one of simple,scache,pbb.
32 # If the target wants it can also provide a fast version of same.
33 # It can't provide more than this.
35 # ??? After a few more ports are done, revisit.
36 # Will eventually need to machine generate a lot of this.
44 static INLINE const IDESC *
45 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
48 const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
49 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
52 int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
53 int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
54 @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
60 execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
64 /* Force gr0 to zero before every insn. */
65 @cpu@_h_gr_set (current_cpu, 0, 0);
69 vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
73 ARGBUF *abuf = &sc->argbuf;
74 const IDESC *idesc = abuf->idesc;
76 int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
83 /* FIXME: call x-before */
84 if (ARGBUF_PROFILE_P (abuf))
85 PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
86 /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
87 if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
89 @cpu@_model_insn_before (current_cpu, sc->first_insn_p);
90 model_insn = FRV_INSN_MODEL_PASS_1;
91 if (idesc->timing->model_fn != NULL)
92 (*idesc->timing->model_fn) (current_cpu, sc);
95 model_insn = FRV_INSN_NO_MODELING;
96 TRACE_INSN_INIT (current_cpu, abuf, 1);
97 TRACE_INSN (current_cpu, idesc->idata,
98 (const struct argbuf *) abuf, abuf->addr);
101 vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
103 vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
107 /* FIXME: call x-after */
108 if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
111 if (idesc->timing->model_fn != NULL)
113 model_insn = FRV_INSN_MODEL_PASS_2;
114 cycles = (*idesc->timing->model_fn) (current_cpu, sc);
118 @cpu@_model_insn_after (current_cpu, sc->last_insn_p, cycles);
120 TRACE_INSN_FINI (current_cpu, abuf, 1);
128 @cpu@_parallel_write_init (SIM_CPU *current_cpu)
130 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
131 CGEN_WRITE_QUEUE_CLEAR (q);
132 previous_vliw_pc = CPU_PC_GET(current_cpu);
133 frv_interrupt_state.f_ne_flags[0] = 0;
134 frv_interrupt_state.f_ne_flags[1] = 0;
135 frv_interrupt_state.imprecise_interrupt = NULL;
139 @cpu@_parallel_write_queued (SIM_CPU *current_cpu)
143 FRV_VLIW *vliw = CPU_VLIW (current_cpu);
144 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
146 /* Loop over the queued writes, executing them. Set the pc to the address
147 of the insn which queued each write for the proper context in case an
148 interrupt is caused. Restore the proper pc after the writes are
150 IADDR save_pc = CPU_PC_GET (current_cpu);
151 IADDR new_pc = save_pc;
152 int branch_taken = 0;
153 int limit = CGEN_WRITE_QUEUE_INDEX (q);
154 frv_interrupt_state.data_written.length = 0;
156 for (i = 0; i < limit; ++i)
158 CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, i);
160 /* If an imprecise interrupt was generated, then, check whether the
161 result should still be written. */
162 if (frv_interrupt_state.imprecise_interrupt != NULL)
164 /* Only check writes by the insn causing the exception. */
165 if (CGEN_WRITE_QUEUE_ELEMENT_IADDR (item)
166 == frv_interrupt_state.imprecise_interrupt->vpc)
168 /* Execute writes of floating point operations resulting in
169 overflow, underflow or inexact. */
170 if (frv_interrupt_state.imprecise_interrupt->kind
173 if ((frv_interrupt_state.imprecise_interrupt
175 & ~(FSR_INEXACT | FSR_OVERFLOW | FSR_UNDERFLOW)))
176 continue; /* Don't execute */
178 /* Execute writes marked as 'forced'. */
179 else if (! (CGEN_WRITE_QUEUE_ELEMENT_FLAGS (item)
180 & FRV_WRITE_QUEUE_FORCE_WRITE))
181 continue; /* Don't execute */
185 /* Only execute the first branch on the queue. */
186 if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE
187 || CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_FN_PC_WRITE)
192 if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE)
193 new_pc = item->kinds.pc_write.value;
195 new_pc = item->kinds.fn_pc_write.value;
198 CPU_PC_SET (current_cpu, CGEN_WRITE_QUEUE_ELEMENT_IADDR (item));
199 frv_save_data_written_for_interrupts (current_cpu, item);
200 cgen_write_queue_element_execute (current_cpu, item);
203 /* Update the LR with the address of the next insn if the flag is set.
204 This flag gets set in frvbf_set_write_next_vliw_to_LR by the JMPL,
205 JMPIL and CALL insns. */
206 if (frvbf_write_next_vliw_addr_to_LR)
208 frvbf_h_spr_set_handler (current_cpu, H_SPR_LR, save_pc);
209 frvbf_write_next_vliw_addr_to_LR = 0;
212 CPU_PC_SET (current_cpu, new_pc);
213 CGEN_WRITE_QUEUE_CLEAR (q);
217 @cpu@_perform_writeback (SIM_CPU *current_cpu)
219 @cpu@_parallel_write_queued (current_cpu);
222 static unsigned cache_reqno = 0x80000000; /* Start value is for debugging. */
224 #if 0 /* experimental */
225 /* FR400 has single prefetch. */
227 fr400_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
232 /* The cpu receives 8 bytes worth of insn data for each fetch aligned
233 on 8 byte boundary. */
234 #define FR400_FETCH_SIZE 8
237 vpc &= ~(FR400_FETCH_SIZE - 1);
238 cache = CPU_INSN_CACHE (current_cpu);
240 /* Request a load of the current address buffer, if necessary. */
241 if (frv_insn_fetch_buffer[cur_ix].address != vpc)
243 frv_insn_fetch_buffer[cur_ix].address = vpc;
244 frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
245 if (FRV_COUNT_CYCLES (current_cpu, 1))
246 frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
247 frv_insn_fetch_buffer[cur_ix].address,
251 /* Wait for the current address buffer to be loaded, if necessary. */
252 if (FRV_COUNT_CYCLES (current_cpu, 1))
254 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
257 /* Account for any branch penalty. */
258 if (ps->branch_penalty > 0 && ! ps->past_first_p)
260 frv_model_advance_cycles (current_cpu, ps->branch_penalty);
261 frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
263 ps->branch_penalty = 0;
266 /* Account for insn fetch latency. */
268 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
270 frv_model_advance_cycles (current_cpu, 1);
273 frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
277 /* Otherwise just load the insns directly from the cache.
279 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
281 frv_cache_read (cache, cur_ix, vpc);
282 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
285 #endif /* experimental */
287 /* FR500 has dual prefetch. */
289 simulate_dual_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc, int fetch_size)
296 /* See if the pc is within the addresses specified by either of the
297 fetch buffers. If so, that will be the current buffer. Otherwise,
298 arbitrarily select the LD buffer as the current one since it gets
299 priority in the case of interfering load requests. */
301 vpc &= ~(fetch_size - 1);
302 for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
304 if (frv_insn_fetch_buffer[i].address == vpc)
310 cache = CPU_INSN_CACHE (current_cpu);
312 /* Request a load of the current address buffer, if necessary. */
313 if (frv_insn_fetch_buffer[cur_ix].address != vpc)
315 frv_insn_fetch_buffer[cur_ix].address = vpc;
316 frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
317 if (FRV_COUNT_CYCLES (current_cpu, 1))
318 frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
319 frv_insn_fetch_buffer[cur_ix].address,
323 /* If the prefetch buffer does not represent the next sequential address, then
324 request a load of the next sequential address. */
325 pre_ix = (cur_ix + 1) % FRV_CACHE_PIPELINES;
326 pre_address = vpc + fetch_size;
327 if (frv_insn_fetch_buffer[pre_ix].address != pre_address)
329 frv_insn_fetch_buffer[pre_ix].address = pre_address;
330 frv_insn_fetch_buffer[pre_ix].reqno = cache_reqno++;
331 if (FRV_COUNT_CYCLES (current_cpu, 1))
332 frv_cache_request_load (cache, frv_insn_fetch_buffer[pre_ix].reqno,
333 frv_insn_fetch_buffer[pre_ix].address,
337 /* If counting cycles, account for any branch penalty and/or insn fetch
339 if (FRV_COUNT_CYCLES (current_cpu, 1))
341 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
344 /* Account for any branch penalty. */
345 if (ps->branch_penalty > 0 && ! ps->past_first_p)
347 frv_model_advance_cycles (current_cpu, ps->branch_penalty);
348 frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
350 ps->branch_penalty = 0;
353 /* Account for insn fetch latency. */
355 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
357 frv_model_advance_cycles (current_cpu, 1);
360 frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
364 /* Otherwise just load the insns directly from the cache.
366 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
368 frv_cache_read (cache, cur_ix, vpc);
369 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
371 if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
373 frv_cache_read (cache, pre_ix, pre_address);
374 frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
379 @cpu@_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
384 /* Nothing to do if not counting cycles and the cache is not enabled. */
386 if (! GET_HSR0_ICE (hsr0) && ! FRV_COUNT_CYCLES (current_cpu, 1))
389 /* Different machines handle prefetch defferently. */
390 sd = CPU_STATE (current_cpu);
391 switch (STATE_ARCHITECTURE (sd)->mach)
394 simulate_dual_insn_prefetch (current_cpu, vpc, 8);
396 case bfd_mach_frvtomcat:
400 simulate_dual_insn_prefetch (current_cpu, vpc, 16);
407 int frv_save_profile_model_p;
416 /* If the timer is enabled, then we will enable model profiling during
417 execution. This is because the timer needs accurate cycles counts to
418 work properly. Save the original setting of model profiling. */
419 if (frv_interrupt_state.timer.enabled)
420 frv_save_profile_model_p = PROFILE_MODEL_P (current_cpu);
425 xextract-simple | xextract-scache)
427 # Inputs: current_cpu, vpc, sc, FAST_P
428 # Outputs: sc filled in
429 # SET_LAST_INSN_P(last_p) called to indicate whether insn is last one
433 CGEN_INSN_INT insn = frvbf_read_imem_USI (current_cpu, vpc);
434 extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
435 SET_LAST_INSN_P ((insn & 0x80000000) != 0);
441 xfull-exec-* | xfast-exec-*)
443 # Inputs: current_cpu, vpc, FAST_P
445 # vpc contains the address of the next insn to execute
446 # pc of current_cpu must be up to date (=vpc) upon exit
447 # CPU_INSN_COUNT (current_cpu) must be updated by number of insns executed
449 # Unlike the non-parallel case, this version is responsible for doing the
455 int first_insn_p = 1;
458 CGEN_ATTR_VALUE_TYPE slot;
460 /* If the timer is enabled, then enable model profiling. This is because
461 the timer needs accurate cycles counts to work properly. */
462 if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
463 sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "1");
465 /* Init parallel-write queue and vliw. */
466 @cpu@_parallel_write_init (current_cpu);
467 vliw = CPU_VLIW (current_cpu);
468 frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
469 CPU_ELF_FLAGS (current_cpu));
470 frv_current_fm_slot = UNIT_NIL;
472 for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
475 const CGEN_INSN *insn;
477 /* Go through the motions of finding the insns in the cache. */
478 @cpu@_simulate_insn_prefetch (current_cpu, vpc);
480 sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
481 sc->first_insn_p = first_insn_p;
482 last_insn_p = sc->last_insn_p;
484 /* Add the insn to the vliw and set up the interrupt state. */
485 insn = sc->argbuf.idesc->idata;
486 error = frv_vliw_add_insn (vliw, insn);
488 frv_vliw_setup_insn (current_cpu, insn);
489 frv_detect_insn_access_interrupts (current_cpu, sc);
490 slot = (*vliw->current_vliw)[vliw->next_slot - 1];
491 if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
492 frv_current_fm_slot = slot;
494 vpc = execute (current_cpu, sc, FAST_P);
496 SET_H_PC (vpc); /* needed for interrupt handling */
500 /* If the timer is enabled, and model profiling was not originally enabled,
501 then turn it off again. This is the only place we can currently gain
502 control to do this. */
503 if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
504 sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0");
506 /* Check for interrupts. Also handles writeback if necessary. */
507 frv_process_interrupts (current_cpu);
509 CPU_INSN_COUNT (current_cpu) += ninsns;
516 echo "Invalid argument to mainloop.in: $1" >&2