1 /* frv simulator support code
2 Copyright (C) 1999, 2000, 2001, 2003, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #define WANT_CPU_FRVBF
27 /* Initialize the frv simulator. */
29 frv_initialize (SIM_CPU
*current_cpu
, SIM_DESC sd
)
31 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (current_cpu
);
32 PROFILE_DATA
*p
= CPU_PROFILE_DATA (current_cpu
);
33 FRV_CACHE
*insn_cache
= CPU_INSN_CACHE (current_cpu
);
34 FRV_CACHE
*data_cache
= CPU_DATA_CACHE (current_cpu
);
35 int insn_cache_enabled
= CACHE_INITIALIZED (insn_cache
);
36 int data_cache_enabled
= CACHE_INITIALIZED (data_cache
);
39 /* Initialize the register control information first since some of the
40 register values are used in further configuration. */
41 frv_register_control_init (current_cpu
);
43 /* We need to ensure that the caches are initialized even if they are not
44 initially enabled (via commandline) because they can be enabled by
46 if (! insn_cache_enabled
)
47 frv_cache_init (current_cpu
, CPU_INSN_CACHE (current_cpu
));
48 if (! data_cache_enabled
)
49 frv_cache_init (current_cpu
, CPU_DATA_CACHE (current_cpu
));
51 /* Set the default cpu frequency if it has not been set on the command
53 if (PROFILE_CPU_FREQ (p
) == 0)
54 PROFILE_CPU_FREQ (p
) = 266000000; /* 266MHz */
56 /* Allocate one cache line of memory containing the address of the reset
57 register Use the largest of the insn cache line size and the data cache
60 int addr
= RSTR_ADDRESS
;
64 if (CPU_INSN_CACHE (current_cpu
)->line_size
65 > CPU_DATA_CACHE (current_cpu
)->line_size
)
66 bytes
= CPU_INSN_CACHE (current_cpu
)->line_size
;
68 bytes
= CPU_DATA_CACHE (current_cpu
)->line_size
;
70 /* 'bytes' is a power of 2. Calculate the starting address of the
73 aligned_buffer
= zalloc (bytes
); /* clear */
74 sim_core_attach (sd
, NULL
, 0, access_read_write
, 0, addr
, bytes
,
75 0, NULL
, aligned_buffer
);
78 PROFILE_INFO_CPU_CALLBACK(p
) = frv_profile_info
;
79 ps
->insn_fetch_address
= -1;
80 ps
->branch_address
= -1;
82 cgen_init_accurate_fpu (current_cpu
, CGEN_CPU_FPU (current_cpu
),
85 /* Now perform power-on reset. */
86 frv_power_on_reset (current_cpu
);
88 /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */
90 if (insn_cache_enabled
)
93 CLEAR_HSR0_ICE (hsr0
);
94 if (data_cache_enabled
)
97 CLEAR_HSR0_DCE (hsr0
);
101 /* Initialize the frv simulator. */
103 frv_term (SIM_DESC sd
)
105 /* If the timer is enabled, and model profiling was not originally enabled,
106 then turn it off again. This is the only place we can currently gain
107 control to do this. */
108 if (frv_interrupt_state
.timer
.enabled
&& ! frv_save_profile_model_p
)
109 sim_profile_set_option (current_state
, "-model", PROFILE_MODEL_IDX
, "0");
112 /* Perform a power on reset. */
114 frv_power_on_reset (SIM_CPU
*cpu
)
116 /* GR, FR and CPR registers are undefined at initialization time. */
117 frv_initialize_spr (cpu
);
118 /* Initialize the RSTR register (in memory). */
119 if (frv_cache_enabled (CPU_DATA_CACHE (cpu
)))
120 frvbf_mem_set_SI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_INITIAL_VALUE
);
122 SETMEMSI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_INITIAL_VALUE
);
125 /* Perform a hardware reset. */
127 frv_hardware_reset (SIM_CPU
*cpu
)
129 /* GR, FR and CPR registers are undefined at hardware reset. */
130 frv_initialize_spr (cpu
);
131 /* Reset the RSTR register (in memory). */
132 if (frv_cache_enabled (CPU_DATA_CACHE (cpu
)))
133 frvbf_mem_set_SI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_HARDWARE_RESET
);
135 SETMEMSI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_HARDWARE_RESET
);
136 /* Reset the insn and data caches. */
137 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0/* no flush */);
138 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 0/* no flush */);
141 /* Perform a software reset. */
143 frv_software_reset (SIM_CPU
*cpu
)
145 /* GR, FR and CPR registers are undefined at software reset. */
147 /* Reset the RSTR register (in memory). */
148 if (frv_cache_enabled (CPU_DATA_CACHE (cpu
)))
149 frvbf_mem_set_SI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_SOFTWARE_RESET
);
151 SETMEMSI (cpu
, CPU_PC_GET (cpu
), RSTR_ADDRESS
, RSTR_SOFTWARE_RESET
);
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