2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #define WANT_CPU frvbf
21 #define WANT_CPU_FRVBF
24 #include "targ-vals.h"
25 #include "cgen-engine.h"
30 #include "libiberty.h"
32 CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot
;
34 /* The semantic code invokes this for invalid (unrecognized) instructions. */
37 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
39 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
43 /* Process an address exception. */
46 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
47 unsigned int map
, int nr_bytes
, address_word addr
,
48 transfer_type transfer
, sim_core_signals sig
)
50 if (sig
== sim_core_unaligned_signal
)
52 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
53 || STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
)
54 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
56 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
60 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
64 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
67 if (current_cpu
!= NULL
)
68 CIA_SET (current_cpu
, cia
);
70 /* Invalidate the insn and data caches of all cpus. */
71 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
73 current_cpu
= STATE_CPU (sd
, i
);
74 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
75 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
80 /* Read/write functions for system call interface. */
83 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
84 unsigned long taddr
, char *buf
, int bytes
)
86 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
87 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
89 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
90 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
94 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
95 unsigned long taddr
, const char *buf
, int bytes
)
97 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
98 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
100 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
101 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
102 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
105 /* Handle TRA and TIRA insns. */
107 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
109 SIM_DESC sd
= CPU_STATE (current_cpu
);
110 host_callback
*cb
= STATE_CALLBACK (sd
);
111 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
113 #ifdef SIM_HAVE_BREAKPOINTS
114 /* Check for breakpoints "owned" by the simulator first, regardless
116 if (num
== TRAP_BREAKPOINT
)
118 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
119 it doesn't return. Otherwise it returns and let's us try. */
120 sim_handle_breakpoint (sd
, current_cpu
, pc
);
125 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
127 frv_queue_software_interrupt (current_cpu
, num
);
136 CB_SYSCALL_INIT (&s
);
137 s
.func
= GET_H_GR (7);
138 s
.arg1
= GET_H_GR (8);
139 s
.arg2
= GET_H_GR (9);
140 s
.arg3
= GET_H_GR (10);
142 if (s
.func
== TARGET_SYS_exit
)
144 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
148 s
.p2
= (PTR
) current_cpu
;
149 s
.read_mem
= syscall_read_mem
;
150 s
.write_mem
= syscall_write_mem
;
152 SET_H_GR (8, s
.result
);
153 SET_H_GR (9, s
.result2
);
154 SET_H_GR (10, s
.errcode
);
158 case TRAP_BREAKPOINT
:
159 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
162 /* Add support for dumping registers, either at fixed traps, or all
163 unknown traps if configured with --enable-sim-trapdump. */
166 frv_queue_software_interrupt (current_cpu
, num
);
178 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
184 if (STATE_TEXT_SECTION (sd
)
185 && pc
>= STATE_TEXT_START (sd
)
186 && pc
< STATE_TEXT_END (sd
))
188 const char *pc_filename
= (const char *)0;
189 const char *pc_function
= (const char *)0;
190 unsigned int pc_linenum
= 0;
192 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
193 STATE_TEXT_SECTION (sd
),
194 (struct bfd_symbol
**) 0,
195 pc
- STATE_TEXT_START (sd
),
196 &pc_filename
, &pc_function
, &pc_linenum
)
197 && (pc_function
|| pc_filename
))
204 strcpy (p
, pc_function
);
209 char *q
= (char *) strrchr (pc_filename
, '/');
210 strcpy (p
, (q
) ? q
+1 : pc_filename
);
216 sprintf (p
, " line %d", pc_linenum
);
222 if ((p
+1) - buf
> sizeof (buf
))
228 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
229 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
231 for (i
= 0; i
< 64; i
+= 8)
233 long g0
= (long)GET_H_GR (i
);
234 long g1
= (long)GET_H_GR (i
+1);
235 long g2
= (long)GET_H_GR (i
+2);
236 long g3
= (long)GET_H_GR (i
+3);
237 long g4
= (long)GET_H_GR (i
+4);
238 long g5
= (long)GET_H_GR (i
+5);
239 long g6
= (long)GET_H_GR (i
+6);
240 long g7
= (long)GET_H_GR (i
+7);
242 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
244 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
245 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
248 for (i
= 0; i
< 64; i
+= 8)
250 long f0
= (long)GET_H_FR (i
);
251 long f1
= (long)GET_H_FR (i
+1);
252 long f2
= (long)GET_H_FR (i
+2);
253 long f3
= (long)GET_H_FR (i
+3);
254 long f4
= (long)GET_H_FR (i
+4);
255 long f5
= (long)GET_H_FR (i
+5);
256 long f6
= (long)GET_H_FR (i
+6);
257 long f7
= (long)GET_H_FR (i
+7);
259 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
261 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
262 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
266 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
267 (long)GET_H_SPR (272),
268 (long)GET_H_SPR (273),
269 (long)GET_H_SPR (256),
270 (long)GET_H_SPR (263));
277 /* Handle the MTRAP insn. */
279 frv_mtrap (SIM_CPU
*current_cpu
)
281 SIM_DESC sd
= CPU_STATE (current_cpu
);
283 /* Check the status of media exceptions in MSR0. */
284 SI msr
= GET_MSR (0);
285 if (GET_MSR_AOVF (msr
) || GET_MSR_MTT (msr
) && STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
286 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
289 /* Handle the BREAK insn. */
291 frv_break (SIM_CPU
*current_cpu
)
294 SIM_DESC sd
= CPU_STATE (current_cpu
);
296 #ifdef SIM_HAVE_BREAKPOINTS
297 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
298 it doesn't return. Otherwise it returns and let's us try. */
300 sim_handle_breakpoint (sd
, current_cpu
, pc
);
304 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
306 /* Invalidate the insn cache because the debugger will presumably
307 replace the breakpoint insn with the real one. */
308 #ifndef SIM_HAVE_BREAKPOINTS
311 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
314 frv_queue_break_interrupt (current_cpu
);
317 /* Return from trap. */
319 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
322 /* if (normal running mode and debug_field==0
326 else if (debug running mode and debug_field==1)
330 change to normal running mode
332 int psr_s
= GET_H_PSR_S ();
333 int psr_et
= GET_H_PSR_ET ();
335 /* Check for exceptions in the priority order listed in the FRV Architecture
339 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
342 SIM_DESC sd
= CPU_STATE (current_cpu
);
343 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
346 /* privileged_instruction interrupt will have already been queued by
347 frv_detect_insn_access_interrupts. */
352 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
355 SIM_DESC sd
= CPU_STATE (current_cpu
);
356 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
359 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
362 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
364 USI psr
= GET_PSR ();
365 /* Return from normal running state. */
366 new_pc
= GET_H_SPR (H_SPR_PCSR
);
368 SET_PSR_S (psr
, GET_PSR_PS (psr
));
369 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
371 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
373 USI psr
= GET_PSR ();
374 /* Return from debug state. */
375 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
376 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
377 SET_PSR_S (psr
, GET_H_BPSR_BS ());
378 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
379 CPU_DEBUG_STATE (current_cpu
) = 0;
387 /* Functions for handling non-excepting instruction side effects. */
388 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
390 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
391 if (control
->spr
[H_SPR_NECR
].implemented
)
394 USI necr
= GET_NECR ();
396 /* See if any NESRs are implemented. First need to check the validity of
398 if (! GET_NECR_VALID (necr
))
401 limit
= GET_NECR_NEN (necr
);
402 for (++current_index
; current_index
< limit
; ++current_index
)
404 SI nesr
= GET_NESR (current_index
);
405 if (! GET_NESR_VALID (nesr
))
406 return current_index
;
412 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
414 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
415 if (control
->spr
[H_SPR_NECR
].implemented
)
418 USI necr
= GET_NECR ();
420 /* See if any NESRs are implemented. First need to check the validity of
422 if (! GET_NECR_VALID (necr
))
425 limit
= GET_NECR_NEN (necr
);
426 for (++current_index
; current_index
< limit
; ++current_index
)
428 SI nesr
= GET_NESR (current_index
);
429 if (GET_NESR_VALID (nesr
))
430 return current_index
;
437 frvbf_check_non_excepting_load (
438 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
439 SI immediate_disp
, QI data_size
, BI is_float
442 BI rc
= 1; /* perform the load. */
443 SIM_DESC sd
= CPU_STATE (current_cpu
);
453 FRV_REGISTER_CONTROL
*control
;
455 SI address
= GET_H_GR (base_index
);
457 address
+= GET_H_GR (disp_index
);
459 address
+= immediate_disp
;
461 /* Check for interrupt factors. */
479 if (target_index
& 1)
485 if (target_index
& 3)
490 IADDR pc
= GET_H_PC ();
491 sim_engine_abort (sd
, current_cpu
, pc
,
492 "check_non_excepting_load: Incorrect data_size\n");
497 control
= CPU_REGISTER_CONTROL (current_cpu
);
498 if (control
->spr
[H_SPR_NECR
].implemented
)
501 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
506 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
509 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
510 if (ne_index
== NO_NESR
)
512 IADDR pc
= GET_H_PC ();
513 sim_engine_abort (sd
, current_cpu
, pc
,
514 "No available NESR register\n");
517 /* Fill in the basic fields of the NESR. */
518 nesr
= GET_NESR (ne_index
);
519 SET_NESR_VALID (nesr
);
521 SET_NESR_DRN (nesr
, target_index
);
522 SET_NESR_SIZE (nesr
, data_size
);
523 SET_NESR_NEAN (nesr
, ne_index
);
527 CLEAR_NESR_FR (nesr
);
529 /* Set the corresponding NEEAR. */
530 SET_NEEAR (ne_index
, address
);
532 SET_NESR_DAEC (nesr
, 0);
533 SET_NESR_REC (nesr
, 0);
534 SET_NESR_EC (nesr
, 0);
537 /* Set the NE flag corresponding to the target register if an interrupt
539 daec is not checked here yet, but is declared for future reference. */
541 NE_base
= H_SPR_FNER0
;
543 NE_base
= H_SPR_GNER0
;
545 GET_NE_FLAGS (NE_flags
, NE_base
);
548 SET_NE_FLAG (NE_flags
, target_index
);
550 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
555 SET_NE_FLAG (NE_flags
, target_index
);
557 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
561 SET_NESR (ne_index
, nesr
);
563 /* If no interrupt factor was detected then set the NE flag on the
564 target register if the NE flag on one of the input registers
566 if (! rec
&& ! ec
&& ! daec
)
568 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
570 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
573 SET_NE_FLAG (NE_flags
, target_index
);
574 rc
= 0; /* Do not perform the load. */
577 CLEAR_NE_FLAG (NE_flags
, target_index
);
580 SET_NE_FLAGS (NE_base
, NE_flags
);
582 return rc
; /* perform the load? */
585 /* Record state for media exception: media_cr_not_aligned. */
587 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
589 SIM_DESC sd
= CPU_STATE (current_cpu
);
591 /* On some machines this generates an illegal_instruction interrupt. */
592 switch (STATE_ARCHITECTURE (sd
)->mach
)
594 /* Note: there is a discrepancy between V2.2 of the FR400
595 instruction manual and the various FR4xx LSI specs. The former
596 claims that unaligned registers cause an mp_exception while the
597 latter say it's an illegal_instruction. The LSI specs appear
598 to be correct since MTT is fixed at 1. */
602 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
605 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
610 /* Record state for media exception: media_acc_not_aligned. */
612 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
614 SIM_DESC sd
= CPU_STATE (current_cpu
);
616 /* On some machines this generates an illegal_instruction interrupt. */
617 switch (STATE_ARCHITECTURE (sd
)->mach
)
619 /* See comment in frvbf_cr_not_aligned(). */
623 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
626 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
631 /* Record state for media exception: media_register_not_aligned. */
633 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
635 SIM_DESC sd
= CPU_STATE (current_cpu
);
637 /* On some machines this generates an illegal_instruction interrupt. */
638 switch (STATE_ARCHITECTURE (sd
)->mach
)
640 /* See comment in frvbf_cr_not_aligned(). */
644 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
647 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
652 /* Record state for media exception: media_overflow. */
654 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
656 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
659 /* Queue a division exception. */
661 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
662 int target_index
, int non_excepting
)
664 /* If there was an overflow and it is masked, then record it in
666 USI isr
= GET_ISR ();
667 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
669 dtt
&= ~FRV_DTT_OVERFLOW
;
673 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
677 /* Non excepting instruction, simply set the NE flag for the target
680 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
681 SET_NE_FLAG (NE_flags
, target_index
);
682 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
685 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
691 frvbf_check_recovering_store (
692 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
695 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
698 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
700 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
702 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
704 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
706 SI nesr
= GET_NESR (reg_ix
);
707 int nesr_drn
= GET_NESR_DRN (nesr
);
708 BI nesr_fr
= GET_NESR_FR (nesr
);
711 /* Invalidate cache block containing this address.
712 If we need to count cycles, then the cache operation will be
713 initiated from the model profiling functions.
714 See frvbf_model_.... */
717 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
718 CPU_LOAD_ADDRESS (current_cpu
) = address
;
721 frv_cache_invalidate (cache
, address
, 1/* flush */);
723 /* Copy the stored value to the register indicated by NESR.DRN. */
724 for (remain
= size
; remain
> 0; remain
-= 4)
729 value
= GET_H_FR (regno
);
731 value
= GET_H_GR (regno
);
746 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
749 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
755 break; /* Only consider the first matching register. */
757 } /* loop over active neear registers. */
761 frvbf_check_acc_range (SIM_CPU
*current_cpu
, SI regno
)
763 /* Only applicable to fr550 */
764 SIM_DESC sd
= CPU_STATE (current_cpu
);
765 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
768 /* On the fr550, media insns in slots 0 and 2 can only access
769 accumulators acc0-acc3. Insns in slots 1 and 3 can only access
770 accumulators acc4-acc7 */
771 switch (frv_current_fm_slot
)
776 return 1; /* all is ok */
781 return 1; /* all is ok */
785 /* The specified accumulator is out of range. Queue an illegal_instruction
787 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
792 frvbf_check_swap_address (SIM_CPU
*current_cpu
, SI address
)
794 /* Only applicable to fr550 */
795 SIM_DESC sd
= CPU_STATE (current_cpu
);
796 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
799 /* Adress must be aligned on a word boundary. */
801 frv_queue_data_access_exception_interrupt (current_cpu
);
805 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
809 /* Only implemented for full frv. */
810 SIM_DESC sd
= CPU_STATE (current_cpu
);
811 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
814 /* Clear the appropriate NESR and NEEAR registers. */
815 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
817 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
820 /* The register is available, now check if it is active. */
821 nesr
= GET_NESR (reg_ix
);
822 if (GET_NESR_FR (nesr
) == is_float
)
824 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
826 SET_NESR (reg_ix
, 0);
827 SET_NEEAR (reg_ix
, 0);
835 SIM_CPU
*current_cpu
,
845 GET_NE_FLAGS (NE_flags
, NE_base
);
846 if (target_index
>= 0)
847 CLEAR_NE_FLAG (NE_flags
, target_index
);
855 SET_NE_FLAGS (NE_base
, NE_flags
);
858 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
859 means to check for any register available. */
861 which_registers_available (
862 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
866 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
868 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
872 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
879 FRV_REGISTER_CONTROL
*control
;
881 /* Check for availability of the target register(s). */
882 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
885 /* Check to make sure that the target register is available. */
886 if (! frv_check_register_access (current_cpu
, target_index
,
887 hi_available
, lo_available
))
890 /* Determine whether we're working with GR or FR registers. */
892 NE_base
= H_SPR_FNER0
;
894 NE_base
= H_SPR_GNER0
;
896 /* Always clear the appropriate NE flags. */
897 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
900 /* Clear the appropriate NESR and NEEAR registers. */
901 control
= CPU_REGISTER_CONTROL (current_cpu
);
902 if (control
->spr
[H_SPR_NECR
].implemented
)
905 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
906 clear_nesr_neear (current_cpu
, target_index
, is_float
);
911 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
920 FRV_REGISTER_CONTROL
*control
;
922 /* Check for availability of the target register(s). */
923 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
926 /* Check to make sure that the target register is available. */
927 if (! frv_check_register_access (current_cpu
, target_index
,
928 hi_available
, lo_available
))
931 /* Determine whether we're working with GR or FR registers. */
933 NE_base
= H_SPR_FNER0
;
935 NE_base
= H_SPR_GNER0
;
937 /* Determine whether a ne exception is pending. */
938 GET_NE_FLAGS (NE_flags
, NE_base
);
939 if (target_index
>= 0)
940 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
944 hi_available
&& NE_flags
[0] != 0 || lo_available
&& NE_flags
[1] != 0;
947 /* Always clear the appropriate NE flags. */
948 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
951 control
= CPU_REGISTER_CONTROL (current_cpu
);
952 if (control
->spr
[H_SPR_NECR
].implemented
)
955 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
957 /* Clear the appropriate NESR and NEEAR registers. */
958 clear_nesr_neear (current_cpu
, target_index
, is_float
);
959 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
964 /* Generate the appropriate fp_exception(s) based on the given status code. */
966 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
968 struct frv_fp_exception_info fp_info
= {
969 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
973 (sim_fpu_status_invalid_snan
|
974 sim_fpu_status_invalid_qnan
|
975 sim_fpu_status_invalid_isi
|
976 sim_fpu_status_invalid_idi
|
977 sim_fpu_status_invalid_zdz
|
978 sim_fpu_status_invalid_imz
|
979 sim_fpu_status_invalid_cvi
|
980 sim_fpu_status_invalid_cmp
|
981 sim_fpu_status_invalid_sqrt
))
982 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
984 if (status
& sim_fpu_status_invalid_div0
)
985 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
987 if (status
& sim_fpu_status_inexact
)
988 fp_info
.fsr_mask
|= FSR_INEXACT
;
990 if (status
& sim_fpu_status_overflow
)
991 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
993 if (status
& sim_fpu_status_underflow
)
994 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
996 if (status
& sim_fpu_status_denorm
)
998 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
999 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
1002 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
1004 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
1005 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);