2 Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #define WANT_CPU frvbf
22 #define WANT_CPU_FRVBF
25 #include "targ-vals.h"
26 #include "cgen-engine.h"
31 #include "libiberty.h"
33 /* The semantic code invokes this for invalid (unrecognized) instructions. */
36 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
38 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
42 /* Process an address exception. */
45 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
46 unsigned int map
, int nr_bytes
, address_word addr
,
47 transfer_type transfer
, sim_core_signals sig
)
49 if (sig
== sim_core_unaligned_signal
)
51 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
)
52 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
54 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
58 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
62 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
65 if (current_cpu
!= NULL
)
66 CIA_SET (current_cpu
, cia
);
68 /* Invalidate the insn and data caches of all cpus. */
69 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
71 current_cpu
= STATE_CPU (sd
, i
);
72 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
73 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
78 /* Read/write functions for system call interface. */
81 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
82 unsigned long taddr
, char *buf
, int bytes
)
84 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
85 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
87 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
88 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
92 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
93 unsigned long taddr
, const char *buf
, int bytes
)
95 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
96 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
98 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
99 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
100 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
103 /* Handle TRA and TIRA insns. */
105 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
107 SIM_DESC sd
= CPU_STATE (current_cpu
);
108 host_callback
*cb
= STATE_CALLBACK (sd
);
109 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
111 #ifdef SIM_HAVE_BREAKPOINTS
112 /* Check for breakpoints "owned" by the simulator first, regardless
114 if (num
== TRAP_BREAKPOINT
)
116 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
117 it doesn't return. Otherwise it returns and let's us try. */
118 sim_handle_breakpoint (sd
, current_cpu
, pc
);
123 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
125 frv_queue_software_interrupt (current_cpu
, num
);
134 CB_SYSCALL_INIT (&s
);
135 s
.func
= GET_H_GR (7);
136 s
.arg1
= GET_H_GR (8);
137 s
.arg2
= GET_H_GR (9);
138 s
.arg3
= GET_H_GR (10);
140 if (s
.func
== TARGET_SYS_exit
)
142 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
146 s
.p2
= (PTR
) current_cpu
;
147 s
.read_mem
= syscall_read_mem
;
148 s
.write_mem
= syscall_write_mem
;
150 SET_H_GR (8, s
.result
);
151 SET_H_GR (9, s
.result2
);
152 SET_H_GR (10, s
.errcode
);
156 case TRAP_BREAKPOINT
:
157 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
160 /* Add support for dumping registers, either at fixed traps, or all
161 unknown traps if configured with --enable-sim-trapdump. */
164 frv_queue_software_interrupt (current_cpu
, num
);
176 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
182 if (STATE_TEXT_SECTION (sd
)
183 && pc
>= STATE_TEXT_START (sd
)
184 && pc
< STATE_TEXT_END (sd
))
186 const char *pc_filename
= (const char *)0;
187 const char *pc_function
= (const char *)0;
188 unsigned int pc_linenum
= 0;
190 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
191 STATE_TEXT_SECTION (sd
),
192 (struct symbol_cache_entry
**) 0,
193 pc
- STATE_TEXT_START (sd
),
194 &pc_filename
, &pc_function
, &pc_linenum
)
195 && (pc_function
|| pc_filename
))
202 strcpy (p
, pc_function
);
207 char *q
= (char *) strrchr (pc_filename
, '/');
208 strcpy (p
, (q
) ? q
+1 : pc_filename
);
214 sprintf (p
, " line %d", pc_linenum
);
220 if ((p
+1) - buf
> sizeof (buf
))
226 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
227 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
229 for (i
= 0; i
< 64; i
+= 8)
231 long g0
= (long)GET_H_GR (i
);
232 long g1
= (long)GET_H_GR (i
+1);
233 long g2
= (long)GET_H_GR (i
+2);
234 long g3
= (long)GET_H_GR (i
+3);
235 long g4
= (long)GET_H_GR (i
+4);
236 long g5
= (long)GET_H_GR (i
+5);
237 long g6
= (long)GET_H_GR (i
+6);
238 long g7
= (long)GET_H_GR (i
+7);
240 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
242 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
243 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
246 for (i
= 0; i
< 64; i
+= 8)
248 long f0
= (long)GET_H_FR (i
);
249 long f1
= (long)GET_H_FR (i
+1);
250 long f2
= (long)GET_H_FR (i
+2);
251 long f3
= (long)GET_H_FR (i
+3);
252 long f4
= (long)GET_H_FR (i
+4);
253 long f5
= (long)GET_H_FR (i
+5);
254 long f6
= (long)GET_H_FR (i
+6);
255 long f7
= (long)GET_H_FR (i
+7);
257 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
259 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
260 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
264 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
265 (long)GET_H_SPR (272),
266 (long)GET_H_SPR (273),
267 (long)GET_H_SPR (256),
268 (long)GET_H_SPR (263));
275 /* Handle the MTRAP insn. */
277 frv_mtrap (SIM_CPU
*current_cpu
)
279 /* Check the status of media exceptions in MSR0. */
280 SI msr
= GET_MSR (0);
281 if (GET_MSR_AOVF (msr
) || GET_MSR_MTT (msr
))
282 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
285 /* Handle the BREAK insn. */
287 frv_break (SIM_CPU
*current_cpu
)
290 SIM_DESC sd
= CPU_STATE (current_cpu
);
292 #ifdef SIM_HAVE_BREAKPOINTS
293 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
294 it doesn't return. Otherwise it returns and let's us try. */
296 sim_handle_breakpoint (sd
, current_cpu
, pc
);
300 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
302 /* Invalidate the insn cache because the debugger will presumably
303 replace the breakpoint insn with the real one. */
304 #ifndef SIM_HAVE_BREAKPOINTS
307 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
310 frv_queue_break_interrupt (current_cpu
);
313 /* Return from trap. */
315 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
318 /* if (normal running mode and debug_field==0
322 else if (debug running mode and debug_field==1)
326 change to normal running mode
328 int psr_s
= GET_H_PSR_S ();
329 int psr_et
= GET_H_PSR_ET ();
331 /* Check for exceptions in the priority order listed in the FRV Architecture
335 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
338 SIM_DESC sd
= CPU_STATE (current_cpu
);
339 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
342 /* privileged_instruction interrupt will have already been queued by
343 frv_detect_insn_access_interrupts. */
348 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
351 SIM_DESC sd
= CPU_STATE (current_cpu
);
352 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
355 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
358 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
360 USI psr
= GET_PSR ();
361 /* Return from normal running state. */
362 new_pc
= GET_H_SPR (H_SPR_PCSR
);
364 SET_PSR_S (psr
, GET_PSR_PS (psr
));
365 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
367 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
369 USI psr
= GET_PSR ();
370 /* Return from debug state. */
371 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
372 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
373 SET_PSR_S (psr
, GET_H_BPSR_BS ());
374 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
375 CPU_DEBUG_STATE (current_cpu
) = 0;
383 /* Functions for handling non-excepting instruction side effects. */
384 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
386 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
387 if (control
->spr
[H_SPR_NECR
].implemented
)
390 USI necr
= GET_NECR ();
392 /* See if any NESRs are implemented. First need to check the validity of
394 if (! GET_NECR_VALID (necr
))
397 limit
= GET_NECR_NEN (necr
);
398 for (++current_index
; current_index
< limit
; ++current_index
)
400 SI nesr
= GET_NESR (current_index
);
401 if (! GET_NESR_VALID (nesr
))
402 return current_index
;
408 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
410 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
411 if (control
->spr
[H_SPR_NECR
].implemented
)
414 USI necr
= GET_NECR ();
416 /* See if any NESRs are implemented. First need to check the validity of
418 if (! GET_NECR_VALID (necr
))
421 limit
= GET_NECR_NEN (necr
);
422 for (++current_index
; current_index
< limit
; ++current_index
)
424 SI nesr
= GET_NESR (current_index
);
425 if (GET_NESR_VALID (nesr
))
426 return current_index
;
433 frvbf_check_non_excepting_load (
434 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
435 SI immediate_disp
, QI data_size
, BI is_float
438 BI rc
= 1; /* perform the load. */
439 SIM_DESC sd
= CPU_STATE (current_cpu
);
449 FRV_REGISTER_CONTROL
*control
;
451 SI address
= GET_H_GR (base_index
);
453 address
+= GET_H_GR (disp_index
);
455 address
+= immediate_disp
;
457 /* Check for interrupt factors. */
475 if (target_index
& 1)
481 if (target_index
& 3)
486 IADDR pc
= GET_H_PC ();
487 sim_engine_abort (sd
, current_cpu
, pc
,
488 "check_non_excepting_load: Incorrect data_size\n");
493 control
= CPU_REGISTER_CONTROL (current_cpu
);
494 if (control
->spr
[H_SPR_NECR
].implemented
)
497 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
502 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
505 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
506 if (ne_index
== NO_NESR
)
508 IADDR pc
= GET_H_PC ();
509 sim_engine_abort (sd
, current_cpu
, pc
,
510 "No available NESR register\n");
513 /* Fill in the basic fields of the NESR. */
514 nesr
= GET_NESR (ne_index
);
515 SET_NESR_VALID (nesr
);
517 SET_NESR_DRN (nesr
, target_index
);
518 SET_NESR_SIZE (nesr
, data_size
);
519 SET_NESR_NEAN (nesr
, ne_index
);
523 CLEAR_NESR_FR (nesr
);
525 /* Set the corresponding NEEAR. */
526 SET_NEEAR (ne_index
, address
);
528 SET_NESR_DAEC (nesr
, 0);
529 SET_NESR_REC (nesr
, 0);
530 SET_NESR_EC (nesr
, 0);
533 /* Set the NE flag corresponding to the target register if an interrupt
535 daec is not checked here yet, but is declared for future reference. */
537 NE_base
= H_SPR_FNER0
;
539 NE_base
= H_SPR_GNER0
;
541 GET_NE_FLAGS (NE_flags
, NE_base
);
544 SET_NE_FLAG (NE_flags
, target_index
);
546 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
551 SET_NE_FLAG (NE_flags
, target_index
);
553 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
557 SET_NESR (ne_index
, nesr
);
559 /* If no interrupt factor was detected then set the NE flag on the
560 target register if the NE flag on one of the input registers
562 if (! rec
&& ! ec
&& ! daec
)
564 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
566 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
569 SET_NE_FLAG (NE_flags
, target_index
);
570 rc
= 0; /* Do not perform the load. */
573 CLEAR_NE_FLAG (NE_flags
, target_index
);
576 SET_NE_FLAGS (NE_base
, NE_flags
);
578 return rc
; /* perform the load? */
581 /* Record state for media exception: media_cr_not_aligned. */
583 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
585 SIM_DESC sd
= CPU_STATE (current_cpu
);
587 /* On the fr400 this generates an illegal_instruction interrupt. */
588 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
)
589 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
591 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
594 /* Record state for media exception: media_acc_not_aligned. */
596 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
598 SIM_DESC sd
= CPU_STATE (current_cpu
);
600 /* On the fr400 this generates an illegal_instruction interrupt. */
601 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
)
602 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
604 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
607 /* Record state for media exception: media_register_not_aligned. */
609 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
611 SIM_DESC sd
= CPU_STATE (current_cpu
);
613 /* On the fr400 this generates an illegal_instruction interrupt. */
614 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
)
615 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
617 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
620 /* Record state for media exception: media_overflow. */
622 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
624 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
627 /* Queue a division exception. */
629 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
630 int target_index
, int non_excepting
)
632 /* If there was an overflow and it is masked, then record it in
634 USI isr
= GET_ISR ();
635 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
637 dtt
&= ~FRV_DTT_OVERFLOW
;
641 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
645 /* Non excepting instruction, simply set the NE flag for the target
648 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
649 SET_NE_FLAG (NE_flags
, target_index
);
650 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
653 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
659 frvbf_check_recovering_store (
660 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
663 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
666 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
668 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
670 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
672 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
674 SI nesr
= GET_NESR (reg_ix
);
675 int nesr_drn
= GET_NESR_DRN (nesr
);
676 BI nesr_fr
= GET_NESR_FR (nesr
);
679 /* Invalidate cache block containing this address.
680 If we need to count cycles, then the cache operation will be
681 initiated from the model profiling functions.
682 See frvbf_model_.... */
685 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
686 CPU_LOAD_ADDRESS (current_cpu
) = address
;
689 frv_cache_invalidate (cache
, address
, 1/* flush */);
691 /* Copy the stored value to the register indicated by NESR.DRN. */
692 for (remain
= size
; remain
> 0; remain
-= 4)
697 value
= GET_H_FR (regno
);
699 value
= GET_H_GR (regno
);
714 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
717 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
723 break; /* Only consider the first matching register. */
725 } /* loop over active neear registers. */
729 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
733 /* Only implemented for full frv. */
734 SIM_DESC sd
= CPU_STATE (current_cpu
);
735 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
738 /* Clear the appropriate NESR and NEEAR registers. */
739 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
741 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
744 /* The register is available, now check if it is active. */
745 nesr
= GET_NESR (reg_ix
);
746 if (GET_NESR_FR (nesr
) == is_float
)
748 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
750 SET_NESR (reg_ix
, 0);
751 SET_NEEAR (reg_ix
, 0);
759 SIM_CPU
*current_cpu
,
769 GET_NE_FLAGS (NE_flags
, NE_base
);
770 if (target_index
>= 0)
771 CLEAR_NE_FLAG (NE_flags
, target_index
);
779 SET_NE_FLAGS (NE_base
, NE_flags
);
782 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
783 means to check for any register available. */
785 which_registers_available (
786 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
790 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
792 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
796 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
803 FRV_REGISTER_CONTROL
*control
;
805 /* Check for availability of the target register(s). */
806 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
809 /* Check to make sure that the target register is available. */
810 if (! frv_check_register_access (current_cpu
, target_index
,
811 hi_available
, lo_available
))
814 /* Determine whether we're working with GR or FR registers. */
816 NE_base
= H_SPR_FNER0
;
818 NE_base
= H_SPR_GNER0
;
820 /* Always clear the appropriate NE flags. */
821 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
824 /* Clear the appropriate NESR and NEEAR registers. */
825 control
= CPU_REGISTER_CONTROL (current_cpu
);
826 if (control
->spr
[H_SPR_NECR
].implemented
)
829 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
830 clear_nesr_neear (current_cpu
, target_index
, is_float
);
835 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
844 FRV_REGISTER_CONTROL
*control
;
846 /* Check for availability of the target register(s). */
847 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
850 /* Check to make sure that the target register is available. */
851 if (! frv_check_register_access (current_cpu
, target_index
,
852 hi_available
, lo_available
))
855 /* Determine whether we're working with GR or FR registers. */
857 NE_base
= H_SPR_FNER0
;
859 NE_base
= H_SPR_GNER0
;
861 /* Determine whether a ne exception is pending. */
862 GET_NE_FLAGS (NE_flags
, NE_base
);
863 if (target_index
>= 0)
864 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
868 hi_available
&& NE_flags
[0] != 0 || lo_available
&& NE_flags
[1] != 0;
871 /* Always clear the appropriate NE flags. */
872 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
875 control
= CPU_REGISTER_CONTROL (current_cpu
);
876 if (control
->spr
[H_SPR_NECR
].implemented
)
879 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
881 /* Clear the appropriate NESR and NEEAR registers. */
882 clear_nesr_neear (current_cpu
, target_index
, is_float
);
883 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
888 /* Generate the appropriate fp_exception(s) based on the given status code. */
890 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
892 struct frv_fp_exception_info fp_info
= {
893 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
897 (sim_fpu_status_invalid_snan
|
898 sim_fpu_status_invalid_qnan
|
899 sim_fpu_status_invalid_isi
|
900 sim_fpu_status_invalid_idi
|
901 sim_fpu_status_invalid_zdz
|
902 sim_fpu_status_invalid_imz
|
903 sim_fpu_status_invalid_cvi
|
904 sim_fpu_status_invalid_cmp
|
905 sim_fpu_status_invalid_sqrt
))
906 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
908 if (status
& sim_fpu_status_invalid_div0
)
909 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
911 if (status
& sim_fpu_status_inexact
)
912 fp_info
.fsr_mask
|= FSR_INEXACT
;
914 if (status
& sim_fpu_status_overflow
)
915 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
917 if (status
& sim_fpu_status_underflow
)
918 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
920 if (status
& sim_fpu_status_denorm
)
922 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
923 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
926 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
928 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
929 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);