0666f6c4cb8e5baad0bdd435bcec73fecea068e7
1 /* Simulator for the FT32 processor
3 Copyright (C) 2008-2015 Free Software Foundation, Inc.
4 Contributed by FTDI <support@ftdichip.com>
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
33 #include "sim-options.h"
35 #include "opcode/ft32.h"
38 * FT32 is a Harvard architecture: RAM and code occupy
39 * different address spaces.
41 * sim and gdb model FT32 memory by adding 0x800000 to RAM
42 * addresses. This means that sim/gdb can treat all addresses
45 * The address space looks like:
47 * 00000 start of code memory
48 * 3ffff end of code memory
53 #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
56 ft32_extract_unsigned_integer (unsigned char *addr
, int len
)
60 unsigned char *startaddr
= (unsigned char *) addr
;
61 unsigned char *endaddr
= startaddr
+ len
;
63 /* Start at the most significant end of the integer, and work towards
64 the least significant. */
67 for (p
= endaddr
; p
> startaddr
;)
68 retval
= (retval
<< 8) | * -- p
;
74 ft32_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
77 unsigned char *startaddr
= (unsigned char *)addr
;
78 unsigned char *endaddr
= startaddr
+ len
;
80 for (p
= startaddr
; p
< endaddr
; p
++)
88 * Align EA according to its size DW.
89 * The FT32 ignores the low bit of a 16-bit addresss,
90 * and the low two bits of a 32-bit address.
92 static uint32_t ft32_align (uint32_t dw
, uint32_t ea
)
108 /* Read an item from memory address EA, sized DW. */
110 ft32_read_item (SIM_DESC sd
, int dw
, uint32_t ea
)
112 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
113 address_word cia
= CIA_GET (cpu
);
117 ea
= ft32_align (dw
, ea
);
121 return sim_core_read_aligned_1 (cpu
, cia
, read_map
, ea
);
123 return sim_core_read_aligned_2 (cpu
, cia
, read_map
, ea
);
125 return sim_core_read_aligned_4 (cpu
, cia
, read_map
, ea
);
131 /* Write item V to memory address EA, sized DW. */
133 ft32_write_item (SIM_DESC sd
, int dw
, uint32_t ea
, uint32_t v
)
135 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
136 address_word cia
= CIA_GET (cpu
);
139 ea
= ft32_align (dw
, ea
);
143 sim_core_write_aligned_1 (cpu
, cia
, write_map
, ea
, v
);
146 sim_core_write_aligned_2 (cpu
, cia
, write_map
, ea
, v
);
149 sim_core_write_aligned_4 (cpu
, cia
, write_map
, ea
, v
);
157 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
159 static uint32_t cpu_mem_read (SIM_DESC sd
, uint32_t dw
, uint32_t ea
)
161 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
162 uint32_t insnpc
= cpu
->state
.pc
;
169 /* Simulate some IO devices */
173 /* Read the simulator cycle timer. */
174 return cpu
->state
.cycles
/ 100;
176 sim_io_eprintf (sd
, "Illegal IO read address %08x, pc %#x\n",
181 return ft32_read_item (sd
, dw
, RAM_BIAS
+ ea
);
184 static void cpu_mem_write (SIM_DESC sd
, uint32_t dw
, uint32_t ea
, uint32_t d
)
186 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
190 /* Simulate some IO devices */
198 /* Unlock the PM write port */
199 cpu
->state
.pm_unlock
= (d
== 0x1337f7d1);
202 /* Set the PM write address register */
203 cpu
->state
.pm_addr
= d
;
207 ft32_write_item (sd
, dw
, cpu
->state
.pm_addr
, d
);
211 sim_engine_halt (sd
, cpu
, NULL
, cpu
->state
.pc
, sim_exited
, cpu
->state
.regs
[0]);
214 sim_io_printf (sd
, "Debug write %08x\n", d
);
217 sim_io_eprintf (sd
, "Unknown IO write %08x to to %08x\n", d
, ea
);
221 ft32_write_item (sd
, dw
, RAM_BIAS
+ ea
, d
);
224 #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
225 #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
227 /* LSBS (n) is a mask of the least significant N bits. */
228 #define LSBS(n) ((1U << (n)) - 1)
230 static void ft32_push (SIM_DESC sd
, uint32_t v
)
232 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
233 cpu
->state
.regs
[FT32_HARD_SP
] -= 4;
234 cpu
->state
.regs
[FT32_HARD_SP
] &= 0xffff;
235 cpu_mem_write (sd
, 2, cpu
->state
.regs
[FT32_HARD_SP
], v
);
238 static uint32_t ft32_pop (SIM_DESC sd
)
240 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
241 uint32_t r
= cpu_mem_read (sd
, 2, cpu
->state
.regs
[FT32_HARD_SP
]);
242 cpu
->state
.regs
[FT32_HARD_SP
] += 4;
243 cpu
->state
.regs
[FT32_HARD_SP
] &= 0xffff;
247 /* Extract the low SIZ bits of N as an unsigned number. */
248 static int nunsigned (int siz
, int n
)
250 return n
& LSBS (siz
);
253 /* Extract the low SIZ bits of N as a signed number. */
254 static int nsigned (int siz
, int n
)
256 int shift
= (sizeof (int) * 8) - siz
;
257 return (n
<< shift
) >> shift
;
260 /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
261 static uint32_t ft32sdiv (uint32_t n
, uint32_t d
)
263 if (n
== 0x80000000UL
&& d
== 0xffffffffUL
)
266 return (uint32_t)((int)n
/ (int)d
);
269 /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
270 static uint32_t ft32smod (uint32_t n
, uint32_t d
)
272 if (n
== 0x80000000UL
&& d
== 0xffffffffUL
)
275 return (uint32_t)((int)n
% (int)d
);
278 /* Circular rotate right N by B bits. */
279 static uint32_t ror (uint32_t n
, uint32_t b
)
282 return (n
>> b
) | (n
<< (32 - b
));
285 /* Implement the BINS machine instruction.
286 See FT32 Programmer's Reference for details. */
287 static uint32_t bins (uint32_t d
, uint32_t f
, uint32_t len
, uint32_t pos
)
289 uint32_t bitmask
= LSBS (len
) << pos
;
290 return (d
& ~bitmask
) | ((f
<< pos
) & bitmask
);
293 /* Implement the FLIP machine instruction.
294 See FT32 Programmer's Reference for details. */
295 static uint32_t flip (uint32_t x
, uint32_t b
)
298 x
= (x
& 0x55555555) << 1 | (x
& 0xAAAAAAAA) >> 1;
300 x
= (x
& 0x33333333) << 2 | (x
& 0xCCCCCCCC) >> 2;
302 x
= (x
& 0x0F0F0F0F) << 4 | (x
& 0xF0F0F0F0) >> 4;
304 x
= (x
& 0x00FF00FF) << 8 | (x
& 0xFF00FF00) >> 8;
306 x
= (x
& 0x0000FFFF) << 16 | (x
& 0xFFFF0000) >> 16;
311 step_once (SIM_DESC sd
)
313 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
314 address_word cia
= CIA_GET (cpu
);
338 if (cpu
->state
.cycles
>= cpu
->state
.next_tick_cycle
)
340 cpu
->state
.next_tick_cycle
+= 100000;
341 ft32_push (sd
, cpu
->state
.pc
);
342 cpu
->state
.pc
= 12; /* interrupt 1. */
344 inst
= ft32_read_item (sd
, 2, cpu
->state
.pc
);
345 cpu
->state
.cycles
+= 1;
347 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
348 if (inst
== 0x00340002)
350 sim_engine_halt (sd
, cpu
, NULL
,
352 sim_stopped
, SIM_SIGTRAP
);
356 dw
= (inst
>> FT32_FLD_DW_BIT
) & LSBS (FT32_FLD_DW_SIZ
);
357 cb
= (inst
>> FT32_FLD_CB_BIT
) & LSBS (FT32_FLD_CB_SIZ
);
358 r_d
= (inst
>> FT32_FLD_R_D_BIT
) & LSBS (FT32_FLD_R_D_SIZ
);
359 cr
= (inst
>> FT32_FLD_CR_BIT
) & LSBS (FT32_FLD_CR_SIZ
);
360 cv
= (inst
>> FT32_FLD_CV_BIT
) & LSBS (FT32_FLD_CV_SIZ
);
361 bt
= (inst
>> FT32_FLD_BT_BIT
) & LSBS (FT32_FLD_BT_SIZ
);
362 r_1
= (inst
>> FT32_FLD_R_1_BIT
) & LSBS (FT32_FLD_R_1_SIZ
);
363 rimm
= (inst
>> FT32_FLD_RIMM_BIT
) & LSBS (FT32_FLD_RIMM_SIZ
);
364 r_2
= (inst
>> FT32_FLD_R_2_BIT
) & LSBS (FT32_FLD_R_2_SIZ
);
365 k20
= nsigned (20, (inst
>> FT32_FLD_K20_BIT
) & LSBS (FT32_FLD_K20_SIZ
));
366 pa
= (inst
>> FT32_FLD_PA_BIT
) & LSBS (FT32_FLD_PA_SIZ
);
367 aa
= (inst
>> FT32_FLD_AA_BIT
) & LSBS (FT32_FLD_AA_SIZ
);
368 k16
= (inst
>> FT32_FLD_K16_BIT
) & LSBS (FT32_FLD_K16_SIZ
);
369 k8
= nsigned (8, (inst
>> FT32_FLD_K8_BIT
) & LSBS (FT32_FLD_K8_SIZ
));
370 al
= (inst
>> FT32_FLD_AL_BIT
) & LSBS (FT32_FLD_AL_SIZ
);
372 r_1v
= cpu
->state
.regs
[r_1
];
373 rimmv
= (rimm
& 0x400) ? nsigned (10, rimm
) : cpu
->state
.regs
[rimm
& 0x1f];
375 bit_pos
= rimmv
& 31;
376 bit_len
= 0xf & (rimmv
>> 5);
380 upper
= (inst
>> 27);
382 insnpc
= cpu
->state
.pc
;
389 int take
= (cr
== 3) || ((1 & (cpu
->state
.regs
[28 + cr
] >> cb
)) == cv
);
392 cpu
->state
.cycles
+= 1;
394 ft32_push (sd
, cpu
->state
.pc
); /* this is a call. */
395 if (upper
== FT32_PAT_TOC
)
396 cpu
->state
.pc
= pa
<< 2;
398 cpu
->state
.pc
= cpu
->state
.regs
[r_2
];
399 if (cpu
->state
.pc
== 0x8)
411 case 0x0: result
= r_1v
+ rimmv
; break;
412 case 0x1: result
= ror (r_1v
, rimmv
); break;
413 case 0x2: result
= r_1v
- rimmv
; break;
414 case 0x3: result
= (r_1v
<< 10) | (1023 & rimmv
); break;
415 case 0x4: result
= r_1v
& rimmv
; break;
416 case 0x5: result
= r_1v
| rimmv
; break;
417 case 0x6: result
= r_1v
^ rimmv
; break;
418 case 0x7: result
= ~(r_1v
^ rimmv
); break;
419 case 0x8: result
= r_1v
<< rimmv
; break;
420 case 0x9: result
= r_1v
>> rimmv
; break;
421 case 0xa: result
= (int32_t)r_1v
>> rimmv
; break;
422 case 0xb: result
= bins (r_1v
, rimmv
>> 10, bit_len
, bit_pos
); break;
423 case 0xc: result
= nsigned (bit_len
, r_1v
>> bit_pos
); break;
424 case 0xd: result
= nunsigned (bit_len
, r_1v
>> bit_pos
); break;
425 case 0xe: result
= flip (r_1v
, rimmv
); break;
427 sim_io_eprintf (sd
, "Unhandled alu %#x\n", al
);
430 if (upper
== FT32_PAT_ALUOP
)
431 cpu
->state
.regs
[r_d
] = result
;
451 case 0: dwsiz
= 7; dwmask
= 0xffU
; break;
452 case 1: dwsiz
= 15; dwmask
= 0xffffU
; break;
453 case 2: dwsiz
= 31; dwmask
= 0xffffffffU
; break;
456 zero
= (0 == (result
& dwmask
));
457 sign
= 1 & (result
>> dwsiz
);
458 ahi
= 1 & (r_1v
>> dwsiz
);
459 bhi
= 1 & (rimmv
>> dwsiz
);
460 overflow
= (sign
!= ahi
) & (ahi
== !bhi
);
466 case 0x0: carry
= 1 & ((ra
+ rb
) >> bit
); break;
467 case 0x2: carry
= 1 & ((ra
- rb
) >> bit
); break;
468 default: carry
= 0; break;
470 above
= (!carry
& !zero
);
471 greater
= (sign
== overflow
) & !zero
;
472 greatereq
= (sign
== overflow
);
474 cpu
->state
.regs
[r_d
] = (
487 cpu
->state
.regs
[r_d
] = k20
;
491 cpu
->state
.regs
[r_d
] = ft32_read_item (sd
, dw
, pa
<< 2);
492 cpu
->state
.cycles
+= 1;
496 cpu
->state
.regs
[r_d
] = ft32_read_item (sd
, dw
, cpu
->state
.regs
[r_1
] + k8
);
497 cpu
->state
.cycles
+= 1;
501 cpu_mem_write (sd
, dw
, aa
, cpu
->state
.regs
[r_d
]);
505 cpu_mem_write (sd
, dw
, cpu
->state
.regs
[r_d
] + k8
, cpu
->state
.regs
[r_1
]);
509 cpu
->state
.regs
[r_d
] = cpu_mem_read (sd
, dw
, aa
);
510 cpu
->state
.cycles
+= 1;
514 cpu
->state
.regs
[r_d
] = cpu_mem_read (sd
, dw
, cpu
->state
.regs
[r_1
] + k8
);
515 cpu
->state
.cycles
+= 1;
521 tmp
= cpu_mem_read (sd
, dw
, aa
);
522 cpu_mem_write (sd
, dw
, aa
, cpu
->state
.regs
[r_d
]);
523 cpu
->state
.regs
[r_d
] = tmp
;
524 cpu
->state
.cycles
+= 1;
531 tmp
= cpu_mem_read (sd
, dw
, cpu
->state
.regs
[r_1
] + k8
);
532 cpu_mem_write (sd
, dw
, cpu
->state
.regs
[r_1
] + k8
, cpu
->state
.regs
[r_d
]);
533 cpu
->state
.regs
[r_d
] = tmp
;
534 cpu
->state
.cycles
+= 1;
539 ft32_push (sd
, r_1v
);
543 ft32_push (sd
, cpu
->state
.regs
[r_d
]);
544 cpu
->state
.regs
[r_d
] = cpu
->state
.regs
[FT32_HARD_SP
];
545 cpu
->state
.regs
[FT32_HARD_SP
] -= k16
;
546 cpu
->state
.regs
[FT32_HARD_SP
] &= 0xffff;
549 case FT32_PAT_UNLINK
:
550 cpu
->state
.regs
[FT32_HARD_SP
] = cpu
->state
.regs
[r_d
];
551 cpu
->state
.regs
[FT32_HARD_SP
] &= 0xffff;
552 cpu
->state
.regs
[r_d
] = ft32_pop (sd
);
556 cpu
->state
.cycles
+= 1;
557 cpu
->state
.regs
[r_d
] = ft32_pop (sd
);
560 case FT32_PAT_RETURN
:
561 cpu
->state
.pc
= ft32_pop (sd
);
568 cpu
->state
.regs
[r_d
] = r_1v
/ rimmv
;
571 cpu
->state
.regs
[r_d
] = r_1v
% rimmv
;
574 cpu
->state
.regs
[r_d
] = ft32sdiv (r_1v
, rimmv
);
577 cpu
->state
.regs
[r_d
] = ft32smod (r_1v
, rimmv
);
582 /* strcmp instruction. */
586 while ((GET_BYTE (a
+ i
) != 0) &&
587 (GET_BYTE (a
+ i
) == GET_BYTE (b
+ i
)))
589 cpu
->state
.regs
[r_d
] = GET_BYTE (a
+ i
) - GET_BYTE (b
+ i
);
595 /* memcpy instruction. */
597 uint32_t dst
= cpu
->state
.regs
[r_d
];
599 for (i
= 0; i
< rimmv
; i
++)
600 PUT_BYTE (dst
+ i
, GET_BYTE (src
+ i
));
605 /* strlen instruction. */
608 for (i
= 0; GET_BYTE (src
+ i
) != 0; i
++)
610 cpu
->state
.regs
[r_d
] = i
;
615 /* memset instruction. */
616 uint32_t dst
= cpu
->state
.regs
[r_d
];
618 for (i
= 0; i
< rimmv
; i
++)
619 PUT_BYTE (dst
+ i
, r_1v
);
623 cpu
->state
.regs
[r_d
] = r_1v
* rimmv
;
626 cpu
->state
.regs
[r_d
] = ((uint64_t)r_1v
* (uint64_t)rimmv
) >> 32;
630 /* stpcpy instruction. */
632 uint32_t dst
= cpu
->state
.regs
[r_d
];
634 for (i
= 0; GET_BYTE (src
+ i
) != 0; i
++)
635 PUT_BYTE (dst
+ i
, GET_BYTE (src
+ i
));
636 PUT_BYTE (dst
+ i
, 0);
637 cpu
->state
.regs
[r_d
] = dst
+ i
;
642 /* streamout instruction. */
644 uint32_t src
= cpu
->state
.regs
[r_1
];
645 for (i
= 0; i
< rimmv
; i
+= (1 << dw
))
649 cpu
->state
.regs
[r_d
],
650 cpu_mem_read (sd
, dw
, src
));
656 sim_io_eprintf (sd
, "Unhandled ffu %#x at %08x\n", al
, insnpc
);
662 sim_io_eprintf (sd
, "Unhandled pattern %d at %08x\n", upper
, insnpc
);
672 sim_engine_run (SIM_DESC sd
,
673 int next_cpu_nr
, /* ignore */
674 int nr_cpus
, /* ignore */
675 int siggnal
) /* ignore */
679 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
681 cpu
= STATE_CPU (sd
, 0);
686 if (sim_events_tick (sd
))
687 sim_events_process (sd
);
692 ft32_lookup_register (SIM_CPU
*cpu
, int nr
)
694 /* Handle the register number translation here.
695 * Sim registers are 0-31.
696 * Other tools (gcc, gdb) use:
703 if ((nr
< 0) || (nr
> 32))
705 sim_io_eprintf (CPU_STATE (cpu
), "unknown register %i\n", nr
);
712 return &cpu
->state
.regs
[FT32_HARD_FP
];
714 return &cpu
->state
.regs
[FT32_HARD_SP
];
716 return &cpu
->state
.regs
[FT32_HARD_CC
];
718 return &cpu
->state
.pc
;
720 return &cpu
->state
.regs
[nr
- 2];
725 ft32_reg_store (SIM_CPU
*cpu
,
727 unsigned char *memory
,
730 if (0 <= rn
&& rn
<= 32)
733 *ft32_lookup_register (cpu
, rn
) = ft32_extract_unsigned_integer (memory
, 4);
742 ft32_reg_fetch (SIM_CPU
*cpu
,
744 unsigned char *memory
,
747 if (0 <= rn
&& rn
<= 32)
750 ft32_store_unsigned_integer (memory
, 4, *ft32_lookup_register (cpu
, rn
));
759 ft32_pc_get (SIM_CPU
*cpu
)
765 ft32_pc_set (SIM_CPU
*cpu
, sim_cia newpc
)
767 cpu
->state
.pc
= newpc
;
770 /* Cover function of sim_state_free to free the cpu buffers as well. */
773 free_state (SIM_DESC sd
)
775 if (STATE_MODULES (sd
) != NULL
)
776 sim_module_uninstall (sd
);
777 sim_cpu_free_all (sd
);
782 sim_open (SIM_OPEN_KIND kind
,
789 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
791 /* The cpu data is kept in a separately allocated chunk of memory. */
792 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
798 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
804 /* getopt will print the error message so we just have to exit if this fails.
805 FIXME: Hmmm... in the case of gdb we need getopt to call
807 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
813 /* Allocate external memory if none specified by user.
814 Use address 4 here in case the user wanted address 0 unmapped. */
815 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
817 sim_do_command (sd
, "memory region 0x00000000,0x40000");
818 sim_do_command (sd
, "memory region 0x800000,0x10000");
821 /* Check for/establish the reference program image. */
822 if (sim_analyze_program (sd
,
823 (STATE_PROG_ARGV (sd
) != NULL
824 ? *STATE_PROG_ARGV (sd
)
825 : NULL
), abfd
) != SIM_RC_OK
)
831 /* Configure/verify the target byte order and other runtime
832 configuration options. */
833 if (sim_config (sd
) != SIM_RC_OK
)
839 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
845 /* CPU specific initialization. */
846 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
848 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
850 CPU_REG_FETCH (cpu
) = ft32_reg_fetch
;
851 CPU_REG_STORE (cpu
) = ft32_reg_store
;
852 CPU_PC_FETCH (cpu
) = ft32_pc_get
;
853 CPU_PC_STORE (cpu
) = ft32_pc_set
;
860 sim_close (SIM_DESC sd
, int quitting
)
862 sim_module_uninstall (sd
);
866 sim_create_inferior (SIM_DESC sd
,
872 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
876 addr
= bfd_get_start_address (abfd
);
880 if (STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
)
882 freeargv (STATE_PROG_ARGV (sd
));
883 STATE_PROG_ARGV (sd
) = dupargv (argv
);
885 cpu
->state
.regs
[FT32_HARD_SP
] = addr
;
886 cpu
->state
.num_i
= 0;
887 cpu
->state
.cycles
= 0;
888 cpu
->state
.next_tick_cycle
= 100000;
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