2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 static void set_simcache_size (SIM_DESC
, int);
55 #define X(op, size) (op * 4 + size)
57 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
59 #define h8_opcodes ops
61 #include "opcode/h8300.h"
63 /* CPU data object: */
66 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
68 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
70 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
71 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
73 cpu
->delayed_branch
= 0;
78 /* Initialize local simulator state. */
80 sd
->sim_cache_size
= 0;
86 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
92 h8_get_pc (SIM_DESC sd
)
94 return (STATE_CPU (sd
, 0)) -> pc
;
98 h8_set_pc (SIM_DESC sd
, unsigned int val
)
100 (STATE_CPU (sd
, 0)) -> pc
= val
;
104 h8_get_ccr (SIM_DESC sd
)
106 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
110 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
112 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
116 h8_get_exr (SIM_DESC sd
)
118 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
122 h8_set_exr (SIM_DESC sd
, unsigned int val
)
124 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
128 h8_get_sbr (SIM_DESC sd
)
130 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
134 h8_set_sbr (SIM_DESC sd
, int val
)
136 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
140 h8_get_vbr (SIM_DESC sd
)
142 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
146 h8_set_vbr (SIM_DESC sd
, int val
)
148 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
152 h8_get_cache_top (SIM_DESC sd
)
154 return sd
-> cache_top
;
158 h8_set_cache_top (SIM_DESC sd
, int val
)
160 sd
-> cache_top
= val
;
164 h8_get_mask (SIM_DESC sd
)
166 return (STATE_CPU (sd
, 0)) -> mask
;
170 h8_set_mask (SIM_DESC sd
, int val
)
172 (STATE_CPU (sd
, 0)) -> mask
= val
;
176 h8_get_exception (SIM_DESC sd
)
178 return (STATE_CPU (sd
, 0)) -> exception
;
182 h8_set_exception (SIM_DESC sd
, int val
)
184 (STATE_CPU (sd
, 0)) -> exception
= val
;
187 static enum h8300_sim_state
188 h8_get_state (SIM_DESC sd
)
194 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
200 h8_get_cycles (SIM_DESC sd
)
202 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
206 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
208 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
212 h8_get_insts (SIM_DESC sd
)
214 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
218 h8_set_insts (SIM_DESC sd
, unsigned int val
)
220 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
224 h8_get_ticks (SIM_DESC sd
)
226 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
230 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
232 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
236 h8_get_mach (SIM_DESC sd
)
238 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
242 h8_set_mach (SIM_DESC sd
, unsigned int val
)
244 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
248 h8_get_macl (SIM_DESC sd
)
250 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
254 h8_set_macl (SIM_DESC sd
, unsigned int val
)
256 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
260 h8_get_compiles (SIM_DESC sd
)
262 return sd
-> compiles
;
266 h8_increment_compiles (SIM_DESC sd
)
271 static unsigned int *
272 h8_get_reg_buf (SIM_DESC sd
)
274 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
278 h8_get_reg (SIM_DESC sd
, int regnum
)
280 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
284 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
286 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
291 h8_get_stats (SIM_DESC sd
, int idx
)
293 return sd
-> stats
[idx
];
297 h8_increment_stats (SIM_DESC sd
, int idx
)
303 static unsigned short *
304 h8_get_cache_idx_buf (SIM_DESC sd
)
306 return sd
-> cache_idx
;
310 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
312 sd
-> cache_idx
= ptr
;
315 static unsigned short
316 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
318 if (idx
> sd
->memory_size
)
319 return (unsigned short) -1;
320 return sd
-> cache_idx
[idx
];
324 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
326 sd
-> cache_idx
[idx
] = (unsigned short) val
;
329 static unsigned char *
330 h8_get_memory_buf (SIM_DESC sd
)
332 return (STATE_CPU (sd
, 0)) -> memory
;
336 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
338 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
342 h8_get_memory (SIM_DESC sd
, int idx
)
344 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
348 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
350 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
353 static unsigned char *
354 h8_get_eightbit_buf (SIM_DESC sd
)
356 return (STATE_CPU (sd
, 0)) -> eightbit
;
360 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
362 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
366 h8_get_eightbit (SIM_DESC sd
, int idx
)
368 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
372 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
374 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
378 h8_get_delayed_branch (SIM_DESC sd
)
380 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
384 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
386 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
390 h8_get_command_line (SIM_DESC sd
)
392 return (STATE_CPU (sd
, 0)) -> command_line
;
396 h8_set_command_line (SIM_DESC sd
, char ** val
)
398 (STATE_CPU (sd
, 0)) -> command_line
= val
;
402 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
404 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
408 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
410 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
413 /* MAC Saturation Mode */
415 h8_get_macS (SIM_DESC sd
)
417 return (STATE_CPU (sd
, 0)) -> macS
;
421 h8_set_macS (SIM_DESC sd
, int val
)
423 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
428 h8_get_macZ (SIM_DESC sd
)
430 return (STATE_CPU (sd
, 0)) -> macZ
;
434 h8_set_macZ (SIM_DESC sd
, int val
)
436 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
439 /* MAC Negative Flag */
441 h8_get_macN (SIM_DESC sd
)
443 return (STATE_CPU (sd
, 0)) -> macN
;
447 h8_set_macN (SIM_DESC sd
, int val
)
449 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
452 /* MAC Overflow Flag */
454 h8_get_macV (SIM_DESC sd
)
456 return (STATE_CPU (sd
, 0)) -> macV
;
460 h8_set_macV (SIM_DESC sd
, int val
)
462 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
465 /* End CPU data object. */
467 /* The rate at which to call the host's poll_quit callback. */
469 enum { POLL_QUIT_INTERVAL
= 0x80000 };
471 #define LOW_BYTE(x) ((x) & 0xff)
472 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
473 #define P(X, Y) ((X << 8) | Y)
482 #define I (intMaskBit != 0)
484 #define BUILDSR(SD) \
485 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
486 | (N << 3) | (Z << 2) | (V << 1) | C)
489 /* Get Status Register (flags). */ \
490 c = (h8_get_ccr (sd) >> 0) & 1; \
491 v = (h8_get_ccr (sd) >> 1) & 1; \
492 nz = !((h8_get_ccr (sd) >> 2) & 1); \
493 n = (h8_get_ccr (sd) >> 3) & 1; \
494 u = (h8_get_ccr (sd) >> 4) & 1; \
495 h = (h8_get_ccr (sd) >> 5) & 1; \
496 ui = ((h8_get_ccr (sd) >> 6) & 1); \
497 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
500 #ifdef __CHAR_IS_SIGNED__
501 #define SEXTCHAR(x) ((char) (x))
505 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
508 #define UEXTCHAR(x) ((x) & 0xff)
509 #define UEXTSHORT(x) ((x) & 0xffff)
510 #define SEXTSHORT(x) ((short) (x))
514 int h8300_normal_mode
= 0;
517 static int memory_size
;
522 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
544 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
549 /* Simulate an indirection / dereference.
550 return 0 for success, -1 for failure.
554 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
556 if (val
== NULL
) /* Paranoia. */
562 if (rn
== ZERO_REGNUM
)
563 *val
= X (OP_IMM
, SP
);
565 *val
= X (OP_REG
, SP
);
568 *val
= X (OP_MEM
, SP
);
571 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
580 if (h8300smode
&& !h8300_normal_mode
)
582 else if (h8300hmode
&& !h8300_normal_mode
)
589 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
591 int cst
[3] = {0, 0, 0};
592 int reg
[3] = {0, 0, 0};
593 int rdisp
[3] = {0, 0, 0};
595 const struct h8_opcode
*q
;
600 /* Find the exact opcode/arg combo. */
601 for (q
= h8_opcodes
; q
->name
; q
++)
603 const op_type
*nib
= q
->data
.nib
;
604 unsigned int len
= 0;
606 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
607 (q
->available
== AV_H8S
&& !h8300smode
) ||
608 (q
->available
== AV_H8H
&& !h8300hmode
))
611 cst
[0] = cst
[1] = cst
[2] = 0;
612 reg
[0] = reg
[1] = reg
[2] = 0;
613 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
617 op_type looking_for
= *nib
;
618 int thisnib
= data
[len
/ 2];
620 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
621 opnum
= ((looking_for
& OP3
) ? 2 :
622 (looking_for
& DST
) ? 1 : 0);
624 if (looking_for
< 16 && looking_for
>= 0)
626 if (looking_for
!= thisnib
)
631 if (looking_for
& B31
)
633 if (!((thisnib
& 0x8) != 0))
636 looking_for
= (op_type
) (looking_for
& ~B31
);
639 else if (looking_for
& B30
)
641 if (!((thisnib
& 0x8) == 0))
644 looking_for
= (op_type
) (looking_for
& ~B30
);
647 if (looking_for
& B21
)
649 if (!((thisnib
& 0x4) != 0))
652 looking_for
= (op_type
) (looking_for
& ~B21
);
655 else if (looking_for
& B20
)
657 if (!((thisnib
& 0x4) == 0))
660 looking_for
= (op_type
) (looking_for
& ~B20
);
663 if (looking_for
& B11
)
665 if (!((thisnib
& 0x2) != 0))
668 looking_for
= (op_type
) (looking_for
& ~B11
);
671 else if (looking_for
& B10
)
673 if (!((thisnib
& 0x2) == 0))
676 looking_for
= (op_type
) (looking_for
& ~B10
);
679 if (looking_for
& B01
)
681 if (!((thisnib
& 0x1) != 0))
684 looking_for
= (op_type
) (looking_for
& ~B01
);
687 else if (looking_for
& B00
)
689 if (!((thisnib
& 0x1) == 0))
692 looking_for
= (op_type
) (looking_for
& ~B00
);
695 if (looking_for
& IGNORE
)
697 /* Hitachi has declared that IGNORE must be zero. */
701 else if ((looking_for
& MODE
) == DATA
)
703 ; /* Skip embedded data. */
705 else if ((looking_for
& MODE
) == DBIT
)
707 /* Exclude adds/subs by looking at bit 0 and 2, and
708 make sure the operand size, either w or l,
709 matches by looking at bit 1. */
710 if ((looking_for
& 7) != (thisnib
& 7))
713 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
715 else if ((looking_for
& MODE
) == REG
||
716 (looking_for
& MODE
) == LOWREG
||
717 (looking_for
& MODE
) == IND
||
718 (looking_for
& MODE
) == PREINC
||
719 (looking_for
& MODE
) == POSTINC
||
720 (looking_for
& MODE
) == PREDEC
||
721 (looking_for
& MODE
) == POSTDEC
)
723 reg
[opnum
] = thisnib
;
725 else if (looking_for
& CTRL
)
728 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
729 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
730 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
731 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
732 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
733 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
735 if (((looking_for
& MODE
) == CCR_EXR
&&
736 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
737 ((looking_for
& MODE
) == VBR_SBR
&&
738 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
739 ((looking_for
& MODE
) == MACREG
&&
740 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
742 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
743 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
744 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
747 reg
[opnum
] = thisnib
;
749 else if ((looking_for
& MODE
) == ABS
)
751 /* Absolute addresses are unsigned. */
752 switch (looking_for
& SIZE
)
755 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
759 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
763 (data
[len
/ 2 + 0] << 24) +
764 (data
[len
/ 2 + 1] << 16) +
765 (data
[len
/ 2 + 2] << 8) +
769 printf ("decode: bad size ABS: %d\n",
770 (looking_for
& SIZE
));
774 else if ((looking_for
& MODE
) == DISP
||
775 (looking_for
& MODE
) == PCREL
||
776 (looking_for
& MODE
) == INDEXB
||
777 (looking_for
& MODE
) == INDEXW
||
778 (looking_for
& MODE
) == INDEXL
)
780 switch (looking_for
& SIZE
)
783 cst
[opnum
] = thisnib
& 3;
786 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
789 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
790 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
793 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
797 (data
[len
/ 2 + 0] << 24) +
798 (data
[len
/ 2 + 1] << 16) +
799 (data
[len
/ 2 + 2] << 8) +
803 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
804 (looking_for
& SIZE
));
808 else if ((looking_for
& SIZE
) == L_16
||
809 (looking_for
& SIZE
) == L_16U
)
811 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
812 /* Immediates are always unsigned. */
813 if ((looking_for
& SIZE
) != L_16U
&&
814 (looking_for
& MODE
) != IMM
)
815 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
817 else if (looking_for
& ABSJMP
)
819 switch (looking_for
& SIZE
) {
821 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
825 (data
[len
/ 2 + 0] << 24) +
826 (data
[len
/ 2 + 1] << 16) +
827 (data
[len
/ 2 + 2] << 8) +
831 printf ("decode: bad size ABSJMP: %d\n",
832 (looking_for
& SIZE
));
836 else if ((looking_for
& MODE
) == MEMIND
)
838 cst
[opnum
] = data
[1];
840 else if ((looking_for
& MODE
) == VECIND
)
842 if(h8300_normal_mode
)
843 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
845 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
846 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
848 else if ((looking_for
& SIZE
) == L_32
)
853 (data
[i
+ 0] << 24) |
854 (data
[i
+ 1] << 16) |
858 else if ((looking_for
& SIZE
) == L_24
)
863 (data
[i
+ 0] << 16) |
867 else if (looking_for
& DISPREG
)
869 rdisp
[opnum
] = thisnib
& 0x7;
871 else if ((looking_for
& MODE
) == KBIT
)
888 else if ((looking_for
& SIZE
) == L_8
)
890 if ((looking_for
& MODE
) == ABS
)
892 /* Will be combined with contents of SBR_REGNUM
893 by fetch (). For all modes except h8sx, this
894 will always contain the value 0xFFFFFF00. */
895 cst
[opnum
] = data
[len
/ 2] & 0xff;
899 cst
[opnum
] = data
[len
/ 2] & 0xff;
902 else if ((looking_for
& SIZE
) == L_2
)
904 cst
[opnum
] = thisnib
& 3;
906 else if ((looking_for
& SIZE
) == L_3
||
907 (looking_for
& SIZE
) == L_3NZ
)
909 cst
[opnum
] = thisnib
& 7;
910 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
913 else if ((looking_for
& SIZE
) == L_4
)
915 cst
[opnum
] = thisnib
& 15;
917 else if ((looking_for
& SIZE
) == L_5
)
919 cst
[opnum
] = data
[len
/ 2] & 0x1f;
921 else if (looking_for
== E
)
926 /* Fill in the args. */
928 const op_type
*args
= q
->args
.nib
;
933 nargs
< 3 && *args
!= E
;
939 opnum
= ((x
& OP3
) ? 2 :
948 if ((x
& MODE
) == IMM
||
949 (x
& MODE
) == KBIT
||
952 /* Use the instruction to determine
954 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
955 p
->literal
= cst
[opnum
];
957 else if ((x
& MODE
) == CONST_2
||
958 (x
& MODE
) == CONST_4
||
959 (x
& MODE
) == CONST_8
||
960 (x
& MODE
) == CONST_16
)
962 /* Use the instruction to determine
964 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
966 case CONST_2
: p
->literal
= 2; break;
967 case CONST_4
: p
->literal
= 4; break;
968 case CONST_8
: p
->literal
= 8; break;
969 case CONST_16
: p
->literal
= 16; break;
972 else if ((x
& MODE
) == REG
)
974 p
->type
= X (OP_REG
, bitfrom (x
));
977 else if ((x
& MODE
) == LOWREG
)
979 p
->type
= X (OP_LOWREG
, bitfrom (x
));
982 else if ((x
& MODE
) == PREINC
)
984 /* Use the instruction to determine
986 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
987 p
->reg
= reg
[opnum
] & 0x7;
989 else if ((x
& MODE
) == POSTINC
)
991 /* Use the instruction to determine
993 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
994 p
->reg
= reg
[opnum
] & 0x7;
996 else if ((x
& MODE
) == PREDEC
)
998 /* Use the instruction to determine
1000 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
1001 p
->reg
= reg
[opnum
] & 0x7;
1003 else if ((x
& MODE
) == POSTDEC
)
1005 /* Use the instruction to determine
1006 the operand size. */
1007 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
1008 p
->reg
= reg
[opnum
] & 0x7;
1010 else if ((x
& MODE
) == IND
)
1012 /* Note: an indirect is transformed into
1013 a displacement of zero.
1015 /* Use the instruction to determine
1016 the operand size. */
1017 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1018 p
->reg
= reg
[opnum
] & 0x7;
1020 if (OP_KIND (q
->how
) == O_JSR
||
1021 OP_KIND (q
->how
) == O_JMP
)
1022 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1025 else if ((x
& MODE
) == ABS
)
1027 /* Note: a 16 or 32 bit ABS is transformed into a
1028 displacement from pseudo-register ZERO_REGNUM,
1029 which is always zero. An 8 bit ABS becomes
1030 a displacement from SBR_REGNUM.
1032 /* Use the instruction to determine
1033 the operand size. */
1034 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1035 p
->literal
= cst
[opnum
];
1037 /* 8-bit ABS is displacement from SBR.
1038 16 and 32-bit ABS are displacement from ZERO.
1039 (SBR will always be zero except for h8/sx)
1041 if ((x
& SIZE
) == L_8
)
1042 p
->reg
= SBR_REGNUM
;
1044 p
->reg
= ZERO_REGNUM
;;
1046 else if ((x
& MODE
) == MEMIND
||
1047 (x
& MODE
) == VECIND
)
1049 /* Size doesn't matter. */
1050 p
->type
= X (OP_MEM
, SB
);
1051 p
->literal
= cst
[opnum
];
1052 if (OP_KIND (q
->how
) == O_JSR
||
1053 OP_KIND (q
->how
) == O_JMP
)
1054 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1057 else if ((x
& MODE
) == PCREL
)
1059 /* Size doesn't matter. */
1060 p
->type
= X (OP_PCREL
, SB
);
1061 p
->literal
= cst
[opnum
];
1063 else if (x
& ABSJMP
)
1065 p
->type
= X (OP_IMM
, SP
);
1066 p
->literal
= cst
[opnum
];
1068 else if ((x
& MODE
) == INDEXB
)
1070 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1071 p
->literal
= cst
[opnum
];
1072 p
->reg
= rdisp
[opnum
];
1074 else if ((x
& MODE
) == INDEXW
)
1076 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1077 p
->literal
= cst
[opnum
];
1078 p
->reg
= rdisp
[opnum
];
1080 else if ((x
& MODE
) == INDEXL
)
1082 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1083 p
->literal
= cst
[opnum
];
1084 p
->reg
= rdisp
[opnum
];
1086 else if ((x
& MODE
) == DISP
)
1088 /* Yuck -- special for mova args. */
1089 if (strncmp (q
->name
, "mova", 4) == 0 &&
1092 /* Mova can have a DISP2 dest, with an
1093 INDEXB or INDEXW src. The multiplier
1094 for the displacement value is determined
1095 by the src operand, not by the insn. */
1097 switch (OP_KIND (dst
->src
.type
))
1100 p
->type
= X (OP_DISP
, SB
);
1101 p
->literal
= cst
[opnum
];
1104 p
->type
= X (OP_DISP
, SW
);
1105 p
->literal
= cst
[opnum
] * 2;
1113 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1114 p
->literal
= cst
[opnum
];
1115 /* DISP2 is special. */
1116 if ((x
& SIZE
) == L_2
)
1117 switch (OP_SIZE (q
->how
))
1120 case SW
: p
->literal
*= 2; break;
1121 case SL
: p
->literal
*= 4; break;
1124 p
->reg
= rdisp
[opnum
];
1131 p
->type
= X (OP_CCR
, SB
);
1134 p
->type
= X (OP_EXR
, SB
);
1137 p
->type
= X (OP_MACH
, SL
);
1140 p
->type
= X (OP_MACL
, SL
);
1143 p
->type
= X (OP_VBR
, SL
);
1146 p
->type
= X (OP_SBR
, SL
);
1150 else if ((x
& MODE
) == CCR
)
1154 else if ((x
& MODE
) == EXR
)
1159 printf ("Hmmmm 0x%x...\n", x
);
1165 /* Unary operators: treat src and dst as equivalent. */
1166 if (dst
->dst
.type
== -1)
1167 dst
->dst
= dst
->src
;
1168 if (dst
->src
.type
== -1)
1169 dst
->src
= dst
->dst
;
1171 dst
->opcode
= q
->how
;
1172 dst
->cycles
= q
->time
;
1174 /* And jsr's to these locations are turned into
1177 if (OP_KIND (dst
->opcode
) == O_JSR
)
1179 switch (dst
->src
.literal
)
1182 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1185 dst
->opcode
= O (O_SYS_READ
, SB
);
1188 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1191 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1194 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1197 dst
->opcode
= O (O_SYS_STAT
, SB
);
1200 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1203 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1206 /* End of Processing for system calls. */
1209 dst
->next_pc
= addr
+ len
/ 2;
1213 printf ("Don't understand 0x%x \n", looking_for
);
1224 /* Fell off the end. */
1225 dst
->opcode
= O (O_ILL
, SB
);
1229 compile (SIM_DESC sd
, int pc
)
1233 /* Find the next cache entry to use. */
1234 idx
= h8_get_cache_top (sd
) + 1;
1235 h8_increment_compiles (sd
);
1236 if (idx
>= sd
->sim_cache_size
)
1240 h8_set_cache_top (sd
, idx
);
1242 /* Throw away its old meaning. */
1243 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1245 /* Set to new address. */
1246 sd
->sim_cache
[idx
].oldpc
= pc
;
1248 /* Fill in instruction info. */
1249 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1251 /* Point to new cache entry. */
1252 h8_set_cache_idx (sd
, pc
, idx
);
1256 static unsigned char *breg
[32];
1257 static unsigned short *wreg
[16];
1258 static unsigned int *lreg
[18];
1260 #define GET_B_REG(X) *(breg[X])
1261 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1262 #define GET_W_REG(X) *(wreg[X])
1263 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1264 #define GET_L_REG(X) h8_get_reg (sd, X)
1265 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1267 #define GET_MEMORY_L(X) \
1268 ((X) < memory_size \
1269 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1270 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1271 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1272 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1273 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1274 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1276 #define GET_MEMORY_W(X) \
1277 ((X) < memory_size \
1278 ? ((h8_get_memory (sd, (X)+0) << 8) \
1279 | (h8_get_memory (sd, (X)+1) << 0)) \
1280 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1281 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1284 #define GET_MEMORY_B(X) \
1285 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1286 : (h8_get_eightbit (sd, (X) & 0xff)))
1288 #define SET_MEMORY_L(X, Y) \
1289 { register unsigned char *_p; register int __y = (Y); \
1290 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1291 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1292 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1293 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1296 #define SET_MEMORY_W(X, Y) \
1297 { register unsigned char *_p; register int __y = (Y); \
1298 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1299 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1300 _p[0] = __y >> 8; _p[1] = __y; \
1303 #define SET_MEMORY_B(X, Y) \
1304 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1305 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1307 /* Simulate a memory fetch.
1308 Return 0 for success, -1 for failure.
1312 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1315 int abs
= arg
->literal
;
1320 return -1; /* Paranoia. */
1324 /* Indexed register plus displacement mode:
1326 This new family of addressing modes are similar to OP_DISP
1327 (register plus displacement), with two differences:
1328 1) INDEXB uses only the least significant byte of the register,
1329 INDEXW uses only the least significant word, and
1330 INDEXL uses the entire register (just like OP_DISP).
1332 2) The displacement value in abs is multiplied by two
1333 for SW-sized operations, and by four for SL-size.
1335 This gives nine possible variations.
1338 case X (OP_INDEXB
, SB
):
1339 case X (OP_INDEXB
, SW
):
1340 case X (OP_INDEXB
, SL
):
1341 case X (OP_INDEXW
, SB
):
1342 case X (OP_INDEXW
, SW
):
1343 case X (OP_INDEXW
, SL
):
1344 case X (OP_INDEXL
, SB
):
1345 case X (OP_INDEXL
, SW
):
1346 case X (OP_INDEXL
, SL
):
1348 switch (OP_KIND (arg
->type
)) {
1349 case OP_INDEXB
: t
&= 0xff; break;
1350 case OP_INDEXW
: t
&= 0xffff; break;
1354 switch (OP_SIZE (arg
->type
)) {
1356 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1359 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1362 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1367 case X (OP_LOWREG
, SB
):
1368 *val
= GET_L_REG (rn
) & 0xff;
1370 case X (OP_LOWREG
, SW
):
1371 *val
= GET_L_REG (rn
) & 0xffff;
1374 case X (OP_REG
, SB
): /* Register direct, byte. */
1375 *val
= GET_B_REG (rn
);
1377 case X (OP_REG
, SW
): /* Register direct, word. */
1378 *val
= GET_W_REG (rn
);
1380 case X (OP_REG
, SL
): /* Register direct, long. */
1381 *val
= GET_L_REG (rn
);
1383 case X (OP_IMM
, SB
): /* Immediate, byte. */
1384 case X (OP_IMM
, SW
): /* Immediate, word. */
1385 case X (OP_IMM
, SL
): /* Immediate, long. */
1388 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1390 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1396 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1398 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1404 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1406 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1413 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1415 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1421 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1423 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1429 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1431 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1438 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1439 t
= GET_L_REG (rn
) - 1;
1441 t
&= h8_get_mask (sd
);
1442 *val
= GET_MEMORY_B (t
);
1445 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1446 t
= GET_L_REG (rn
) - 2;
1448 t
&= h8_get_mask (sd
);
1449 *val
= GET_MEMORY_W (t
);
1452 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1453 t
= GET_L_REG (rn
) - 4;
1455 t
&= h8_get_mask (sd
);
1456 *val
= GET_MEMORY_L (t
);
1459 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1460 t
= GET_L_REG (rn
) + 1;
1462 t
&= h8_get_mask (sd
);
1463 *val
= GET_MEMORY_B (t
);
1466 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1467 t
= GET_L_REG (rn
) + 2;
1469 t
&= h8_get_mask (sd
);
1470 *val
= GET_MEMORY_W (t
);
1473 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1474 t
= GET_L_REG (rn
) + 4;
1476 t
&= h8_get_mask (sd
);
1477 *val
= GET_MEMORY_L (t
);
1480 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1481 t
= GET_L_REG (rn
) + abs
;
1482 t
&= h8_get_mask (sd
);
1483 *val
= GET_MEMORY_B (t
);
1486 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1487 t
= GET_L_REG (rn
) + abs
;
1488 t
&= h8_get_mask (sd
);
1489 *val
= GET_MEMORY_W (t
);
1492 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1493 t
= GET_L_REG (rn
) + abs
;
1494 t
&= h8_get_mask (sd
);
1495 *val
=GET_MEMORY_L (t
);
1498 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1499 t
= GET_MEMORY_L (abs
);
1500 t
&= h8_get_mask (sd
);
1504 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1505 t
= GET_MEMORY_W (abs
);
1506 t
&= h8_get_mask (sd
);
1510 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1511 case X (OP_PCREL
, SW
):
1512 case X (OP_PCREL
, SL
):
1513 case X (OP_PCREL
, SN
):
1517 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1519 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1522 return 0; /* Success. */
1528 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1530 return fetch_1 (sd
, arg
, val
, 0);
1533 /* Fetch which will be followed by a store to the same location.
1534 The difference being that we don't want to do a post-increment
1535 or post-decrement at this time: we'll do it when we store. */
1538 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1540 return fetch_1 (sd
, arg
, val
, 1);
1543 /* Simulate a memory store.
1544 Return 0 for success, -1 for failure.
1548 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1551 int abs
= arg
->literal
;
1556 /* Indexed register plus displacement mode:
1558 This new family of addressing modes are similar to OP_DISP
1559 (register plus displacement), with two differences:
1560 1) INDEXB uses only the least significant byte of the register,
1561 INDEXW uses only the least significant word, and
1562 INDEXL uses the entire register (just like OP_DISP).
1564 2) The displacement value in abs is multiplied by two
1565 for SW-sized operations, and by four for SL-size.
1567 This gives nine possible variations.
1570 case X (OP_INDEXB
, SB
):
1571 case X (OP_INDEXB
, SW
):
1572 case X (OP_INDEXB
, SL
):
1573 case X (OP_INDEXW
, SB
):
1574 case X (OP_INDEXW
, SW
):
1575 case X (OP_INDEXW
, SL
):
1576 case X (OP_INDEXL
, SB
):
1577 case X (OP_INDEXL
, SW
):
1578 case X (OP_INDEXL
, SL
):
1580 switch (OP_KIND (arg
->type
)) {
1581 case OP_INDEXB
: t
&= 0xff; break;
1582 case OP_INDEXW
: t
&= 0xffff; break;
1586 switch (OP_SIZE (arg
->type
)) {
1588 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1591 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1594 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1599 case X (OP_REG
, SB
): /* Register direct, byte. */
1602 case X (OP_REG
, SW
): /* Register direct, word. */
1605 case X (OP_REG
, SL
): /* Register direct, long. */
1609 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1614 t
&= h8_get_mask (sd
);
1615 SET_MEMORY_B (t
, n
);
1618 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1623 t
&= h8_get_mask (sd
);
1624 SET_MEMORY_W (t
, n
);
1627 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1632 t
&= h8_get_mask (sd
);
1633 SET_MEMORY_L (t
, n
);
1636 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1641 t
&= h8_get_mask (sd
);
1642 SET_MEMORY_B (t
, n
);
1645 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1650 t
&= h8_get_mask (sd
);
1651 SET_MEMORY_W (t
, n
);
1654 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1659 t
&= h8_get_mask (sd
);
1660 SET_MEMORY_L (t
, n
);
1663 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1665 SET_L_REG (rn
, t
- 1);
1666 t
&= h8_get_mask (sd
);
1667 SET_MEMORY_B (t
, n
);
1670 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1672 SET_L_REG (rn
, t
- 2);
1673 t
&= h8_get_mask (sd
);
1674 SET_MEMORY_W (t
, n
);
1677 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1679 SET_L_REG (rn
, t
- 4);
1680 t
&= h8_get_mask (sd
);
1681 SET_MEMORY_L (t
, n
);
1684 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1686 SET_L_REG (rn
, t
+ 1);
1687 t
&= h8_get_mask (sd
);
1688 SET_MEMORY_B (t
, n
);
1691 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1693 SET_L_REG (rn
, t
+ 2);
1694 t
&= h8_get_mask (sd
);
1695 SET_MEMORY_W (t
, n
);
1698 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1700 SET_L_REG (rn
, t
+ 4);
1701 t
&= h8_get_mask (sd
);
1702 SET_MEMORY_L (t
, n
);
1705 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1706 t
= GET_L_REG (rn
) + abs
;
1707 t
&= h8_get_mask (sd
);
1708 SET_MEMORY_B (t
, n
);
1711 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1712 t
= GET_L_REG (rn
) + abs
;
1713 t
&= h8_get_mask (sd
);
1714 SET_MEMORY_W (t
, n
);
1717 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1718 t
= GET_L_REG (rn
) + abs
;
1719 t
&= h8_get_mask (sd
);
1720 SET_MEMORY_L (t
, n
);
1724 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1725 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1726 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1728 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1737 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1739 return store_1 (sd
, arg
, n
, 0);
1742 /* Store which follows a fetch from the same location.
1743 The difference being that we don't want to do a pre-increment
1744 or pre-decrement at this time: it was already done when we fetched. */
1747 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1749 return store_1 (sd
, arg
, n
, 1);
1763 /* Flag to be set whenever a new SIM_DESC object is created. */
1764 static int init_pointers_needed
= 1;
1767 init_pointers (SIM_DESC sd
)
1769 if (init_pointers_needed
)
1775 if (h8300smode
&& !h8300_normal_mode
)
1776 memory_size
= H8300S_MSIZE
;
1777 else if (h8300hmode
&& !h8300_normal_mode
)
1778 memory_size
= H8300H_MSIZE
;
1780 memory_size
= H8300_MSIZE
;
1781 /* `msize' must be a power of two. */
1782 if ((memory_size
& (memory_size
- 1)) != 0)
1784 (*sim_callback
->printf_filtered
)
1786 "init_pointers: bad memory size %d, defaulting to %d.\n",
1787 memory_size
, memory_size
= H8300S_MSIZE
);
1790 if (h8_get_memory_buf (sd
))
1791 free (h8_get_memory_buf (sd
));
1792 if (h8_get_cache_idx_buf (sd
))
1793 free (h8_get_cache_idx_buf (sd
));
1794 if (h8_get_eightbit_buf (sd
))
1795 free (h8_get_eightbit_buf (sd
));
1797 h8_set_memory_buf (sd
, (unsigned char *)
1798 calloc (sizeof (char), memory_size
));
1799 h8_set_cache_idx_buf (sd
, (unsigned short *)
1800 calloc (sizeof (short), memory_size
));
1801 sd
->memory_size
= memory_size
;
1802 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1804 h8_set_mask (sd
, memory_size
- 1);
1806 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1808 for (i
= 0; i
< 8; i
++)
1810 /* FIXME: rewrite using local buffer. */
1811 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1812 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1813 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1814 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1815 h8_set_reg (sd
, i
, 0x00112233);
1830 wreg
[i
] = wreg
[i
+ 8] = 0;
1844 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1845 (*sim_callback
->printf_filtered
) (sim_callback
,
1846 "init_pointers: internal error.\n");
1848 h8_set_reg (sd
, i
, 0);
1849 lreg
[i
] = h8_get_reg_buf (sd
) + i
;
1852 /* Note: sim uses pseudo-register ZERO as a zero register. */
1853 lreg
[ZERO_REGNUM
] = h8_get_reg_buf (sd
) + ZERO_REGNUM
;
1854 init_pointers_needed
= 0;
1856 /* Initialize the seg registers. */
1858 set_simcache_size (sd
, CSIZE
);
1862 /* Grotty global variable for use by control_c signal handler. */
1863 static SIM_DESC control_c_sim_desc
;
1868 sim_engine_set_run_state (control_c_sim_desc
, sim_stopped
, SIGINT
);
1872 sim_stop (SIM_DESC sd
)
1874 /* FIXME: use a real signal value. */
1875 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
1879 #define OBITOP(name, f, s, op) \
1880 case O (name, SB): \
1885 if (fetch (sd, &code->dst, &ea)) \
1887 if (fetch (sd, &code->src, &tmp)) \
1889 m = 1 << (tmp & 7); \
1892 if (store (sd, &code->dst,ea)) \
1898 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1903 int tick_start
= get_now ();
1912 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1915 enum sim_stop reason
;
1920 control_c_sim_desc
= sd
;
1921 prev
= signal (SIGINT
, control_c
);
1925 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
1929 sim_engine_set_run_state (sd
, sim_running
, 0);
1932 pc
= h8_get_pc (sd
);
1934 /* The PC should never be odd. */
1937 sim_engine_set_run_state (sd
, sim_stopped
, SIGBUS
);
1941 /* Get Status Register (flags). */
1944 if (h8300smode
) /* Get exr. */
1946 trace
= (h8_get_exr (sd
) >> 7) & 1;
1947 intMask
= h8_get_exr (sd
) & 7;
1950 oldmask
= h8_get_mask (sd
);
1951 if (!h8300hmode
|| h8300_normal_mode
)
1952 h8_set_mask (sd
, 0xffff);
1955 unsigned short cidx
;
1959 cidx
= h8_get_cache_idx (sd
, pc
);
1960 if (cidx
== (unsigned short) -1 ||
1961 cidx
>= sd
->sim_cache_size
)
1964 code
= sd
->sim_cache
+ cidx
;
1969 printf ("%x %d %s\n", pc
, code
->opcode
,
1970 code
->op
? code
->op
->name
: "**");
1972 h8_increment_stats (sd
, code
->opcode
);
1977 cycles
+= code
->cycles
;
1981 switch (code
->opcode
)
1985 * This opcode is a fake for when we get to an
1986 * instruction which hasnt been compiled
1992 case O (O_MOVAB
, SL
):
1993 case O (O_MOVAW
, SL
):
1994 case O (O_MOVAL
, SL
):
1995 /* 1) Evaluate 2nd argument (dst).
1996 2) Mask / zero extend according to whether 1st argument (src)
1997 is INDEXB, INDEXW, or INDEXL.
1998 3) Left-shift the result by 0, 1 or 2, according to size of mova
1999 (mova/b, mova/w, mova/l).
2000 4) Add literal value of 1st argument (src).
2001 5) Store result in 3rd argument (op3).
2004 /* Alas, since this is the only instruction with 3 arguments,
2005 decode doesn't handle them very well. Some fix-up is required.
2007 a) The size of dst is determined by whether src is
2008 INDEXB or INDEXW. */
2010 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
2011 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
2012 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
2013 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
2015 /* b) If op3 == null, then this is the short form of the insn.
2016 Dst is the dispreg of src, and op3 is the 32-bit form
2017 of the same register.
2020 if (code
->op3
.type
== 0)
2022 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
2023 We get to compose dst and op3 as follows:
2025 op3 is a 32-bit register, ID == src.reg.
2026 dst is the same register, but 8 or 16 bits
2027 depending on whether src is INDEXB or INDEXW.
2030 code
->op3
.type
= X (OP_REG
, SL
);
2031 code
->op3
.reg
= code
->src
.reg
;
2032 code
->op3
.literal
= 0;
2034 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
2036 code
->dst
.type
= X (OP_REG
, SB
);
2037 code
->dst
.reg
= code
->op3
.reg
+ 8;
2040 code
->dst
.type
= X (OP_REG
, SW
);
2043 if (fetch (sd
, &code
->dst
, &ea
))
2046 switch (OP_KIND (code
->src
.type
)) {
2047 case OP_INDEXB
: ea
= ea
& 0xff; break;
2048 case OP_INDEXW
: ea
= ea
& 0xffff; break;
2049 case OP_INDEXL
: break;
2050 default: goto illegal
;
2053 switch (code
->opcode
) {
2054 case O (O_MOVAB
, SL
): break;
2055 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
2056 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
2057 default: goto illegal
;
2060 ea
= ea
+ code
->src
.literal
;
2062 if (store (sd
, &code
->op3
, ea
))
2067 case O (O_SUBX
, SB
): /* subx, extended sub */
2068 if (fetch2 (sd
, &code
->dst
, &rd
))
2070 if (fetch (sd
, &code
->src
, &ea
))
2076 case O (O_SUBX
, SW
): /* subx, extended sub */
2077 if (fetch2 (sd
, &code
->dst
, &rd
))
2079 if (fetch (sd
, &code
->src
, &ea
))
2085 case O (O_SUBX
, SL
): /* subx, extended sub */
2086 if (fetch2 (sd
, &code
->dst
, &rd
))
2088 if (fetch (sd
, &code
->src
, &ea
))
2094 case O (O_ADDX
, SB
): /* addx, extended add */
2095 if (fetch2 (sd
, &code
->dst
, &rd
))
2097 if (fetch (sd
, &code
->src
, &ea
))
2103 case O (O_ADDX
, SW
): /* addx, extended add */
2104 if (fetch2 (sd
, &code
->dst
, &rd
))
2106 if (fetch (sd
, &code
->src
, &ea
))
2112 case O (O_ADDX
, SL
): /* addx, extended add */
2113 if (fetch2 (sd
, &code
->dst
, &rd
))
2115 if (fetch (sd
, &code
->src
, &ea
))
2121 case O (O_SUB
, SB
): /* sub.b */
2122 /* Fetch rd and ea. */
2123 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2129 case O (O_SUB
, SW
): /* sub.w */
2130 /* Fetch rd and ea. */
2131 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2137 case O (O_SUB
, SL
): /* sub.l */
2138 /* Fetch rd and ea. */
2139 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2145 case O (O_NEG
, SB
): /* neg.b */
2147 if (fetch2 (sd
, &code
->src
, &ea
))
2154 case O (O_NEG
, SW
): /* neg.w */
2156 if (fetch2 (sd
, &code
->src
, &ea
))
2163 case O (O_NEG
, SL
): /* neg.l */
2165 if (fetch2 (sd
, &code
->src
, &ea
))
2172 case O (O_ADD
, SB
): /* add.b */
2173 if (fetch2 (sd
, &code
->dst
, &rd
))
2175 if (fetch (sd
, &code
->src
, &ea
))
2180 case O (O_ADD
, SW
): /* add.w */
2181 if (fetch2 (sd
, &code
->dst
, &rd
))
2183 if (fetch (sd
, &code
->src
, &ea
))
2188 case O (O_ADD
, SL
): /* add.l */
2189 if (fetch2 (sd
, &code
->dst
, &rd
))
2191 if (fetch (sd
, &code
->src
, &ea
))
2196 case O (O_AND
, SB
): /* and.b */
2197 /* Fetch rd and ea. */
2198 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2203 case O (O_AND
, SW
): /* and.w */
2204 /* Fetch rd and ea. */
2205 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2210 case O (O_AND
, SL
): /* and.l */
2211 /* Fetch rd and ea. */
2212 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2217 case O (O_OR
, SB
): /* or.b */
2218 /* Fetch rd and ea. */
2219 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2224 case O (O_OR
, SW
): /* or.w */
2225 /* Fetch rd and ea. */
2226 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2231 case O (O_OR
, SL
): /* or.l */
2232 /* Fetch rd and ea. */
2233 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2238 case O (O_XOR
, SB
): /* xor.b */
2239 /* Fetch rd and ea. */
2240 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2245 case O (O_XOR
, SW
): /* xor.w */
2246 /* Fetch rd and ea. */
2247 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2252 case O (O_XOR
, SL
): /* xor.l */
2253 /* Fetch rd and ea. */
2254 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2260 if (fetch (sd
, &code
->src
, &res
))
2262 if (store (sd
, &code
->dst
, res
))
2264 goto just_flags_log8
;
2266 if (fetch (sd
, &code
->src
, &res
))
2268 if (store (sd
, &code
->dst
, res
))
2270 goto just_flags_log16
;
2272 if (fetch (sd
, &code
->src
, &res
))
2274 if (store (sd
, &code
->dst
, res
))
2276 goto just_flags_log32
;
2278 case O (O_MOVMD
, SB
): /* movmd.b */
2285 rd
= GET_MEMORY_B (GET_L_REG (5));
2286 SET_MEMORY_B (GET_L_REG (6), rd
);
2287 SET_L_REG (5, GET_L_REG (5) + 1);
2288 SET_L_REG (6, GET_L_REG (6) + 1);
2293 case O (O_MOVMD
, SW
): /* movmd.w */
2300 rd
= GET_MEMORY_W (GET_L_REG (5));
2301 SET_MEMORY_W (GET_L_REG (6), rd
);
2302 SET_L_REG (5, GET_L_REG (5) + 2);
2303 SET_L_REG (6, GET_L_REG (6) + 2);
2308 case O (O_MOVMD
, SL
): /* movmd.l */
2315 rd
= GET_MEMORY_L (GET_L_REG (5));
2316 SET_MEMORY_L (GET_L_REG (6), rd
);
2317 SET_L_REG (5, GET_L_REG (5) + 4);
2318 SET_L_REG (6, GET_L_REG (6) + 4);
2323 case O (O_MOVSD
, SB
): /* movsd.b */
2324 /* This instruction implements strncpy, with a conditional branch.
2325 r4 contains n, r5 contains src, and r6 contains dst.
2326 The 16-bit displacement operand is added to the pc
2327 if and only if the end of string is reached before
2328 n bytes are transferred. */
2330 ea
= GET_L_REG (4) & 0xffff;
2336 rd
= GET_MEMORY_B (GET_L_REG (5));
2337 SET_MEMORY_B (GET_L_REG (6), rd
);
2338 SET_L_REG (5, GET_L_REG (5) + 1);
2339 SET_L_REG (6, GET_L_REG (6) + 1);
2346 case O (O_EEPMOV
, SB
): /* eepmov.b */
2347 case O (O_EEPMOV
, SW
): /* eepmov.w */
2348 if (h8300hmode
|| h8300smode
)
2350 register unsigned char *_src
, *_dst
;
2351 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2352 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2353 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2355 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2356 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2357 : h8_get_eightbit_buf (sd
) +
2358 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2359 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2361 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2364 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2365 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2366 : h8_get_eightbit_buf (sd
) +
2367 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2369 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2371 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2374 memcpy (_dst
, _src
, count
);
2376 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2377 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2378 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2379 ((code
->opcode
== O (O_EEPMOV
, SW
))
2380 ? (~0xffff) : (~0xff)));
2381 cycles
+= 2 * count
;
2386 case O (O_ADDS
, SL
): /* adds (.l) */
2388 * This insn only uses register operands, but still
2389 * it would be cleaner to use fetch and store... */
2390 SET_L_REG (code
->dst
.reg
,
2391 GET_L_REG (code
->dst
.reg
)
2392 + code
->src
.literal
);
2396 case O (O_SUBS
, SL
): /* subs (.l) */
2398 * This insn only uses register operands, but still
2399 * it would be cleaner to use fetch and store... */
2400 SET_L_REG (code
->dst
.reg
,
2401 GET_L_REG (code
->dst
.reg
)
2402 - code
->src
.literal
);
2405 case O (O_CMP
, SB
): /* cmp.b */
2406 if (fetch (sd
, &code
->dst
, &rd
))
2408 if (fetch (sd
, &code
->src
, &ea
))
2412 goto just_flags_alu8
;
2414 case O (O_CMP
, SW
): /* cmp.w */
2415 if (fetch (sd
, &code
->dst
, &rd
))
2417 if (fetch (sd
, &code
->src
, &ea
))
2421 goto just_flags_alu16
;
2423 case O (O_CMP
, SL
): /* cmp.l */
2424 if (fetch (sd
, &code
->dst
, &rd
))
2426 if (fetch (sd
, &code
->src
, &ea
))
2430 goto just_flags_alu32
;
2432 case O (O_DEC
, SB
): /* dec.b */
2434 * This insn only uses register operands, but still
2435 * it would be cleaner to use fetch and store... */
2436 rd
= GET_B_REG (code
->src
.reg
);
2439 SET_B_REG (code
->src
.reg
, res
);
2440 goto just_flags_inc8
;
2442 case O (O_DEC
, SW
): /* dec.w */
2444 * This insn only uses register operands, but still
2445 * it would be cleaner to use fetch and store... */
2446 rd
= GET_W_REG (code
->dst
.reg
);
2447 ea
= -code
->src
.literal
;
2449 SET_W_REG (code
->dst
.reg
, res
);
2450 goto just_flags_inc16
;
2452 case O (O_DEC
, SL
): /* dec.l */
2454 * This insn only uses register operands, but still
2455 * it would be cleaner to use fetch and store... */
2456 rd
= GET_L_REG (code
->dst
.reg
);
2457 ea
= -code
->src
.literal
;
2459 SET_L_REG (code
->dst
.reg
, res
);
2460 goto just_flags_inc32
;
2462 case O (O_INC
, SB
): /* inc.b */
2464 * This insn only uses register operands, but still
2465 * it would be cleaner to use fetch and store... */
2466 rd
= GET_B_REG (code
->src
.reg
);
2469 SET_B_REG (code
->src
.reg
, res
);
2470 goto just_flags_inc8
;
2472 case O (O_INC
, SW
): /* inc.w */
2474 * This insn only uses register operands, but still
2475 * it would be cleaner to use fetch and store... */
2476 rd
= GET_W_REG (code
->dst
.reg
);
2477 ea
= code
->src
.literal
;
2479 SET_W_REG (code
->dst
.reg
, res
);
2480 goto just_flags_inc16
;
2482 case O (O_INC
, SL
): /* inc.l */
2484 * This insn only uses register operands, but still
2485 * it would be cleaner to use fetch and store... */
2486 rd
= GET_L_REG (code
->dst
.reg
);
2487 ea
= code
->src
.literal
;
2489 SET_L_REG (code
->dst
.reg
, res
);
2490 goto just_flags_inc32
;
2492 case O (O_LDC
, SB
): /* ldc.b */
2493 if (fetch (sd
, &code
->src
, &res
))
2497 case O (O_LDC
, SW
): /* ldc.w */
2498 if (fetch (sd
, &code
->src
, &res
))
2501 /* Word operand, value from MSB, must be shifted. */
2505 case O (O_LDC
, SL
): /* ldc.l */
2506 if (fetch (sd
, &code
->src
, &res
))
2508 switch (code
->dst
.type
) {
2509 case X (OP_SBR
, SL
):
2510 h8_set_sbr (sd
, res
);
2512 case X (OP_VBR
, SL
):
2513 h8_set_vbr (sd
, res
);
2520 case O (O_STC
, SW
): /* stc.w */
2521 case O (O_STC
, SB
): /* stc.b */
2522 if (code
->src
.type
== X (OP_CCR
, SB
))
2525 res
= h8_get_ccr (sd
);
2527 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2530 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2531 res
= h8_get_exr (sd
);
2536 /* Word operand, value to MSB, must be shifted. */
2537 if (code
->opcode
== X (O_STC
, SW
))
2539 if (store (sd
, &code
->dst
, res
))
2542 case O (O_STC
, SL
): /* stc.l */
2543 switch (code
->src
.type
) {
2544 case X (OP_SBR
, SL
):
2545 res
= h8_get_sbr (sd
);
2547 case X (OP_VBR
, SL
):
2548 res
= h8_get_vbr (sd
);
2553 if (store (sd
, &code
->dst
, res
))
2557 case O (O_ANDC
, SB
): /* andc.b */
2558 if (code
->dst
.type
== X (OP_CCR
, SB
))
2561 rd
= h8_get_ccr (sd
);
2563 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2566 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2567 rd
= h8_get_exr (sd
);
2571 ea
= code
->src
.literal
;
2575 case O (O_ORC
, SB
): /* orc.b */
2576 if (code
->dst
.type
== X (OP_CCR
, SB
))
2579 rd
= h8_get_ccr (sd
);
2581 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2584 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2585 rd
= h8_get_exr (sd
);
2589 ea
= code
->src
.literal
;
2593 case O (O_XORC
, SB
): /* xorc.b */
2594 if (code
->dst
.type
== X (OP_CCR
, SB
))
2597 rd
= h8_get_ccr (sd
);
2599 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2602 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2603 rd
= h8_get_exr (sd
);
2607 ea
= code
->src
.literal
;
2611 case O (O_BRAS
, SB
): /* bra/s */
2612 /* This is basically an ordinary branch, with a delay slot. */
2613 if (fetch (sd
, &code
->src
, &res
))
2621 /* Execution continues at next instruction, but
2622 delayed_branch is set up for next cycle. */
2623 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2627 case O (O_BRAB
, SB
): /* bra rd.b */
2628 case O (O_BRAW
, SW
): /* bra rd.w */
2629 case O (O_BRAL
, SL
): /* bra erd.l */
2630 if (fetch (sd
, &code
->src
, &rd
))
2632 switch (OP_SIZE (code
->opcode
)) {
2633 case SB
: rd
&= 0xff; break;
2634 case SW
: rd
&= 0xffff; break;
2635 case SL
: rd
&= 0xffffffff; break;
2637 pc
= code
->next_pc
+ rd
;
2640 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2641 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2642 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2643 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2644 if (fetch (sd
, &code
->dst
, &rd
) ||
2645 fetch (sd
, &code
->src
, &bit
))
2648 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2649 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2651 if ((rd
& (1 << bit
))) /* no branch */
2654 else /* branch/call if set */
2656 if (!(rd
& (1 << bit
))) /* no branch */
2660 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2662 pc
= code
->next_pc
+ res
;
2664 if (code
->opcode
== O (O_BRABC
, SB
) ||
2665 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2673 case O (O_BRA
, SB
): /* bra, branch always */
2678 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2683 case O (O_BHI
, SB
): /* bhi */
2689 case O (O_BLS
, SB
): /* bls */
2694 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2699 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2704 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2708 case O (O_BGT
, SB
): /* bgt */
2709 if (((Z
|| (N
^ V
)) == 0))
2713 case O (O_BLE
, SB
): /* ble */
2714 if (((Z
|| (N
^ V
)) == 1))
2718 case O (O_BGE
, SB
): /* bge */
2722 case O (O_BLT
, SB
): /* blt */
2726 case O (O_BMI
, SB
): /* bmi */
2730 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2735 case O (O_BPL
, SB
): /* bpl */
2739 case O (O_BVC
, SB
): /* bvc */
2743 case O (O_BVS
, SB
): /* bvs */
2748 /* Trap for Command Line setup. */
2749 case O (O_SYS_CMDLINE
, SB
):
2751 int i
= 0; /* Loop counter. */
2752 int j
= 0; /* Loop counter. */
2753 int ind_arg_len
= 0; /* Length of each argument. */
2754 int no_of_args
= 0; /* The no. or cmdline args. */
2755 int current_location
= 0; /* Location of string. */
2756 int old_sp
= 0; /* The Initial Stack Pointer. */
2757 int no_of_slots
= 0; /* No. of slots required on the stack
2758 for storing cmdline args. */
2759 int sp_move
= 0; /* No. of locations by which the stack needs
2761 int new_sp
= 0; /* The final stack pointer location passed
2763 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2764 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2765 args on the stack. */
2766 int char_ptr_size
= 0; /* Size of a character pointer on
2768 int addr_cmdline
= 0; /* Memory location where cmdline has
2770 int size_cmdline
= 0; /* Size of cmdline. */
2772 /* Set the address of 256 free locations where command line is
2774 addr_cmdline
= cmdline_location();
2775 h8_set_reg (sd
, 0, addr_cmdline
);
2777 /* Counting the no. of commandline arguments. */
2778 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2781 /* No. of arguments in the command line. */
2784 /* Current location is just a temporary variable,which we are
2785 setting to the point to the start of our commandline string. */
2786 current_location
= addr_cmdline
;
2788 /* Allocating space for storing pointers of the command line
2790 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2792 /* Setting char_ptr_size to the sizeof (char *) on the different
2794 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2803 for (i
= 0; i
< no_of_args
; i
++)
2807 /* The size of the commandline argument. */
2808 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2810 /* The total size of the command line string. */
2811 size_cmdline
+= ind_arg_len
;
2813 /* As we have only 256 bytes, we need to provide a graceful
2814 exit. Anyways, a program using command line arguments
2815 where we cannot store all the command line arguments
2816 given may behave unpredictably. */
2817 if (size_cmdline
>= 256)
2819 h8_set_reg (sd
, 0, 0);
2824 /* current_location points to the memory where the next
2825 commandline argument is stored. */
2826 argv_ptrs
[i
] = current_location
;
2827 for (j
= 0; j
< ind_arg_len
; j
++)
2829 SET_MEMORY_B ((current_location
+
2830 (sizeof (char) * j
)),
2831 *(h8_get_cmdline_arg (sd
, i
) +
2832 sizeof (char) * j
));
2835 /* Setting current_location to the starting of next
2837 current_location
+= ind_arg_len
;
2841 /* This is the original position of the stack pointer. */
2842 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2844 /* We need space from the stack to store the pointers to argvs. */
2845 /* As we will infringe on the stack, we need to shift the stack
2846 pointer so that the data is not overwritten. We calculate how
2847 much space is required. */
2848 sp_move
= (no_of_args
) * (char_ptr_size
);
2850 /* The final position of stack pointer, we have thus taken some
2851 space from the stack. */
2852 new_sp
= old_sp
- sp_move
;
2854 /* Temporary variable holding value where the argv pointers need
2856 argv_ptrs_location
= new_sp
;
2858 /* The argv pointers are stored at sequential locations. As per
2860 for (i
= 0; i
< no_of_args
; i
++)
2862 /* Saving the argv pointer. */
2863 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2865 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2869 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2872 /* The next location where the pointer to the next argv
2873 string has to be stored. */
2874 argv_ptrs_location
+= char_ptr_size
;
2877 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2879 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2881 SET_MEMORY_L (old_sp
, 0x0);
2885 SET_MEMORY_W (old_sp
, 0x0);
2888 /* Freeing allocated memory. */
2890 for (i
= 0; i
<= no_of_args
; i
++)
2892 free (h8_get_cmdline_arg (sd
, i
));
2894 free (h8_get_command_line (sd
));
2896 /* The no. of argv arguments are returned in Reg 0. */
2897 h8_set_reg (sd
, 0, no_of_args
);
2898 /* The Pointer to argv in Register 1. */
2899 h8_set_reg (sd
, 1, new_sp
);
2900 /* Setting the stack pointer to the new value. */
2901 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2905 /* System call processing starts. */
2906 case O (O_SYS_OPEN
, SB
):
2908 int len
= 0; /* Length of filename. */
2909 char *filename
; /* Filename would go here. */
2910 char temp_char
; /* Temporary character */
2911 int mode
= 0; /* Mode bits for the file. */
2912 int open_return
; /* Return value of open, file descriptor. */
2913 int i
; /* Loop counter */
2914 int filename_ptr
; /* Pointer to filename in cpu memory. */
2916 /* Setting filename_ptr to first argument of open, */
2917 /* and trying to get mode. */
2918 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2920 filename_ptr
= GET_L_REG (0);
2921 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2925 filename_ptr
= GET_W_REG (0);
2926 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2929 /* Trying to find the length of the filename. */
2930 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2933 while (temp_char
!= '\0')
2935 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2939 /* Allocating space for the filename. */
2940 filename
= (char *) malloc (sizeof (char) * len
);
2942 /* String copying the filename from memory. */
2943 for (i
= 0; i
< len
; i
++)
2945 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2946 filename
[i
] = temp_char
;
2949 /* Callback to open and return the file descriptor. */
2950 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2952 /* Return value in register 0. */
2953 h8_set_reg (sd
, 0, open_return
);
2955 /* Freeing memory used for filename. */
2960 case O (O_SYS_READ
, SB
):
2962 char *char_ptr
; /* Where characters read would be stored. */
2963 int fd
; /* File descriptor */
2964 int buf_size
; /* BUF_SIZE parameter in read. */
2965 int i
= 0; /* Temporary Loop counter */
2966 int read_return
= 0; /* Return value from callback to
2969 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2970 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2972 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2974 /* Callback to read and return the no. of characters read. */
2976 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2978 /* The characters read are stored in cpu memory. */
2979 for (i
= 0; i
< buf_size
; i
++)
2981 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2982 *(char_ptr
+ (sizeof (char) * i
)));
2985 /* Return value in Register 0. */
2986 h8_set_reg (sd
, 0, read_return
);
2988 /* Freeing memory used as buffer. */
2993 case O (O_SYS_WRITE
, SB
):
2995 int fd
; /* File descriptor */
2996 char temp_char
; /* Temporary character */
2997 int len
; /* Length of write, Parameter II to write. */
2998 int char_ptr
; /* Character Pointer, Parameter I of write. */
2999 char *ptr
; /* Where characters to be written are stored.
3001 int write_return
; /* Return value from callback to write. */
3002 int i
= 0; /* Loop counter */
3004 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3005 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3006 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
3008 /* Allocating space for the characters to be written. */
3009 ptr
= (char *) malloc (sizeof (char) * len
);
3011 /* Fetching the characters from cpu memory. */
3012 for (i
= 0; i
< len
; i
++)
3014 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
3018 /* Callback write and return the no. of characters written. */
3019 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
3021 /* Return value in Register 0. */
3022 h8_set_reg (sd
, 0, write_return
);
3024 /* Freeing memory used as buffer. */
3029 case O (O_SYS_LSEEK
, SB
):
3031 int fd
; /* File descriptor */
3032 int offset
; /* Offset */
3033 int origin
; /* Origin */
3034 int lseek_return
; /* Return value from callback to lseek. */
3036 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3037 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3038 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
3040 /* Callback lseek and return offset. */
3042 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
3044 /* Return value in register 0. */
3045 h8_set_reg (sd
, 0, lseek_return
);
3049 case O (O_SYS_CLOSE
, SB
):
3051 int fd
; /* File descriptor */
3052 int close_return
; /* Return value from callback to close. */
3054 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3056 /* Callback close and return. */
3057 close_return
= sim_callback
->close (sim_callback
, fd
);
3059 /* Return value in register 0. */
3060 h8_set_reg (sd
, 0, close_return
);
3064 case O (O_SYS_FSTAT
, SB
):
3066 int fd
; /* File descriptor */
3067 struct stat stat_rec
; /* Stat record */
3068 int fstat_return
; /* Return value from callback to stat. */
3069 int stat_ptr
; /* Pointer to stat record. */
3070 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3072 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3074 /* Setting stat_ptr to second argument of stat. */
3075 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3077 /* Callback stat and return. */
3078 fstat_return
= sim_callback
->fstat (sim_callback
, fd
, &stat_rec
);
3080 /* Have stat_ptr point to starting of stat_rec. */
3081 temp_stat_ptr
= (char *) (&stat_rec
);
3083 /* Setting up the stat structure returned. */
3084 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3086 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3088 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3090 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3092 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3094 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3096 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3098 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3100 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3102 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3104 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3106 /* Return value in register 0. */
3107 h8_set_reg (sd
, 0, fstat_return
);
3111 case O (O_SYS_STAT
, SB
):
3113 int len
= 0; /* Length of filename. */
3114 char *filename
; /* Filename would go here. */
3115 char temp_char
; /* Temporary character */
3116 int filename_ptr
; /* Pointer to filename in cpu memory. */
3117 struct stat stat_rec
; /* Stat record */
3118 int stat_return
; /* Return value from callback to stat */
3119 int stat_ptr
; /* Pointer to stat record. */
3120 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3121 int i
= 0; /* Loop Counter */
3123 /* Setting filename_ptr to first argument of open. */
3124 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3126 /* Trying to find the length of the filename. */
3127 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3130 while (temp_char
!= '\0')
3132 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3136 /* Allocating space for the filename. */
3137 filename
= (char *) malloc (sizeof (char) * len
);
3139 /* String copying the filename from memory. */
3140 for (i
= 0; i
< len
; i
++)
3142 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3143 filename
[i
] = temp_char
;
3146 /* Setting stat_ptr to second argument of stat. */
3147 /* stat_ptr = h8_get_reg (sd, 1); */
3148 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3150 /* Callback stat and return. */
3152 sim_callback
->stat (sim_callback
, filename
, &stat_rec
);
3154 /* Have stat_ptr point to starting of stat_rec. */
3155 temp_stat_ptr
= (char *) (&stat_rec
);
3157 /* Freeing memory used for filename. */
3160 /* Setting up the stat structure returned. */
3161 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3163 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3165 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3167 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3169 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3171 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3173 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3175 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3177 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3179 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3181 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3183 /* Return value in register 0. */
3184 h8_set_reg (sd
, 0, stat_return
);
3187 /* End of system call processing. */
3189 case O (O_NOT
, SB
): /* not.b */
3190 if (fetch2 (sd
, &code
->src
, &rd
))
3196 case O (O_NOT
, SW
): /* not.w */
3197 if (fetch2 (sd
, &code
->src
, &rd
))
3203 case O (O_NOT
, SL
): /* not.l */
3204 if (fetch2 (sd
, &code
->src
, &rd
))
3210 case O (O_SHLL
, SB
): /* shll.b */
3211 case O (O_SHLR
, SB
): /* shlr.b */
3212 if (fetch2 (sd
, &code
->dst
, &rd
))
3215 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3216 ea
= 1; /* unary op */
3217 else /* binary op */
3218 fetch (sd
, &code
->src
, &ea
);
3220 if (code
->opcode
== O (O_SHLL
, SB
))
3223 c
= rd
& (0x80 >> (ea
- 1));
3229 c
= rd
& (1 << (ea
- 1));
3230 rd
= (unsigned char) rd
>> ea
;
3234 case O (O_SHLL
, SW
): /* shll.w */
3235 case O (O_SHLR
, SW
): /* shlr.w */
3236 if (fetch2 (sd
, &code
->dst
, &rd
))
3239 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3240 ea
= 1; /* unary op */
3242 fetch (sd
, &code
->src
, &ea
);
3244 if (code
->opcode
== O (O_SHLL
, SW
))
3247 c
= rd
& (0x8000 >> (ea
- 1));
3253 c
= rd
& (1 << (ea
- 1));
3254 rd
= (unsigned short) rd
>> ea
;
3258 case O (O_SHLL
, SL
): /* shll.l */
3259 case O (O_SHLR
, SL
): /* shlr.l */
3260 if (fetch2 (sd
, &code
->dst
, &rd
))
3263 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3264 ea
= 1; /* unary op */
3266 fetch (sd
, &code
->src
, &ea
);
3268 if (code
->opcode
== O (O_SHLL
, SL
))
3271 c
= rd
& (0x80000000 >> (ea
- 1));
3277 c
= rd
& (1 << (ea
- 1));
3278 rd
= (unsigned int) rd
>> ea
;
3282 case O (O_SHAL
, SB
):
3283 case O (O_SHAR
, SB
):
3284 if (fetch2 (sd
, &code
->dst
, &rd
))
3287 if (code
->src
.type
== X (OP_IMM
, SB
))
3288 fetch (sd
, &code
->src
, &ea
);
3292 if (code
->opcode
== O (O_SHAL
, SB
))
3294 c
= rd
& (0x80 >> (ea
- 1));
3295 res
= rd
>> (7 - ea
);
3296 v
= ((res
& 1) && !(res
& 2))
3297 || (!(res
& 1) && (res
& 2));
3302 c
= rd
& (1 << (ea
- 1));
3304 rd
= ((signed char) rd
) >> ea
;
3308 case O (O_SHAL
, SW
):
3309 case O (O_SHAR
, SW
):
3310 if (fetch2 (sd
, &code
->dst
, &rd
))
3313 if (code
->src
.type
== X (OP_IMM
, SW
))
3314 fetch (sd
, &code
->src
, &ea
);
3318 if (code
->opcode
== O (O_SHAL
, SW
))
3320 c
= rd
& (0x8000 >> (ea
- 1));
3321 res
= rd
>> (15 - ea
);
3322 v
= ((res
& 1) && !(res
& 2))
3323 || (!(res
& 1) && (res
& 2));
3328 c
= rd
& (1 << (ea
- 1));
3330 rd
= ((signed short) rd
) >> ea
;
3334 case O (O_SHAL
, SL
):
3335 case O (O_SHAR
, SL
):
3336 if (fetch2 (sd
, &code
->dst
, &rd
))
3339 if (code
->src
.type
== X (OP_IMM
, SL
))
3340 fetch (sd
, &code
->src
, &ea
);
3344 if (code
->opcode
== O (O_SHAL
, SL
))
3346 c
= rd
& (0x80000000 >> (ea
- 1));
3347 res
= rd
>> (31 - ea
);
3348 v
= ((res
& 1) && !(res
& 2))
3349 || (!(res
& 1) && (res
& 2));
3354 c
= rd
& (1 << (ea
- 1));
3356 rd
= ((signed int) rd
) >> ea
;
3360 case O (O_ROTL
, SB
):
3361 case O (O_ROTR
, SB
):
3362 if (fetch2 (sd
, &code
->dst
, &rd
))
3365 if (code
->src
.type
== X (OP_IMM
, SB
))
3366 fetch (sd
, &code
->src
, &ea
);
3371 if (code
->opcode
== O (O_ROTL
, SB
))
3381 rd
= ((unsigned char) rd
) >> 1;
3389 case O (O_ROTL
, SW
):
3390 case O (O_ROTR
, SW
):
3391 if (fetch2 (sd
, &code
->dst
, &rd
))
3394 if (code
->src
.type
== X (OP_IMM
, SW
))
3395 fetch (sd
, &code
->src
, &ea
);
3400 if (code
->opcode
== O (O_ROTL
, SW
))
3410 rd
= ((unsigned short) rd
) >> 1;
3418 case O (O_ROTL
, SL
):
3419 case O (O_ROTR
, SL
):
3420 if (fetch2 (sd
, &code
->dst
, &rd
))
3423 if (code
->src
.type
== X (OP_IMM
, SL
))
3424 fetch (sd
, &code
->src
, &ea
);
3429 if (code
->opcode
== O (O_ROTL
, SL
))
3431 c
= rd
& 0x80000000;
3439 rd
= ((unsigned int) rd
) >> 1;
3447 case O (O_ROTXL
, SB
):
3448 case O (O_ROTXR
, SB
):
3449 if (fetch2 (sd
, &code
->dst
, &rd
))
3452 if (code
->src
.type
== X (OP_IMM
, SB
))
3453 fetch (sd
, &code
->src
, &ea
);
3458 if (code
->opcode
== O (O_ROTXL
, SB
))
3469 rd
= ((unsigned char) rd
) >> 1;
3478 case O (O_ROTXL
, SW
):
3479 case O (O_ROTXR
, SW
):
3480 if (fetch2 (sd
, &code
->dst
, &rd
))
3483 if (code
->src
.type
== X (OP_IMM
, SW
))
3484 fetch (sd
, &code
->src
, &ea
);
3489 if (code
->opcode
== O (O_ROTXL
, SW
))
3500 rd
= ((unsigned short) rd
) >> 1;
3509 case O (O_ROTXL
, SL
):
3510 case O (O_ROTXR
, SL
):
3511 if (fetch2 (sd
, &code
->dst
, &rd
))
3514 if (code
->src
.type
== X (OP_IMM
, SL
))
3515 fetch (sd
, &code
->src
, &ea
);
3520 if (code
->opcode
== O (O_ROTXL
, SL
))
3522 res
= rd
& 0x80000000;
3531 rd
= ((unsigned int) rd
) >> 1;
3542 case O (O_JMP
, SB
): /* jmp */
3544 fetch (sd
, &code
->src
, &pc
);
3549 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3551 if (fetch (sd
, &code
->src
, &pc
))
3554 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3556 if (h8300hmode
&& !h8300_normal_mode
)
3559 SET_MEMORY_L (tmp
, code
->next_pc
);
3564 SET_MEMORY_W (tmp
, code
->next_pc
);
3566 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3572 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3573 if (fetch (sd
, &code
->src
, &res
))
3575 pc
= code
->next_pc
+ res
;
3578 case O (O_RTE
, SN
): /* rte, return from exception */
3580 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3581 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3583 if (h8300smode
) /* pop exr */
3585 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3588 if (h8300hmode
&& !h8300_normal_mode
)
3590 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3592 pc
= GET_MEMORY_L (tmp
);
3597 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3599 pc
= GET_MEMORY_W (tmp
);
3604 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3607 case O (O_RTS
, SN
): /* rts, return from subroutine */
3609 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3611 if (h8300hmode
&& !h8300_normal_mode
)
3613 pc
= GET_MEMORY_L (tmp
);
3618 pc
= GET_MEMORY_W (tmp
);
3622 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3625 case O (O_ILL
, SB
): /* illegal */
3626 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
3629 case O (O_SLEEP
, SN
): /* sleep */
3630 /* Check for magic numbers in r1 and r2. */
3631 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3632 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3633 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3635 /* This trap comes from _exit, not from gdb. */
3636 sim_engine_set_run_state (sd
, sim_exited
,
3637 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3640 /* Unfortunately this won't really work, because
3641 when we take a breakpoint trap, R0 has a "random",
3642 user-defined value. Don't see any immediate solution. */
3643 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3645 /* Pass the stop signal up to gdb. */
3646 sim_engine_set_run_state (sd
, sim_stopped
,
3647 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3652 /* Treat it as a sigtrap. */
3653 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3657 case O (O_TRAPA
, SB
): /* trapa */
3658 if (fetch (sd
, &code
->src
, &res
))
3659 goto end
; /* res is vector number. */
3661 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3662 if(h8300_normal_mode
)
3665 SET_MEMORY_W (tmp
, code
->next_pc
);
3667 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3672 SET_MEMORY_L (tmp
, code
->next_pc
);
3674 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3682 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3685 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3687 if(h8300_normal_mode
)
3688 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3690 pc
= GET_MEMORY_L (0x20 + res
* 4);
3694 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3697 case O (O_BSETEQ
, SB
):
3702 case O (O_BSETNE
, SB
):
3707 case O (O_BCLREQ
, SB
):
3712 case O (O_BCLRNE
, SB
):
3717 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3718 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3720 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3722 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3723 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3724 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3725 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3726 if (C
) ea
|= m
); /* bst */
3727 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3728 if (!C
) ea
|= m
); /* bist */
3729 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3730 if (Z
) ea
|= m
); /* bstz */
3731 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3732 if (!Z
) ea
|= m
); /* bistz */
3733 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3734 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3735 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3736 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3737 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3738 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3740 case O (O_BFLD
, SB
): /* bfld */
3743 if (fetch (sd
, &code
->src
, &bit
))
3748 if (fetch (sd
, &code
->dst
, &ea
))
3758 if (store (sd
, &code
->op3
, ea
))
3763 case O(O_BFST
, SB
): /* bfst */
3764 /* bitfield store */
3765 /* NOTE: the imm8 value is in dst, and the ea value
3766 (which is actually the destination) is in op3.
3767 It has to be that way, to avoid breaking the assembler. */
3769 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3771 if (bit
== 0) /* noop -- nothing to do. */
3774 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3777 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3780 /* Left-shift the register data into position. */
3781 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3784 /* Combine it with the neighboring bits. */
3785 ea
= (ea
& ~bit
) | (rd
& bit
);
3788 if (store2 (sd
, &code
->op3
, ea
))
3792 case O (O_CLRMAC
, SN
): /* clrmac */
3793 h8_set_mach (sd
, 0);
3794 h8_set_macl (sd
, 0);
3795 h8_set_macZ (sd
, 1);
3796 h8_set_macV (sd
, 0);
3797 h8_set_macN (sd
, 0);
3800 case O (O_STMAC
, SL
): /* stmac, 260 */
3801 switch (code
->src
.type
) {
3802 case X (OP_MACH
, SL
):
3803 res
= h8_get_mach (sd
);
3804 if (res
& 0x200) /* sign extend */
3807 case X (OP_MACL
, SL
):
3808 res
= h8_get_macl (sd
);
3810 default: goto illegal
;
3812 nz
= !h8_get_macZ (sd
);
3813 n
= h8_get_macN (sd
);
3814 v
= h8_get_macV (sd
);
3816 if (store (sd
, &code
->dst
, res
))
3821 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3822 if (fetch (sd
, &code
->src
, &rd
))
3825 switch (code
->dst
.type
) {
3826 case X (OP_MACH
, SL
):
3827 rd
&= 0x3ff; /* Truncate to 10 bits */
3828 h8_set_mach (sd
, rd
);
3830 case X (OP_MACL
, SL
):
3831 h8_set_macl (sd
, rd
);
3833 default: goto illegal
;
3835 h8_set_macV (sd
, 0);
3839 if (fetch (sd
, &code
->src
, &rd
) ||
3840 fetch (sd
, &code
->dst
, &res
))
3843 /* Ye gods, this is non-portable!
3844 However, the existing mul/div code is similar. */
3845 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3847 if (h8_get_macS (sd
)) /* Saturating mode */
3849 long long mac
= h8_get_macl (sd
);
3851 if (mac
& 0x80000000) /* sign extend */
3852 mac
|= 0xffffffff00000000LL
;
3855 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3856 h8_set_macV (sd
, 1);
3857 h8_set_macZ (sd
, (mac
== 0));
3858 h8_set_macN (sd
, (mac
< 0));
3859 h8_set_macl (sd
, (int) mac
);
3861 else /* "Less Saturating" mode */
3863 long long mac
= h8_get_mach (sd
);
3865 mac
+= h8_get_macl (sd
);
3867 if (mac
& 0x20000000000LL
) /* sign extend */
3868 mac
|= 0xfffffc0000000000LL
;
3871 if (mac
> 0x1ffffffffffLL
||
3872 mac
< (long long) 0xfffffe0000000000LL
)
3873 h8_set_macV (sd
, 1);
3874 h8_set_macZ (sd
, (mac
== 0));
3875 h8_set_macN (sd
, (mac
< 0));
3876 h8_set_macl (sd
, (int) mac
);
3878 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3882 case O (O_MULS
, SW
): /* muls.w */
3883 if (fetch (sd
, &code
->src
, &ea
) ||
3884 fetch (sd
, &code
->dst
, &rd
))
3887 ea
= SEXTSHORT (ea
);
3888 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3892 if (store (sd
, &code
->dst
, res
))
3897 case O (O_MULS
, SL
): /* muls.l */
3898 if (fetch (sd
, &code
->src
, &ea
) ||
3899 fetch (sd
, &code
->dst
, &rd
))
3904 n
= res
& 0x80000000;
3905 nz
= res
& 0xffffffff;
3906 if (store (sd
, &code
->dst
, res
))
3910 case O (O_MULSU
, SL
): /* muls/u.l */
3911 if (fetch (sd
, &code
->src
, &ea
) ||
3912 fetch (sd
, &code
->dst
, &rd
))
3915 /* Compute upper 32 bits of the 64-bit result. */
3916 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3918 n
= res
& 0x80000000;
3919 nz
= res
& 0xffffffff;
3920 if (store (sd
, &code
->dst
, res
))
3924 case O (O_MULU
, SW
): /* mulu.w */
3925 if (fetch (sd
, &code
->src
, &ea
) ||
3926 fetch (sd
, &code
->dst
, &rd
))
3929 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3931 /* Don't set Z or N. */
3932 if (store (sd
, &code
->dst
, res
))
3937 case O (O_MULU
, SL
): /* mulu.l */
3938 if (fetch (sd
, &code
->src
, &ea
) ||
3939 fetch (sd
, &code
->dst
, &rd
))
3944 /* Don't set Z or N. */
3945 if (store (sd
, &code
->dst
, res
))
3950 case O (O_MULUU
, SL
): /* mulu/u.l */
3951 if (fetch (sd
, &code
->src
, &ea
) ||
3952 fetch (sd
, &code
->dst
, &rd
))
3955 /* Compute upper 32 bits of the 64-bit result. */
3956 res
= (((unsigned long long) (unsigned) ea
) *
3957 ((unsigned long long) (unsigned) rd
)) >> 32;
3959 /* Don't set Z or N. */
3960 if (store (sd
, &code
->dst
, res
))
3965 case O (O_MULXS
, SB
): /* mulxs.b */
3966 if (fetch (sd
, &code
->src
, &ea
) ||
3967 fetch (sd
, &code
->dst
, &rd
))
3971 res
= ea
* SEXTCHAR (rd
);
3975 if (store (sd
, &code
->dst
, res
))
3980 case O (O_MULXS
, SW
): /* mulxs.w */
3981 if (fetch (sd
, &code
->src
, &ea
) ||
3982 fetch (sd
, &code
->dst
, &rd
))
3985 ea
= SEXTSHORT (ea
);
3986 res
= ea
* SEXTSHORT (rd
& 0xffff);
3988 n
= res
& 0x80000000;
3989 nz
= res
& 0xffffffff;
3990 if (store (sd
, &code
->dst
, res
))
3995 case O (O_MULXU
, SB
): /* mulxu.b */
3996 if (fetch (sd
, &code
->src
, &ea
) ||
3997 fetch (sd
, &code
->dst
, &rd
))
4000 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
4002 if (store (sd
, &code
->dst
, res
))
4007 case O (O_MULXU
, SW
): /* mulxu.w */
4008 if (fetch (sd
, &code
->src
, &ea
) ||
4009 fetch (sd
, &code
->dst
, &rd
))
4012 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
4014 if (store (sd
, &code
->dst
, res
))
4019 case O (O_TAS
, SB
): /* tas (test and set) */
4020 if (!h8300sxmode
) /* h8sx can use any register. */
4021 switch (code
->src
.reg
)
4032 if (fetch (sd
, &code
->src
, &res
))
4034 if (store (sd
, &code
->src
, res
| 0x80))
4037 goto just_flags_log8
;
4039 case O (O_DIVU
, SW
): /* divu.w */
4040 if (fetch (sd
, &code
->src
, &ea
) ||
4041 fetch (sd
, &code
->dst
, &rd
))
4047 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
4051 if (store (sd
, &code
->dst
, res
))
4055 case O (O_DIVU
, SL
): /* divu.l */
4056 if (fetch (sd
, &code
->src
, &ea
) ||
4057 fetch (sd
, &code
->dst
, &rd
))
4060 n
= ea
& 0x80000000;
4061 nz
= ea
& 0xffffffff;
4063 res
= (unsigned) rd
/ ea
;
4067 if (store (sd
, &code
->dst
, res
))
4071 case O (O_DIVS
, SW
): /* divs.w */
4072 if (fetch (sd
, &code
->src
, &ea
) ||
4073 fetch (sd
, &code
->dst
, &rd
))
4078 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
4088 if (store (sd
, &code
->dst
, res
))
4092 case O (O_DIVS
, SL
): /* divs.l */
4093 if (fetch (sd
, &code
->src
, &ea
) ||
4094 fetch (sd
, &code
->dst
, &rd
))
4108 n
= res
& 0x80000000;
4109 if (store (sd
, &code
->dst
, res
))
4113 case O (O_DIVXU
, SB
): /* divxu.b */
4114 if (fetch (sd
, &code
->src
, &ea
) ||
4115 fetch (sd
, &code
->dst
, &rd
))
4118 rd
= UEXTSHORT (rd
);
4125 tmp
= (unsigned) rd
% ea
;
4126 res
= (unsigned) rd
/ ea
;
4134 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4138 case O (O_DIVXU
, SW
): /* divxu.w */
4139 if (fetch (sd
, &code
->src
, &ea
) ||
4140 fetch (sd
, &code
->dst
, &rd
))
4143 ea
= UEXTSHORT (ea
);
4149 tmp
= (unsigned) rd
% ea
;
4150 res
= (unsigned) rd
/ ea
;
4158 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4162 case O (O_DIVXS
, SB
): /* divxs.b */
4163 if (fetch (sd
, &code
->src
, &ea
) ||
4164 fetch (sd
, &code
->dst
, &rd
))
4167 rd
= SEXTSHORT (rd
);
4172 tmp
= (int) rd
% (int) ea
;
4173 res
= (int) rd
/ (int) ea
;
4184 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4188 case O (O_DIVXS
, SW
): /* divxs.w */
4189 if (fetch (sd
, &code
->src
, &ea
) ||
4190 fetch (sd
, &code
->dst
, &rd
))
4193 ea
= SEXTSHORT (ea
);
4197 tmp
= (int) rd
% (int) ea
;
4198 res
= (int) rd
/ (int) ea
;
4208 n
= res
& 0x80000000;
4209 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4213 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4214 if (fetch2 (sd
, &code
->dst
, &rd
))
4216 ea
= rd
& 0x80 ? -256 : 0;
4217 res
= (rd
& 0xff) + ea
;
4220 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4221 if (fetch2 (sd
, &code
->dst
, &rd
))
4223 if (code
->src
.type
== X (OP_IMM
, SL
))
4225 if (fetch (sd
, &code
->src
, &ea
))
4228 if (ea
== 2) /* exts.l #2, nn */
4230 /* Sign-extend from 8-bit to 32-bit. */
4231 ea
= rd
& 0x80 ? -256 : 0;
4232 res
= (rd
& 0xff) + ea
;
4236 /* Sign-extend from 16-bit to 32-bit. */
4237 ea
= rd
& 0x8000 ? -65536 : 0;
4238 res
= (rd
& 0xffff) + ea
;
4241 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4242 if (fetch2 (sd
, &code
->dst
, &rd
))
4245 res
= (rd
& 0xff) + ea
;
4248 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4249 if (fetch2 (sd
, &code
->dst
, &rd
))
4251 if (code
->src
.type
== X (OP_IMM
, SL
))
4253 if (fetch (sd
, &code
->src
, &ea
))
4256 if (ea
== 2) /* extu.l #2, nn */
4258 /* Zero-extend from 8-bit to 32-bit. */
4260 res
= (rd
& 0xff) + ea
;
4264 /* Zero-extend from 16-bit to 32-bit. */
4266 res
= (rd
& 0xffff) + ea
;
4269 case O (O_NOP
, SN
): /* nop */
4272 case O (O_STM
, SL
): /* stm, store to memory */
4274 int nregs
, firstreg
, i
;
4276 nregs
= GET_MEMORY_B (pc
+ 1);
4279 firstreg
= code
->src
.reg
;
4281 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4283 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4284 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4289 case O (O_LDM
, SL
): /* ldm, load from memory */
4290 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4291 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4293 int nregs
, firstreg
, i
;
4295 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4296 firstreg
= code
->dst
.reg
& 0xf;
4297 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4299 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4300 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4303 switch (code
->opcode
) {
4304 case O (O_RTEL
, SN
):
4306 case O (O_RTSL
, SN
):
4315 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4316 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4317 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4318 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4319 res
= res
; /* Value added == 0. */
4320 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4321 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4322 res
= res
+ 0x6; /* Value added == 6. */
4323 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4324 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4325 res
= res
+ 0x6; /* Value added == 6. */
4326 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4327 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4328 res
= res
+ 0x60; /* Value added == 60. */
4329 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4330 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4331 res
= res
+ 0x66; /* Value added == 66. */
4332 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4333 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4334 res
= res
+ 0x66; /* Value added == 66. */
4335 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4336 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4337 res
= res
+ 0x60; /* Value added == 60. */
4338 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4339 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4340 res
= res
+ 0x66; /* Value added == 66. */
4341 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4342 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4343 res
= res
+ 0x66; /* Value added == 66. */
4348 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4349 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4350 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4351 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4352 res
= res
; /* Value added == 0. */
4353 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4354 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4355 res
= res
+ 0xfa; /* Value added == 0xfa. */
4356 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4357 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4358 res
= res
+ 0xa0; /* Value added == 0xa0. */
4359 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4360 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4361 res
= res
+ 0x9a; /* Value added == 0x9a. */
4367 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4372 (*sim_callback
->printf_filtered
) (sim_callback
,
4373 "sim_resume: internal error.\n");
4374 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4378 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4379 code
->dst
.type
== X (OP_CCR
, SW
))
4381 h8_set_ccr (sd
, res
);
4384 else if (h8300smode
&&
4385 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4386 code
->dst
.type
== X (OP_EXR
, SW
)))
4388 h8_set_exr (sd
, res
);
4389 if (h8300smode
) /* Get exr. */
4391 trace
= (h8_get_exr (sd
) >> 7) & 1;
4392 intMask
= h8_get_exr (sd
) & 7;
4401 /* When a branch works */
4402 if (fetch (sd
, &code
->src
, &res
))
4404 if (res
& 1) /* bad address */
4406 pc
= code
->next_pc
+ res
;
4409 /* Set the cond codes from res */
4412 /* Set the flags after an 8 bit inc/dec operation */
4416 v
= (rd
& 0x7f) == 0x7f;
4419 /* Set the flags after an 16 bit inc/dec operation */
4423 v
= (rd
& 0x7fff) == 0x7fff;
4426 /* Set the flags after an 32 bit inc/dec operation */
4428 n
= res
& 0x80000000;
4429 nz
= res
& 0xffffffff;
4430 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4434 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4437 if (store2 (sd
, &code
->dst
, rd
))
4442 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4445 if (store2 (sd
, &code
->dst
, rd
))
4450 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4451 n
= (rd
& 0x80000000);
4452 nz
= rd
& 0xffffffff;
4453 if (store2 (sd
, &code
->dst
, rd
))
4458 if (store2 (sd
, &code
->dst
, res
))
4462 /* flags after a 32bit logical operation */
4463 n
= res
& 0x80000000;
4464 nz
= res
& 0xffffffff;
4469 if (store2 (sd
, &code
->dst
, res
))
4473 /* flags after a 16bit logical operation */
4480 if (store2 (sd
, &code
->dst
, res
))
4490 if (store2 (sd
, &code
->dst
, res
))
4497 switch (code
->opcode
/ 4)
4501 v
= ((rd
& 0x80) == (ea
& 0x80)
4502 && (rd
& 0x80) != (res
& 0x80));
4507 v
= ((rd
& 0x80) != (-ea
& 0x80)
4508 && (rd
& 0x80) != (res
& 0x80));
4515 break; /* No effect on v flag. */
4520 if (store2 (sd
, &code
->dst
, res
))
4526 c
= (res
& 0x10000);
4527 switch (code
->opcode
/ 4)
4531 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4532 && (rd
& 0x8000) != (res
& 0x8000));
4537 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4538 && (rd
& 0x8000) != (res
& 0x8000));
4547 if (store2 (sd
, &code
->dst
, res
))
4551 n
= res
& 0x80000000;
4552 nz
= res
& 0xffffffff;
4553 switch (code
->opcode
/ 4)
4557 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4558 && (rd
& 0x80000000) != (res
& 0x80000000));
4559 c
= ((unsigned) res
< (unsigned) rd
) ||
4560 ((unsigned) res
< (unsigned) ea
);
4565 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4566 && (rd
& 0x80000000) != (res
& 0x80000000));
4567 c
= (unsigned) rd
< (unsigned) -ea
;
4570 v
= (rd
== 0x80000000);
4577 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4580 h8_set_delayed_branch (sd
, 0);
4587 if (--poll_count
< 0)
4589 poll_count
= POLL_QUIT_INTERVAL
;
4590 if ((*sim_callback
->poll_quit
) != NULL
4591 && (*sim_callback
->poll_quit
) (sim_callback
))
4592 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
4594 sim_engine_get_run_state (sd
, &reason
, &sigrc
);
4595 } while (reason
== sim_running
);
4597 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4598 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4599 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4604 h8_set_exr (sd
, (trace
<<7) | intMask
);
4606 h8_set_mask (sd
, oldmask
);
4607 signal (SIGINT
, prev
);
4611 sim_trace (SIM_DESC sd
)
4613 /* FIXME: Unfinished. */
4614 (*sim_callback
->printf_filtered
) (sim_callback
,
4615 "sim_trace: trace not supported.\n");
4616 return 1; /* Done. */
4620 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4627 for (i
= 0; i
< size
; i
++)
4629 if (addr
< memory_size
)
4631 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4632 h8_set_cache_idx (sd
, addr
+ i
, 0);
4636 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4643 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4648 if (addr
< memory_size
)
4649 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4651 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4657 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
4662 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4663 shortval
= (value
[0] << 8) | (value
[1]);
4664 intval
= h8300hmode
? longval
: shortval
;
4670 if(h8300_normal_mode
)
4671 h8_set_pc (sd
, shortval
); /* PC for Normal mode is 2 bytes */
4673 h8_set_pc (sd
, intval
);
4676 (*sim_callback
->printf_filtered
) (sim_callback
,
4677 "sim_store_register: bad regnum %d.\n",
4687 h8_set_reg (sd
, rn
, intval
);
4690 h8_set_ccr (sd
, intval
);
4693 h8_set_exr (sd
, intval
);
4696 h8_set_sbr (sd
, intval
);
4699 h8_set_vbr (sd
, intval
);
4702 h8_set_mach (sd
, intval
);
4705 h8_set_macl (sd
, intval
);
4708 h8_set_cycles (sd
, longval
);
4712 h8_set_insts (sd
, longval
);
4716 h8_set_ticks (sd
, longval
);
4723 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
4730 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4735 (*sim_callback
->printf_filtered
) (sim_callback
,
4736 "sim_fetch_register: bad regnum %d.\n",
4741 v
= h8_get_ccr (sd
);
4744 v
= h8_get_exr (sd
);
4750 v
= h8_get_sbr (sd
);
4753 v
= h8_get_vbr (sd
);
4756 v
= h8_get_mach (sd
);
4759 v
= h8_get_macl (sd
);
4769 v
= h8_get_reg (sd
, rn
);
4772 v
= h8_get_cycles (sd
);
4776 v
= h8_get_ticks (sd
);
4780 v
= h8_get_insts (sd
);
4784 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4785 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4801 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
4803 sim_engine_get_run_state (sd
, reason
, sigrc
);
4806 /* FIXME: Rename to sim_set_mem_size. */
4811 /* Memory size is fixed. */
4815 set_simcache_size (SIM_DESC sd
, int n
)
4818 free (sd
->sim_cache
);
4821 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4822 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4823 sd
->sim_cache_size
= n
;
4828 sim_info (SIM_DESC sd
, int verbose
)
4830 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4831 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4833 (*sim_callback
->printf_filtered
) (sim_callback
,
4834 "\n\n#instructions executed %10d\n",
4836 (*sim_callback
->printf_filtered
) (sim_callback
,
4837 "#cycles (v approximate) %10d\n",
4838 h8_get_cycles (sd
));
4839 (*sim_callback
->printf_filtered
) (sim_callback
,
4840 "#real time taken %10.4f\n",
4842 (*sim_callback
->printf_filtered
) (sim_callback
,
4843 "#virtual time taken %10.4f\n",
4845 if (timetaken
!= 0.0)
4846 (*sim_callback
->printf_filtered
) (sim_callback
,
4847 "#simulation ratio %10.4f\n",
4848 virttime
/ timetaken
);
4849 (*sim_callback
->printf_filtered
) (sim_callback
,
4851 h8_get_compiles (sd
));
4852 (*sim_callback
->printf_filtered
) (sim_callback
,
4853 "#cache size %10d\n",
4854 sd
->sim_cache_size
);
4857 /* This to be conditional on `what' (aka `verbose'),
4858 however it was never passed as non-zero. */
4862 for (i
= 0; i
< O_LAST
; i
++)
4864 if (h8_get_stats (sd
, i
))
4865 (*sim_callback
->printf_filtered
) (sim_callback
, "%d: %d\n",
4866 i
, h8_get_stats (sd
, i
));
4872 /* Indicate whether the cpu is an H8/300 or H8/300H.
4873 FLAG is non-zero for the H8/300H. */
4876 set_h8300h (unsigned long machine
)
4878 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4879 This function being replaced by a sim_open:ARGV configuration
4882 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4884 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4887 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4890 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4893 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4894 h8300_normal_mode
= 1;
4897 /* Cover function of sim_state_free to free the cpu buffers as well. */
4900 free_state (SIM_DESC sd
)
4902 if (STATE_MODULES (sd
) != NULL
)
4903 sim_module_uninstall (sd
);
4905 /* Fixme: free buffers in _sim_cpu. */
4906 sim_state_free (sd
);
4910 sim_open (SIM_OPEN_KIND kind
,
4911 struct host_callback_struct
*callback
,
4918 sd
= sim_state_alloc (kind
, callback
);
4919 sd
->cpu
= sim_cpu_alloc (sd
, 0);
4920 cpu
= STATE_CPU (sd
, 0);
4921 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4922 sim_state_initialize (sd
, cpu
);
4923 /* sim_cpu object is new, so some initialization is needed. */
4924 init_pointers_needed
= 1;
4926 /* For compatibility (FIXME: is this right?). */
4927 current_alignment
= NONSTRICT_ALIGNMENT
;
4928 current_target_byte_order
= BIG_ENDIAN
;
4930 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4936 /* getopt will print the error message so we just have to exit if
4937 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4938 to call print_filtered. */
4939 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4941 /* Uninstall the modules to avoid memory leaks,
4942 file descriptor leaks, etc. */
4947 /* Check for/establish the a reference program image. */
4948 if (sim_analyze_program (sd
,
4949 (STATE_PROG_ARGV (sd
) != NULL
4950 ? *STATE_PROG_ARGV (sd
)
4951 : NULL
), abfd
) != SIM_RC_OK
)
4957 /* Establish any remaining configuration options. */
4958 if (sim_config (sd
) != SIM_RC_OK
)
4964 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4966 /* Uninstall the modules to avoid memory leaks,
4967 file descriptor leaks, etc. */
4972 /* sim_hw_configure (sd); */
4974 /* FIXME: Much of the code in sim_load can be moved here. */
4978 sim_callback
= callback
;
4983 sim_close (SIM_DESC sd
, int quitting
)
4985 /* Nothing to do. */
4988 /* Called by gdb to load a program into memory. */
4991 sim_load (SIM_DESC sd
, char *prog
, bfd
*abfd
, int from_tty
)
4995 /* FIXME: The code below that sets a specific variant of the H8/300
4996 being simulated should be moved to sim_open(). */
4998 /* See if the file is for the H8/300 or H8/300H. */
4999 /* ??? This may not be the most efficient way. The z8k simulator
5000 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
5004 prog_bfd
= bfd_openr (prog
, NULL
);
5005 if (prog_bfd
!= NULL
)
5007 /* Set the cpu type. We ignore failure from bfd_check_format
5008 and bfd_openr as sim_load_file checks too. */
5009 if (bfd_check_format (prog_bfd
, bfd_object
))
5011 set_h8300h (bfd_get_mach (prog_bfd
));
5015 /* If we're using gdb attached to the simulator, then we have to
5016 reallocate memory for the simulator.
5018 When gdb first starts, it calls fetch_registers (among other
5019 functions), which in turn calls init_pointers, which allocates
5022 The problem is when we do that, we don't know whether we're
5023 debugging an H8/300 or H8/300H program.
5025 This is the first point at which we can make that determination,
5026 so we just reallocate memory now; this will also allow us to handle
5027 switching between H8/300 and H8/300H programs without exiting
5030 if (h8300smode
&& !h8300_normal_mode
)
5031 memory_size
= H8300S_MSIZE
;
5032 else if (h8300hmode
&& !h8300_normal_mode
)
5033 memory_size
= H8300H_MSIZE
;
5035 memory_size
= H8300_MSIZE
;
5037 if (h8_get_memory_buf (sd
))
5038 free (h8_get_memory_buf (sd
));
5039 if (h8_get_cache_idx_buf (sd
))
5040 free (h8_get_cache_idx_buf (sd
));
5041 if (h8_get_eightbit_buf (sd
))
5042 free (h8_get_eightbit_buf (sd
));
5044 h8_set_memory_buf (sd
, (unsigned char *)
5045 calloc (sizeof (char), memory_size
));
5046 h8_set_cache_idx_buf (sd
, (unsigned short *)
5047 calloc (sizeof (short), memory_size
));
5048 sd
->memory_size
= memory_size
;
5049 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
5051 /* `msize' must be a power of two. */
5052 if ((memory_size
& (memory_size
- 1)) != 0)
5054 (*sim_callback
->printf_filtered
) (sim_callback
,
5055 "sim_load: bad memory size.\n");
5058 h8_set_mask (sd
, memory_size
- 1);
5060 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
5061 sim_kind
== SIM_OPEN_DEBUG
,
5065 /* Close the bfd if we opened it. */
5066 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5067 bfd_close (prog_bfd
);
5071 /* Close the bfd if we opened it. */
5072 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5073 bfd_close (prog_bfd
);
5078 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
5085 h8_set_pc (sd
, bfd_get_start_address (abfd
));
5089 /* Command Line support. */
5092 /* Counting the no. of commandline arguments. */
5093 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
5096 /* Allocating memory for the argv pointers. */
5097 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
5098 * (no_of_args
+ 1)));
5100 for (i
= 0; i
< no_of_args
; i
++)
5102 /* Copying the argument string. */
5103 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
5105 h8_set_cmdline_arg (sd
, i
, NULL
);
5112 sim_set_callbacks (struct host_callback_struct
*ptr
)