sim/h8300/compile.c

   1 /*
   2  * Simulator for the Hitachi H8/300 architecture.
   3  *
   4  * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   5  *
   6  * This file is part of H8/300 sim
   7  *
   8  *
   9  * THIS SOFTWARE IS NOT COPYRIGHTED
  10  *
  11  * Cygnus offers the following for use in the public domain.  Cygnus makes no
  12  * warranty with regard to the software or its performance and the user
  13  * accepts the software "AS IS" with all faults.
  14  *
  15  * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
  16  * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
  17  * AND FITNESS FOR A PARTICULAR PURPOSE.
  18  */
  19
  20 #include <signal.h>
  21 #ifndef WIN32
  22 #include <sys/times.h>
  23 #endif
  24 #include <sys/param.h>
  25 #include "ansidecl.h"
  26 #include "sysdep.h"
  27 #include "remote-sim.h"
  28 #include "bfd.h"
  29
  30 int debug;
  31
  32
  33 #define X(op, size)  op*4+size
  34
  35 #define SP (h8300hmode ? SL:SW)
  36 #define SB 0
  37 #define SW 1
  38 #define SL 2
  39 #define OP_REG 1
  40 #define OP_DEC 2
  41 #define OP_DISP 3
  42 #define OP_INC 4
  43 #define OP_PCREL 5
  44 #define OP_MEM 6
  45 #define OP_CCR 7
  46 #define OP_IMM 8
  47 #define OP_ABS 10
  48 #define h8_opcodes ops
  49 #define DEFINE_TABLE
  50 #include "opcode/h8300.h"
  51
  52 #include "inst.h"
  53
  54 #define LOW_BYTE(x) ((x) & 0xff)
  55 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
  56 #define P(X,Y) ((X<<8) | Y)
  57
  58 #define BUILDSR()   cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
  59
  60 #define GETSR()             \
  61   c = (cpu.ccr >> 0) & 1;\
  62   v = (cpu.ccr >> 1) & 1;\
  63   nz = !((cpu.ccr >> 2) & 1);\
  64   n = (cpu.ccr >> 3) & 1;
  65
  66 #ifdef __CHAR_IS_SIGNED__
  67 #define SEXTCHAR(x) ((char)(x))
  68 #endif
  69
  70 #ifndef SEXTCHAR
  71 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
  72 #endif
  73
  74 #define UEXTCHAR(x) ((x) & 0xff)
  75 #define UEXTSHORT(x) ((x) & 0xffff)
  76 #define SEXTSHORT(x) ((short)(x))
  77
  78 static cpu_state_type cpu;
  79
  80 int h8300hmode = 0;
  81
  82
  83 static int
  84 get_now ()
  85 {
  86 #ifndef WIN32
  87   struct tms b;
  88
  89   return time (0);
  90 #endif
  91   return 0;
  92 }
  93
  94 static int
  95 now_persec ()
  96 {
  97   return 1;
  98 }
  99
 100
 101 static int
 102 bitfrom (x)
 103 {
 104   switch (x & SIZE)
 105     {
 106     case L_8:
 107       return SB;
 108     case L_16:
 109       return SW;
 110     case L_32:
 111       return SL;
 112     case L_P:
 113       return h8300hmode ? SL : SW;
 114     }
 115 }
 116
 117 static
 118 unsigned int
 119 lvalue (x, rn)
 120 {
 121   switch (x / 4)
 122     {
 123     case OP_DISP:
 124       if (rn == 8)
 125         {
 126           return X (OP_IMM, SP);
 127         }
 128       return X (OP_REG, SP);
 129
 130     case OP_MEM:
 131
 132       return X (OP_MEM, SP);
 133     default:
 134       abort ();
 135     }
 136 }
 137
 138 static unsigned int
 139 decode (addr, data, dst)
 140      int addr;
 141      unsigned char *data;
 142      decoded_inst *dst;
 143
 144 {
 145   int rs = 0;
 146   int rd = 0;
 147   int rdisp = 0;
 148   int abs = 0;
 149   int plen = 0;
 150
 151   struct h8_opcode *q = h8_opcodes;
 152   int size = 0;
 153   dst->dst.type = -1;
 154   dst->src.type = -1;
 155   /* Find the exact opcode/arg combo */
 156   while (q->name)
 157     {
 158       op_type *nib;
 159       unsigned int len = 0;
 160
 161       nib = q->data.nib;
 162
 163       while (1)
 164         {
 165           op_type looking_for = *nib;
 166           int thisnib = data[len >> 1];
 167
 168           thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
 169
 170           if (looking_for < 16 && looking_for >= 0)
 171             {
 172               if (looking_for != thisnib)
 173                 goto fail;
 174             }
 175           else
 176             {
 177               if ((int) looking_for & (int) B31)
 178                 {
 179                   if (!(((int) thisnib & 0x8) != 0))
 180                     goto fail;
 181                   looking_for = (op_type) ((int) looking_for & ~(int)
 182                                            B31);
 183                   thisnib &= 0x7;
 184                 }
 185               if ((int) looking_for & (int) B30)
 186                 {
 187                   if (!(((int) thisnib & 0x8) == 0))
 188                     goto fail;
 189                   looking_for = (op_type) ((int) looking_for & ~(int) B30);
 190                 }
 191               if (looking_for & DBIT)
 192                 {
 193                   if ((looking_for & 5) != (thisnib & 5))
 194                     goto fail;
 195                   abs = (thisnib & 0x8) ? 2 : 1;
 196                 }
 197               else if (looking_for & (REG | IND | INC | DEC))
 198                 {
 199                   if (looking_for & REG)
 200                     {
 201                       /*
 202                        * Can work out size from the
 203                        * register
 204                        */
 205                       size = bitfrom (looking_for);
 206                     }
 207                   if (looking_for & SRC)
 208                     {
 209                       rs = thisnib;
 210                     }
 211                   else
 212                     {
 213                       rd = thisnib;
 214                     }
 215                 }
 216               else if (looking_for & L_16)
 217                 {
 218                   abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
 219                   plen = 16;
 220                   if (looking_for & (PCREL | DISP))
 221                     {
 222                       abs = (short) (abs);
 223                     }
 224                 }
 225               else if (looking_for & ABSJMP)
 226                 {
 227                   abs =
 228                     (data[1] << 16)
 229                     | (data[2] << 8)
 230                     | (data[3]);
 231                 }
 232               else if (looking_for & MEMIND)
 233                 {
 234                   abs = data[1];
 235                 }
 236               else if (looking_for & L_32)
 237                 {
 238                   int i = len >> 1;
 239                   abs = (data[i] << 24)
 240                     | (data[i + 1] << 16)
 241                     | (data[i + 2] << 8)
 242                     | (data[i + 3]);
 243
 244                   plen = 32;
 245                 }
 246               else if (looking_for & L_24)
 247                 {
 248                   int i = len >> 1;
 249                   abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
 250                   plen = 24;
 251                 }
 252               else if (looking_for & IGNORE)
 253                 {
 254                   /* nothing to do */
 255                 }
 256               else if (looking_for & DISPREG)
 257                 {
 258                   rdisp = thisnib & 0x7;
 259                 }
 260               else if (looking_for & KBIT)
 261                 {
 262                   switch (thisnib)
 263                     {
 264                     case 9:
 265                       abs = 4;
 266                       break;
 267                     case 8:
 268                       abs = 2;
 269                       break;
 270                     case 0:
 271                       abs = 1;
 272                       break;
 273                     }
 274                 }
 275               else if (looking_for & L_8)
 276                 {
 277                   plen = 8;
 278
 279                   if (looking_for & PCREL)
 280                     {
 281                       abs = SEXTCHAR (data[len >> 1]);
 282                     }
 283                   else
 284                     {
 285                       abs = data[len >> 1] & 0xff;
 286                     }
 287                 }
 288               else if (looking_for & L_3)
 289                 {
 290                   plen = 3;
 291
 292                   abs = thisnib;
 293                 }
 294               else if (looking_for == E)
 295                 {
 296                   dst->op = q;
 297
 298                   /* Fill in the args */
 299                   {
 300                     op_type *args = q->args.nib;
 301                     int hadone = 0;
 302
 303                     while (*args != E)
 304                       {
 305                         int x = *args;
 306                         int rn = (x & DST) ? rd : rs;
 307                         ea_type *p;
 308
 309                         if (x & DST)
 310                           {
 311                             p = &(dst->dst);
 312                           }
 313                         else
 314                           {
 315                             p = &(dst->src);
 316                           }
 317
 318                         if (x & (IMM | KBIT | DBIT))
 319                           {
 320                             p->type = X (OP_IMM, size);
 321                             p->literal = abs;
 322                           }
 323                         else if (x & REG)
 324                           {
 325                             /* Reset the size, some
 326                                ops (like mul) have two sizes */
 327
 328                             size = bitfrom (x);
 329                             p->type = X (OP_REG, size);
 330                             p->reg = rn;
 331                           }
 332                         else if (x & INC)
 333                           {
 334                             p->type = X (OP_INC, size);
 335                             p->reg = rn & 0x7;
 336                           }
 337                         else if (x & DEC)
 338                           {
 339                             p->type = X (OP_DEC, size);
 340                             p->reg = rn & 0x7;
 341                           }
 342                         else if (x & IND)
 343                           {
 344                             p->type = X (OP_DISP, size);
 345                             p->reg = rn & 0x7;
 346                             p->literal = 0;
 347                           }
 348                         else if (x & (ABS | ABSJMP | ABSMOV))
 349                           {
 350                             p->type = X (OP_DISP, size);
 351                             p->literal = abs;
 352                             p->reg = 8;
 353                           }
 354                         else if (x & MEMIND)
 355                           {
 356                             p->type = X (OP_MEM, size);
 357                             p->literal = abs;
 358                           }
 359                         else if (x & PCREL)
 360                           {
 361                             p->type = X (OP_PCREL, size);
 362                             p->literal = abs + addr + 2;
 363                             if (x & L_16)
 364                               p->literal += 2;
 365                           }
 366                         else if (x & ABSJMP)
 367                           {
 368                             p->type = X (OP_IMM, SP);
 369                             p->literal = abs;
 370                           }
 371                         else if (x & DISP)
 372                           {
 373                             p->type = X (OP_DISP, size);
 374                             p->literal = abs;
 375                             p->reg = rdisp & 0x7;
 376                           }
 377                         else if (x & CCR)
 378                           {
 379                             p->type = OP_CCR;
 380                           }
 381                         else
 382                           printf ("Hmmmm %x", x);
 383
 384                         args++;
 385                       }
 386                   }
 387
 388                   /*
 389                      * But a jmp or a jsr gets
 390                      * automagically lvalued, since we
 391                      * branch to their address not their
 392                      * contents
 393                    */
 394                   if (q->how == O (O_JSR, SB)
 395                       || q->how == O (O_JMP, SB))
 396                     {
 397                       dst->src.type = lvalue (dst->src.type, dst->src.reg);
 398                     }
 399
 400                   if (dst->dst.type == -1)
 401                     dst->dst = dst->src;
 402
 403                   dst->opcode = q->how;
 404                   dst->cycles = q->time;
 405
 406                   /* And a jsr to 0xc4 is turned into a magic trap */
 407
 408                   if (dst->opcode == O (O_JSR, SB))
 409                     {
 410                       if (dst->src.literal == 0xc4)
 411                         {
 412                           dst->opcode = O (O_SYSCALL, SB);
 413                         }
 414                     }
 415
 416                   dst->next_pc = addr + len / 2;
 417                   return;
 418                 }
 419               else
 420                 {
 421                   printf ("Dont understand %x \n", looking_for);
 422                 }
 423             }
 424
 425           len++;
 426           nib++;
 427         }
 428
 429     fail:
 430       q++;
 431     }
 432
 433   dst->opcode = O (O_ILL, SB);
 434 }
 435
 436
 437 static void
 438 compile (pc)
 439 {
 440   int idx;
 441
 442   /* find the next cache entry to use */
 443
 444   idx = cpu.cache_top + 1;
 445   cpu.compiles++;
 446   if (idx >= cpu.csize)
 447     {
 448       idx = 1;
 449     }
 450   cpu.cache_top = idx;
 451
 452   /* Throw away its old meaning */
 453   cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
 454
 455   /* set to new address */
 456   cpu.cache[idx].oldpc = pc;
 457
 458   /* fill in instruction info */
 459   decode (pc, cpu.memory + pc, cpu.cache + idx);
 460
 461   /* point to new cache entry */
 462   cpu.cache_idx[pc] = idx;
 463 }
 464
 465
 466 static unsigned char *breg[18];
 467 static unsigned short *wreg[18];
 468 static unsigned int *lreg[18];
 469
 470 #define GET_B_REG(x) *(breg[x])
 471 #define SET_B_REG(x,y) (*(breg[x])) = (y)
 472 #define GET_W_REG(x) *(wreg[x])
 473 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
 474
 475 #define GET_L_REG(x) *(lreg[x])
 476 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
 477
 478 #define GET_MEMORY_L(x) \
 479   ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
 480
 481 #define GET_MEMORY_W(x) \
 482   ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
 483
 484
 485 #define SET_MEMORY_B(x,y) \
 486   (cpu.memory[(x)] = y)
 487
 488 #define SET_MEMORY_W(x,y) \
 489 {register unsigned char *_p = cpu.memory+x;\
 490    register int __y = y;\
 491      _p[0] = (__y)>>8;\
 492        _p[1] =(__y);     }
 493
 494 #define SET_MEMORY_L(x,y)  \
 495 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
 496    _p[0] = (__y)>>24;    _p[1] = (__y)>>16;      _p[2] = (__y)>>8;       _p[3] = (__y)>>0;}
 497
 498 #define GET_MEMORY_B(x)  (cpu.memory[x])
 499
 500 int
 501 fetch (arg, n)
 502      ea_type *arg;
 503 {
 504   int rn = arg->reg;
 505   int abs = arg->literal;
 506   int r;
 507   int t;
 508
 509   switch (arg->type)
 510     {
 511     case X (OP_REG, SB):
 512       return GET_B_REG (rn);
 513     case X (OP_REG, SW):
 514       return GET_W_REG (rn);
 515     case X (OP_REG, SL):
 516       return GET_L_REG (rn);
 517     case X (OP_IMM, SB):
 518     case X (OP_IMM, SW):
 519     case X (OP_IMM, SL):
 520       return abs;
 521     case X (OP_DEC, SB):
 522       abort ();
 523
 524     case X (OP_INC, SB):
 525       t = GET_L_REG (rn);
 526       t &= cpu.mask;
 527       r = GET_MEMORY_B (t);
 528       t++;
 529       t = t & cpu.mask;
 530       SET_L_REG (rn, t);
 531       return r;
 532       break;
 533     case X (OP_INC, SW):
 534       t = GET_L_REG (rn);
 535       t &= cpu.mask;
 536       r = GET_MEMORY_W (t);
 537       t += 2;
 538       t = t & cpu.mask;
 539       SET_L_REG (rn, t);
 540       return r;
 541     case X (OP_INC, SL):
 542       t = GET_L_REG (rn);
 543       t &= cpu.mask;
 544       r = GET_MEMORY_L (t);
 545
 546       t += 4;
 547       t = t & cpu.mask;
 548       SET_L_REG (rn, t);
 549       return r;
 550
 551     case X (OP_DISP, SB):
 552       t = GET_L_REG (rn) + abs;
 553       t &= cpu.mask;
 554       return GET_MEMORY_B (t);
 555
 556     case X (OP_DISP, SW):
 557       t = GET_L_REG (rn) + abs;
 558       t &= cpu.mask;
 559       return GET_MEMORY_W (t);
 560
 561     case X (OP_DISP, SL):
 562       t = GET_L_REG (rn) + abs;
 563       t &= cpu.mask;
 564       return GET_MEMORY_L (t);
 565
 566     case X (OP_MEM, SL):
 567       t = GET_MEMORY_L (abs);
 568       t &= cpu.mask;
 569       return t;
 570
 571     default:
 572       abort ();
 573
 574     }
 575 }
 576
 577
 578 static
 579 void
 580 store (arg, n)
 581      ea_type *arg;
 582      int n;
 583 {
 584   int rn = arg->reg;
 585   int abs = arg->literal;
 586   int t;
 587
 588   switch (arg->type)
 589     {
 590     case X (OP_REG, SB):
 591       SET_B_REG (rn, n);
 592       break;
 593     case X (OP_REG, SW):
 594       SET_W_REG (rn, n);
 595       break;
 596     case X (OP_REG, SL):
 597       SET_L_REG (rn, n);
 598       break;
 599
 600     case X (OP_DEC, SB):
 601       t = GET_L_REG (rn) - 1;
 602       t &= cpu.mask;
 603       SET_L_REG (rn, t);
 604       SET_MEMORY_B (t, n);
 605
 606       break;
 607     case X (OP_DEC, SW):
 608       t = (GET_L_REG (rn) - 2) & cpu.mask;
 609       SET_L_REG (rn, t);
 610       SET_MEMORY_W (t, n);
 611       break;
 612
 613     case X (OP_DEC, SL):
 614       t = (GET_L_REG (rn) - 4) & cpu.mask;
 615       SET_L_REG (rn, t);
 616       SET_MEMORY_L (t, n);
 617       break;
 618
 619     case X (OP_DISP, SB):
 620       t = GET_L_REG (rn) + abs;
 621       t &= cpu.mask;
 622       SET_MEMORY_B (t, n);
 623       break;
 624
 625     case X (OP_DISP, SW):
 626       t = GET_L_REG (rn) + abs;
 627       t &= cpu.mask;
 628       SET_MEMORY_W (t, n);
 629       break;
 630
 631     case X (OP_DISP, SL):
 632       t = GET_L_REG (rn) + abs;
 633       t &= cpu.mask;
 634       SET_MEMORY_L (t, n);
 635       break;
 636     default:
 637       abort ();
 638     }
 639 }
 640
 641
 642 static union
 643 {
 644   short int i;
 645   struct
 646     {
 647       char low;
 648       char high;
 649     }
 650   u;
 651 }
 652
 653 littleendian;
 654
 655 static
 656 void
 657 init_pointers ()
 658 {
 659   static int init;
 660
 661   if (!init)
 662     {
 663       int i;
 664
 665       init = 1;
 666       littleendian.i = 1;
 667
 668       cpu.memory = (unsigned char *) calloc (sizeof (char), MSIZE);
 669       cpu.cache_idx = (unsigned short *) calloc (sizeof (short), MSIZE);
 670
 671       cpu.mask = (1 << MPOWER) - 1;
 672       for (i = 0; i < 9; i++)
 673         {
 674           cpu.regs[i] = 0;
 675         }
 676
 677       for (i = 0; i < 8; i++)
 678         {
 679           unsigned char *p = (unsigned char *) (cpu.regs + i);
 680           unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
 681           unsigned short *q = (unsigned short *) (cpu.regs + i);
 682           unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
 683           cpu.regs[i] = 0x00112233;
 684           while (p < e)
 685             {
 686               if (*p == 0x22)
 687                 {
 688                   breg[i] = p;
 689                 }
 690               if (*p == 0x33)
 691                 {
 692                   breg[i + 8] = p;
 693                 }
 694               p++;
 695             }
 696           while (q < u)
 697             {
 698               if (*q == 0x2233)
 699                 {
 700                   wreg[i] = q;
 701                 }
 702               if (*q == 0x0011)
 703                 {
 704                   wreg[i + 8] = q;
 705                 }
 706               q++;
 707             }
 708           cpu.regs[i] = 0;
 709           lreg[i] = &cpu.regs[i];
 710         }
 711
 712       lreg[8] = &cpu.regs[8];
 713
 714       /* initialize the seg registers */
 715       if (!cpu.cache)
 716         sim_csize (CSIZE);
 717     }
 718 }
 719
 720 static void
 721 control_c (sig, code, scp, addr)
 722      int sig;
 723      int code;
 724      char *scp;
 725      char *addr;
 726 {
 727   cpu.exception = SIGINT;
 728 }
 729
 730 #define C (c != 0)
 731 #define Z (nz == 0)
 732 #define V (v != 0)
 733 #define N (n != 0)
 734
 735 static int
 736 mop (code, bsize, sign)
 737      decoded_inst *code;
 738      int bsize;
 739      int sign;
 740 {
 741   int multiplier;
 742   int multiplicand;
 743   int result;
 744   int n, nz;
 745
 746   if (sign)
 747     {
 748       multiplicand =
 749         bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
 750         SEXTSHORT (GET_W_REG (code->dst.reg));
 751       multiplier =
 752         bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
 753         SEXTSHORT (GET_W_REG (code->src.reg));
 754     }
 755   else
 756     {
 757       multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
 758         UEXTSHORT (GET_W_REG (code->dst.reg));
 759       multiplier =
 760         bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
 761         UEXTSHORT (GET_W_REG (code->src.reg));
 762
 763     }
 764   result = multiplier * multiplicand;
 765
 766   if (sign)
 767     {
 768       n = result & (bsize ? 0x8000 : 0x80000000);
 769       nz = result & (bsize ? 0xffff : 0xffffffff);
 770     }
 771   if (bsize)
 772     {
 773       SET_W_REG (code->dst.reg, result);
 774     }
 775   else
 776     {
 777       SET_L_REG (code->dst.reg, result);
 778     }
 779 /*  return ((n==1) << 1) | (nz==1); */
 780
 781 }
 782
 783 #define OSHIFTS(name, how) \
 784 case O(name, SB):                               \
 785 {                                               \
 786   int t;                                        \
 787   int hm = 0x80;                                \
 788   rd = GET_B_REG (code->src.reg);               \
 789   how;                                          \
 790   goto shift8;                                  \
 791 }                                               \
 792 case O(name, SW):                               \
 793 {                                               \
 794   int t;                                        \
 795   int hm = 0x8000;                              \
 796   rd = GET_W_REG (code->src.reg);               \
 797   how;                                          \
 798   goto shift16;                                 \
 799 }                                               \
 800 case O(name, SL):                               \
 801 {                                               \
 802   int t;                                        \
 803   int hm = 0x80000000;                          \
 804   rd = GET_L_REG (code->src.reg);               \
 805   how;                                          \
 806   goto shift32;                                 \
 807 }
 808
 809 #define OBITOP(name,f, s, op)                   \
 810 case  O(name, SB):                              \
 811 {                                               \
 812   int m;                                        \
 813   int b;                                        \
 814   if (f) ea = fetch (&code->dst);               \
 815   m=1<< fetch(&code->src);                      \
 816   op;                                           \
 817   if(s) store (&code->dst,ea); goto next;       \
 818 }
 819
 820 void
 821 sim_resume (step, siggnal)
 822 {
 823   static int init1;
 824   int cycles = 0;
 825   int insts = 0;
 826   int tick_start = get_now ();
 827   void (*prev) ();
 828   int poll_count = 0;
 829   int res;
 830   int tmp;
 831   int rd;
 832   int ea;
 833   int bit;
 834   int pc;
 835   int c, nz, v, n;
 836   int oldmask;
 837   init_pointers ();
 838
 839   prev = signal (SIGINT, control_c);
 840
 841   if (step)
 842     {
 843       cpu.exception = SIGTRAP;
 844     }
 845   else
 846     {
 847       cpu.exception = 0;
 848     }
 849
 850   pc = cpu.pc;
 851
 852   GETSR ();
 853   oldmask = cpu.mask;
 854   if (!h8300hmode)
 855     cpu.mask = 0xffff;
 856   do
 857     {
 858       int cidx;
 859       decoded_inst *code;
 860
 861     top:
 862       cidx = cpu.cache_idx[pc];
 863       code = cpu.cache + cidx;
 864
 865
 866 #define ALUOP(STORE, NAME, HOW) \
 867     case O(NAME,SB):  HOW; if(STORE)goto alu8;else goto just_flags_alu8;  \
 868     case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
 869     case O(NAME,SL):  HOW; if(STORE)goto alu32;else goto just_flags_alu32;
 870
 871
 872 #define LOGOP(NAME, HOW) \
 873     case O(NAME,SB): HOW; goto log8;\
 874     case O(NAME, SW): HOW; goto log16;\
 875     case O(NAME,SL): HOW; goto log32;
 876
 877
 878
 879 #if ADEBUG
 880       if (debug)
 881         {
 882           printf ("%x %d %s\n", pc, code->opcode,
 883                   code->op ? code->op->name : "**");
 884         }
 885       cpu.stats[code->opcode]++;
 886
 887 #endif
 888
 889       cycles += code->cycles;
 890       insts++;
 891       switch (code->opcode)
 892         {
 893         case 0:
 894           /*
 895            * This opcode is a fake for when we get to an
 896            * instruction which hasnt been compiled
 897            */
 898           compile (pc);
 899           goto top;
 900           break;
 901
 902
 903         case O (O_SUBX, SB):
 904           rd = fetch (&code->dst);
 905           ea = fetch (&code->src);
 906           ea = -(ea + C);
 907           res = rd + ea;
 908           goto alu8;
 909
 910         case O (O_ADDX, SB):
 911           rd = fetch (&code->dst);
 912           ea = fetch (&code->src);
 913           ea = C + ea;
 914           res = rd + ea;
 915           goto alu8;
 916
 917 #define EA    ea = fetch(&code->src);
 918 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
 919
 920           ALUOP (1, O_SUB, RD_EA;
 921                  ea = -ea;
 922                  res = rd + ea);
 923           ALUOP (1, O_NEG, EA;
 924                  ea = -ea;
 925                  rd = 0;
 926                  res = rd + ea);
 927
 928         case O (O_ADD, SB):
 929           rd = GET_B_REG (code->dst.reg);
 930           ea = fetch (&code->src);
 931           res = rd + ea;
 932           goto alu8;
 933         case O (O_ADD, SW):
 934           rd = GET_W_REG (code->dst.reg);
 935           ea = fetch (&code->src);
 936           res = rd + ea;
 937           goto alu16;
 938         case O (O_ADD, SL):
 939           rd = GET_L_REG (code->dst.reg);
 940           ea = fetch (&code->src);
 941           res = rd + ea;
 942           goto alu32;
 943
 944
 945           LOGOP (O_AND, RD_EA;
 946                  res = rd & ea);
 947
 948           LOGOP (O_OR, RD_EA;
 949                  res = rd | ea);
 950
 951           LOGOP (O_XOR, RD_EA;
 952                  res = rd ^ ea);
 953
 954
 955         case O (O_MOV_TO_MEM, SB):
 956           res = GET_B_REG (code->src.reg);
 957           goto log8;
 958         case O (O_MOV_TO_MEM, SW):
 959           res = GET_W_REG (code->src.reg);
 960           goto log16;
 961         case O (O_MOV_TO_MEM, SL):
 962           res = GET_L_REG (code->src.reg);
 963           goto log32;
 964
 965
 966         case O (O_MOV_TO_REG, SB):
 967           res = fetch (&code->src);
 968           SET_B_REG (code->dst.reg, res);
 969           goto just_flags_log8;
 970         case O (O_MOV_TO_REG, SW):
 971           res = fetch (&code->src);
 972           SET_W_REG (code->dst.reg, res);
 973           goto just_flags_log16;
 974         case O (O_MOV_TO_REG, SL):
 975           res = fetch (&code->src);
 976           SET_L_REG (code->dst.reg, res);
 977           goto just_flags_log32;
 978
 979
 980         case O (O_ADDS, SL):
 981           SET_L_REG (code->dst.reg,
 982                      GET_L_REG (code->dst.reg)
 983                      + code->src.literal);
 984
 985           goto next;
 986
 987         case O (O_SUBS, SL):
 988           SET_L_REG (code->dst.reg,
 989                      GET_L_REG (code->dst.reg)
 990                      - code->src.literal);
 991           goto next;
 992
 993         case O (O_CMP, SB):
 994           rd = fetch (&code->dst);
 995           ea = fetch (&code->src);
 996           ea = -ea;
 997           res = rd + ea;
 998           goto just_flags_alu8;
 999
1000         case O (O_CMP, SW):
1001           rd = fetch (&code->dst);
1002           ea = fetch (&code->src);
1003           ea = -ea;
1004           res = rd + ea;
1005           goto just_flags_alu16;
1006
1007         case O (O_CMP, SL):
1008           rd = fetch (&code->dst);
1009           ea = fetch (&code->src);
1010           ea = -ea;
1011           res = rd + ea;
1012           goto just_flags_alu32;
1013
1014
1015         case O (O_DEC, SB):
1016           rd = GET_B_REG (code->src.reg);
1017           ea = -1;
1018           res = rd + ea;
1019           SET_B_REG (code->src.reg, res);
1020           goto just_flags_inc8;
1021
1022         case O (O_DEC, SW):
1023           rd = GET_W_REG (code->dst.reg);
1024           ea = -code->src.literal;
1025           res = rd + ea;
1026           SET_W_REG (code->dst.reg, res);
1027           goto just_flags_inc16;
1028
1029         case O (O_DEC, SL):
1030           rd = GET_L_REG (code->dst.reg);
1031           ea = -code->src.literal;
1032           res = rd + ea;
1033           SET_L_REG (code->dst.reg, res);
1034           goto just_flags_inc32;
1035
1036
1037         case O (O_INC, SB):
1038           rd = GET_B_REG (code->src.reg);
1039           ea = 1;
1040           res = rd + ea;
1041           SET_B_REG (code->src.reg, res);
1042           goto just_flags_inc8;
1043
1044         case O (O_INC, SW):
1045           rd = GET_W_REG (code->dst.reg);
1046           ea = code->src.literal;
1047           res = rd + ea;
1048           SET_W_REG (code->dst.reg, res);
1049           goto just_flags_inc16;
1050
1051         case O (O_INC, SL):
1052           rd = GET_L_REG (code->dst.reg);
1053           ea = code->src.literal;
1054           res = rd + ea;
1055           SET_L_REG (code->dst.reg, res);
1056           goto just_flags_inc32;
1057
1058
1059 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1060
1061         case O (O_ANDC, SB):
1062           GET_CCR (rd);
1063           ea = code->src.literal;
1064           res = rd & ea;
1065           goto setc;
1066
1067         case O (O_ORC, SB):
1068           GET_CCR (rd);
1069           ea = code->src.literal;
1070           res = rd | ea;
1071           goto setc;
1072
1073         case O (O_XORC, SB):
1074           GET_CCR (rd);
1075           ea = code->src.literal;
1076           res = rd ^ ea;
1077           goto setc;
1078
1079
1080         case O (O_BRA, SB):
1081           if (1)
1082             goto condtrue;
1083           goto next;
1084
1085         case O (O_BRN, SB):
1086           if (0)
1087             goto condtrue;
1088           goto next;
1089
1090         case O (O_BHI, SB):
1091           if ((C || Z) == 0)
1092             goto condtrue;
1093           goto next;
1094
1095
1096         case O (O_BLS, SB):
1097           if ((C || Z))
1098             goto condtrue;
1099           goto next;
1100
1101         case O (O_BCS, SB):
1102           if ((C == 1))
1103             goto condtrue;
1104           goto next;
1105
1106         case O (O_BCC, SB):
1107           if ((C == 0))
1108             goto condtrue;
1109           goto next;
1110
1111         case O (O_BEQ, SB):
1112           if (Z)
1113             goto condtrue;
1114           goto next;
1115         case O (O_BGT, SB):
1116           if (((Z || (N ^ V)) == 0))
1117             goto condtrue;
1118           goto next;
1119
1120
1121         case O (O_BLE, SB):
1122           if (((Z || (N ^ V)) == 1))
1123             goto condtrue;
1124           goto next;
1125
1126         case O (O_BGE, SB):
1127           if ((N ^ V) == 0)
1128             goto condtrue;
1129           goto next;
1130         case O (O_BLT, SB):
1131           if ((N ^ V))
1132             goto condtrue;
1133           goto next;
1134         case O (O_BMI, SB):
1135           if ((N))
1136             goto condtrue;
1137           goto next;
1138         case O (O_BNE, SB):
1139           if ((Z == 0))
1140             goto condtrue;
1141           goto next;
1142
1143         case O (O_BPL, SB):
1144           if (N == 0)
1145             goto condtrue;
1146           goto next;
1147         case O (O_BVC, SB):
1148           if ((V == 0))
1149             goto condtrue;
1150           goto next;
1151         case O (O_BVS, SB):
1152           if ((V == 1))
1153             goto condtrue;
1154           goto next;
1155
1156         case O (O_SYSCALL, SB):
1157           printf ("%c", cpu.regs[2]);
1158           goto next;
1159
1160           OSHIFTS (O_NOT, rd = ~rd);
1161           OSHIFTS (O_SHLL, c = rd & hm;
1162                    rd <<= 1);
1163           OSHIFTS (O_SHLR, c = rd & 1;
1164                    rd = (unsigned int) rd >> 1);
1165           OSHIFTS (O_SHAL, c = rd & hm;
1166                    rd <<= 1);
1167           OSHIFTS (O_SHAR, t = rd & hm;
1168                    c = rd & 1;
1169                    rd >>= 1;
1170                    rd |= t;
1171                    );
1172           OSHIFTS (O_ROTL, c = rd & hm;
1173                    rd <<= 1;
1174                    rd |= C);
1175           OSHIFTS (O_ROTR, c = rd & 1;
1176                    rd = (unsigned int) rd >> 1;
1177                    if (c) rd |= hm;);
1178           OSHIFTS (O_ROTXL, t = rd & hm;
1179                    rd <<= 1;
1180                    rd |= C;
1181                    c = t;
1182                    );
1183           OSHIFTS (O_ROTXR, t = rd & 1;
1184                    rd = (unsigned int) rd >> 1;
1185                    if (C) rd |= hm; c = t;);
1186
1187         case O (O_JMP, SB):
1188           {
1189             pc = fetch (&code->src);
1190             goto end;
1191
1192           }
1193
1194         case O (O_JSR, SB):
1195           {
1196             int tmp;
1197             pc = fetch (&code->src);
1198           call:
1199             tmp = cpu.regs[7];
1200
1201             if (h8300hmode)
1202               {
1203                 tmp -= 4;
1204                 SET_MEMORY_L (tmp, code->next_pc);
1205               }
1206             else
1207               {
1208                 tmp -= 2;
1209                 SET_MEMORY_W (tmp, code->next_pc);
1210               }
1211             cpu.regs[7] = tmp;
1212
1213             goto end;
1214           }
1215         case O (O_BSR, SB):
1216           pc = code->src.literal;
1217           goto call;
1218
1219         case O (O_RTS, SB):
1220           {
1221             int tmp;
1222
1223             tmp = cpu.regs[7];
1224
1225             if (h8300hmode)
1226               {
1227                 pc = GET_MEMORY_L (tmp);
1228                 tmp += 4;
1229               }
1230             else
1231               {
1232                 pc = GET_MEMORY_W (tmp);
1233                 tmp += 2;
1234               }
1235
1236             cpu.regs[7] = tmp;
1237             goto end;
1238           }
1239
1240         case O (O_ILL, SB):
1241           cpu.exception = SIGILL;
1242           goto end;
1243         case O (O_SLEEP, SB):
1244         case O (O_BPT, SB):
1245           cpu.exception = SIGTRAP;
1246           goto end;
1247
1248           OBITOP (O_BNOT, 1, 1, ea ^= m);
1249           OBITOP (O_BTST, 1, 0, nz = ea & m);
1250           OBITOP (O_BCLR, 1, 1, ea &= ~m);
1251           OBITOP (O_BSET, 1, 1, ea |= m);
1252           OBITOP (O_BLD, 1, 0, c = ea & m);
1253           OBITOP (O_BILD, 1, 0, c = !(ea & m));
1254           OBITOP (O_BST, 1, 1, ea &= ~m;
1255                   if (C) ea |= m);
1256           OBITOP (O_BIST, 1, 1, ea &= ~m;
1257                   if (!C) ea |= m);
1258           OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1259           OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1260           OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1261           OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1262           OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1263           OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1264
1265
1266 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1267
1268         case O (O_MULS, SB):
1269           MOP (1, 1);
1270           break;
1271         case O (O_MULS, SW):
1272           MOP (0, 1);
1273           break;
1274         case O (O_MULU, SB):
1275           MOP (1, 0);
1276           break;
1277         case O (O_MULU, SW):
1278           MOP (0, 0);
1279           break;
1280
1281
1282         case O (O_DIVU, SB):
1283           {
1284             rd = GET_W_REG (code->dst.reg);
1285             ea = GET_B_REG (code->src.reg);
1286             if (ea)
1287               {
1288                 tmp = rd % ea;
1289                 rd = rd / ea;
1290               }
1291             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1292             n = ea & 0x80;
1293             nz = ea & 0xff;
1294
1295             goto next;
1296           }
1297         case O (O_DIVU, SW):
1298           {
1299             rd = GET_L_REG (code->dst.reg);
1300             ea = GET_W_REG (code->src.reg);
1301             n = ea & 0x8000;
1302             nz = ea & 0xffff;
1303             if (ea)
1304               {
1305                 tmp = rd % ea;
1306                 rd = rd / ea;
1307               }
1308             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1309             goto next;
1310           }
1311
1312         case O (O_DIVS, SB):
1313           {
1314
1315             rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1316             ea = SEXTCHAR (GET_B_REG (code->src.reg));
1317             if (ea)
1318               {
1319                 tmp = (int) rd % (int) ea;
1320                 rd = (int) rd / (int) ea;
1321                 n = rd & 0x8000;
1322                 nz = 1;
1323               }
1324             else
1325               nz = 0;
1326             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1327             goto next;
1328           }
1329         case O (O_DIVS, SW):
1330           {
1331             rd = GET_L_REG (code->dst.reg);
1332             ea = SEXTSHORT (GET_W_REG (code->src.reg));
1333             if (ea)
1334               {
1335                 tmp = (int) rd % (int) ea;
1336                 rd = (int) rd / (int) ea;
1337                 n = rd & 0x80000000;
1338                 nz = 1;
1339               }
1340             else
1341               nz = 0;
1342             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1343             goto next;
1344           }
1345         case O (O_EXTS, SW):
1346           rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst.  */
1347           ea = rd & 0x80 ? -256 : 0;
1348           res = rd + ea;
1349           goto log16;
1350         case O (O_EXTS, SL):
1351           rd = GET_W_REG (code->src.reg) & 0xffff;
1352           ea = rd & 0x8000 ? -65536 : 0;
1353           res = rd + ea;
1354           goto log32;
1355         case O (O_EXTU, SW):
1356           rd = GET_B_REG (code->src.reg + 8) & 0xff;
1357           ea = 0;
1358           res = rd + ea;
1359           goto log16;
1360         case O (O_EXTU, SL):
1361           rd = GET_W_REG (code->src.reg) & 0xffff;
1362           ea = 0;
1363           res = rd + ea;
1364           goto log32;
1365
1366         case O (O_NOP, SB):
1367           goto next;
1368
1369         default:
1370           cpu.exception = SIGILL;
1371           goto end;
1372
1373         }
1374       abort ();
1375
1376     setc:
1377       cpu.ccr = res;
1378       GETSR ();
1379       goto next;
1380
1381     condtrue:
1382       /* When a branch works */
1383       pc = code->src.literal;
1384       goto end;
1385
1386       /* Set the cond codes from res */
1387     bitop:
1388
1389       /* Set the flags after an 8 bit inc/dec operation */
1390     just_flags_inc8:
1391       n = res & 0x80;
1392       nz = res & 0xff;
1393       v = (rd & 0x7f) == 0x7f;
1394       goto next;
1395
1396
1397       /* Set the flags after an 16 bit inc/dec operation */
1398     just_flags_inc16:
1399       n = res & 0x8000;
1400       nz = res & 0xffff;
1401       v = (rd & 0x7fff) == 0x7fff;
1402       goto next;
1403
1404
1405       /* Set the flags after an 32 bit inc/dec operation */
1406     just_flags_inc32:
1407       n = res & 0x80000000;
1408       nz = res & 0xffffffff;
1409       v = (rd & 0x7fffffff) == 0x7fffffff;
1410       goto next;
1411
1412
1413     shift8:
1414       /* Set flags after an 8 bit shift op, carry set in insn */
1415       n = (rd & 0x80);
1416       v = 0;
1417       nz = rd & 0xff;
1418       SET_B_REG (code->src.reg, rd);
1419       goto next;
1420
1421
1422     shift16:
1423       /* Set flags after an 16 bit shift op, carry set in insn */
1424       n = (rd & 0x8000);
1425       v = 0;
1426       nz = rd & 0xffff;
1427
1428       SET_W_REG (code->src.reg, rd);
1429       goto next;
1430
1431     shift32:
1432       /* Set flags after an 32 bit shift op, carry set in insn */
1433       n = (rd & 0x80000000);
1434       v = 0;
1435       nz = rd & 0xffffffff;
1436       SET_L_REG (code->src.reg, rd);
1437       goto next;
1438
1439     log32:
1440       store (&code->dst, res);
1441     just_flags_log32:
1442       /* flags after a 32bit logical operation */
1443       n = res & 0x80000000;
1444       nz = res & 0xffffffff;
1445       v = 0;
1446       goto next;
1447
1448     log16:
1449       store (&code->dst, res);
1450     just_flags_log16:
1451       /* flags after a 16bit logical operation */
1452       n = res & 0x8000;
1453       nz = res & 0xffff;
1454       v = 0;
1455       goto next;
1456
1457
1458     log8:
1459       store (&code->dst, res);
1460     just_flags_log8:
1461       n = res & 0x80;
1462       nz = res & 0xff;
1463       v = 0;
1464       goto next;
1465
1466     alu8:
1467       SET_B_REG (code->dst.reg, res);
1468     just_flags_alu8:
1469       n = res & 0x80;
1470       nz = res & 0xff;
1471       v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1472       c = (res & 0x100);
1473       goto next;
1474
1475     alu16:
1476       SET_W_REG (code->dst.reg, res);
1477     just_flags_alu16:
1478       n = res & 0x8000;
1479       nz = res & 0xffff;
1480       v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1481       c = (res & 0x10000);
1482       goto next;
1483
1484     alu32:
1485       SET_L_REG (code->dst.reg, res);
1486     just_flags_alu32:
1487       n = res & 0x80000000;
1488       nz = res & 0xffffffff;
1489       v = ((ea & 0x80000000) == (rd & 0x80000000))
1490         && ((ea & 0x80000000) != (res & 0x80000000));
1491       switch (code->opcode / 4)
1492         {
1493         case O_ADD:
1494           c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1495           break;
1496         case O_SUB:
1497         case O_CMP:
1498           c = (unsigned) rd < (unsigned) -ea;
1499           break;
1500         case O_NEG:
1501           c = res != 0;
1502           break;
1503         }
1504       goto next;
1505
1506     next:;
1507       pc = code->next_pc;
1508
1509     end:
1510       ;
1511       /*      if (cpu.regs[8] ) abort(); */
1512
1513 #if defined (WIN32)
1514       /* Poll after every 100th insn, */
1515       if (poll_count++ > 100)
1516         {
1517           poll_count = 0;
1518           if (win32pollquit())
1519             {
1520               control_c();
1521             }
1522         }
1523 #endif
1524 #if defined(__GO32__)
1525       /* Poll after every 100th insn, */
1526       if (poll_count++ > 100)
1527         {
1528           poll_count = 0;
1529           if (kbhit ())
1530             {
1531               int c = getkey ();
1532               control_c ();
1533             }
1534         }
1535 #endif
1536
1537     }
1538   while (!cpu.exception);
1539   cpu.ticks += get_now () - tick_start;
1540   cpu.cycles += cycles;
1541   cpu.insts += insts;
1542
1543   cpu.pc = pc;
1544   BUILDSR ();
1545   cpu.mask = oldmask;
1546   signal (SIGINT, prev);
1547 }
1548
1549
1550 int
1551 sim_write (addr, buffer, size)
1552      SIM_ADDR addr;
1553      unsigned char *buffer;
1554      int size;
1555 {
1556   int i;
1557
1558   init_pointers ();
1559   if (addr < 0 || addr + size > MSIZE)
1560     return 0;
1561   for (i = 0; i < size; i++)
1562     {
1563       cpu.memory[addr + i] = buffer[i];
1564       cpu.cache_idx[addr + i] = 0;
1565     }
1566   return size;
1567 }
1568
1569 int
1570 sim_read (addr, buffer, size)
1571      SIM_ADDR addr;
1572      unsigned char *buffer;
1573      int size;
1574 {
1575   init_pointers ();
1576   if (addr < 0 || addr + size > MSIZE)
1577     return 0;
1578   memcpy (buffer, cpu.memory + addr, size);
1579   return size;
1580 }
1581
1582
1583 #define R0_REGNUM       0
1584 #define R1_REGNUM       1
1585 #define R2_REGNUM       2
1586 #define R3_REGNUM       3
1587 #define R4_REGNUM       4
1588 #define R5_REGNUM       5
1589 #define R6_REGNUM       6
1590 #define R7_REGNUM       7
1591
1592 #define SP_REGNUM       R7_REGNUM       /* Contains address of top of stack */
1593 #define FP_REGNUM       R6_REGNUM       /* Contains address of executing
1594                                            * stack frame */
1595
1596 #define CCR_REGNUM      8       /* Contains processor status */
1597 #define PC_REGNUM       9       /* Contains program counter */
1598
1599 #define CYCLE_REGNUM    10
1600 #define INST_REGNUM     11
1601 #define TICK_REGNUM     12
1602
1603
1604 void
1605 sim_store_register (rn, value)
1606      int rn;
1607      unsigned char *value;
1608 {
1609   int longval;
1610   int shortval;
1611   int intval;
1612   longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1613   shortval = (value[0] << 8) | (value[1]);
1614   intval = h8300hmode ? longval : shortval;
1615
1616   init_pointers ();
1617   switch (rn)
1618     {
1619     case PC_REGNUM:
1620       cpu.pc = intval;
1621       break;
1622     default:
1623       abort ();
1624     case R0_REGNUM:
1625     case R1_REGNUM:
1626     case R2_REGNUM:
1627     case R3_REGNUM:
1628     case R4_REGNUM:
1629     case R5_REGNUM:
1630     case R6_REGNUM:
1631     case R7_REGNUM:
1632       cpu.regs[rn] = intval;
1633       break;
1634     case CCR_REGNUM:
1635       cpu.ccr = intval;
1636       break;
1637     case CYCLE_REGNUM:
1638       cpu.cycles = longval;
1639       break;
1640
1641     case INST_REGNUM:
1642       cpu.insts = longval;
1643       break;
1644
1645     case TICK_REGNUM:
1646       cpu.ticks = longval;
1647       break;
1648     }
1649 }
1650
1651 void
1652 sim_fetch_register (rn, buf)
1653      int rn;
1654      unsigned char *buf;
1655 {
1656   int v;
1657   int longreg = 0;
1658
1659   init_pointers ();
1660
1661   switch (rn)
1662     {
1663     default:
1664       abort ();
1665     case 8:
1666       v = cpu.ccr;
1667       break;
1668     case 9:
1669       v = cpu.pc;
1670       break;
1671     case R0_REGNUM:
1672     case R1_REGNUM:
1673     case R2_REGNUM:
1674     case R3_REGNUM:
1675     case R4_REGNUM:
1676     case R5_REGNUM:
1677     case R6_REGNUM:
1678     case R7_REGNUM:
1679       v = cpu.regs[rn];
1680       break;
1681     case 10:
1682       v = cpu.cycles;
1683       longreg = 1;
1684       break;
1685     case 11:
1686       v = cpu.ticks;
1687       longreg = 1;
1688       break;
1689     case 12:
1690       v = cpu.insts;
1691       longreg = 1;
1692       break;
1693     }
1694   if (h8300hmode || longreg)
1695     {
1696       buf[0] = v >> 24;
1697       buf[1] = v >> 16;
1698       buf[2] = v >> 8;
1699       buf[3] = v >> 0;
1700     }
1701   else
1702     {
1703       buf[0] = v >> 8;
1704       buf[1] = v;
1705     }
1706 }
1707
1708 void
1709 sim_stop_reason (reason, sigrc)
1710      enum sim_stop *reason;
1711      int *sigrc;
1712 {
1713   *reason = sim_stopped;
1714   *sigrc = cpu.exception;
1715 }
1716
1717 sim_csize (n)
1718 {
1719   if (cpu.cache)
1720     free (cpu.cache);
1721   if (n < 2)
1722     n = 2;
1723   cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1724   memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1725   cpu.csize = n;
1726 }
1727
1728
1729 void
1730 sim_info (verbose)
1731      int verbose;
1732 {
1733   double timetaken = (double) cpu.ticks / (double) now_persec ();
1734   double virttime = cpu.cycles / 10.0e6;
1735
1736   printf_filtered ("\n\n#instructions executed  %10d\n", cpu.insts);
1737   printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1738   printf_filtered ("#real time taken        %10.4f\n", timetaken);
1739   printf_filtered ("#virtual time taked     %10.4f\n", virttime);
1740   if (timetaken != 0.0)
1741     printf_filtered ("#simulation ratio       %10.4f\n", virttime / timetaken);
1742   printf_filtered ("#compiles               %10d\n", cpu.compiles);
1743   printf_filtered ("#cache size             %10d\n", cpu.csize);
1744
1745 #ifdef ADEBUG
1746   if (verbose)
1747     {
1748       int i;
1749       for (i = 0; i < O_LAST; i++)
1750         {
1751           if (cpu.stats[i])
1752             printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1753         }
1754     }
1755 #endif
1756 }
1757
1758 /* Indicate whether the cpu is an h8/300 or h8/300h.
1759    FLAG is non-zero for the h8/300h.  */
1760
1761 void
1762 set_h8300h (flag)
1763      int flag;
1764 {
1765   h8300hmode = flag;
1766 }
1767
1768 void
1769 sim_kill ()
1770 {
1771   /* nothing to do */
1772 }
1773
1774 void
1775 sim_open (args)
1776      char *args;
1777 {
1778   /* nothing to do */
1779 }
1780
1781 void
1782 sim_close (quitting)
1783      int quitting;
1784 {
1785   /* nothing to do */
1786 }
1787
1788 /* Called by gdb to load a program into memory.  */
1789
1790 int
1791 sim_load (prog, from_tty)
1792      char *prog;
1793      int from_tty;
1794 {
1795   bfd *abfd;
1796
1797   /* See if the file is for the h8/300 or h8/300h.  */
1798   /* ??? This may not be the most efficient way.  The z8k simulator
1799      does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO).  */
1800   if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1801     {
1802       if (bfd_check_format (abfd, bfd_object))
1803         set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1804       bfd_close (abfd);
1805     }
1806
1807   /* Return non-zero so gdb will handle it.  */
1808   return 1;
1809 }
1810
1811 void
1812 sim_create_inferior (start_address, argv, env)
1813      SIM_ADDR start_address;
1814      char **argv;
1815      char **env;
1816 {
1817   cpu.pc = start_address;
1818 }