2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size
PARAMS ((int));
55 #define X(op, size) op * 4 + size
57 #define SP (h8300hmode ? SL : SW)
71 #define h8_opcodes ops
73 #include "opcode/h8300.h"
77 /* The rate at which to call the host's poll_quit callback. */
79 #define POLL_QUIT_INTERVAL 0x80000
81 #define LOW_BYTE(x) ((x) & 0xff)
82 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
83 #define P(X,Y) ((X << 8) | Y)
85 #define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
86 (N << 3) | (Z << 2) | (V<<1) | C;
89 if (h8300smode) cpu.exr = (trace<<7) | intMask;
92 c = (cpu.ccr >> 0) & 1;\
93 v = (cpu.ccr >> 1) & 1;\
94 nz = !((cpu.ccr >> 2) & 1);\
95 n = (cpu.ccr >> 3) & 1;\
96 u = (cpu.ccr >> 4) & 1;\
97 h = (cpu.ccr >> 5) & 1;\
98 ui = ((cpu.ccr >> 6) & 1);\
99 intMaskBit = (cpu.ccr >> 7) & 1;
103 trace = (cpu.exr >> 7) & 1;\
104 intMask = cpu.exr & 7; }
106 #ifdef __CHAR_IS_SIGNED__
107 #define SEXTCHAR(x) ((char) (x))
111 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
114 #define UEXTCHAR(x) ((x) & 0xff)
115 #define UEXTSHORT(x) ((x) & 0xffff)
116 #define SEXTSHORT(x) ((short) (x))
118 static cpu_state_type cpu
;
123 static int memory_size
;
128 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
149 return h8300hmode
? SL
: SW
;
161 return X (OP_IMM
, SP
);
163 return X (OP_REG
, SP
);
166 return X (OP_MEM
, SP
);
169 abort (); /* ?? May be something more usefull? */
174 decode (addr
, data
, dst
)
192 /* Find the exact opcode/arg combo. */
193 for (q
= h8_opcodes
; q
->name
; q
++)
195 op_type
*nib
= q
->data
.nib
;
196 unsigned int len
= 0;
200 op_type looking_for
= *nib
;
201 int thisnib
= data
[len
>> 1];
203 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
205 if (looking_for
< 16 && looking_for
>= 0)
207 if (looking_for
!= thisnib
)
212 if ((int) looking_for
& (int) B31
)
214 if (!(((int) thisnib
& 0x8) != 0))
217 looking_for
= (op_type
) ((int) looking_for
& ~(int) B31
);
221 if ((int) looking_for
& (int) B30
)
223 if (!(((int) thisnib
& 0x8) == 0))
226 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
229 if (looking_for
& DBIT
)
231 /* Exclude adds/subs by looking at bit 0 and 2, and
232 make sure the operand size, either w or l,
233 matches by looking at bit 1. */
234 if ((looking_for
& 7) != (thisnib
& 7))
237 abs
= (thisnib
& 0x8) ? 2 : 1;
239 else if (looking_for
& (REG
| IND
| INC
| DEC
))
241 if (looking_for
& REG
)
243 /* Can work out size from the register. */
244 size
= bitfrom (looking_for
);
246 if (looking_for
& SRC
)
251 else if (looking_for
& L_16
)
253 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
255 if (looking_for
& (PCREL
| DISP
))
260 else if (looking_for
& ABSJMP
)
262 abs
= (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
264 else if (looking_for
& MEMIND
)
268 else if (looking_for
& L_32
)
272 abs
= (data
[i
] << 24)
273 | (data
[i
+ 1] << 16)
279 else if (looking_for
& L_24
)
283 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
286 else if (looking_for
& IGNORE
)
290 else if (looking_for
& DISPREG
)
292 rdisp
= thisnib
& 0x7;
294 else if (looking_for
& KBIT
)
311 else if (looking_for
& L_8
)
315 if (looking_for
& PCREL
)
317 abs
= SEXTCHAR (data
[len
>> 1]);
319 else if (looking_for
& ABS8MEM
)
322 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
323 abs
|= data
[len
>> 1] & 0xff;
327 abs
= data
[len
>> 1] & 0xff;
330 else if (looking_for
& L_3
)
336 else if (looking_for
== E
)
340 /* Fill in the args. */
342 op_type
*args
= q
->args
.nib
;
348 int rn
= (x
& DST
) ? rd
: rs
;
358 p
->type
= X (OP_IMM
, size
);
361 else if (x
& (IMM
| KBIT
| DBIT
))
363 p
->type
= X (OP_IMM
, size
);
369 Some ops (like mul) have two sizes. */
372 p
->type
= X (OP_REG
, size
);
377 p
->type
= X (OP_INC
, size
);
382 p
->type
= X (OP_DEC
, size
);
387 p
->type
= X (OP_DISP
, size
);
391 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
393 p
->type
= X (OP_DISP
, size
);
399 p
->type
= X (OP_MEM
, size
);
404 p
->type
= X (OP_PCREL
, size
);
405 p
->literal
= abs
+ addr
+ 2;
411 p
->type
= X (OP_IMM
, SP
);
416 p
->type
= X (OP_DISP
, size
);
418 p
->reg
= rdisp
& 0x7;
429 printf ("Hmmmm %x", x
);
435 /* But a jmp or a jsr gets automagically lvalued,
436 since we branch to their address not their
438 if (q
->how
== O (O_JSR
, SB
)
439 || q
->how
== O (O_JMP
, SB
))
441 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
444 if (dst
->dst
.type
== -1)
447 dst
->opcode
= q
->how
;
448 dst
->cycles
= q
->time
;
450 /* And a jsr to 0xc4 is turned into a magic trap. */
452 if (dst
->opcode
== O (O_JSR
, SB
))
454 if (dst
->src
.literal
== 0xc4)
456 dst
->opcode
= O (O_SYSCALL
, SB
);
460 dst
->next_pc
= addr
+ len
/ 2;
464 printf ("Don't understand %x \n", looking_for
);
475 /* Fell off the end. */
476 dst
->opcode
= O (O_ILL
, SB
);
484 /* Find the next cache entry to use. */
485 idx
= cpu
.cache_top
+ 1;
487 if (idx
>= cpu
.csize
)
493 /* Throw away its old meaning. */
494 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
496 /* Set to new address. */
497 cpu
.cache
[idx
].oldpc
= pc
;
499 /* Fill in instruction info. */
500 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
502 /* Point to new cache entry. */
503 cpu
.cache_idx
[pc
] = idx
;
507 static unsigned char *breg
[18];
508 static unsigned short *wreg
[18];
509 static unsigned int *lreg
[18];
511 #define GET_B_REG(x) *(breg[x])
512 #define SET_B_REG(x,y) (*(breg[x])) = (y)
513 #define GET_W_REG(x) *(wreg[x])
514 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
516 #define GET_L_REG(x) *(lreg[x])
517 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
519 #define GET_MEMORY_L(x) \
521 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
522 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
523 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
524 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
526 #define GET_MEMORY_W(x) \
528 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
529 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
532 #define GET_MEMORY_B(x) \
533 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
535 #define SET_MEMORY_L(x,y) \
536 { register unsigned char *_p; register int __y = y; \
537 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
538 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
539 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
541 #define SET_MEMORY_W(x,y) \
542 { register unsigned char *_p; register int __y = y; \
543 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
544 _p[0] = (__y)>>8; _p[1] =(__y);}
546 #define SET_MEMORY_B(x,y) \
547 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
554 int abs
= arg
->literal
;
561 return GET_B_REG (rn
);
563 return GET_W_REG (rn
);
565 return GET_L_REG (rn
);
576 r
= GET_MEMORY_B (t
);
585 r
= GET_MEMORY_W (t
);
593 r
= GET_MEMORY_L (t
);
600 case X (OP_DISP
, SB
):
601 t
= GET_L_REG (rn
) + abs
;
603 return GET_MEMORY_B (t
);
605 case X (OP_DISP
, SW
):
606 t
= GET_L_REG (rn
) + abs
;
608 return GET_MEMORY_W (t
);
610 case X (OP_DISP
, SL
):
611 t
= GET_L_REG (rn
) + abs
;
613 return GET_MEMORY_L (t
);
616 t
= GET_MEMORY_L (abs
);
621 t
= GET_MEMORY_W (abs
);
626 abort (); /* ?? May be something more usefull? */
638 int abs
= arg
->literal
;
654 t
= GET_L_REG (rn
) - 1;
661 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
667 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
672 case X (OP_DISP
, SB
):
673 t
= GET_L_REG (rn
) + abs
;
678 case X (OP_DISP
, SW
):
679 t
= GET_L_REG (rn
) + abs
;
684 case X (OP_DISP
, SL
):
685 t
= GET_L_REG (rn
) + abs
;
721 memory_size
= H8300S_MSIZE
;
723 memory_size
= H8300H_MSIZE
;
725 memory_size
= H8300_MSIZE
;
726 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
727 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
728 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
730 /* `msize' must be a power of two. */
731 if ((memory_size
& (memory_size
- 1)) != 0)
733 cpu
.mask
= memory_size
- 1;
735 for (i
= 0; i
< 9; i
++)
740 for (i
= 0; i
< 8; i
++)
742 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
743 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
744 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
745 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
746 cpu
.regs
[i
] = 0x00112233;
772 lreg
[i
] = &cpu
.regs
[i
];
775 lreg
[8] = &cpu
.regs
[8];
777 /* Initialize the seg registers. */
779 sim_set_simcache_size (CSIZE
);
784 control_c (sig
, code
, scp
, addr
)
790 cpu
.state
= SIM_STATE_STOPPED
;
791 cpu
.exception
= SIGINT
;
801 #define I (intMaskBit != 0)
804 mop (code
, bsize
, sign
)
817 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
818 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
820 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
821 SEXTSHORT (GET_W_REG (code
->src
.reg
));
825 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
826 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
828 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
829 UEXTSHORT (GET_W_REG (code
->src
.reg
));
832 result
= multiplier
* multiplicand
;
836 n
= result
& (bsize
? 0x8000 : 0x80000000);
837 nz
= result
& (bsize
? 0xffff : 0xffffffff);
841 SET_W_REG (code
->dst
.reg
, result
);
845 SET_L_REG (code
->dst
.reg
, result
);
848 return ((n
== 1) << 1) | (nz
== 1);
852 #define ONOT(name, how) \
857 rd = GET_B_REG (code->src.reg); \
865 rd = GET_W_REG (code->src.reg); \
872 int hm = 0x80000000; \
873 rd = GET_L_REG (code->src.reg); \
878 #define OSHIFTS(name, how1, how2) \
883 rd = GET_B_REG (code->src.reg); \
884 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
898 rd = GET_W_REG (code->src.reg); \
899 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
912 int hm = 0x80000000; \
913 rd = GET_L_REG (code->src.reg); \
914 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
925 #define OBITOP(name,f, s, op) \
930 if (f) ea = fetch (&code->dst); \
931 m=1<< fetch (&code->src); \
933 if (s) store (&code->dst,ea); goto next; \
940 cpu
.state
= SIM_STATE_STOPPED
;
941 cpu
.exception
= SIGINT
;
954 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
955 #define FP_REGNUM R6_REGNUM /* Contains address of executing
958 #define CCR_REGNUM 8 /* Contains processor status */
959 #define PC_REGNUM 9 /* Contains program counter */
961 #define CYCLE_REGNUM 10
963 #define EXR_REGNUM 11
964 #define INST_REGNUM 12
965 #define TICK_REGNUM 13
968 sim_resume (sd
, step
, siggnal
)
974 int tick_start
= get_now ();
983 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
988 prev
= signal (SIGINT
, control_c
);
992 cpu
.state
= SIM_STATE_STOPPED
;
993 cpu
.exception
= SIGTRAP
;
997 cpu
.state
= SIM_STATE_RUNNING
;
1003 /* The PC should never be odd. */
1019 cidx
= cpu
.cache_idx
[pc
];
1020 code
= cpu
.cache
+ cidx
;
1023 #define ALUOP(STORE, NAME, HOW) \
1024 case O (NAME,SB): HOW; if (STORE)goto alu8;else goto just_flags_alu8; \
1025 case O (NAME, SW): HOW; if (STORE)goto alu16;else goto just_flags_alu16; \
1026 case O (NAME,SL): HOW; if (STORE)goto alu32;else goto just_flags_alu32;
1029 #define LOGOP(NAME, HOW) \
1030 case O (NAME,SB): HOW; goto log8;\
1031 case O (NAME, SW): HOW; goto log16;\
1032 case O (NAME,SL): HOW; goto log32;
1039 printf ("%x %d %s\n", pc
, code
->opcode
,
1040 code
->op
? code
->op
->name
: "**");
1042 cpu
.stats
[code
->opcode
]++;
1048 cycles
+= code
->cycles
;
1052 switch (code
->opcode
)
1056 * This opcode is a fake for when we get to an
1057 * instruction which hasnt been compiled
1064 case O (O_SUBX
, SB
):
1065 rd
= fetch (&code
->dst
);
1066 ea
= fetch (&code
->src
);
1071 case O (O_ADDX
, SB
):
1072 rd
= fetch (&code
->dst
);
1073 ea
= fetch (&code
->src
);
1078 #define EA ea = fetch (&code->src);
1079 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1081 ALUOP (1, O_SUB
, RD_EA
;
1084 ALUOP (1, O_NEG
, EA
;
1090 rd
= GET_B_REG (code
->dst
.reg
);
1091 ea
= fetch (&code
->src
);
1095 rd
= GET_W_REG (code
->dst
.reg
);
1096 ea
= fetch (&code
->src
);
1100 rd
= GET_L_REG (code
->dst
.reg
);
1101 ea
= fetch (&code
->src
);
1106 LOGOP (O_AND
, RD_EA
;
1112 LOGOP (O_XOR
, RD_EA
;
1116 case O (O_MOV_TO_MEM
, SB
):
1117 res
= GET_B_REG (code
->src
.reg
);
1119 case O (O_MOV_TO_MEM
, SW
):
1120 res
= GET_W_REG (code
->src
.reg
);
1122 case O (O_MOV_TO_MEM
, SL
):
1123 res
= GET_L_REG (code
->src
.reg
);
1127 case O (O_MOV_TO_REG
, SB
):
1128 res
= fetch (&code
->src
);
1129 SET_B_REG (code
->dst
.reg
, res
);
1130 goto just_flags_log8
;
1131 case O (O_MOV_TO_REG
, SW
):
1132 res
= fetch (&code
->src
);
1133 SET_W_REG (code
->dst
.reg
, res
);
1134 goto just_flags_log16
;
1135 case O (O_MOV_TO_REG
, SL
):
1136 res
= fetch (&code
->src
);
1137 SET_L_REG (code
->dst
.reg
, res
);
1138 goto just_flags_log32
;
1140 case O (O_EEPMOV
, SB
):
1141 case O (O_EEPMOV
, SW
):
1142 if (h8300hmode
||h8300smode
)
1144 register unsigned char *_src
,*_dst
;
1145 unsigned int count
= (code
->opcode
== O(O_EEPMOV
, SW
))?cpu
.regs
[R4_REGNUM
]&0xffff:
1146 cpu
.regs
[R4_REGNUM
]&0xff;
1148 _src
= cpu
.regs
[R5_REGNUM
] < memory_size
? cpu
.memory
+cpu
.regs
[R5_REGNUM
] :
1149 cpu
.eightbit
+ (cpu
.regs
[R5_REGNUM
] & 0xff);
1150 if ((_src
+count
)>=(cpu
.memory
+memory_size
))
1152 if ((_src
+count
)>=(cpu
.eightbit
+0x100))
1155 _dst
= cpu
.regs
[R6_REGNUM
] < memory_size
? cpu
.memory
+cpu
.regs
[R6_REGNUM
] :
1156 cpu
.eightbit
+ (cpu
.regs
[R6_REGNUM
] & 0xff);
1157 if ((_dst
+count
)>=(cpu
.memory
+memory_size
))
1159 if ((_dst
+count
)>=(cpu
.eightbit
+0x100))
1162 memcpy(_dst
,_src
,count
);
1164 cpu
.regs
[R5_REGNUM
]+=count
;
1165 cpu
.regs
[R6_REGNUM
]+=count
;
1166 cpu
.regs
[R4_REGNUM
]&=(code
->opcode
== O(O_EEPMOV
, SW
))?(~0xffff):(~0xff);
1172 case O (O_ADDS
, SL
):
1173 SET_L_REG (code
->dst
.reg
,
1174 GET_L_REG (code
->dst
.reg
)
1175 + code
->src
.literal
);
1179 case O (O_SUBS
, SL
):
1180 SET_L_REG (code
->dst
.reg
,
1181 GET_L_REG (code
->dst
.reg
)
1182 - code
->src
.literal
);
1186 rd
= fetch (&code
->dst
);
1187 ea
= fetch (&code
->src
);
1190 goto just_flags_alu8
;
1193 rd
= fetch (&code
->dst
);
1194 ea
= fetch (&code
->src
);
1197 goto just_flags_alu16
;
1200 rd
= fetch (&code
->dst
);
1201 ea
= fetch (&code
->src
);
1204 goto just_flags_alu32
;
1208 rd
= GET_B_REG (code
->src
.reg
);
1211 SET_B_REG (code
->src
.reg
, res
);
1212 goto just_flags_inc8
;
1215 rd
= GET_W_REG (code
->dst
.reg
);
1216 ea
= -code
->src
.literal
;
1218 SET_W_REG (code
->dst
.reg
, res
);
1219 goto just_flags_inc16
;
1222 rd
= GET_L_REG (code
->dst
.reg
);
1223 ea
= -code
->src
.literal
;
1225 SET_L_REG (code
->dst
.reg
, res
);
1226 goto just_flags_inc32
;
1230 rd
= GET_B_REG (code
->src
.reg
);
1233 SET_B_REG (code
->src
.reg
, res
);
1234 goto just_flags_inc8
;
1237 rd
= GET_W_REG (code
->dst
.reg
);
1238 ea
= code
->src
.literal
;
1240 SET_W_REG (code
->dst
.reg
, res
);
1241 goto just_flags_inc16
;
1244 rd
= GET_L_REG (code
->dst
.reg
);
1245 ea
= code
->src
.literal
;
1247 SET_L_REG (code
->dst
.reg
, res
);
1248 goto just_flags_inc32
;
1250 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1251 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1255 res
= fetch (&code
->src
);
1259 if (code
->src
.type
== OP_CCR
)
1263 else if (code
->src
.type
== OP_EXR
&& h8300smode
)
1269 store (&code
->dst
, res
);
1272 case O (O_ANDC
, SB
):
1273 if (code
->dst
.type
== OP_CCR
)
1277 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1283 ea
= code
->src
.literal
;
1288 if (code
->dst
.type
== OP_CCR
)
1292 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1298 ea
= code
->src
.literal
;
1302 case O (O_XORC
, SB
):
1303 if (code
->dst
.type
== OP_CCR
)
1307 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1313 ea
= code
->src
.literal
;
1354 if (((Z
|| (N
^ V
)) == 0))
1360 if (((Z
|| (N
^ V
)) == 1))
1394 case O (O_SYSCALL
, SB
):
1396 char c
= cpu
.regs
[2];
1397 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1401 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1403 c
= rd
& hm
; v
= 0; rd
<<= 1,
1404 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1406 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1407 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1409 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1410 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1412 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1413 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1);
1415 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1416 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1418 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1419 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1421 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1422 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1424 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1425 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1429 pc
= fetch (&code
->src
);
1437 pc
= fetch (&code
->src
);
1444 SET_MEMORY_L (tmp
, code
->next_pc
);
1449 SET_MEMORY_W (tmp
, code
->next_pc
);
1456 pc
= code
->src
.literal
;
1467 pc
= GET_MEMORY_L (tmp
);
1472 pc
= GET_MEMORY_W (tmp
);
1481 cpu
.state
= SIM_STATE_STOPPED
;
1482 cpu
.exception
= SIGILL
;
1484 case O (O_SLEEP
, SN
):
1485 /* FIXME: Doesn't this break for breakpoints when r0
1486 contains just the right (er, wrong) value? */
1487 cpu
.state
= SIM_STATE_STOPPED
;
1488 /* The format of r0 is defined by target newlib. Expand
1489 the macros here instead of looking for .../sys/wait.h. */
1490 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1491 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1492 if (! SIM_WIFEXITED (cpu
.regs
[0]) && SIM_WIFSIGNALED (cpu
.regs
[0]))
1493 cpu
.exception
= SIGILL
;
1495 cpu
.exception
= SIGTRAP
;
1498 cpu
.state
= SIM_STATE_STOPPED
;
1499 cpu
.exception
= SIGTRAP
;
1502 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1503 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1504 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1505 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1506 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1507 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1508 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1510 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1512 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1513 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1514 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1515 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1516 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1517 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1519 #define MOP(bsize, signed) \
1520 mop (code, bsize, signed); \
1523 case O (O_MULS
, SB
):
1526 case O (O_MULS
, SW
):
1529 case O (O_MULU
, SB
):
1532 case O (O_MULU
, SW
):
1537 if (!h8300smode
|| code
->src
.type
!= X (OP_REG
, SL
))
1539 switch (code
->src
.reg
)
1549 res
= fetch (&code
->src
);
1550 store (&code
->src
,res
|0x80);
1551 goto just_flags_log8
;
1553 case O (O_DIVU
, SB
):
1555 rd
= GET_W_REG (code
->dst
.reg
);
1556 ea
= GET_B_REG (code
->src
.reg
);
1559 tmp
= (unsigned) rd
% ea
;
1560 rd
= (unsigned) rd
/ ea
;
1562 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1568 case O (O_DIVU
, SW
):
1570 rd
= GET_L_REG (code
->dst
.reg
);
1571 ea
= GET_W_REG (code
->src
.reg
);
1576 tmp
= (unsigned) rd
% ea
;
1577 rd
= (unsigned) rd
/ ea
;
1579 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1583 case O (O_DIVS
, SB
):
1586 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1587 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1590 tmp
= (int) rd
% (int) ea
;
1591 rd
= (int) rd
/ (int) ea
;
1597 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1600 case O (O_DIVS
, SW
):
1602 rd
= GET_L_REG (code
->dst
.reg
);
1603 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1606 tmp
= (int) rd
% (int) ea
;
1607 rd
= (int) rd
/ (int) ea
;
1608 n
= rd
& 0x80000000;
1613 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1616 case O (O_EXTS
, SW
):
1617 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1618 ea
= rd
& 0x80 ? -256 : 0;
1621 case O (O_EXTS
, SL
):
1622 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1623 ea
= rd
& 0x8000 ? -65536 : 0;
1626 case O (O_EXTU
, SW
):
1627 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1631 case O (O_EXTU
, SL
):
1632 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1642 int nregs
, firstreg
, i
;
1644 nregs
= GET_MEMORY_B (pc
+ 1);
1647 firstreg
= GET_MEMORY_B (pc
+ 3);
1649 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1652 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1659 int nregs
, firstreg
, i
;
1661 nregs
= GET_MEMORY_B (pc
+ 1);
1664 firstreg
= GET_MEMORY_B (pc
+ 3);
1666 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1668 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1676 cpu
.state
= SIM_STATE_STOPPED
;
1677 cpu
.exception
= SIGILL
;
1684 if (code
->dst
.type
== OP_CCR
)
1689 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1700 /* When a branch works */
1701 pc
= code
->src
.literal
;
1704 /* Set the cond codes from res */
1707 /* Set the flags after an 8 bit inc/dec operation */
1711 v
= (rd
& 0x7f) == 0x7f;
1715 /* Set the flags after an 16 bit inc/dec operation */
1719 v
= (rd
& 0x7fff) == 0x7fff;
1723 /* Set the flags after an 32 bit inc/dec operation */
1725 n
= res
& 0x80000000;
1726 nz
= res
& 0xffffffff;
1727 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1732 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1735 SET_B_REG (code
->src
.reg
, rd
);
1739 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1742 SET_W_REG (code
->src
.reg
, rd
);
1746 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1747 n
= (rd
& 0x80000000);
1748 nz
= rd
& 0xffffffff;
1749 SET_L_REG (code
->src
.reg
, rd
);
1753 store (&code
->dst
, res
);
1755 /* flags after a 32bit logical operation */
1756 n
= res
& 0x80000000;
1757 nz
= res
& 0xffffffff;
1762 store (&code
->dst
, res
);
1764 /* flags after a 16bit logical operation */
1772 store (&code
->dst
, res
);
1780 SET_B_REG (code
->dst
.reg
, res
);
1785 switch (code
->opcode
/ 4)
1788 v
= ((rd
& 0x80) == (ea
& 0x80)
1789 && (rd
& 0x80) != (res
& 0x80));
1793 v
= ((rd
& 0x80) != (-ea
& 0x80)
1794 && (rd
& 0x80) != (res
& 0x80));
1803 SET_W_REG (code
->dst
.reg
, res
);
1807 c
= (res
& 0x10000);
1808 switch (code
->opcode
/ 4)
1811 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1812 && (rd
& 0x8000) != (res
& 0x8000));
1816 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1817 && (rd
& 0x8000) != (res
& 0x8000));
1826 SET_L_REG (code
->dst
.reg
, res
);
1828 n
= res
& 0x80000000;
1829 nz
= res
& 0xffffffff;
1830 switch (code
->opcode
/ 4)
1833 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1834 && (rd
& 0x80000000) != (res
& 0x80000000));
1835 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1839 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1840 && (rd
& 0x80000000) != (res
& 0x80000000));
1841 c
= (unsigned) rd
< (unsigned) -ea
;
1844 v
= (rd
== 0x80000000);
1860 if (--poll_count
< 0)
1862 poll_count
= POLL_QUIT_INTERVAL
;
1863 if ((*sim_callback
->poll_quit
) != NULL
1864 && (*sim_callback
->poll_quit
) (sim_callback
))
1869 while (cpu
.state
== SIM_STATE_RUNNING
);
1870 cpu
.ticks
+= get_now () - tick_start
;
1871 cpu
.cycles
+= cycles
;
1878 signal (SIGINT
, prev
);
1885 /* FIXME: Unfinished. */
1890 sim_write (sd
, addr
, buffer
, size
)
1893 unsigned char *buffer
;
1901 for (i
= 0; i
< size
; i
++)
1903 if (addr
< memory_size
)
1905 cpu
.memory
[addr
+ i
] = buffer
[i
];
1906 cpu
.cache_idx
[addr
+ i
] = 0;
1909 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1915 sim_read (sd
, addr
, buffer
, size
)
1918 unsigned char *buffer
;
1924 if (addr
< memory_size
)
1925 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1927 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1933 sim_store_register (sd
, rn
, value
, length
)
1936 unsigned char *value
;
1942 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1943 shortval
= (value
[0] << 8) | (value
[1]);
1944 intval
= h8300hmode
? longval
: shortval
;
1962 cpu
.regs
[rn
] = intval
;
1971 cpu
.cycles
= longval
;
1975 cpu
.insts
= longval
;
1979 cpu
.ticks
= longval
;
1986 sim_fetch_register (sd
, rn
, buf
, length
)
1997 if (!h8300smode
&& rn
>=EXR_REGNUM
)
2035 if (h8300hmode
|| longreg
)
2051 sim_stop_reason (sd
, reason
, sigrc
)
2053 enum sim_stop
*reason
;
2056 #if 0 /* FIXME: This should work but we can't use it.
2057 grep for SLEEP above. */
2060 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
2061 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
2062 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
2066 *reason
= sim_stopped
;
2068 *sigrc
= cpu
.exception
;
2071 /* FIXME: Rename to sim_set_mem_size. */
2077 /* Memory size is fixed. */
2081 sim_set_simcache_size (n
)
2087 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
2088 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
2094 sim_info (sd
, verbose
)
2098 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
2099 double virttime
= cpu
.cycles
/ 10.0e6
;
2101 (*sim_callback
->printf_filtered
) (sim_callback
,
2102 "\n\n#instructions executed %10d\n",
2104 (*sim_callback
->printf_filtered
) (sim_callback
,
2105 "#cycles (v approximate) %10d\n",
2107 (*sim_callback
->printf_filtered
) (sim_callback
,
2108 "#real time taken %10.4f\n",
2110 (*sim_callback
->printf_filtered
) (sim_callback
,
2111 "#virtual time taked %10.4f\n",
2113 if (timetaken
!= 0.0)
2114 (*sim_callback
->printf_filtered
) (sim_callback
,
2115 "#simulation ratio %10.4f\n",
2116 virttime
/ timetaken
);
2117 (*sim_callback
->printf_filtered
) (sim_callback
,
2120 (*sim_callback
->printf_filtered
) (sim_callback
,
2121 "#cache size %10d\n",
2125 /* This to be conditional on `what' (aka `verbose'),
2126 however it was never passed as non-zero. */
2130 for (i
= 0; i
< O_LAST
; i
++)
2133 (*sim_callback
->printf_filtered
) (sim_callback
,
2134 "%d: %d\n", i
, cpu
.stats
[i
]);
2140 /* Indicate whether the cpu is an H8/300 or H8/300H.
2141 FLAG is non-zero for the H8/300H. */
2144 set_h8300h (h_flag
, s_flag
)
2147 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2148 This function being replaced by a sim_open:ARGV configuration
2150 h8300hmode
= h_flag
;
2151 h8300smode
= s_flag
;
2155 sim_open (kind
, ptr
, abfd
, argv
)
2157 struct host_callback_struct
*ptr
;
2161 /* FIXME: Much of the code in sim_load can be moved here. */
2166 /* Fudge our descriptor. */
2167 return (SIM_DESC
) 1;
2171 sim_close (sd
, quitting
)
2175 /* Nothing to do. */
2178 /* Called by gdb to load a program into memory. */
2181 sim_load (sd
, prog
, abfd
, from_tty
)
2189 /* FIXME: The code below that sets a specific variant of the H8/300
2190 being simulated should be moved to sim_open(). */
2192 /* See if the file is for the H8/300 or H8/300H. */
2193 /* ??? This may not be the most efficient way. The z8k simulator
2194 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2198 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2199 if (prog_bfd
!= NULL
)
2201 /* Set the cpu type. We ignore failure from bfd_check_format
2202 and bfd_openr as sim_load_file checks too. */
2203 if (bfd_check_format (prog_bfd
, bfd_object
))
2205 unsigned long mach
= bfd_get_mach (prog_bfd
);
2206 set_h8300h (mach
== bfd_mach_h8300h
|| mach
== bfd_mach_h8300s
,
2207 mach
== bfd_mach_h8300s
);
2211 /* If we're using gdb attached to the simulator, then we have to
2212 reallocate memory for the simulator.
2214 When gdb first starts, it calls fetch_registers (among other
2215 functions), which in turn calls init_pointers, which allocates
2218 The problem is when we do that, we don't know whether we're
2219 debugging an H8/300 or H8/300H program.
2221 This is the first point at which we can make that determination,
2222 so we just reallocate memory now; this will also allow us to handle
2223 switching between H8/300 and H8/300H programs without exiting
2227 memory_size
= H8300S_MSIZE
;
2228 else if (h8300hmode
)
2229 memory_size
= H8300H_MSIZE
;
2231 memory_size
= H8300_MSIZE
;
2236 free (cpu
.cache_idx
);
2238 free (cpu
.eightbit
);
2240 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2241 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2242 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2244 /* `msize' must be a power of two. */
2245 if ((memory_size
& (memory_size
- 1)) != 0)
2247 cpu
.mask
= memory_size
- 1;
2249 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2250 sim_kind
== SIM_OPEN_DEBUG
,
2254 /* Close the bfd if we opened it. */
2255 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2256 bfd_close (prog_bfd
);
2260 /* Close the bfd if we opened it. */
2261 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2262 bfd_close (prog_bfd
);
2267 sim_create_inferior (sd
, abfd
, argv
, env
)
2274 cpu
.pc
= bfd_get_start_address (abfd
);
2281 sim_do_command (sd
, cmd
)
2285 (*sim_callback
->printf_filtered
) (sim_callback
,
2286 "This simulator does not accept any commands.\n");
2290 sim_set_callbacks (ptr
)
2291 struct host_callback_struct
*ptr
;
This page took 0.086453 seconds and 4 git commands to generate.