2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 static void set_simcache_size (SIM_DESC
, int);
55 #define X(op, size) (op * 4 + size)
57 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
59 #define h8_opcodes ops
61 #include "opcode/h8300.h"
63 /* CPU data object: */
66 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
68 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
70 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
71 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
73 cpu
->delayed_branch
= 0;
78 /* Initialize local simulator state. */
80 sd
->sim_cache_size
= 0;
86 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
92 h8_get_pc (SIM_DESC sd
)
94 return (STATE_CPU (sd
, 0)) -> pc
;
98 h8_set_pc (SIM_DESC sd
, unsigned int val
)
100 (STATE_CPU (sd
, 0)) -> pc
= val
;
104 h8_get_ccr (SIM_DESC sd
)
106 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
110 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
112 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
116 h8_get_exr (SIM_DESC sd
)
118 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
122 h8_set_exr (SIM_DESC sd
, unsigned int val
)
124 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
128 h8_get_sbr (SIM_DESC sd
)
130 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
134 h8_set_sbr (SIM_DESC sd
, int val
)
136 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
140 h8_get_vbr (SIM_DESC sd
)
142 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
146 h8_set_vbr (SIM_DESC sd
, int val
)
148 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
152 h8_get_cache_top (SIM_DESC sd
)
154 return sd
-> cache_top
;
158 h8_set_cache_top (SIM_DESC sd
, int val
)
160 sd
-> cache_top
= val
;
164 h8_get_mask (SIM_DESC sd
)
166 return (STATE_CPU (sd
, 0)) -> mask
;
170 h8_set_mask (SIM_DESC sd
, int val
)
172 (STATE_CPU (sd
, 0)) -> mask
= val
;
176 h8_get_exception (SIM_DESC sd
)
178 return (STATE_CPU (sd
, 0)) -> exception
;
182 h8_set_exception (SIM_DESC sd
, int val
)
184 (STATE_CPU (sd
, 0)) -> exception
= val
;
187 static enum h8300_sim_state
188 h8_get_state (SIM_DESC sd
)
194 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
200 h8_get_cycles (SIM_DESC sd
)
202 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
206 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
208 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
212 h8_get_insts (SIM_DESC sd
)
214 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
218 h8_set_insts (SIM_DESC sd
, unsigned int val
)
220 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
224 h8_get_ticks (SIM_DESC sd
)
226 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
230 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
232 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
236 h8_get_mach (SIM_DESC sd
)
238 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
242 h8_set_mach (SIM_DESC sd
, unsigned int val
)
244 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
248 h8_get_macl (SIM_DESC sd
)
250 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
254 h8_set_macl (SIM_DESC sd
, unsigned int val
)
256 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
260 h8_get_compiles (SIM_DESC sd
)
262 return sd
-> compiles
;
266 h8_increment_compiles (SIM_DESC sd
)
271 static unsigned int *
272 h8_get_reg_buf (SIM_DESC sd
)
274 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
278 h8_get_reg (SIM_DESC sd
, int regnum
)
280 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
284 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
286 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
291 h8_get_stats (SIM_DESC sd
, int idx
)
293 return sd
-> stats
[idx
];
297 h8_increment_stats (SIM_DESC sd
, int idx
)
303 static unsigned short *
304 h8_get_cache_idx_buf (SIM_DESC sd
)
306 return sd
-> cache_idx
;
310 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
312 sd
-> cache_idx
= ptr
;
315 static unsigned short
316 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
318 if (idx
> sd
->memory_size
)
319 return (unsigned short) -1;
320 return sd
-> cache_idx
[idx
];
324 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
326 sd
-> cache_idx
[idx
] = (unsigned short) val
;
329 static unsigned char *
330 h8_get_memory_buf (SIM_DESC sd
)
332 return (STATE_CPU (sd
, 0)) -> memory
;
336 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
338 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
342 h8_get_memory (SIM_DESC sd
, int idx
)
344 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
348 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
350 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
353 static unsigned char *
354 h8_get_eightbit_buf (SIM_DESC sd
)
356 return (STATE_CPU (sd
, 0)) -> eightbit
;
360 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
362 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
366 h8_get_eightbit (SIM_DESC sd
, int idx
)
368 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
372 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
374 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
378 h8_get_delayed_branch (SIM_DESC sd
)
380 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
384 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
386 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
390 h8_get_command_line (SIM_DESC sd
)
392 return (STATE_CPU (sd
, 0)) -> command_line
;
396 h8_set_command_line (SIM_DESC sd
, char ** val
)
398 (STATE_CPU (sd
, 0)) -> command_line
= val
;
402 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
404 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
408 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
410 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
413 /* MAC Saturation Mode */
415 h8_get_macS (SIM_DESC sd
)
417 return (STATE_CPU (sd
, 0)) -> macS
;
421 h8_set_macS (SIM_DESC sd
, int val
)
423 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
428 h8_get_macZ (SIM_DESC sd
)
430 return (STATE_CPU (sd
, 0)) -> macZ
;
434 h8_set_macZ (SIM_DESC sd
, int val
)
436 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
439 /* MAC Negative Flag */
441 h8_get_macN (SIM_DESC sd
)
443 return (STATE_CPU (sd
, 0)) -> macN
;
447 h8_set_macN (SIM_DESC sd
, int val
)
449 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
452 /* MAC Overflow Flag */
454 h8_get_macV (SIM_DESC sd
)
456 return (STATE_CPU (sd
, 0)) -> macV
;
460 h8_set_macV (SIM_DESC sd
, int val
)
462 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
465 /* End CPU data object. */
467 /* The rate at which to call the host's poll_quit callback. */
469 enum { POLL_QUIT_INTERVAL
= 0x80000 };
471 #define LOW_BYTE(x) ((x) & 0xff)
472 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
473 #define P(X, Y) ((X << 8) | Y)
482 #define I (intMaskBit != 0)
484 #define BUILDSR(SD) \
485 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
486 | (N << 3) | (Z << 2) | (V << 1) | C)
489 /* Get Status Register (flags). */ \
490 c = (h8_get_ccr (sd) >> 0) & 1; \
491 v = (h8_get_ccr (sd) >> 1) & 1; \
492 nz = !((h8_get_ccr (sd) >> 2) & 1); \
493 n = (h8_get_ccr (sd) >> 3) & 1; \
494 u = (h8_get_ccr (sd) >> 4) & 1; \
495 h = (h8_get_ccr (sd) >> 5) & 1; \
496 ui = ((h8_get_ccr (sd) >> 6) & 1); \
497 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
500 #ifdef __CHAR_IS_SIGNED__
501 #define SEXTCHAR(x) ((char) (x))
505 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
508 #define UEXTCHAR(x) ((x) & 0xff)
509 #define UEXTSHORT(x) ((x) & 0xffff)
510 #define SEXTSHORT(x) ((short) (x))
514 int h8300_normal_mode
= 0;
517 static int memory_size
;
522 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
544 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
549 /* Simulate an indirection / dereference.
550 return 0 for success, -1 for failure.
554 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
556 if (val
== NULL
) /* Paranoia. */
562 if (rn
== ZERO_REGNUM
)
563 *val
= X (OP_IMM
, SP
);
565 *val
= X (OP_REG
, SP
);
568 *val
= X (OP_MEM
, SP
);
571 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
580 if (h8300smode
&& !h8300_normal_mode
)
582 else if (h8300hmode
&& !h8300_normal_mode
)
589 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
591 int cst
[3] = {0, 0, 0};
592 int reg
[3] = {0, 0, 0};
593 int rdisp
[3] = {0, 0, 0};
595 const struct h8_opcode
*q
;
600 /* Find the exact opcode/arg combo. */
601 for (q
= h8_opcodes
; q
->name
; q
++)
603 const op_type
*nib
= q
->data
.nib
;
604 unsigned int len
= 0;
606 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
607 (q
->available
== AV_H8S
&& !h8300smode
) ||
608 (q
->available
== AV_H8H
&& !h8300hmode
))
611 cst
[0] = cst
[1] = cst
[2] = 0;
612 reg
[0] = reg
[1] = reg
[2] = 0;
613 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
617 op_type looking_for
= *nib
;
618 int thisnib
= data
[len
/ 2];
620 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
621 opnum
= ((looking_for
& OP3
) ? 2 :
622 (looking_for
& DST
) ? 1 : 0);
624 if (looking_for
< 16 && looking_for
>= 0)
626 if (looking_for
!= thisnib
)
631 if (looking_for
& B31
)
633 if (!((thisnib
& 0x8) != 0))
636 looking_for
= (op_type
) (looking_for
& ~B31
);
639 else if (looking_for
& B30
)
641 if (!((thisnib
& 0x8) == 0))
644 looking_for
= (op_type
) (looking_for
& ~B30
);
647 if (looking_for
& B21
)
649 if (!((thisnib
& 0x4) != 0))
652 looking_for
= (op_type
) (looking_for
& ~B21
);
655 else if (looking_for
& B20
)
657 if (!((thisnib
& 0x4) == 0))
660 looking_for
= (op_type
) (looking_for
& ~B20
);
663 if (looking_for
& B11
)
665 if (!((thisnib
& 0x2) != 0))
668 looking_for
= (op_type
) (looking_for
& ~B11
);
671 else if (looking_for
& B10
)
673 if (!((thisnib
& 0x2) == 0))
676 looking_for
= (op_type
) (looking_for
& ~B10
);
679 if (looking_for
& B01
)
681 if (!((thisnib
& 0x1) != 0))
684 looking_for
= (op_type
) (looking_for
& ~B01
);
687 else if (looking_for
& B00
)
689 if (!((thisnib
& 0x1) == 0))
692 looking_for
= (op_type
) (looking_for
& ~B00
);
695 if (looking_for
& IGNORE
)
697 /* Hitachi has declared that IGNORE must be zero. */
701 else if ((looking_for
& MODE
) == DATA
)
703 ; /* Skip embedded data. */
705 else if ((looking_for
& MODE
) == DBIT
)
707 /* Exclude adds/subs by looking at bit 0 and 2, and
708 make sure the operand size, either w or l,
709 matches by looking at bit 1. */
710 if ((looking_for
& 7) != (thisnib
& 7))
713 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
715 else if ((looking_for
& MODE
) == REG
||
716 (looking_for
& MODE
) == LOWREG
||
717 (looking_for
& MODE
) == IND
||
718 (looking_for
& MODE
) == PREINC
||
719 (looking_for
& MODE
) == POSTINC
||
720 (looking_for
& MODE
) == PREDEC
||
721 (looking_for
& MODE
) == POSTDEC
)
723 reg
[opnum
] = thisnib
;
725 else if (looking_for
& CTRL
)
728 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
729 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
730 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
731 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
732 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
733 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
735 if (((looking_for
& MODE
) == CCR_EXR
&&
736 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
737 ((looking_for
& MODE
) == VBR_SBR
&&
738 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
739 ((looking_for
& MODE
) == MACREG
&&
740 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
742 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
743 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
744 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
747 reg
[opnum
] = thisnib
;
749 else if ((looking_for
& MODE
) == ABS
)
751 /* Absolute addresses are unsigned. */
752 switch (looking_for
& SIZE
)
755 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
759 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
763 (data
[len
/ 2 + 0] << 24) +
764 (data
[len
/ 2 + 1] << 16) +
765 (data
[len
/ 2 + 2] << 8) +
769 printf ("decode: bad size ABS: %d\n",
770 (looking_for
& SIZE
));
774 else if ((looking_for
& MODE
) == DISP
||
775 (looking_for
& MODE
) == PCREL
||
776 (looking_for
& MODE
) == INDEXB
||
777 (looking_for
& MODE
) == INDEXW
||
778 (looking_for
& MODE
) == INDEXL
)
780 switch (looking_for
& SIZE
)
783 cst
[opnum
] = thisnib
& 3;
786 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
789 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
790 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
793 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
797 (data
[len
/ 2 + 0] << 24) +
798 (data
[len
/ 2 + 1] << 16) +
799 (data
[len
/ 2 + 2] << 8) +
803 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
804 (looking_for
& SIZE
));
808 else if ((looking_for
& SIZE
) == L_16
||
809 (looking_for
& SIZE
) == L_16U
)
811 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
812 /* Immediates are always unsigned. */
813 if ((looking_for
& SIZE
) != L_16U
&&
814 (looking_for
& MODE
) != IMM
)
815 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
817 else if (looking_for
& ABSJMP
)
819 switch (looking_for
& SIZE
) {
821 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
825 (data
[len
/ 2 + 0] << 24) +
826 (data
[len
/ 2 + 1] << 16) +
827 (data
[len
/ 2 + 2] << 8) +
831 printf ("decode: bad size ABSJMP: %d\n",
832 (looking_for
& SIZE
));
836 else if ((looking_for
& MODE
) == MEMIND
)
838 cst
[opnum
] = data
[1];
840 else if ((looking_for
& MODE
) == VECIND
)
842 if(h8300_normal_mode
)
843 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
845 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
846 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
848 else if ((looking_for
& SIZE
) == L_32
)
853 (data
[i
+ 0] << 24) |
854 (data
[i
+ 1] << 16) |
858 else if ((looking_for
& SIZE
) == L_24
)
863 (data
[i
+ 0] << 16) |
867 else if (looking_for
& DISPREG
)
869 rdisp
[opnum
] = thisnib
& 0x7;
871 else if ((looking_for
& MODE
) == KBIT
)
888 else if ((looking_for
& SIZE
) == L_8
)
890 if ((looking_for
& MODE
) == ABS
)
892 /* Will be combined with contents of SBR_REGNUM
893 by fetch (). For all modes except h8sx, this
894 will always contain the value 0xFFFFFF00. */
895 cst
[opnum
] = data
[len
/ 2] & 0xff;
899 cst
[opnum
] = data
[len
/ 2] & 0xff;
902 else if ((looking_for
& SIZE
) == L_2
)
904 cst
[opnum
] = thisnib
& 3;
906 else if ((looking_for
& SIZE
) == L_3
||
907 (looking_for
& SIZE
) == L_3NZ
)
909 cst
[opnum
] = thisnib
& 7;
910 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
913 else if ((looking_for
& SIZE
) == L_4
)
915 cst
[opnum
] = thisnib
& 15;
917 else if ((looking_for
& SIZE
) == L_5
)
919 cst
[opnum
] = data
[len
/ 2] & 0x1f;
921 else if (looking_for
== E
)
926 /* Fill in the args. */
928 const op_type
*args
= q
->args
.nib
;
933 nargs
< 3 && *args
!= E
;
939 opnum
= ((x
& OP3
) ? 2 :
948 if ((x
& MODE
) == IMM
||
949 (x
& MODE
) == KBIT
||
952 /* Use the instruction to determine
954 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
955 p
->literal
= cst
[opnum
];
957 else if ((x
& MODE
) == CONST_2
||
958 (x
& MODE
) == CONST_4
||
959 (x
& MODE
) == CONST_8
||
960 (x
& MODE
) == CONST_16
)
962 /* Use the instruction to determine
964 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
966 case CONST_2
: p
->literal
= 2; break;
967 case CONST_4
: p
->literal
= 4; break;
968 case CONST_8
: p
->literal
= 8; break;
969 case CONST_16
: p
->literal
= 16; break;
972 else if ((x
& MODE
) == REG
)
974 p
->type
= X (OP_REG
, bitfrom (x
));
977 else if ((x
& MODE
) == LOWREG
)
979 p
->type
= X (OP_LOWREG
, bitfrom (x
));
982 else if ((x
& MODE
) == PREINC
)
984 /* Use the instruction to determine
986 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
987 p
->reg
= reg
[opnum
] & 0x7;
989 else if ((x
& MODE
) == POSTINC
)
991 /* Use the instruction to determine
993 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
994 p
->reg
= reg
[opnum
] & 0x7;
996 else if ((x
& MODE
) == PREDEC
)
998 /* Use the instruction to determine
1000 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
1001 p
->reg
= reg
[opnum
] & 0x7;
1003 else if ((x
& MODE
) == POSTDEC
)
1005 /* Use the instruction to determine
1006 the operand size. */
1007 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
1008 p
->reg
= reg
[opnum
] & 0x7;
1010 else if ((x
& MODE
) == IND
)
1012 /* Note: an indirect is transformed into
1013 a displacement of zero.
1015 /* Use the instruction to determine
1016 the operand size. */
1017 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1018 p
->reg
= reg
[opnum
] & 0x7;
1020 if (OP_KIND (q
->how
) == O_JSR
||
1021 OP_KIND (q
->how
) == O_JMP
)
1022 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1025 else if ((x
& MODE
) == ABS
)
1027 /* Note: a 16 or 32 bit ABS is transformed into a
1028 displacement from pseudo-register ZERO_REGNUM,
1029 which is always zero. An 8 bit ABS becomes
1030 a displacement from SBR_REGNUM.
1032 /* Use the instruction to determine
1033 the operand size. */
1034 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1035 p
->literal
= cst
[opnum
];
1037 /* 8-bit ABS is displacement from SBR.
1038 16 and 32-bit ABS are displacement from ZERO.
1039 (SBR will always be zero except for h8/sx)
1041 if ((x
& SIZE
) == L_8
)
1042 p
->reg
= SBR_REGNUM
;
1044 p
->reg
= ZERO_REGNUM
;;
1046 else if ((x
& MODE
) == MEMIND
||
1047 (x
& MODE
) == VECIND
)
1049 /* Size doesn't matter. */
1050 p
->type
= X (OP_MEM
, SB
);
1051 p
->literal
= cst
[opnum
];
1052 if (OP_KIND (q
->how
) == O_JSR
||
1053 OP_KIND (q
->how
) == O_JMP
)
1054 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1057 else if ((x
& MODE
) == PCREL
)
1059 /* Size doesn't matter. */
1060 p
->type
= X (OP_PCREL
, SB
);
1061 p
->literal
= cst
[opnum
];
1063 else if (x
& ABSJMP
)
1065 p
->type
= X (OP_IMM
, SP
);
1066 p
->literal
= cst
[opnum
];
1068 else if ((x
& MODE
) == INDEXB
)
1070 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1071 p
->literal
= cst
[opnum
];
1072 p
->reg
= rdisp
[opnum
];
1074 else if ((x
& MODE
) == INDEXW
)
1076 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1077 p
->literal
= cst
[opnum
];
1078 p
->reg
= rdisp
[opnum
];
1080 else if ((x
& MODE
) == INDEXL
)
1082 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1083 p
->literal
= cst
[opnum
];
1084 p
->reg
= rdisp
[opnum
];
1086 else if ((x
& MODE
) == DISP
)
1088 /* Yuck -- special for mova args. */
1089 if (strncmp (q
->name
, "mova", 4) == 0 &&
1092 /* Mova can have a DISP2 dest, with an
1093 INDEXB or INDEXW src. The multiplier
1094 for the displacement value is determined
1095 by the src operand, not by the insn. */
1097 switch (OP_KIND (dst
->src
.type
))
1100 p
->type
= X (OP_DISP
, SB
);
1101 p
->literal
= cst
[opnum
];
1104 p
->type
= X (OP_DISP
, SW
);
1105 p
->literal
= cst
[opnum
] * 2;
1113 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1114 p
->literal
= cst
[opnum
];
1115 /* DISP2 is special. */
1116 if ((x
& SIZE
) == L_2
)
1117 switch (OP_SIZE (q
->how
))
1120 case SW
: p
->literal
*= 2; break;
1121 case SL
: p
->literal
*= 4; break;
1124 p
->reg
= rdisp
[opnum
];
1131 p
->type
= X (OP_CCR
, SB
);
1134 p
->type
= X (OP_EXR
, SB
);
1137 p
->type
= X (OP_MACH
, SL
);
1140 p
->type
= X (OP_MACL
, SL
);
1143 p
->type
= X (OP_VBR
, SL
);
1146 p
->type
= X (OP_SBR
, SL
);
1150 else if ((x
& MODE
) == CCR
)
1154 else if ((x
& MODE
) == EXR
)
1159 printf ("Hmmmm 0x%x...\n", x
);
1165 /* Unary operators: treat src and dst as equivalent. */
1166 if (dst
->dst
.type
== -1)
1167 dst
->dst
= dst
->src
;
1168 if (dst
->src
.type
== -1)
1169 dst
->src
= dst
->dst
;
1171 dst
->opcode
= q
->how
;
1172 dst
->cycles
= q
->time
;
1174 /* And jsr's to these locations are turned into
1177 if (OP_KIND (dst
->opcode
) == O_JSR
)
1179 switch (dst
->src
.literal
)
1182 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1185 dst
->opcode
= O (O_SYS_READ
, SB
);
1188 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1191 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1194 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1197 dst
->opcode
= O (O_SYS_STAT
, SB
);
1200 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1203 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1206 /* End of Processing for system calls. */
1209 dst
->next_pc
= addr
+ len
/ 2;
1213 printf ("Don't understand 0x%x \n", looking_for
);
1224 /* Fell off the end. */
1225 dst
->opcode
= O (O_ILL
, SB
);
1229 compile (SIM_DESC sd
, int pc
)
1233 /* Find the next cache entry to use. */
1234 idx
= h8_get_cache_top (sd
) + 1;
1235 h8_increment_compiles (sd
);
1236 if (idx
>= sd
->sim_cache_size
)
1240 h8_set_cache_top (sd
, idx
);
1242 /* Throw away its old meaning. */
1243 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1245 /* Set to new address. */
1246 sd
->sim_cache
[idx
].oldpc
= pc
;
1248 /* Fill in instruction info. */
1249 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1251 /* Point to new cache entry. */
1252 h8_set_cache_idx (sd
, pc
, idx
);
1256 static unsigned char *breg
[32];
1257 static unsigned short *wreg
[16];
1258 static unsigned int *lreg
[18];
1260 #define GET_B_REG(X) *(breg[X])
1261 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1262 #define GET_W_REG(X) *(wreg[X])
1263 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1264 #define GET_L_REG(X) h8_get_reg (sd, X)
1265 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1267 #define GET_MEMORY_L(X) \
1268 ((X) < memory_size \
1269 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1270 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1271 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1272 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1273 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1274 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1276 #define GET_MEMORY_W(X) \
1277 ((X) < memory_size \
1278 ? ((h8_get_memory (sd, (X)+0) << 8) \
1279 | (h8_get_memory (sd, (X)+1) << 0)) \
1280 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1281 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1284 #define GET_MEMORY_B(X) \
1285 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1286 : (h8_get_eightbit (sd, (X) & 0xff)))
1288 #define SET_MEMORY_L(X, Y) \
1289 { register unsigned char *_p; register int __y = (Y); \
1290 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1291 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1292 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1293 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1296 #define SET_MEMORY_W(X, Y) \
1297 { register unsigned char *_p; register int __y = (Y); \
1298 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1299 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1300 _p[0] = __y >> 8; _p[1] = __y; \
1303 #define SET_MEMORY_B(X, Y) \
1304 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1305 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1307 /* Simulate a memory fetch.
1308 Return 0 for success, -1 for failure.
1312 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1315 int abs
= arg
->literal
;
1320 return -1; /* Paranoia. */
1324 /* Indexed register plus displacement mode:
1326 This new family of addressing modes are similar to OP_DISP
1327 (register plus displacement), with two differences:
1328 1) INDEXB uses only the least significant byte of the register,
1329 INDEXW uses only the least significant word, and
1330 INDEXL uses the entire register (just like OP_DISP).
1332 2) The displacement value in abs is multiplied by two
1333 for SW-sized operations, and by four for SL-size.
1335 This gives nine possible variations.
1338 case X (OP_INDEXB
, SB
):
1339 case X (OP_INDEXB
, SW
):
1340 case X (OP_INDEXB
, SL
):
1341 case X (OP_INDEXW
, SB
):
1342 case X (OP_INDEXW
, SW
):
1343 case X (OP_INDEXW
, SL
):
1344 case X (OP_INDEXL
, SB
):
1345 case X (OP_INDEXL
, SW
):
1346 case X (OP_INDEXL
, SL
):
1348 switch (OP_KIND (arg
->type
)) {
1349 case OP_INDEXB
: t
&= 0xff; break;
1350 case OP_INDEXW
: t
&= 0xffff; break;
1354 switch (OP_SIZE (arg
->type
)) {
1356 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1359 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1362 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1367 case X (OP_LOWREG
, SB
):
1368 *val
= GET_L_REG (rn
) & 0xff;
1370 case X (OP_LOWREG
, SW
):
1371 *val
= GET_L_REG (rn
) & 0xffff;
1374 case X (OP_REG
, SB
): /* Register direct, byte. */
1375 *val
= GET_B_REG (rn
);
1377 case X (OP_REG
, SW
): /* Register direct, word. */
1378 *val
= GET_W_REG (rn
);
1380 case X (OP_REG
, SL
): /* Register direct, long. */
1381 *val
= GET_L_REG (rn
);
1383 case X (OP_IMM
, SB
): /* Immediate, byte. */
1384 case X (OP_IMM
, SW
): /* Immediate, word. */
1385 case X (OP_IMM
, SL
): /* Immediate, long. */
1388 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1390 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1396 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1398 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1404 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1406 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1413 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1415 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1421 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1423 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1429 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1431 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1438 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1439 t
= GET_L_REG (rn
) - 1;
1441 t
&= h8_get_mask (sd
);
1442 *val
= GET_MEMORY_B (t
);
1445 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1446 t
= GET_L_REG (rn
) - 2;
1448 t
&= h8_get_mask (sd
);
1449 *val
= GET_MEMORY_W (t
);
1452 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1453 t
= GET_L_REG (rn
) - 4;
1455 t
&= h8_get_mask (sd
);
1456 *val
= GET_MEMORY_L (t
);
1459 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1460 t
= GET_L_REG (rn
) + 1;
1462 t
&= h8_get_mask (sd
);
1463 *val
= GET_MEMORY_B (t
);
1466 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1467 t
= GET_L_REG (rn
) + 2;
1469 t
&= h8_get_mask (sd
);
1470 *val
= GET_MEMORY_W (t
);
1473 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1474 t
= GET_L_REG (rn
) + 4;
1476 t
&= h8_get_mask (sd
);
1477 *val
= GET_MEMORY_L (t
);
1480 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1481 t
= GET_L_REG (rn
) + abs
;
1482 t
&= h8_get_mask (sd
);
1483 *val
= GET_MEMORY_B (t
);
1486 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1487 t
= GET_L_REG (rn
) + abs
;
1488 t
&= h8_get_mask (sd
);
1489 *val
= GET_MEMORY_W (t
);
1492 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1493 t
= GET_L_REG (rn
) + abs
;
1494 t
&= h8_get_mask (sd
);
1495 *val
=GET_MEMORY_L (t
);
1498 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1499 t
= GET_MEMORY_L (abs
);
1500 t
&= h8_get_mask (sd
);
1504 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1505 t
= GET_MEMORY_W (abs
);
1506 t
&= h8_get_mask (sd
);
1510 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1511 case X (OP_PCREL
, SW
):
1512 case X (OP_PCREL
, SL
):
1513 case X (OP_PCREL
, SN
):
1517 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1519 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1522 return 0; /* Success. */
1528 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1530 return fetch_1 (sd
, arg
, val
, 0);
1533 /* Fetch which will be followed by a store to the same location.
1534 The difference being that we don't want to do a post-increment
1535 or post-decrement at this time: we'll do it when we store. */
1538 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1540 return fetch_1 (sd
, arg
, val
, 1);
1543 /* Simulate a memory store.
1544 Return 0 for success, -1 for failure.
1548 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1551 int abs
= arg
->literal
;
1556 /* Indexed register plus displacement mode:
1558 This new family of addressing modes are similar to OP_DISP
1559 (register plus displacement), with two differences:
1560 1) INDEXB uses only the least significant byte of the register,
1561 INDEXW uses only the least significant word, and
1562 INDEXL uses the entire register (just like OP_DISP).
1564 2) The displacement value in abs is multiplied by two
1565 for SW-sized operations, and by four for SL-size.
1567 This gives nine possible variations.
1570 case X (OP_INDEXB
, SB
):
1571 case X (OP_INDEXB
, SW
):
1572 case X (OP_INDEXB
, SL
):
1573 case X (OP_INDEXW
, SB
):
1574 case X (OP_INDEXW
, SW
):
1575 case X (OP_INDEXW
, SL
):
1576 case X (OP_INDEXL
, SB
):
1577 case X (OP_INDEXL
, SW
):
1578 case X (OP_INDEXL
, SL
):
1580 switch (OP_KIND (arg
->type
)) {
1581 case OP_INDEXB
: t
&= 0xff; break;
1582 case OP_INDEXW
: t
&= 0xffff; break;
1586 switch (OP_SIZE (arg
->type
)) {
1588 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1591 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1594 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1599 case X (OP_REG
, SB
): /* Register direct, byte. */
1602 case X (OP_REG
, SW
): /* Register direct, word. */
1605 case X (OP_REG
, SL
): /* Register direct, long. */
1609 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1614 t
&= h8_get_mask (sd
);
1615 SET_MEMORY_B (t
, n
);
1618 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1623 t
&= h8_get_mask (sd
);
1624 SET_MEMORY_W (t
, n
);
1627 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1632 t
&= h8_get_mask (sd
);
1633 SET_MEMORY_L (t
, n
);
1636 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1641 t
&= h8_get_mask (sd
);
1642 SET_MEMORY_B (t
, n
);
1645 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1650 t
&= h8_get_mask (sd
);
1651 SET_MEMORY_W (t
, n
);
1654 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1659 t
&= h8_get_mask (sd
);
1660 SET_MEMORY_L (t
, n
);
1663 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1665 SET_L_REG (rn
, t
- 1);
1666 t
&= h8_get_mask (sd
);
1667 SET_MEMORY_B (t
, n
);
1670 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1672 SET_L_REG (rn
, t
- 2);
1673 t
&= h8_get_mask (sd
);
1674 SET_MEMORY_W (t
, n
);
1677 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1679 SET_L_REG (rn
, t
- 4);
1680 t
&= h8_get_mask (sd
);
1681 SET_MEMORY_L (t
, n
);
1684 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1686 SET_L_REG (rn
, t
+ 1);
1687 t
&= h8_get_mask (sd
);
1688 SET_MEMORY_B (t
, n
);
1691 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1693 SET_L_REG (rn
, t
+ 2);
1694 t
&= h8_get_mask (sd
);
1695 SET_MEMORY_W (t
, n
);
1698 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1700 SET_L_REG (rn
, t
+ 4);
1701 t
&= h8_get_mask (sd
);
1702 SET_MEMORY_L (t
, n
);
1705 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1706 t
= GET_L_REG (rn
) + abs
;
1707 t
&= h8_get_mask (sd
);
1708 SET_MEMORY_B (t
, n
);
1711 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1712 t
= GET_L_REG (rn
) + abs
;
1713 t
&= h8_get_mask (sd
);
1714 SET_MEMORY_W (t
, n
);
1717 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1718 t
= GET_L_REG (rn
) + abs
;
1719 t
&= h8_get_mask (sd
);
1720 SET_MEMORY_L (t
, n
);
1724 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1725 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1726 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1728 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1737 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1739 return store_1 (sd
, arg
, n
, 0);
1742 /* Store which follows a fetch from the same location.
1743 The difference being that we don't want to do a pre-increment
1744 or pre-decrement at this time: it was already done when we fetched. */
1747 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1749 return store_1 (sd
, arg
, n
, 1);
1763 /* Flag to be set whenever a new SIM_DESC object is created. */
1764 static int init_pointers_needed
= 1;
1767 init_pointers (SIM_DESC sd
)
1769 if (init_pointers_needed
)
1775 if (h8300smode
&& !h8300_normal_mode
)
1776 memory_size
= H8300S_MSIZE
;
1777 else if (h8300hmode
&& !h8300_normal_mode
)
1778 memory_size
= H8300H_MSIZE
;
1780 memory_size
= H8300_MSIZE
;
1781 /* `msize' must be a power of two. */
1782 if ((memory_size
& (memory_size
- 1)) != 0)
1784 (*sim_callback
->printf_filtered
)
1786 "init_pointers: bad memory size %d, defaulting to %d.\n",
1787 memory_size
, memory_size
= H8300S_MSIZE
);
1790 if (h8_get_memory_buf (sd
))
1791 free (h8_get_memory_buf (sd
));
1792 if (h8_get_cache_idx_buf (sd
))
1793 free (h8_get_cache_idx_buf (sd
));
1794 if (h8_get_eightbit_buf (sd
))
1795 free (h8_get_eightbit_buf (sd
));
1797 h8_set_memory_buf (sd
, (unsigned char *)
1798 calloc (sizeof (char), memory_size
));
1799 h8_set_cache_idx_buf (sd
, (unsigned short *)
1800 calloc (sizeof (short), memory_size
));
1801 sd
->memory_size
= memory_size
;
1802 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1804 h8_set_mask (sd
, memory_size
- 1);
1806 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1808 for (i
= 0; i
< 8; i
++)
1810 /* FIXME: rewrite using local buffer. */
1811 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1812 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1813 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1814 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1815 h8_set_reg (sd
, i
, 0x00112233);
1830 wreg
[i
] = wreg
[i
+ 8] = 0;
1844 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1845 (*sim_callback
->printf_filtered
) (sim_callback
,
1846 "init_pointers: internal error.\n");
1848 h8_set_reg (sd
, i
, 0);
1849 lreg
[i
] = h8_get_reg_buf (sd
) + i
;
1852 /* Note: sim uses pseudo-register ZERO as a zero register. */
1853 lreg
[ZERO_REGNUM
] = h8_get_reg_buf (sd
) + ZERO_REGNUM
;
1854 init_pointers_needed
= 0;
1856 /* Initialize the seg registers. */
1858 set_simcache_size (sd
, CSIZE
);
1863 sim_stop (SIM_DESC sd
)
1865 /* FIXME: use a real signal value. */
1866 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
1870 #define OBITOP(name, f, s, op) \
1871 case O (name, SB): \
1876 if (fetch (sd, &code->dst, &ea)) \
1878 if (fetch (sd, &code->src, &tmp)) \
1880 m = 1 << (tmp & 7); \
1883 if (store (sd, &code->dst,ea)) \
1889 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1894 int tick_start
= get_now ();
1902 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1905 enum sim_stop reason
;
1912 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
1916 sim_engine_set_run_state (sd
, sim_running
, 0);
1919 pc
= h8_get_pc (sd
);
1921 /* The PC should never be odd. */
1924 sim_engine_set_run_state (sd
, sim_stopped
, SIGBUS
);
1928 /* Get Status Register (flags). */
1931 if (h8300smode
) /* Get exr. */
1933 trace
= (h8_get_exr (sd
) >> 7) & 1;
1934 intMask
= h8_get_exr (sd
) & 7;
1937 oldmask
= h8_get_mask (sd
);
1938 if (!h8300hmode
|| h8300_normal_mode
)
1939 h8_set_mask (sd
, 0xffff);
1942 unsigned short cidx
;
1946 cidx
= h8_get_cache_idx (sd
, pc
);
1947 if (cidx
== (unsigned short) -1 ||
1948 cidx
>= sd
->sim_cache_size
)
1951 code
= sd
->sim_cache
+ cidx
;
1956 printf ("%x %d %s\n", pc
, code
->opcode
,
1957 code
->op
? code
->op
->name
: "**");
1959 h8_increment_stats (sd
, code
->opcode
);
1964 cycles
+= code
->cycles
;
1968 switch (code
->opcode
)
1972 * This opcode is a fake for when we get to an
1973 * instruction which hasnt been compiled
1979 case O (O_MOVAB
, SL
):
1980 case O (O_MOVAW
, SL
):
1981 case O (O_MOVAL
, SL
):
1982 /* 1) Evaluate 2nd argument (dst).
1983 2) Mask / zero extend according to whether 1st argument (src)
1984 is INDEXB, INDEXW, or INDEXL.
1985 3) Left-shift the result by 0, 1 or 2, according to size of mova
1986 (mova/b, mova/w, mova/l).
1987 4) Add literal value of 1st argument (src).
1988 5) Store result in 3rd argument (op3).
1991 /* Alas, since this is the only instruction with 3 arguments,
1992 decode doesn't handle them very well. Some fix-up is required.
1994 a) The size of dst is determined by whether src is
1995 INDEXB or INDEXW. */
1997 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1998 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1999 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
2000 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
2002 /* b) If op3 == null, then this is the short form of the insn.
2003 Dst is the dispreg of src, and op3 is the 32-bit form
2004 of the same register.
2007 if (code
->op3
.type
== 0)
2009 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
2010 We get to compose dst and op3 as follows:
2012 op3 is a 32-bit register, ID == src.reg.
2013 dst is the same register, but 8 or 16 bits
2014 depending on whether src is INDEXB or INDEXW.
2017 code
->op3
.type
= X (OP_REG
, SL
);
2018 code
->op3
.reg
= code
->src
.reg
;
2019 code
->op3
.literal
= 0;
2021 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
2023 code
->dst
.type
= X (OP_REG
, SB
);
2024 code
->dst
.reg
= code
->op3
.reg
+ 8;
2027 code
->dst
.type
= X (OP_REG
, SW
);
2030 if (fetch (sd
, &code
->dst
, &ea
))
2033 switch (OP_KIND (code
->src
.type
)) {
2034 case OP_INDEXB
: ea
= ea
& 0xff; break;
2035 case OP_INDEXW
: ea
= ea
& 0xffff; break;
2036 case OP_INDEXL
: break;
2037 default: goto illegal
;
2040 switch (code
->opcode
) {
2041 case O (O_MOVAB
, SL
): break;
2042 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
2043 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
2044 default: goto illegal
;
2047 ea
= ea
+ code
->src
.literal
;
2049 if (store (sd
, &code
->op3
, ea
))
2054 case O (O_SUBX
, SB
): /* subx, extended sub */
2055 if (fetch2 (sd
, &code
->dst
, &rd
))
2057 if (fetch (sd
, &code
->src
, &ea
))
2063 case O (O_SUBX
, SW
): /* subx, extended sub */
2064 if (fetch2 (sd
, &code
->dst
, &rd
))
2066 if (fetch (sd
, &code
->src
, &ea
))
2072 case O (O_SUBX
, SL
): /* subx, extended sub */
2073 if (fetch2 (sd
, &code
->dst
, &rd
))
2075 if (fetch (sd
, &code
->src
, &ea
))
2081 case O (O_ADDX
, SB
): /* addx, extended add */
2082 if (fetch2 (sd
, &code
->dst
, &rd
))
2084 if (fetch (sd
, &code
->src
, &ea
))
2090 case O (O_ADDX
, SW
): /* addx, extended add */
2091 if (fetch2 (sd
, &code
->dst
, &rd
))
2093 if (fetch (sd
, &code
->src
, &ea
))
2099 case O (O_ADDX
, SL
): /* addx, extended add */
2100 if (fetch2 (sd
, &code
->dst
, &rd
))
2102 if (fetch (sd
, &code
->src
, &ea
))
2108 case O (O_SUB
, SB
): /* sub.b */
2109 /* Fetch rd and ea. */
2110 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2116 case O (O_SUB
, SW
): /* sub.w */
2117 /* Fetch rd and ea. */
2118 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2124 case O (O_SUB
, SL
): /* sub.l */
2125 /* Fetch rd and ea. */
2126 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2132 case O (O_NEG
, SB
): /* neg.b */
2134 if (fetch2 (sd
, &code
->src
, &ea
))
2141 case O (O_NEG
, SW
): /* neg.w */
2143 if (fetch2 (sd
, &code
->src
, &ea
))
2150 case O (O_NEG
, SL
): /* neg.l */
2152 if (fetch2 (sd
, &code
->src
, &ea
))
2159 case O (O_ADD
, SB
): /* add.b */
2160 if (fetch2 (sd
, &code
->dst
, &rd
))
2162 if (fetch (sd
, &code
->src
, &ea
))
2167 case O (O_ADD
, SW
): /* add.w */
2168 if (fetch2 (sd
, &code
->dst
, &rd
))
2170 if (fetch (sd
, &code
->src
, &ea
))
2175 case O (O_ADD
, SL
): /* add.l */
2176 if (fetch2 (sd
, &code
->dst
, &rd
))
2178 if (fetch (sd
, &code
->src
, &ea
))
2183 case O (O_AND
, SB
): /* and.b */
2184 /* Fetch rd and ea. */
2185 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2190 case O (O_AND
, SW
): /* and.w */
2191 /* Fetch rd and ea. */
2192 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2197 case O (O_AND
, SL
): /* and.l */
2198 /* Fetch rd and ea. */
2199 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2204 case O (O_OR
, SB
): /* or.b */
2205 /* Fetch rd and ea. */
2206 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2211 case O (O_OR
, SW
): /* or.w */
2212 /* Fetch rd and ea. */
2213 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2218 case O (O_OR
, SL
): /* or.l */
2219 /* Fetch rd and ea. */
2220 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2225 case O (O_XOR
, SB
): /* xor.b */
2226 /* Fetch rd and ea. */
2227 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2232 case O (O_XOR
, SW
): /* xor.w */
2233 /* Fetch rd and ea. */
2234 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2239 case O (O_XOR
, SL
): /* xor.l */
2240 /* Fetch rd and ea. */
2241 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2247 if (fetch (sd
, &code
->src
, &res
))
2249 if (store (sd
, &code
->dst
, res
))
2251 goto just_flags_log8
;
2253 if (fetch (sd
, &code
->src
, &res
))
2255 if (store (sd
, &code
->dst
, res
))
2257 goto just_flags_log16
;
2259 if (fetch (sd
, &code
->src
, &res
))
2261 if (store (sd
, &code
->dst
, res
))
2263 goto just_flags_log32
;
2265 case O (O_MOVMD
, SB
): /* movmd.b */
2272 rd
= GET_MEMORY_B (GET_L_REG (5));
2273 SET_MEMORY_B (GET_L_REG (6), rd
);
2274 SET_L_REG (5, GET_L_REG (5) + 1);
2275 SET_L_REG (6, GET_L_REG (6) + 1);
2280 case O (O_MOVMD
, SW
): /* movmd.w */
2287 rd
= GET_MEMORY_W (GET_L_REG (5));
2288 SET_MEMORY_W (GET_L_REG (6), rd
);
2289 SET_L_REG (5, GET_L_REG (5) + 2);
2290 SET_L_REG (6, GET_L_REG (6) + 2);
2295 case O (O_MOVMD
, SL
): /* movmd.l */
2302 rd
= GET_MEMORY_L (GET_L_REG (5));
2303 SET_MEMORY_L (GET_L_REG (6), rd
);
2304 SET_L_REG (5, GET_L_REG (5) + 4);
2305 SET_L_REG (6, GET_L_REG (6) + 4);
2310 case O (O_MOVSD
, SB
): /* movsd.b */
2311 /* This instruction implements strncpy, with a conditional branch.
2312 r4 contains n, r5 contains src, and r6 contains dst.
2313 The 16-bit displacement operand is added to the pc
2314 if and only if the end of string is reached before
2315 n bytes are transferred. */
2317 ea
= GET_L_REG (4) & 0xffff;
2323 rd
= GET_MEMORY_B (GET_L_REG (5));
2324 SET_MEMORY_B (GET_L_REG (6), rd
);
2325 SET_L_REG (5, GET_L_REG (5) + 1);
2326 SET_L_REG (6, GET_L_REG (6) + 1);
2333 case O (O_EEPMOV
, SB
): /* eepmov.b */
2334 case O (O_EEPMOV
, SW
): /* eepmov.w */
2335 if (h8300hmode
|| h8300smode
)
2337 register unsigned char *_src
, *_dst
;
2338 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2339 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2340 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2342 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2343 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2344 : h8_get_eightbit_buf (sd
) +
2345 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2346 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2348 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2351 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2352 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2353 : h8_get_eightbit_buf (sd
) +
2354 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2356 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2358 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2361 memcpy (_dst
, _src
, count
);
2363 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2364 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2365 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2366 ((code
->opcode
== O (O_EEPMOV
, SW
))
2367 ? (~0xffff) : (~0xff)));
2368 cycles
+= 2 * count
;
2373 case O (O_ADDS
, SL
): /* adds (.l) */
2375 * This insn only uses register operands, but still
2376 * it would be cleaner to use fetch and store... */
2377 SET_L_REG (code
->dst
.reg
,
2378 GET_L_REG (code
->dst
.reg
)
2379 + code
->src
.literal
);
2383 case O (O_SUBS
, SL
): /* subs (.l) */
2385 * This insn only uses register operands, but still
2386 * it would be cleaner to use fetch and store... */
2387 SET_L_REG (code
->dst
.reg
,
2388 GET_L_REG (code
->dst
.reg
)
2389 - code
->src
.literal
);
2392 case O (O_CMP
, SB
): /* cmp.b */
2393 if (fetch (sd
, &code
->dst
, &rd
))
2395 if (fetch (sd
, &code
->src
, &ea
))
2399 goto just_flags_alu8
;
2401 case O (O_CMP
, SW
): /* cmp.w */
2402 if (fetch (sd
, &code
->dst
, &rd
))
2404 if (fetch (sd
, &code
->src
, &ea
))
2408 goto just_flags_alu16
;
2410 case O (O_CMP
, SL
): /* cmp.l */
2411 if (fetch (sd
, &code
->dst
, &rd
))
2413 if (fetch (sd
, &code
->src
, &ea
))
2417 goto just_flags_alu32
;
2419 case O (O_DEC
, SB
): /* dec.b */
2421 * This insn only uses register operands, but still
2422 * it would be cleaner to use fetch and store... */
2423 rd
= GET_B_REG (code
->src
.reg
);
2426 SET_B_REG (code
->src
.reg
, res
);
2427 goto just_flags_inc8
;
2429 case O (O_DEC
, SW
): /* dec.w */
2431 * This insn only uses register operands, but still
2432 * it would be cleaner to use fetch and store... */
2433 rd
= GET_W_REG (code
->dst
.reg
);
2434 ea
= -code
->src
.literal
;
2436 SET_W_REG (code
->dst
.reg
, res
);
2437 goto just_flags_inc16
;
2439 case O (O_DEC
, SL
): /* dec.l */
2441 * This insn only uses register operands, but still
2442 * it would be cleaner to use fetch and store... */
2443 rd
= GET_L_REG (code
->dst
.reg
);
2444 ea
= -code
->src
.literal
;
2446 SET_L_REG (code
->dst
.reg
, res
);
2447 goto just_flags_inc32
;
2449 case O (O_INC
, SB
): /* inc.b */
2451 * This insn only uses register operands, but still
2452 * it would be cleaner to use fetch and store... */
2453 rd
= GET_B_REG (code
->src
.reg
);
2456 SET_B_REG (code
->src
.reg
, res
);
2457 goto just_flags_inc8
;
2459 case O (O_INC
, SW
): /* inc.w */
2461 * This insn only uses register operands, but still
2462 * it would be cleaner to use fetch and store... */
2463 rd
= GET_W_REG (code
->dst
.reg
);
2464 ea
= code
->src
.literal
;
2466 SET_W_REG (code
->dst
.reg
, res
);
2467 goto just_flags_inc16
;
2469 case O (O_INC
, SL
): /* inc.l */
2471 * This insn only uses register operands, but still
2472 * it would be cleaner to use fetch and store... */
2473 rd
= GET_L_REG (code
->dst
.reg
);
2474 ea
= code
->src
.literal
;
2476 SET_L_REG (code
->dst
.reg
, res
);
2477 goto just_flags_inc32
;
2479 case O (O_LDC
, SB
): /* ldc.b */
2480 if (fetch (sd
, &code
->src
, &res
))
2484 case O (O_LDC
, SW
): /* ldc.w */
2485 if (fetch (sd
, &code
->src
, &res
))
2488 /* Word operand, value from MSB, must be shifted. */
2492 case O (O_LDC
, SL
): /* ldc.l */
2493 if (fetch (sd
, &code
->src
, &res
))
2495 switch (code
->dst
.type
) {
2496 case X (OP_SBR
, SL
):
2497 h8_set_sbr (sd
, res
);
2499 case X (OP_VBR
, SL
):
2500 h8_set_vbr (sd
, res
);
2507 case O (O_STC
, SW
): /* stc.w */
2508 case O (O_STC
, SB
): /* stc.b */
2509 if (code
->src
.type
== X (OP_CCR
, SB
))
2512 res
= h8_get_ccr (sd
);
2514 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2517 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2518 res
= h8_get_exr (sd
);
2523 /* Word operand, value to MSB, must be shifted. */
2524 if (code
->opcode
== X (O_STC
, SW
))
2526 if (store (sd
, &code
->dst
, res
))
2529 case O (O_STC
, SL
): /* stc.l */
2530 switch (code
->src
.type
) {
2531 case X (OP_SBR
, SL
):
2532 res
= h8_get_sbr (sd
);
2534 case X (OP_VBR
, SL
):
2535 res
= h8_get_vbr (sd
);
2540 if (store (sd
, &code
->dst
, res
))
2544 case O (O_ANDC
, SB
): /* andc.b */
2545 if (code
->dst
.type
== X (OP_CCR
, SB
))
2548 rd
= h8_get_ccr (sd
);
2550 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2553 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2554 rd
= h8_get_exr (sd
);
2558 ea
= code
->src
.literal
;
2562 case O (O_ORC
, SB
): /* orc.b */
2563 if (code
->dst
.type
== X (OP_CCR
, SB
))
2566 rd
= h8_get_ccr (sd
);
2568 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2571 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2572 rd
= h8_get_exr (sd
);
2576 ea
= code
->src
.literal
;
2580 case O (O_XORC
, SB
): /* xorc.b */
2581 if (code
->dst
.type
== X (OP_CCR
, SB
))
2584 rd
= h8_get_ccr (sd
);
2586 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2589 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2590 rd
= h8_get_exr (sd
);
2594 ea
= code
->src
.literal
;
2598 case O (O_BRAS
, SB
): /* bra/s */
2599 /* This is basically an ordinary branch, with a delay slot. */
2600 if (fetch (sd
, &code
->src
, &res
))
2608 /* Execution continues at next instruction, but
2609 delayed_branch is set up for next cycle. */
2610 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2614 case O (O_BRAB
, SB
): /* bra rd.b */
2615 case O (O_BRAW
, SW
): /* bra rd.w */
2616 case O (O_BRAL
, SL
): /* bra erd.l */
2617 if (fetch (sd
, &code
->src
, &rd
))
2619 switch (OP_SIZE (code
->opcode
)) {
2620 case SB
: rd
&= 0xff; break;
2621 case SW
: rd
&= 0xffff; break;
2622 case SL
: rd
&= 0xffffffff; break;
2624 pc
= code
->next_pc
+ rd
;
2627 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2628 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2629 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2630 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2631 if (fetch (sd
, &code
->dst
, &rd
) ||
2632 fetch (sd
, &code
->src
, &bit
))
2635 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2636 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2638 if ((rd
& (1 << bit
))) /* no branch */
2641 else /* branch/call if set */
2643 if (!(rd
& (1 << bit
))) /* no branch */
2647 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2649 pc
= code
->next_pc
+ res
;
2651 if (code
->opcode
== O (O_BRABC
, SB
) ||
2652 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2660 case O (O_BRA
, SB
): /* bra, branch always */
2665 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2670 case O (O_BHI
, SB
): /* bhi */
2676 case O (O_BLS
, SB
): /* bls */
2681 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2686 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2691 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2695 case O (O_BGT
, SB
): /* bgt */
2696 if (((Z
|| (N
^ V
)) == 0))
2700 case O (O_BLE
, SB
): /* ble */
2701 if (((Z
|| (N
^ V
)) == 1))
2705 case O (O_BGE
, SB
): /* bge */
2709 case O (O_BLT
, SB
): /* blt */
2713 case O (O_BMI
, SB
): /* bmi */
2717 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2722 case O (O_BPL
, SB
): /* bpl */
2726 case O (O_BVC
, SB
): /* bvc */
2730 case O (O_BVS
, SB
): /* bvs */
2735 /* Trap for Command Line setup. */
2736 case O (O_SYS_CMDLINE
, SB
):
2738 int i
= 0; /* Loop counter. */
2739 int j
= 0; /* Loop counter. */
2740 int ind_arg_len
= 0; /* Length of each argument. */
2741 int no_of_args
= 0; /* The no. or cmdline args. */
2742 int current_location
= 0; /* Location of string. */
2743 int old_sp
= 0; /* The Initial Stack Pointer. */
2744 int no_of_slots
= 0; /* No. of slots required on the stack
2745 for storing cmdline args. */
2746 int sp_move
= 0; /* No. of locations by which the stack needs
2748 int new_sp
= 0; /* The final stack pointer location passed
2750 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2751 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2752 args on the stack. */
2753 int char_ptr_size
= 0; /* Size of a character pointer on
2755 int addr_cmdline
= 0; /* Memory location where cmdline has
2757 int size_cmdline
= 0; /* Size of cmdline. */
2759 /* Set the address of 256 free locations where command line is
2761 addr_cmdline
= cmdline_location();
2762 h8_set_reg (sd
, 0, addr_cmdline
);
2764 /* Counting the no. of commandline arguments. */
2765 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2768 /* No. of arguments in the command line. */
2771 /* Current location is just a temporary variable,which we are
2772 setting to the point to the start of our commandline string. */
2773 current_location
= addr_cmdline
;
2775 /* Allocating space for storing pointers of the command line
2777 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2779 /* Setting char_ptr_size to the sizeof (char *) on the different
2781 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2790 for (i
= 0; i
< no_of_args
; i
++)
2794 /* The size of the commandline argument. */
2795 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2797 /* The total size of the command line string. */
2798 size_cmdline
+= ind_arg_len
;
2800 /* As we have only 256 bytes, we need to provide a graceful
2801 exit. Anyways, a program using command line arguments
2802 where we cannot store all the command line arguments
2803 given may behave unpredictably. */
2804 if (size_cmdline
>= 256)
2806 h8_set_reg (sd
, 0, 0);
2811 /* current_location points to the memory where the next
2812 commandline argument is stored. */
2813 argv_ptrs
[i
] = current_location
;
2814 for (j
= 0; j
< ind_arg_len
; j
++)
2816 SET_MEMORY_B ((current_location
+
2817 (sizeof (char) * j
)),
2818 *(h8_get_cmdline_arg (sd
, i
) +
2819 sizeof (char) * j
));
2822 /* Setting current_location to the starting of next
2824 current_location
+= ind_arg_len
;
2828 /* This is the original position of the stack pointer. */
2829 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2831 /* We need space from the stack to store the pointers to argvs. */
2832 /* As we will infringe on the stack, we need to shift the stack
2833 pointer so that the data is not overwritten. We calculate how
2834 much space is required. */
2835 sp_move
= (no_of_args
) * (char_ptr_size
);
2837 /* The final position of stack pointer, we have thus taken some
2838 space from the stack. */
2839 new_sp
= old_sp
- sp_move
;
2841 /* Temporary variable holding value where the argv pointers need
2843 argv_ptrs_location
= new_sp
;
2845 /* The argv pointers are stored at sequential locations. As per
2847 for (i
= 0; i
< no_of_args
; i
++)
2849 /* Saving the argv pointer. */
2850 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2852 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2856 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2859 /* The next location where the pointer to the next argv
2860 string has to be stored. */
2861 argv_ptrs_location
+= char_ptr_size
;
2864 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2866 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2868 SET_MEMORY_L (old_sp
, 0x0);
2872 SET_MEMORY_W (old_sp
, 0x0);
2875 /* Freeing allocated memory. */
2877 for (i
= 0; i
<= no_of_args
; i
++)
2879 free (h8_get_cmdline_arg (sd
, i
));
2881 free (h8_get_command_line (sd
));
2883 /* The no. of argv arguments are returned in Reg 0. */
2884 h8_set_reg (sd
, 0, no_of_args
);
2885 /* The Pointer to argv in Register 1. */
2886 h8_set_reg (sd
, 1, new_sp
);
2887 /* Setting the stack pointer to the new value. */
2888 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2892 /* System call processing starts. */
2893 case O (O_SYS_OPEN
, SB
):
2895 int len
= 0; /* Length of filename. */
2896 char *filename
; /* Filename would go here. */
2897 char temp_char
; /* Temporary character */
2898 int mode
= 0; /* Mode bits for the file. */
2899 int open_return
; /* Return value of open, file descriptor. */
2900 int i
; /* Loop counter */
2901 int filename_ptr
; /* Pointer to filename in cpu memory. */
2903 /* Setting filename_ptr to first argument of open, */
2904 /* and trying to get mode. */
2905 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2907 filename_ptr
= GET_L_REG (0);
2908 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2912 filename_ptr
= GET_W_REG (0);
2913 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2916 /* Trying to find the length of the filename. */
2917 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2920 while (temp_char
!= '\0')
2922 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2926 /* Allocating space for the filename. */
2927 filename
= (char *) malloc (sizeof (char) * len
);
2929 /* String copying the filename from memory. */
2930 for (i
= 0; i
< len
; i
++)
2932 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2933 filename
[i
] = temp_char
;
2936 /* Callback to open and return the file descriptor. */
2937 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2939 /* Return value in register 0. */
2940 h8_set_reg (sd
, 0, open_return
);
2942 /* Freeing memory used for filename. */
2947 case O (O_SYS_READ
, SB
):
2949 char *char_ptr
; /* Where characters read would be stored. */
2950 int fd
; /* File descriptor */
2951 int buf_size
; /* BUF_SIZE parameter in read. */
2952 int i
= 0; /* Temporary Loop counter */
2953 int read_return
= 0; /* Return value from callback to
2956 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2957 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2959 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2961 /* Callback to read and return the no. of characters read. */
2963 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2965 /* The characters read are stored in cpu memory. */
2966 for (i
= 0; i
< buf_size
; i
++)
2968 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2969 *(char_ptr
+ (sizeof (char) * i
)));
2972 /* Return value in Register 0. */
2973 h8_set_reg (sd
, 0, read_return
);
2975 /* Freeing memory used as buffer. */
2980 case O (O_SYS_WRITE
, SB
):
2982 int fd
; /* File descriptor */
2983 char temp_char
; /* Temporary character */
2984 int len
; /* Length of write, Parameter II to write. */
2985 int char_ptr
; /* Character Pointer, Parameter I of write. */
2986 char *ptr
; /* Where characters to be written are stored.
2988 int write_return
; /* Return value from callback to write. */
2989 int i
= 0; /* Loop counter */
2991 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2992 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2993 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2995 /* Allocating space for the characters to be written. */
2996 ptr
= (char *) malloc (sizeof (char) * len
);
2998 /* Fetching the characters from cpu memory. */
2999 for (i
= 0; i
< len
; i
++)
3001 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
3005 /* Callback write and return the no. of characters written. */
3006 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
3008 /* Return value in Register 0. */
3009 h8_set_reg (sd
, 0, write_return
);
3011 /* Freeing memory used as buffer. */
3016 case O (O_SYS_LSEEK
, SB
):
3018 int fd
; /* File descriptor */
3019 int offset
; /* Offset */
3020 int origin
; /* Origin */
3021 int lseek_return
; /* Return value from callback to lseek. */
3023 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3024 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3025 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
3027 /* Callback lseek and return offset. */
3029 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
3031 /* Return value in register 0. */
3032 h8_set_reg (sd
, 0, lseek_return
);
3036 case O (O_SYS_CLOSE
, SB
):
3038 int fd
; /* File descriptor */
3039 int close_return
; /* Return value from callback to close. */
3041 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3043 /* Callback close and return. */
3044 close_return
= sim_callback
->close (sim_callback
, fd
);
3046 /* Return value in register 0. */
3047 h8_set_reg (sd
, 0, close_return
);
3051 case O (O_SYS_FSTAT
, SB
):
3053 int fd
; /* File descriptor */
3054 struct stat stat_rec
; /* Stat record */
3055 int fstat_return
; /* Return value from callback to stat. */
3056 int stat_ptr
; /* Pointer to stat record. */
3057 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3059 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3061 /* Setting stat_ptr to second argument of stat. */
3062 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3064 /* Callback stat and return. */
3065 fstat_return
= sim_callback
->fstat (sim_callback
, fd
, &stat_rec
);
3067 /* Have stat_ptr point to starting of stat_rec. */
3068 temp_stat_ptr
= (char *) (&stat_rec
);
3070 /* Setting up the stat structure returned. */
3071 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3073 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3075 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3077 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3079 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3081 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3083 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3085 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3087 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3089 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3091 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3093 /* Return value in register 0. */
3094 h8_set_reg (sd
, 0, fstat_return
);
3098 case O (O_SYS_STAT
, SB
):
3100 int len
= 0; /* Length of filename. */
3101 char *filename
; /* Filename would go here. */
3102 char temp_char
; /* Temporary character */
3103 int filename_ptr
; /* Pointer to filename in cpu memory. */
3104 struct stat stat_rec
; /* Stat record */
3105 int stat_return
; /* Return value from callback to stat */
3106 int stat_ptr
; /* Pointer to stat record. */
3107 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3108 int i
= 0; /* Loop Counter */
3110 /* Setting filename_ptr to first argument of open. */
3111 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3113 /* Trying to find the length of the filename. */
3114 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3117 while (temp_char
!= '\0')
3119 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3123 /* Allocating space for the filename. */
3124 filename
= (char *) malloc (sizeof (char) * len
);
3126 /* String copying the filename from memory. */
3127 for (i
= 0; i
< len
; i
++)
3129 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3130 filename
[i
] = temp_char
;
3133 /* Setting stat_ptr to second argument of stat. */
3134 /* stat_ptr = h8_get_reg (sd, 1); */
3135 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3137 /* Callback stat and return. */
3139 sim_callback
->stat (sim_callback
, filename
, &stat_rec
);
3141 /* Have stat_ptr point to starting of stat_rec. */
3142 temp_stat_ptr
= (char *) (&stat_rec
);
3144 /* Freeing memory used for filename. */
3147 /* Setting up the stat structure returned. */
3148 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3150 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3152 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3154 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3156 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3158 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3160 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3162 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3164 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3166 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3168 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3170 /* Return value in register 0. */
3171 h8_set_reg (sd
, 0, stat_return
);
3174 /* End of system call processing. */
3176 case O (O_NOT
, SB
): /* not.b */
3177 if (fetch2 (sd
, &code
->src
, &rd
))
3183 case O (O_NOT
, SW
): /* not.w */
3184 if (fetch2 (sd
, &code
->src
, &rd
))
3190 case O (O_NOT
, SL
): /* not.l */
3191 if (fetch2 (sd
, &code
->src
, &rd
))
3197 case O (O_SHLL
, SB
): /* shll.b */
3198 case O (O_SHLR
, SB
): /* shlr.b */
3199 if (fetch2 (sd
, &code
->dst
, &rd
))
3202 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3203 ea
= 1; /* unary op */
3204 else /* binary op */
3205 fetch (sd
, &code
->src
, &ea
);
3207 if (code
->opcode
== O (O_SHLL
, SB
))
3210 c
= rd
& (0x80 >> (ea
- 1));
3216 c
= rd
& (1 << (ea
- 1));
3217 rd
= (unsigned char) rd
>> ea
;
3221 case O (O_SHLL
, SW
): /* shll.w */
3222 case O (O_SHLR
, SW
): /* shlr.w */
3223 if (fetch2 (sd
, &code
->dst
, &rd
))
3226 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3227 ea
= 1; /* unary op */
3229 fetch (sd
, &code
->src
, &ea
);
3231 if (code
->opcode
== O (O_SHLL
, SW
))
3234 c
= rd
& (0x8000 >> (ea
- 1));
3240 c
= rd
& (1 << (ea
- 1));
3241 rd
= (unsigned short) rd
>> ea
;
3245 case O (O_SHLL
, SL
): /* shll.l */
3246 case O (O_SHLR
, SL
): /* shlr.l */
3247 if (fetch2 (sd
, &code
->dst
, &rd
))
3250 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3251 ea
= 1; /* unary op */
3253 fetch (sd
, &code
->src
, &ea
);
3255 if (code
->opcode
== O (O_SHLL
, SL
))
3258 c
= rd
& (0x80000000 >> (ea
- 1));
3264 c
= rd
& (1 << (ea
- 1));
3265 rd
= (unsigned int) rd
>> ea
;
3269 case O (O_SHAL
, SB
):
3270 case O (O_SHAR
, SB
):
3271 if (fetch2 (sd
, &code
->dst
, &rd
))
3274 if (code
->src
.type
== X (OP_IMM
, SB
))
3275 fetch (sd
, &code
->src
, &ea
);
3279 if (code
->opcode
== O (O_SHAL
, SB
))
3281 c
= rd
& (0x80 >> (ea
- 1));
3282 res
= rd
>> (7 - ea
);
3283 v
= ((res
& 1) && !(res
& 2))
3284 || (!(res
& 1) && (res
& 2));
3289 c
= rd
& (1 << (ea
- 1));
3291 rd
= ((signed char) rd
) >> ea
;
3295 case O (O_SHAL
, SW
):
3296 case O (O_SHAR
, SW
):
3297 if (fetch2 (sd
, &code
->dst
, &rd
))
3300 if (code
->src
.type
== X (OP_IMM
, SW
))
3301 fetch (sd
, &code
->src
, &ea
);
3305 if (code
->opcode
== O (O_SHAL
, SW
))
3307 c
= rd
& (0x8000 >> (ea
- 1));
3308 res
= rd
>> (15 - ea
);
3309 v
= ((res
& 1) && !(res
& 2))
3310 || (!(res
& 1) && (res
& 2));
3315 c
= rd
& (1 << (ea
- 1));
3317 rd
= ((signed short) rd
) >> ea
;
3321 case O (O_SHAL
, SL
):
3322 case O (O_SHAR
, SL
):
3323 if (fetch2 (sd
, &code
->dst
, &rd
))
3326 if (code
->src
.type
== X (OP_IMM
, SL
))
3327 fetch (sd
, &code
->src
, &ea
);
3331 if (code
->opcode
== O (O_SHAL
, SL
))
3333 c
= rd
& (0x80000000 >> (ea
- 1));
3334 res
= rd
>> (31 - ea
);
3335 v
= ((res
& 1) && !(res
& 2))
3336 || (!(res
& 1) && (res
& 2));
3341 c
= rd
& (1 << (ea
- 1));
3343 rd
= ((signed int) rd
) >> ea
;
3347 case O (O_ROTL
, SB
):
3348 case O (O_ROTR
, SB
):
3349 if (fetch2 (sd
, &code
->dst
, &rd
))
3352 if (code
->src
.type
== X (OP_IMM
, SB
))
3353 fetch (sd
, &code
->src
, &ea
);
3358 if (code
->opcode
== O (O_ROTL
, SB
))
3368 rd
= ((unsigned char) rd
) >> 1;
3376 case O (O_ROTL
, SW
):
3377 case O (O_ROTR
, SW
):
3378 if (fetch2 (sd
, &code
->dst
, &rd
))
3381 if (code
->src
.type
== X (OP_IMM
, SW
))
3382 fetch (sd
, &code
->src
, &ea
);
3387 if (code
->opcode
== O (O_ROTL
, SW
))
3397 rd
= ((unsigned short) rd
) >> 1;
3405 case O (O_ROTL
, SL
):
3406 case O (O_ROTR
, SL
):
3407 if (fetch2 (sd
, &code
->dst
, &rd
))
3410 if (code
->src
.type
== X (OP_IMM
, SL
))
3411 fetch (sd
, &code
->src
, &ea
);
3416 if (code
->opcode
== O (O_ROTL
, SL
))
3418 c
= rd
& 0x80000000;
3426 rd
= ((unsigned int) rd
) >> 1;
3434 case O (O_ROTXL
, SB
):
3435 case O (O_ROTXR
, SB
):
3436 if (fetch2 (sd
, &code
->dst
, &rd
))
3439 if (code
->src
.type
== X (OP_IMM
, SB
))
3440 fetch (sd
, &code
->src
, &ea
);
3445 if (code
->opcode
== O (O_ROTXL
, SB
))
3456 rd
= ((unsigned char) rd
) >> 1;
3465 case O (O_ROTXL
, SW
):
3466 case O (O_ROTXR
, SW
):
3467 if (fetch2 (sd
, &code
->dst
, &rd
))
3470 if (code
->src
.type
== X (OP_IMM
, SW
))
3471 fetch (sd
, &code
->src
, &ea
);
3476 if (code
->opcode
== O (O_ROTXL
, SW
))
3487 rd
= ((unsigned short) rd
) >> 1;
3496 case O (O_ROTXL
, SL
):
3497 case O (O_ROTXR
, SL
):
3498 if (fetch2 (sd
, &code
->dst
, &rd
))
3501 if (code
->src
.type
== X (OP_IMM
, SL
))
3502 fetch (sd
, &code
->src
, &ea
);
3507 if (code
->opcode
== O (O_ROTXL
, SL
))
3509 res
= rd
& 0x80000000;
3518 rd
= ((unsigned int) rd
) >> 1;
3529 case O (O_JMP
, SB
): /* jmp */
3531 fetch (sd
, &code
->src
, &pc
);
3536 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3538 if (fetch (sd
, &code
->src
, &pc
))
3541 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3543 if (h8300hmode
&& !h8300_normal_mode
)
3546 SET_MEMORY_L (tmp
, code
->next_pc
);
3551 SET_MEMORY_W (tmp
, code
->next_pc
);
3553 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3559 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3560 if (fetch (sd
, &code
->src
, &res
))
3562 pc
= code
->next_pc
+ res
;
3565 case O (O_RTE
, SN
): /* rte, return from exception */
3567 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3568 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3570 if (h8300smode
) /* pop exr */
3572 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3575 if (h8300hmode
&& !h8300_normal_mode
)
3577 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3579 pc
= GET_MEMORY_L (tmp
);
3584 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3586 pc
= GET_MEMORY_W (tmp
);
3591 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3594 case O (O_RTS
, SN
): /* rts, return from subroutine */
3596 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3598 if (h8300hmode
&& !h8300_normal_mode
)
3600 pc
= GET_MEMORY_L (tmp
);
3605 pc
= GET_MEMORY_W (tmp
);
3609 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3612 case O (O_ILL
, SB
): /* illegal */
3613 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
3616 case O (O_SLEEP
, SN
): /* sleep */
3617 /* Check for magic numbers in r1 and r2. */
3618 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3619 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3620 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3622 /* This trap comes from _exit, not from gdb. */
3623 sim_engine_set_run_state (sd
, sim_exited
,
3624 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3627 /* Unfortunately this won't really work, because
3628 when we take a breakpoint trap, R0 has a "random",
3629 user-defined value. Don't see any immediate solution. */
3630 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3632 /* Pass the stop signal up to gdb. */
3633 sim_engine_set_run_state (sd
, sim_stopped
,
3634 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3639 /* Treat it as a sigtrap. */
3640 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3644 case O (O_TRAPA
, SB
): /* trapa */
3645 if (fetch (sd
, &code
->src
, &res
))
3646 goto end
; /* res is vector number. */
3648 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3649 if(h8300_normal_mode
)
3652 SET_MEMORY_W (tmp
, code
->next_pc
);
3654 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3659 SET_MEMORY_L (tmp
, code
->next_pc
);
3661 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3669 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3672 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3674 if(h8300_normal_mode
)
3675 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3677 pc
= GET_MEMORY_L (0x20 + res
* 4);
3681 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3684 case O (O_BSETEQ
, SB
):
3689 case O (O_BSETNE
, SB
):
3694 case O (O_BCLREQ
, SB
):
3699 case O (O_BCLRNE
, SB
):
3704 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3705 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3707 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3709 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3710 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3711 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3712 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3713 if (C
) ea
|= m
); /* bst */
3714 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3715 if (!C
) ea
|= m
); /* bist */
3716 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3717 if (Z
) ea
|= m
); /* bstz */
3718 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3719 if (!Z
) ea
|= m
); /* bistz */
3720 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3721 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3722 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3723 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3724 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3725 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3727 case O (O_BFLD
, SB
): /* bfld */
3730 if (fetch (sd
, &code
->src
, &bit
))
3735 if (fetch (sd
, &code
->dst
, &ea
))
3745 if (store (sd
, &code
->op3
, ea
))
3750 case O(O_BFST
, SB
): /* bfst */
3751 /* bitfield store */
3752 /* NOTE: the imm8 value is in dst, and the ea value
3753 (which is actually the destination) is in op3.
3754 It has to be that way, to avoid breaking the assembler. */
3756 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3758 if (bit
== 0) /* noop -- nothing to do. */
3761 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3764 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3767 /* Left-shift the register data into position. */
3768 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3771 /* Combine it with the neighboring bits. */
3772 ea
= (ea
& ~bit
) | (rd
& bit
);
3775 if (store2 (sd
, &code
->op3
, ea
))
3779 case O (O_CLRMAC
, SN
): /* clrmac */
3780 h8_set_mach (sd
, 0);
3781 h8_set_macl (sd
, 0);
3782 h8_set_macZ (sd
, 1);
3783 h8_set_macV (sd
, 0);
3784 h8_set_macN (sd
, 0);
3787 case O (O_STMAC
, SL
): /* stmac, 260 */
3788 switch (code
->src
.type
) {
3789 case X (OP_MACH
, SL
):
3790 res
= h8_get_mach (sd
);
3791 if (res
& 0x200) /* sign extend */
3794 case X (OP_MACL
, SL
):
3795 res
= h8_get_macl (sd
);
3797 default: goto illegal
;
3799 nz
= !h8_get_macZ (sd
);
3800 n
= h8_get_macN (sd
);
3801 v
= h8_get_macV (sd
);
3803 if (store (sd
, &code
->dst
, res
))
3808 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3809 if (fetch (sd
, &code
->src
, &rd
))
3812 switch (code
->dst
.type
) {
3813 case X (OP_MACH
, SL
):
3814 rd
&= 0x3ff; /* Truncate to 10 bits */
3815 h8_set_mach (sd
, rd
);
3817 case X (OP_MACL
, SL
):
3818 h8_set_macl (sd
, rd
);
3820 default: goto illegal
;
3822 h8_set_macV (sd
, 0);
3826 if (fetch (sd
, &code
->src
, &rd
) ||
3827 fetch (sd
, &code
->dst
, &res
))
3830 /* Ye gods, this is non-portable!
3831 However, the existing mul/div code is similar. */
3832 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3834 if (h8_get_macS (sd
)) /* Saturating mode */
3836 long long mac
= h8_get_macl (sd
);
3838 if (mac
& 0x80000000) /* sign extend */
3839 mac
|= 0xffffffff00000000LL
;
3842 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3843 h8_set_macV (sd
, 1);
3844 h8_set_macZ (sd
, (mac
== 0));
3845 h8_set_macN (sd
, (mac
< 0));
3846 h8_set_macl (sd
, (int) mac
);
3848 else /* "Less Saturating" mode */
3850 long long mac
= h8_get_mach (sd
);
3852 mac
+= h8_get_macl (sd
);
3854 if (mac
& 0x20000000000LL
) /* sign extend */
3855 mac
|= 0xfffffc0000000000LL
;
3858 if (mac
> 0x1ffffffffffLL
||
3859 mac
< (long long) 0xfffffe0000000000LL
)
3860 h8_set_macV (sd
, 1);
3861 h8_set_macZ (sd
, (mac
== 0));
3862 h8_set_macN (sd
, (mac
< 0));
3863 h8_set_macl (sd
, (int) mac
);
3865 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3869 case O (O_MULS
, SW
): /* muls.w */
3870 if (fetch (sd
, &code
->src
, &ea
) ||
3871 fetch (sd
, &code
->dst
, &rd
))
3874 ea
= SEXTSHORT (ea
);
3875 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3879 if (store (sd
, &code
->dst
, res
))
3884 case O (O_MULS
, SL
): /* muls.l */
3885 if (fetch (sd
, &code
->src
, &ea
) ||
3886 fetch (sd
, &code
->dst
, &rd
))
3891 n
= res
& 0x80000000;
3892 nz
= res
& 0xffffffff;
3893 if (store (sd
, &code
->dst
, res
))
3897 case O (O_MULSU
, SL
): /* muls/u.l */
3898 if (fetch (sd
, &code
->src
, &ea
) ||
3899 fetch (sd
, &code
->dst
, &rd
))
3902 /* Compute upper 32 bits of the 64-bit result. */
3903 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3905 n
= res
& 0x80000000;
3906 nz
= res
& 0xffffffff;
3907 if (store (sd
, &code
->dst
, res
))
3911 case O (O_MULU
, SW
): /* mulu.w */
3912 if (fetch (sd
, &code
->src
, &ea
) ||
3913 fetch (sd
, &code
->dst
, &rd
))
3916 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3918 /* Don't set Z or N. */
3919 if (store (sd
, &code
->dst
, res
))
3924 case O (O_MULU
, SL
): /* mulu.l */
3925 if (fetch (sd
, &code
->src
, &ea
) ||
3926 fetch (sd
, &code
->dst
, &rd
))
3931 /* Don't set Z or N. */
3932 if (store (sd
, &code
->dst
, res
))
3937 case O (O_MULUU
, SL
): /* mulu/u.l */
3938 if (fetch (sd
, &code
->src
, &ea
) ||
3939 fetch (sd
, &code
->dst
, &rd
))
3942 /* Compute upper 32 bits of the 64-bit result. */
3943 res
= (((unsigned long long) (unsigned) ea
) *
3944 ((unsigned long long) (unsigned) rd
)) >> 32;
3946 /* Don't set Z or N. */
3947 if (store (sd
, &code
->dst
, res
))
3952 case O (O_MULXS
, SB
): /* mulxs.b */
3953 if (fetch (sd
, &code
->src
, &ea
) ||
3954 fetch (sd
, &code
->dst
, &rd
))
3958 res
= ea
* SEXTCHAR (rd
);
3962 if (store (sd
, &code
->dst
, res
))
3967 case O (O_MULXS
, SW
): /* mulxs.w */
3968 if (fetch (sd
, &code
->src
, &ea
) ||
3969 fetch (sd
, &code
->dst
, &rd
))
3972 ea
= SEXTSHORT (ea
);
3973 res
= ea
* SEXTSHORT (rd
& 0xffff);
3975 n
= res
& 0x80000000;
3976 nz
= res
& 0xffffffff;
3977 if (store (sd
, &code
->dst
, res
))
3982 case O (O_MULXU
, SB
): /* mulxu.b */
3983 if (fetch (sd
, &code
->src
, &ea
) ||
3984 fetch (sd
, &code
->dst
, &rd
))
3987 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3989 if (store (sd
, &code
->dst
, res
))
3994 case O (O_MULXU
, SW
): /* mulxu.w */
3995 if (fetch (sd
, &code
->src
, &ea
) ||
3996 fetch (sd
, &code
->dst
, &rd
))
3999 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
4001 if (store (sd
, &code
->dst
, res
))
4006 case O (O_TAS
, SB
): /* tas (test and set) */
4007 if (!h8300sxmode
) /* h8sx can use any register. */
4008 switch (code
->src
.reg
)
4019 if (fetch (sd
, &code
->src
, &res
))
4021 if (store (sd
, &code
->src
, res
| 0x80))
4024 goto just_flags_log8
;
4026 case O (O_DIVU
, SW
): /* divu.w */
4027 if (fetch (sd
, &code
->src
, &ea
) ||
4028 fetch (sd
, &code
->dst
, &rd
))
4034 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
4038 if (store (sd
, &code
->dst
, res
))
4042 case O (O_DIVU
, SL
): /* divu.l */
4043 if (fetch (sd
, &code
->src
, &ea
) ||
4044 fetch (sd
, &code
->dst
, &rd
))
4047 n
= ea
& 0x80000000;
4048 nz
= ea
& 0xffffffff;
4050 res
= (unsigned) rd
/ ea
;
4054 if (store (sd
, &code
->dst
, res
))
4058 case O (O_DIVS
, SW
): /* divs.w */
4059 if (fetch (sd
, &code
->src
, &ea
) ||
4060 fetch (sd
, &code
->dst
, &rd
))
4065 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
4075 if (store (sd
, &code
->dst
, res
))
4079 case O (O_DIVS
, SL
): /* divs.l */
4080 if (fetch (sd
, &code
->src
, &ea
) ||
4081 fetch (sd
, &code
->dst
, &rd
))
4095 n
= res
& 0x80000000;
4096 if (store (sd
, &code
->dst
, res
))
4100 case O (O_DIVXU
, SB
): /* divxu.b */
4101 if (fetch (sd
, &code
->src
, &ea
) ||
4102 fetch (sd
, &code
->dst
, &rd
))
4105 rd
= UEXTSHORT (rd
);
4112 tmp
= (unsigned) rd
% ea
;
4113 res
= (unsigned) rd
/ ea
;
4121 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4125 case O (O_DIVXU
, SW
): /* divxu.w */
4126 if (fetch (sd
, &code
->src
, &ea
) ||
4127 fetch (sd
, &code
->dst
, &rd
))
4130 ea
= UEXTSHORT (ea
);
4136 tmp
= (unsigned) rd
% ea
;
4137 res
= (unsigned) rd
/ ea
;
4145 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4149 case O (O_DIVXS
, SB
): /* divxs.b */
4150 if (fetch (sd
, &code
->src
, &ea
) ||
4151 fetch (sd
, &code
->dst
, &rd
))
4154 rd
= SEXTSHORT (rd
);
4159 tmp
= (int) rd
% (int) ea
;
4160 res
= (int) rd
/ (int) ea
;
4171 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4175 case O (O_DIVXS
, SW
): /* divxs.w */
4176 if (fetch (sd
, &code
->src
, &ea
) ||
4177 fetch (sd
, &code
->dst
, &rd
))
4180 ea
= SEXTSHORT (ea
);
4184 tmp
= (int) rd
% (int) ea
;
4185 res
= (int) rd
/ (int) ea
;
4195 n
= res
& 0x80000000;
4196 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4200 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4201 if (fetch2 (sd
, &code
->dst
, &rd
))
4203 ea
= rd
& 0x80 ? -256 : 0;
4204 res
= (rd
& 0xff) + ea
;
4207 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4208 if (fetch2 (sd
, &code
->dst
, &rd
))
4210 if (code
->src
.type
== X (OP_IMM
, SL
))
4212 if (fetch (sd
, &code
->src
, &ea
))
4215 if (ea
== 2) /* exts.l #2, nn */
4217 /* Sign-extend from 8-bit to 32-bit. */
4218 ea
= rd
& 0x80 ? -256 : 0;
4219 res
= (rd
& 0xff) + ea
;
4223 /* Sign-extend from 16-bit to 32-bit. */
4224 ea
= rd
& 0x8000 ? -65536 : 0;
4225 res
= (rd
& 0xffff) + ea
;
4228 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4229 if (fetch2 (sd
, &code
->dst
, &rd
))
4232 res
= (rd
& 0xff) + ea
;
4235 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4236 if (fetch2 (sd
, &code
->dst
, &rd
))
4238 if (code
->src
.type
== X (OP_IMM
, SL
))
4240 if (fetch (sd
, &code
->src
, &ea
))
4243 if (ea
== 2) /* extu.l #2, nn */
4245 /* Zero-extend from 8-bit to 32-bit. */
4247 res
= (rd
& 0xff) + ea
;
4251 /* Zero-extend from 16-bit to 32-bit. */
4253 res
= (rd
& 0xffff) + ea
;
4256 case O (O_NOP
, SN
): /* nop */
4259 case O (O_STM
, SL
): /* stm, store to memory */
4261 int nregs
, firstreg
, i
;
4263 nregs
= GET_MEMORY_B (pc
+ 1);
4266 firstreg
= code
->src
.reg
;
4268 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4270 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4271 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4276 case O (O_LDM
, SL
): /* ldm, load from memory */
4277 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4278 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4280 int nregs
, firstreg
, i
;
4282 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4283 firstreg
= code
->dst
.reg
& 0xf;
4284 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4286 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4287 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4290 switch (code
->opcode
) {
4291 case O (O_RTEL
, SN
):
4293 case O (O_RTSL
, SN
):
4302 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4303 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4304 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4305 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4306 res
= res
; /* Value added == 0. */
4307 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4308 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4309 res
= res
+ 0x6; /* Value added == 6. */
4310 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4311 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4312 res
= res
+ 0x6; /* Value added == 6. */
4313 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4314 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4315 res
= res
+ 0x60; /* Value added == 60. */
4316 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4317 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4318 res
= res
+ 0x66; /* Value added == 66. */
4319 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4320 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4321 res
= res
+ 0x66; /* Value added == 66. */
4322 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4323 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4324 res
= res
+ 0x60; /* Value added == 60. */
4325 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4326 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4327 res
= res
+ 0x66; /* Value added == 66. */
4328 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4329 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4330 res
= res
+ 0x66; /* Value added == 66. */
4335 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4336 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4337 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4338 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4339 res
= res
; /* Value added == 0. */
4340 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4341 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4342 res
= res
+ 0xfa; /* Value added == 0xfa. */
4343 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4344 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4345 res
= res
+ 0xa0; /* Value added == 0xa0. */
4346 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4347 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4348 res
= res
+ 0x9a; /* Value added == 0x9a. */
4354 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4359 (*sim_callback
->printf_filtered
) (sim_callback
,
4360 "sim_resume: internal error.\n");
4361 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4365 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4366 code
->dst
.type
== X (OP_CCR
, SW
))
4368 h8_set_ccr (sd
, res
);
4371 else if (h8300smode
&&
4372 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4373 code
->dst
.type
== X (OP_EXR
, SW
)))
4375 h8_set_exr (sd
, res
);
4376 if (h8300smode
) /* Get exr. */
4378 trace
= (h8_get_exr (sd
) >> 7) & 1;
4379 intMask
= h8_get_exr (sd
) & 7;
4388 /* When a branch works */
4389 if (fetch (sd
, &code
->src
, &res
))
4391 if (res
& 1) /* bad address */
4393 pc
= code
->next_pc
+ res
;
4396 /* Set the cond codes from res */
4399 /* Set the flags after an 8 bit inc/dec operation */
4403 v
= (rd
& 0x7f) == 0x7f;
4406 /* Set the flags after an 16 bit inc/dec operation */
4410 v
= (rd
& 0x7fff) == 0x7fff;
4413 /* Set the flags after an 32 bit inc/dec operation */
4415 n
= res
& 0x80000000;
4416 nz
= res
& 0xffffffff;
4417 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4421 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4424 if (store2 (sd
, &code
->dst
, rd
))
4429 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4432 if (store2 (sd
, &code
->dst
, rd
))
4437 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4438 n
= (rd
& 0x80000000);
4439 nz
= rd
& 0xffffffff;
4440 if (store2 (sd
, &code
->dst
, rd
))
4445 if (store2 (sd
, &code
->dst
, res
))
4449 /* flags after a 32bit logical operation */
4450 n
= res
& 0x80000000;
4451 nz
= res
& 0xffffffff;
4456 if (store2 (sd
, &code
->dst
, res
))
4460 /* flags after a 16bit logical operation */
4467 if (store2 (sd
, &code
->dst
, res
))
4477 if (store2 (sd
, &code
->dst
, res
))
4484 switch (code
->opcode
/ 4)
4488 v
= ((rd
& 0x80) == (ea
& 0x80)
4489 && (rd
& 0x80) != (res
& 0x80));
4494 v
= ((rd
& 0x80) != (-ea
& 0x80)
4495 && (rd
& 0x80) != (res
& 0x80));
4502 break; /* No effect on v flag. */
4507 if (store2 (sd
, &code
->dst
, res
))
4513 c
= (res
& 0x10000);
4514 switch (code
->opcode
/ 4)
4518 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4519 && (rd
& 0x8000) != (res
& 0x8000));
4524 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4525 && (rd
& 0x8000) != (res
& 0x8000));
4534 if (store2 (sd
, &code
->dst
, res
))
4538 n
= res
& 0x80000000;
4539 nz
= res
& 0xffffffff;
4540 switch (code
->opcode
/ 4)
4544 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4545 && (rd
& 0x80000000) != (res
& 0x80000000));
4546 c
= ((unsigned) res
< (unsigned) rd
) ||
4547 ((unsigned) res
< (unsigned) ea
);
4552 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4553 && (rd
& 0x80000000) != (res
& 0x80000000));
4554 c
= (unsigned) rd
< (unsigned) -ea
;
4557 v
= (rd
== 0x80000000);
4564 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4567 h8_set_delayed_branch (sd
, 0);
4574 if (--poll_count
< 0)
4576 poll_count
= POLL_QUIT_INTERVAL
;
4577 if ((*sim_callback
->poll_quit
) != NULL
4578 && (*sim_callback
->poll_quit
) (sim_callback
))
4579 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
4581 sim_engine_get_run_state (sd
, &reason
, &sigrc
);
4582 } while (reason
== sim_running
);
4584 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4585 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4586 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4591 h8_set_exr (sd
, (trace
<<7) | intMask
);
4593 h8_set_mask (sd
, oldmask
);
4597 sim_trace (SIM_DESC sd
)
4599 /* FIXME: Unfinished. */
4600 (*sim_callback
->printf_filtered
) (sim_callback
,
4601 "sim_trace: trace not supported.\n");
4602 return 1; /* Done. */
4606 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4613 for (i
= 0; i
< size
; i
++)
4615 if (addr
< memory_size
)
4617 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4618 h8_set_cache_idx (sd
, addr
+ i
, 0);
4622 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4629 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4634 if (addr
< memory_size
)
4635 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4637 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4643 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
4648 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4649 shortval
= (value
[0] << 8) | (value
[1]);
4650 intval
= h8300hmode
? longval
: shortval
;
4656 if(h8300_normal_mode
)
4657 h8_set_pc (sd
, shortval
); /* PC for Normal mode is 2 bytes */
4659 h8_set_pc (sd
, intval
);
4662 (*sim_callback
->printf_filtered
) (sim_callback
,
4663 "sim_store_register: bad regnum %d.\n",
4673 h8_set_reg (sd
, rn
, intval
);
4676 h8_set_ccr (sd
, intval
);
4679 h8_set_exr (sd
, intval
);
4682 h8_set_sbr (sd
, intval
);
4685 h8_set_vbr (sd
, intval
);
4688 h8_set_mach (sd
, intval
);
4691 h8_set_macl (sd
, intval
);
4694 h8_set_cycles (sd
, longval
);
4698 h8_set_insts (sd
, longval
);
4702 h8_set_ticks (sd
, longval
);
4709 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
4716 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4721 (*sim_callback
->printf_filtered
) (sim_callback
,
4722 "sim_fetch_register: bad regnum %d.\n",
4727 v
= h8_get_ccr (sd
);
4730 v
= h8_get_exr (sd
);
4736 v
= h8_get_sbr (sd
);
4739 v
= h8_get_vbr (sd
);
4742 v
= h8_get_mach (sd
);
4745 v
= h8_get_macl (sd
);
4755 v
= h8_get_reg (sd
, rn
);
4758 v
= h8_get_cycles (sd
);
4762 v
= h8_get_ticks (sd
);
4766 v
= h8_get_insts (sd
);
4770 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4771 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4787 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
4789 sim_engine_get_run_state (sd
, reason
, sigrc
);
4792 /* FIXME: Rename to sim_set_mem_size. */
4797 /* Memory size is fixed. */
4801 set_simcache_size (SIM_DESC sd
, int n
)
4804 free (sd
->sim_cache
);
4807 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4808 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4809 sd
->sim_cache_size
= n
;
4814 sim_info (SIM_DESC sd
, int verbose
)
4816 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4817 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4819 (*sim_callback
->printf_filtered
) (sim_callback
,
4820 "\n\n#instructions executed %10d\n",
4822 (*sim_callback
->printf_filtered
) (sim_callback
,
4823 "#cycles (v approximate) %10d\n",
4824 h8_get_cycles (sd
));
4825 (*sim_callback
->printf_filtered
) (sim_callback
,
4826 "#real time taken %10.4f\n",
4828 (*sim_callback
->printf_filtered
) (sim_callback
,
4829 "#virtual time taken %10.4f\n",
4831 if (timetaken
!= 0.0)
4832 (*sim_callback
->printf_filtered
) (sim_callback
,
4833 "#simulation ratio %10.4f\n",
4834 virttime
/ timetaken
);
4835 (*sim_callback
->printf_filtered
) (sim_callback
,
4837 h8_get_compiles (sd
));
4838 (*sim_callback
->printf_filtered
) (sim_callback
,
4839 "#cache size %10d\n",
4840 sd
->sim_cache_size
);
4843 /* This to be conditional on `what' (aka `verbose'),
4844 however it was never passed as non-zero. */
4848 for (i
= 0; i
< O_LAST
; i
++)
4850 if (h8_get_stats (sd
, i
))
4851 (*sim_callback
->printf_filtered
) (sim_callback
, "%d: %d\n",
4852 i
, h8_get_stats (sd
, i
));
4858 /* Indicate whether the cpu is an H8/300 or H8/300H.
4859 FLAG is non-zero for the H8/300H. */
4862 set_h8300h (unsigned long machine
)
4864 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4865 This function being replaced by a sim_open:ARGV configuration
4868 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4870 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4873 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4876 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4879 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4880 h8300_normal_mode
= 1;
4883 /* Cover function of sim_state_free to free the cpu buffers as well. */
4886 free_state (SIM_DESC sd
)
4888 if (STATE_MODULES (sd
) != NULL
)
4889 sim_module_uninstall (sd
);
4891 /* Fixme: free buffers in _sim_cpu. */
4892 sim_state_free (sd
);
4896 sim_open (SIM_OPEN_KIND kind
,
4897 struct host_callback_struct
*callback
,
4904 sd
= sim_state_alloc (kind
, callback
);
4905 sd
->cpu
= sim_cpu_alloc (sd
, 0);
4906 cpu
= STATE_CPU (sd
, 0);
4907 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4908 sim_state_initialize (sd
, cpu
);
4909 /* sim_cpu object is new, so some initialization is needed. */
4910 init_pointers_needed
= 1;
4912 /* For compatibility (FIXME: is this right?). */
4913 current_alignment
= NONSTRICT_ALIGNMENT
;
4914 current_target_byte_order
= BIG_ENDIAN
;
4916 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4922 /* getopt will print the error message so we just have to exit if
4923 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4924 to call print_filtered. */
4925 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4927 /* Uninstall the modules to avoid memory leaks,
4928 file descriptor leaks, etc. */
4933 /* Check for/establish the a reference program image. */
4934 if (sim_analyze_program (sd
,
4935 (STATE_PROG_ARGV (sd
) != NULL
4936 ? *STATE_PROG_ARGV (sd
)
4937 : NULL
), abfd
) != SIM_RC_OK
)
4943 /* Establish any remaining configuration options. */
4944 if (sim_config (sd
) != SIM_RC_OK
)
4950 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4952 /* Uninstall the modules to avoid memory leaks,
4953 file descriptor leaks, etc. */
4958 /* sim_hw_configure (sd); */
4960 /* FIXME: Much of the code in sim_load can be moved here. */
4964 sim_callback
= callback
;
4969 sim_close (SIM_DESC sd
, int quitting
)
4971 /* Nothing to do. */
4974 /* Called by gdb to load a program into memory. */
4977 sim_load (SIM_DESC sd
, char *prog
, bfd
*abfd
, int from_tty
)
4981 /* FIXME: The code below that sets a specific variant of the H8/300
4982 being simulated should be moved to sim_open(). */
4984 /* See if the file is for the H8/300 or H8/300H. */
4985 /* ??? This may not be the most efficient way. The z8k simulator
4986 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4990 prog_bfd
= bfd_openr (prog
, NULL
);
4991 if (prog_bfd
!= NULL
)
4993 /* Set the cpu type. We ignore failure from bfd_check_format
4994 and bfd_openr as sim_load_file checks too. */
4995 if (bfd_check_format (prog_bfd
, bfd_object
))
4997 set_h8300h (bfd_get_mach (prog_bfd
));
5001 /* If we're using gdb attached to the simulator, then we have to
5002 reallocate memory for the simulator.
5004 When gdb first starts, it calls fetch_registers (among other
5005 functions), which in turn calls init_pointers, which allocates
5008 The problem is when we do that, we don't know whether we're
5009 debugging an H8/300 or H8/300H program.
5011 This is the first point at which we can make that determination,
5012 so we just reallocate memory now; this will also allow us to handle
5013 switching between H8/300 and H8/300H programs without exiting
5016 if (h8300smode
&& !h8300_normal_mode
)
5017 memory_size
= H8300S_MSIZE
;
5018 else if (h8300hmode
&& !h8300_normal_mode
)
5019 memory_size
= H8300H_MSIZE
;
5021 memory_size
= H8300_MSIZE
;
5023 if (h8_get_memory_buf (sd
))
5024 free (h8_get_memory_buf (sd
));
5025 if (h8_get_cache_idx_buf (sd
))
5026 free (h8_get_cache_idx_buf (sd
));
5027 if (h8_get_eightbit_buf (sd
))
5028 free (h8_get_eightbit_buf (sd
));
5030 h8_set_memory_buf (sd
, (unsigned char *)
5031 calloc (sizeof (char), memory_size
));
5032 h8_set_cache_idx_buf (sd
, (unsigned short *)
5033 calloc (sizeof (short), memory_size
));
5034 sd
->memory_size
= memory_size
;
5035 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
5037 /* `msize' must be a power of two. */
5038 if ((memory_size
& (memory_size
- 1)) != 0)
5040 (*sim_callback
->printf_filtered
) (sim_callback
,
5041 "sim_load: bad memory size.\n");
5044 h8_set_mask (sd
, memory_size
- 1);
5046 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
5047 sim_kind
== SIM_OPEN_DEBUG
,
5051 /* Close the bfd if we opened it. */
5052 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5053 bfd_close (prog_bfd
);
5057 /* Close the bfd if we opened it. */
5058 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5059 bfd_close (prog_bfd
);
5064 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
5071 h8_set_pc (sd
, bfd_get_start_address (abfd
));
5075 /* Command Line support. */
5078 /* Counting the no. of commandline arguments. */
5079 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
5082 /* Allocating memory for the argv pointers. */
5083 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
5084 * (no_of_args
+ 1)));
5086 for (i
= 0; i
< no_of_args
; i
++)
5088 /* Copying the argument string. */
5089 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
5091 h8_set_cmdline_arg (sd
, i
, NULL
);
5098 sim_set_callbacks (struct host_callback_struct
*ptr
)