2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
22 #include <sys/times.h>
23 #include <sys/param.h>
29 #define X(op, size) op*4+size
31 #define SP (HMODE ? SL:SW)
44 #define h8_opcodes ops
46 #include "opcode/h8300.h"
50 #define LOW_BYTE(x) ((x) & 0xff)
51 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
52 #define P(X,Y) ((X<<8) | Y)
54 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
57 c = (cpu.ccr >> 0) & 1;\
58 v = (cpu.ccr >> 1) & 1;\
59 nz = !((cpu.ccr >> 2) & 1);\
60 n = (cpu.ccr >> 3) & 1;
62 #ifdef __CHAR_IS_SIGNED__
63 #define SEXTCHAR(x) ((char)(x))
67 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
70 #define UEXTCHAR(x) ((x) & 0xff)
71 #define UEXTSHORT(x) ((x) & 0xffff)
72 #define SEXTSHORT(x) ((short)(x))
74 static cpu_state_type cpu
;
84 return b
.tms_utime
+ b
.tms_stime
;
106 return HMODE
? SL
: SW
;
125 return X (OP_MEM
, SP
);
132 decode (addr
, data
, dst
)
144 struct h8_opcode
*q
= h8_opcodes
;
148 /* Find the exact opcode/arg combo */
152 unsigned int len
= 0;
158 op_type looking_for
= *nib
;
159 int thisnib
= data
[len
>> 1];
161 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
163 if (looking_for
< 16)
166 if (looking_for
!= thisnib
)
172 if ((int) looking_for
& (int) B31
)
174 if (!(((int) thisnib
& 0x8) != 0))
176 looking_for
= (op_type
) ((int) looking_for
& ~(int)
181 if ((int) looking_for
& (int) B30
)
183 if (!(((int) thisnib
& 0x8) == 0))
185 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
187 if (looking_for
& DBIT
)
189 if ((looking_for
& 5) != (thisnib
&5)) goto fail
;
190 abs
= (thisnib
& 0x8) ? 2 : 1;
192 else if (looking_for
& (REG
| IND
| INC
| DEC
))
194 if (looking_for
& REG
)
197 * Can work out size from the
200 size
= bitfrom (looking_for
);
202 if (looking_for
& SRC
)
211 else if (looking_for
& L_16
)
213 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
215 if (looking_for
& (PCREL
|DISP
))
220 else if (looking_for
& ABSJMP
)
227 else if (looking_for
& L_32
)
230 abs
= (data
[i
] << 24)
231 | (data
[i
+ 1] << 16)
238 else if (looking_for
& L_24
)
241 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+
245 else if (looking_for
& IGNORE
)
249 else if (looking_for
& DISPREG
)
251 rdisp
= thisnib
& 0x7;
253 else if (looking_for
& KBIT
)
268 else if (looking_for
& L_8
)
272 if (looking_for
& PCREL
)
274 abs
= SEXTCHAR (data
[len
>> 1]);
278 abs
= data
[len
>> 1] & 0xff;
281 else if (looking_for
& L_3
)
287 else if (looking_for
== E
)
291 /* Fill in the args */
293 op_type
*args
= q
->args
.nib
;
300 int rn
= (x
& DST
) ? rd
: rs
;
313 if (x
& (IMM
| KBIT
| DBIT
))
315 p
->type
= X (OP_IMM
, size
);
322 ops (like mul) have two sizes */
325 p
->type
= X (OP_REG
, size
);
330 p
->type
= X (OP_INC
, size
);
335 p
->type
= X (OP_DEC
, size
);
340 p
->type
= X (OP_DISP
, size
);
344 else if (x
& (ABS
| ABSJMP
| ABSMOV
))
346 p
->type
= X (OP_DISP
, size
);
352 p
->type
= X (OP_MEM
, size
);
357 p
->type
= X (OP_PCREL
, size
);
358 p
->literal
= abs
+ addr
+ 2;
362 p
->type
= X (OP_IMM
, SP
);
367 p
->type
= X (OP_DISP
, size
);
369 p
->reg
= rdisp
& 0x7;
376 printf ("Hmmmm %x", x
);
384 * But a jmp or a jsr gets
385 * automagically lvalued, since we
386 * branch to their address not their
389 if (q
->how
== O (O_JSR
, SB
)
390 || q
->how
== O (O_JMP
, SB
))
392 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
396 if (dst
->dst
.type
== -1)
399 dst
->opcode
= q
->how
;
400 dst
->cycles
= q
->time
;
402 /* And a jsr to 0xc4 is turned into a magic trap */
404 if (dst
->opcode
== O(O_JSR
, SB
))
406 if(dst
->src
.literal
== 0xc4)
408 dst
->opcode
= O(O_SYSCALL
,SB
);
412 dst
->next_pc
= addr
+ len
/ 2;
417 printf ("Dont understand %x \n", looking_for
);
429 dst
->opcode
= O (O_ILL
, SB
);
438 /* find the next cache entry to use */
440 idx
= cpu
.cache_top
+ 1;
442 if (idx
>= cpu
.csize
)
448 /* Throw away its old meaning */
449 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
451 /* set to new address */
452 cpu
.cache
[idx
].oldpc
= pc
;
454 /* fill in instruction info */
455 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
457 /* point to new cache entry */
458 cpu
.cache_idx
[pc
] = idx
;
462 static unsigned char *breg
[18];
463 static unsigned short *wreg
[18];
464 static unsigned int *lreg
[18];
466 #define GET_B_REG(x) *(breg[x])
467 #define SET_B_REG(x,y) (*(breg[x])) = (y)
468 #define GET_W_REG(x) *(wreg[x])
469 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
471 #define GET_L_REG(x) *(lreg[x])
472 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
474 #define GET_MEMORY_L(x) \
475 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
477 #define GET_MEMORY_W(x) \
478 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
481 #define SET_MEMORY_B(x,y) \
482 (cpu.memory[(x)] = y)
484 #define SET_MEMORY_W(x,y) \
485 {register unsigned char *_p = cpu.memory+x;\
486 register int __y = y;\
490 #define SET_MEMORY_L(x,y) \
491 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
492 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
494 #define GET_MEMORY_B(x) (cpu.memory[x])
501 int abs
= arg
->literal
;
508 return GET_B_REG (rn
);
510 return GET_W_REG (rn
);
512 return GET_L_REG (rn
);
547 case X (OP_DISP
, SB
):
548 t
= GET_L_REG (rn
) + abs
;
550 return GET_MEMORY_B (t
);
552 case X (OP_DISP
, SW
):
553 t
= GET_L_REG (rn
) + abs
;
555 return GET_MEMORY_W (t
);
557 case X (OP_DISP
, SL
):
558 t
= GET_L_REG (rn
) + abs
;
560 return GET_MEMORY_L (t
);
578 int abs
= arg
->literal
;
594 t
= GET_L_REG (rn
) - 1;
601 t
= (GET_L_REG (rn
) - 2 ) & cpu
.mask
;
607 t
= (GET_L_REG(rn
) -4 ) & cpu
.mask
;
613 case X (OP_DISP
, SB
):
614 t
= GET_L_REG (rn
) + abs
;
619 case X (OP_DISP
, SW
):
620 t
= GET_L_REG (rn
) + abs
;
625 case X (OP_DISP
, SL
):
626 t
= GET_L_REG (rn
) + abs
;
662 cpu
.memory
= (unsigned char *) calloc (sizeof (char), MSIZE
);
663 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), MSIZE
);
664 cpu
.mask
= (1<<MPOWER
)-1;
666 for (i
= 0; i
< 9; i
++)
671 for (i
= 0; i
< 8; i
++)
673 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
674 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
675 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
676 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
677 cpu
.regs
[i
] = 0x00112233;
703 lreg
[i
] = &cpu
.regs
[i
];
707 lreg
[8] = &cpu
.regs
[8];
709 /* initialize the seg registers */
717 control_c (sig
, code
, scp
, addr
)
723 cpu
.exception
= SIGINT
;
737 int tick_start
= get_now ();
750 prev
= signal (SIGINT
, control_c
);
754 cpu
.exception
= SIGTRAP
;
771 cidx
= cpu
.cache_idx
[pc
];
772 code
= cpu
.cache
+ cidx
;
775 #define ALUOP(STORE, NAME, HOW) \
776 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
777 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
778 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
781 #define LOGOP(NAME, HOW) \
782 case O(NAME,SB): HOW; goto log8;\
783 case O(NAME, SW): HOW; goto log16;\
784 case O(NAME,SL): HOW; goto log32;
791 printf ("%x %d %s\n", pc
, code
->opcode
,
792 code
->op
? code
->op
->name
: "**");
794 cpu
.stats
[code
->opcode
]++;
798 cycles
+= code
->cycles
;
800 switch (code
->opcode
)
804 * This opcode is a fake for when we get to an
805 * instruction which hasnt been compiled
813 rd
= fetch (&code
->dst
);
814 ea
= fetch (&code
->src
);
820 rd
= fetch (&code
->dst
);
821 ea
= fetch (&code
->src
);
826 #define RD rd = fetch(&code->src);
827 #define RD_EA rd = fetch(&code->dst); ea = fetch(&code->src);
829 ALUOP (1, O_SUB
, RD_EA
; ea
= -ea
; res
= rd
+ ea
);
830 ALUOP (1, O_NEG
, RD
; ea
= -ea
;rd
= 0; res
= rd
+ ea
);
833 rd
= GET_B_REG(code
->dst
.reg
);
834 ea
= fetch(&code
->src
);
838 rd
= GET_W_REG(code
->dst
.reg
);
839 ea
= fetch(&code
->src
);
843 rd
= GET_L_REG(code
->dst
.reg
);
844 ea
= fetch(&code
->src
);
849 LOGOP (O_AND
, RD_EA
; res
= rd
& ea
);
851 LOGOP (O_OR
, RD_EA
; res
= rd
| ea
);
853 LOGOP (O_XOR
, RD_EA
; res
= rd
^ ea
);
856 case O(O_MOV_TO_MEM
,SB
):
857 res
= GET_B_REG(code
->src
.reg
);
859 case O(O_MOV_TO_MEM
,SW
):
860 res
= GET_W_REG(code
->src
.reg
);
862 case O(O_MOV_TO_MEM
,SL
):
863 res
= GET_L_REG(code
->src
.reg
);
867 case O(O_MOV_TO_REG
,SB
):
868 res
= fetch(&code
->src
);
869 SET_B_REG(code
->dst
.reg
, res
);
870 goto just_flags_log8
;
871 case O(O_MOV_TO_REG
,SW
):
872 res
= fetch(&code
->src
);
873 SET_W_REG(code
->dst
.reg
, res
);
874 goto just_flags_log16
;
875 case O(O_MOV_TO_REG
,SL
):
876 res
= fetch(&code
->src
);
877 SET_L_REG(code
->dst
.reg
, res
);
878 goto just_flags_log32
;
882 SET_L_REG(code
->dst
.reg
,
883 GET_L_REG(code
->dst
.reg
)
884 + code
->src
.literal
);
889 SET_L_REG(code
->dst
.reg
,
890 GET_L_REG(code
->dst
.reg
)
891 - code
->src
.literal
);
895 rd
= fetch (&code
->dst
);
896 ea
= fetch (&code
->src
);
899 goto just_flags_alu8
;
902 rd
= fetch (&code
->dst
);
903 ea
= fetch (&code
->src
);
906 goto just_flags_alu16
;
909 rd
= fetch (&code
->dst
);
910 ea
= fetch (&code
->src
);
913 goto just_flags_alu32
;
917 rd
= GET_B_REG (code
->src
.reg
);
920 SET_B_REG (code
->src
.reg
, res
);
921 goto just_flags_inc8
;
924 rd
= GET_W_REG (code
->dst
.reg
);
925 ea
= - code
->src
.literal
;
927 SET_W_REG (code
->dst
.reg
, res
);
928 goto just_flags_inc16
;
931 rd
= GET_L_REG (code
->dst
.reg
);
932 ea
= -code
->src
.literal
;
934 SET_L_REG (code
->dst
.reg
, res
);
935 goto just_flags_inc32
;
939 rd
= GET_B_REG (code
->src
.reg
);
942 SET_B_REG (code
->src
.reg
, res
);
943 goto just_flags_inc8
;
946 rd
= GET_W_REG (code
->dst
.reg
);
947 ea
= code
->src
.literal
;
949 SET_W_REG (code
->dst
.reg
, res
);
950 goto just_flags_inc16
;
953 rd
= GET_L_REG (code
->dst
.reg
);
954 ea
= code
->src
.literal
;
956 SET_L_REG (code
->dst
.reg
, res
);
957 goto just_flags_inc32
;
960 #define GET_CCR(x) BUILDSR();x = cpu.ccr
964 ea
= code
->src
.literal
;
1005 if (((Z
|| (N
^ V
)) == 0))
1011 if (((Z
|| (N
^ V
)) == 1))
1045 case O(O_SYSCALL
, SB
):
1046 printf("%c", cpu
.regs
[2]);
1051 #define OSHIFTS(name, how) \
1052 case O(name, SB):{ int t;int hm = 0x80; rd = GET_B_REG(code->src.reg);how; goto shift8;} \
1053 case O(name, SW):{ int t;int hm = 0x8000; rd = GET_W_REG(code->src.reg); how; goto shift16;} \
1054 case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how; goto shift32;}
1057 OSHIFTS(O_NOT
, rd
= ~rd
);
1058 OSHIFTS(O_SHLL
, c
= rd
& hm
; rd
<<=1);
1059 OSHIFTS(O_SHLR
, c
= rd
& 1; rd
= (unsigned int) rd
>> 1);
1060 OSHIFTS(O_SHAL
, c
= rd
& hm
; rd
<<=1);
1061 OSHIFTS(O_SHAR
, t
= rd
& hm
; c
= rd
&1;rd
>>=1;rd
|=t
;);
1062 OSHIFTS(O_ROTL
, c
= rd
& hm
; rd
<<=1; rd
|= C
);
1063 OSHIFTS(O_ROTR
, c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
;);
1064 OSHIFTS(O_ROTXL
,t
= rd
& hm
; rd
<<=1; rd
|=C
; c
=t
;);
1065 OSHIFTS(O_ROTXR
,t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|=hm
; c
=t
;);
1069 pc
= fetch (&code
->src
);
1077 pc
= fetch (&code
->src
);
1084 SET_MEMORY_L (tmp
, code
->next_pc
);
1089 SET_MEMORY_W (tmp
, code
->next_pc
);
1096 pc
= code
->src
.literal
;
1108 pc
= GET_MEMORY_L (tmp
);
1114 pc
= GET_MEMORY_W (tmp
);
1123 cpu
.exception
= SIGILL
;
1127 cpu
.exception
= SIGTRAP
;
1130 #define OBITOP(name,f, s, op) \
1131 case O(name, SB): {int m;int b; \
1132 if (f) ea = fetch(&code->dst);\
1133 m=1<<code->src.literal;\
1135 if(s) store(&code->dst,ea); goto next;\
1137 OBITOP(O_BNOT
,1,1,ea
^= m
);
1138 OBITOP(O_BTST
,1,0,nz
= ea
& m
);
1139 OBITOP(O_BLD
,1,0, c
= ea
& m
);
1140 OBITOP(O_BILD
,1,0, c
= !(ea
& m
));
1141 OBITOP(O_BST
,1,1, ea
&= ~m
; if (C
) ea
|=m
);
1142 OBITOP(O_BIST
,1,1, ea
&= ~m
; if (!C
) ea
|=m
);
1143 OBITOP(O_BAND
,1,1, b
= (ea
& m
) && C
; ea
&= ~m
; if (b
) ea
|=m
);
1144 OBITOP(O_BIAND
,1,1, b
= (ea
& m
) && C
; ea
&= ~m
; if (!b
) ea
|=m
);
1145 OBITOP(O_BOR
,1,1, b
= (ea
& m
) || C
; ea
&= ~m
; if (b
) ea
|=m
);
1146 OBITOP(O_BIOR
,1,1, b
= (ea
& m
) || C
; ea
&= ~m
; if (!b
) ea
|=m
);
1147 OBITOP(O_BXOR
,1,1, b
= (ea
& m
) != C
; ea
&= ~m
; if (b
) ea
|=m
);
1148 OBITOP(O_BIXOR
,1,1, b
= (ea
& m
) != C
; ea
&= ~m
; if (!b
) ea
|=m
);
1149 OBITOP(O_BCLR
,1,1, ea
&= ~m
; );
1150 OBITOP(O_BSET
,1,1, ea
|= m
; );
1153 #define MOP(bsize, signed) \
1162 bsize ? SEXTCHAR(GET_W_REG(code->dst.reg)): \
1163 SEXTSHORT(GET_W_REG(code->dst.reg)); \
1165 bsize ? SEXTCHAR(GET_B_REG(code->src.reg)): \
1166 SEXTSHORT(GET_B_REG(code->src.reg)); \
1170 multiplicand = bsize ? UEXTCHAR(GET_W_REG(code->dst.reg)): \
1171 UEXTSHORT(GET_W_REG(code->dst.reg)); \
1173 bsize ? UEXTCHAR(GET_B_REG(code->src.reg)): \
1174 UEXTSHORT(GET_B_REG(code->src.reg)); \
1177 result = multiplier * multiplicand; \
1181 n = result & (bsize ? 0x8000: 0x80000000); \
1182 nz = result & (bsize ? 0xffff: 0xffffffff); \
1186 SET_W_REG(code->dst.reg, result); \
1190 SET_L_REG(code->dst.reg, result); \
1195 case O(O_MULS
, SB
): MOP(1,1);break;
1196 case O(O_MULS
, SW
): MOP(0,1); break;
1197 case O(O_MULU
, SB
): MOP(1,0);break;
1198 case O(O_MULU
, SW
): MOP(0,0); break;
1204 rd
= GET_W_REG(code
->dst
.reg
);
1205 ea
= GET_B_REG(code
->src
.reg
);
1211 SET_W_REG(code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1220 rd
= GET_L_REG(code
->dst
.reg
);
1221 ea
= GET_W_REG(code
->src
.reg
);
1229 SET_L_REG(code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1238 rd
= SEXTSHORT(GET_W_REG(code
->dst
.reg
));
1239 ea
= SEXTCHAR(GET_B_REG(code
->src
.reg
));
1242 tmp
= (int)rd
% (int)ea
;
1243 rd
= (int)rd
/ (int)ea
;
1250 SET_W_REG(code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1256 rd
= GET_L_REG(code
->dst
.reg
);
1257 ea
= SEXTSHORT(GET_W_REG(code
->src
.reg
));
1260 tmp
= (int)rd
% (int)ea
;
1261 rd
= (int)rd
/ (int)ea
;
1262 n
= rd
& 0x80000000;
1267 SET_L_REG(code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1270 case O (O_EXTS
, SW
):
1271 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1272 ea
= rd
& 0x80 ? -256 : 0;
1275 case O (O_EXTS
, SL
):
1276 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1277 ea
= rd
& 0x8000 ? -65536 : 0;
1280 case O (O_EXTU
, SW
):
1281 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1285 case O (O_EXTU
, SL
):
1286 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1292 cpu
.exception
= 123;
1303 /* When a branch works */
1304 pc
= code
->src
.literal
;
1307 /* Set the cond codes from res */
1310 /* Set the flags after an 8 bit inc/dec operation */
1314 v
= (rd
& 0x7f) == 0x7f;
1318 /* Set the flags after an 16 bit inc/dec operation */
1322 v
= (rd
& 0x7fff) == 0x7fff;
1326 /* Set the flags after an 32 bit inc/dec operation */
1328 n
= res
& 0x80000000;
1329 nz
= res
& 0xffffffff;
1330 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1335 /* Set flags after an 8 bit shift op, carry set in insn */
1339 SET_B_REG(code
->src
.reg
, rd
);
1344 /* Set flags after an 16 bit shift op, carry set in insn */
1349 SET_W_REG(code
->src
.reg
, rd
);
1353 /* Set flags after an 32 bit shift op, carry set in insn */
1354 n
= (rd
& 0x80000000);
1356 nz
= rd
& 0xffffffff;
1357 SET_L_REG(code
->src
.reg
, rd
);
1361 store (&code
->dst
, res
);
1363 /* flags after a 32bit logical operation */
1364 n
= res
& 0x80000000;
1365 nz
= res
& 0xffffffff;
1370 store (&code
->dst
, res
);
1372 /* flags after a 16bit logical operation */
1380 store (&code
->dst
, res
);
1388 SET_B_REG (code
->dst
.reg
, res
);
1392 v
= ((ea
& 0x80) == (rd
& 0x80)) && ((ea
& 0x80) != (res
& 0x80));
1397 SET_W_REG (code
->dst
.reg
, res
);
1401 v
= ((ea
& 0x8000) == (rd
& 0x8000)) && ((ea
& 0x8000) != (res
& 0x8000));
1402 c
= (res
& 0x10000);
1406 SET_L_REG (code
->dst
.reg
, res
);
1408 n
= res
& 0x80000000;
1409 nz
= res
& 0xffffffff;
1410 v
= ((ea
& 0x80000000) == (rd
& 0x80000000))
1411 && ((ea
& 0x80000000) != (res
& 0x80000000));
1412 switch (code
->opcode
/ 4)
1415 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1419 c
= (unsigned) rd
< (unsigned) -ea
;
1431 if (cpu
.regs
[8] ) abort();
1436 while (!cpu
.exception
);
1437 cpu
.ticks
+= get_now () - tick_start
;
1438 cpu
.cycles
+= cycles
;
1443 signal (SIGINT
, prev
);
1450 sim_write (addr
, buffer
, size
)
1452 unsigned char *buffer
;
1458 if (addr
< 0 || addr
+ size
> MSIZE
)
1460 for (i
= 0; i
< size
; i
++)
1462 cpu
.memory
[addr
+ i
] = buffer
[i
];
1463 cpu
.cache_idx
[addr
+ i
] = 0;
1468 sim_read (addr
, buffer
, size
)
1474 if (addr
< 0 || addr
+ size
> MSIZE
)
1476 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1490 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1491 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1494 #define CCR_REGNUM 8 /* Contains processor status */
1495 #define PC_REGNUM 9 /* Contains program counter */
1497 #define CYCLE_REGNUM 10
1498 #define INST_REGNUM 11
1499 #define TICK_REGNUM 12
1503 sim_store_register (rn
, value
)
1524 cpu
.regs
[rn
] = value
;
1544 sim_fetch_register (rn
, buf
)
1588 if (HMODE
|| longreg
)
1610 return cpu
.exception
;
1615 sim_store_register (PC_REGNUM
, n
);
1625 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1626 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1637 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1638 double virttime
= cpu
.cycles
/ 10.0e6
;
1641 printf ("\n\n#instructions executed %10d\n", cpu
.insts
);
1642 printf ("#cycles (v approximate) %10d\n", cpu
.cycles
);
1643 printf ("#real time taken %10.4f\n", timetaken
);
1644 printf ("#virtual time taked %10.4f\n", virttime
);
1645 if (timetaken
!= 0.0)
1646 printf ("#simulation ratio %10.4f\n", virttime
/ timetaken
);
1647 printf ("#compiles %10d\n", cpu
.compiles
);
1648 printf ("#cache size %10d\n", cpu
.csize
);
1655 for (i
= 0; i
< O_LAST
; i
++)
1658 printf("%d: %d\n", i
, cpu
.stats
[i
]);
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