2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
37 #include "remote-sim.h"
45 host_callback
*sim_callback
;
47 static SIM_OPEN_KIND sim_kind
;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size
PARAMS ((int));
56 #define X(op, size) op*4+size
58 #define SP (h8300hmode ? SL:SW)
71 #define h8_opcodes ops
73 #include "opcode/h8300.h"
77 /* The rate at which to call the host's poll_quit callback. */
79 #define POLL_QUIT_INTERVAL 0x80000
81 #define LOW_BYTE(x) ((x) & 0xff)
82 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
83 #define P(X,Y) ((X<<8) | Y)
85 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
88 c = (cpu.ccr >> 0) & 1;\
89 v = (cpu.ccr >> 1) & 1;\
90 nz = !((cpu.ccr >> 2) & 1);\
91 n = (cpu.ccr >> 3) & 1;
93 #ifdef __CHAR_IS_SIGNED__
94 #define SEXTCHAR(x) ((char)(x))
98 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
101 #define UEXTCHAR(x) ((x) & 0xff)
102 #define UEXTSHORT(x) ((x) & 0xffff)
103 #define SEXTSHORT(x) ((short)(x))
105 static cpu_state_type cpu
;
110 static int memory_size
;
141 return h8300hmode
? SL
: SW
;
154 return X (OP_IMM
, SP
);
156 return X (OP_REG
, SP
);
160 return X (OP_MEM
, SP
);
167 decode (addr
, data
, dst
)
180 struct h8_opcode
*q
= h8_opcodes
;
184 /* Find the exact opcode/arg combo */
188 unsigned int len
= 0;
194 op_type looking_for
= *nib
;
195 int thisnib
= data
[len
>> 1];
197 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
199 if (looking_for
< 16 && looking_for
>= 0)
201 if (looking_for
!= thisnib
)
206 if ((int) looking_for
& (int) B31
)
208 if (!(((int) thisnib
& 0x8) != 0))
210 looking_for
= (op_type
) ((int) looking_for
& ~(int)
214 if ((int) looking_for
& (int) B30
)
216 if (!(((int) thisnib
& 0x8) == 0))
218 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
220 if (looking_for
& DBIT
)
222 if ((looking_for
& 5) != (thisnib
& 5))
224 abs
= (thisnib
& 0x8) ? 2 : 1;
226 else if (looking_for
& (REG
| IND
| INC
| DEC
))
228 if (looking_for
& REG
)
231 * Can work out size from the
234 size
= bitfrom (looking_for
);
236 if (looking_for
& SRC
)
245 else if (looking_for
& L_16
)
247 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
249 if (looking_for
& (PCREL
| DISP
))
254 else if (looking_for
& ABSJMP
)
261 else if (looking_for
& MEMIND
)
265 else if (looking_for
& L_32
)
268 abs
= (data
[i
] << 24)
269 | (data
[i
+ 1] << 16)
275 else if (looking_for
& L_24
)
278 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
281 else if (looking_for
& IGNORE
)
285 else if (looking_for
& DISPREG
)
287 rdisp
= thisnib
& 0x7;
289 else if (looking_for
& KBIT
)
304 else if (looking_for
& L_8
)
308 if (looking_for
& PCREL
)
310 abs
= SEXTCHAR (data
[len
>> 1]);
312 else if (looking_for
& ABS8MEM
)
315 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
316 abs
|= data
[len
>> 1] & 0xff ;
320 abs
= data
[len
>> 1] & 0xff;
323 else if (looking_for
& L_3
)
329 else if (looking_for
== E
)
333 /* Fill in the args */
335 op_type
*args
= q
->args
.nib
;
341 int rn
= (x
& DST
) ? rd
: rs
;
355 p
->type
= X (OP_IMM
, size
);
358 else if (x
& (IMM
| KBIT
| DBIT
))
360 p
->type
= X (OP_IMM
, size
);
365 /* Reset the size, some
366 ops (like mul) have two sizes */
369 p
->type
= X (OP_REG
, size
);
374 p
->type
= X (OP_INC
, size
);
379 p
->type
= X (OP_DEC
, size
);
384 p
->type
= X (OP_DISP
, size
);
388 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
390 p
->type
= X (OP_DISP
, size
);
396 p
->type
= X (OP_MEM
, size
);
401 p
->type
= X (OP_PCREL
, size
);
402 p
->literal
= abs
+ addr
+ 2;
408 p
->type
= X (OP_IMM
, SP
);
413 p
->type
= X (OP_DISP
, size
);
415 p
->reg
= rdisp
& 0x7;
422 printf ("Hmmmm %x", x
);
429 * But a jmp or a jsr gets
430 * automagically lvalued, since we
431 * branch to their address not their
434 if (q
->how
== O (O_JSR
, SB
)
435 || q
->how
== O (O_JMP
, SB
))
437 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
440 if (dst
->dst
.type
== -1)
443 dst
->opcode
= q
->how
;
444 dst
->cycles
= q
->time
;
446 /* And a jsr to 0xc4 is turned into a magic trap */
448 if (dst
->opcode
== O (O_JSR
, SB
))
450 if (dst
->src
.literal
== 0xc4)
452 dst
->opcode
= O (O_SYSCALL
, SB
);
456 dst
->next_pc
= addr
+ len
/ 2;
461 printf ("Dont understand %x \n", looking_for
);
473 dst
->opcode
= O (O_ILL
, SB
);
482 /* find the next cache entry to use */
484 idx
= cpu
.cache_top
+ 1;
486 if (idx
>= cpu
.csize
)
492 /* Throw away its old meaning */
493 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
495 /* set to new address */
496 cpu
.cache
[idx
].oldpc
= pc
;
498 /* fill in instruction info */
499 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
501 /* point to new cache entry */
502 cpu
.cache_idx
[pc
] = idx
;
506 static unsigned char *breg
[18];
507 static unsigned short *wreg
[18];
508 static unsigned int *lreg
[18];
510 #define GET_B_REG(x) *(breg[x])
511 #define SET_B_REG(x,y) (*(breg[x])) = (y)
512 #define GET_W_REG(x) *(wreg[x])
513 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
515 #define GET_L_REG(x) *(lreg[x])
516 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
518 #define GET_MEMORY_L(x) \
520 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
521 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
522 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
523 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
525 #define GET_MEMORY_W(x) \
527 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
528 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
531 #define GET_MEMORY_B(x) \
532 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
534 #define SET_MEMORY_L(x,y) \
535 { register unsigned char *_p; register int __y = y; \
536 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
537 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
538 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
540 #define SET_MEMORY_W(x,y) \
541 { register unsigned char *_p; register int __y = y; \
542 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
543 _p[0] = (__y)>>8; _p[1] =(__y);}
545 #define SET_MEMORY_B(x,y) \
546 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
553 int abs
= arg
->literal
;
560 return GET_B_REG (rn
);
562 return GET_W_REG (rn
);
564 return GET_L_REG (rn
);
575 r
= GET_MEMORY_B (t
);
584 r
= GET_MEMORY_W (t
);
592 r
= GET_MEMORY_L (t
);
599 case X (OP_DISP
, SB
):
600 t
= GET_L_REG (rn
) + abs
;
602 return GET_MEMORY_B (t
);
604 case X (OP_DISP
, SW
):
605 t
= GET_L_REG (rn
) + abs
;
607 return GET_MEMORY_W (t
);
609 case X (OP_DISP
, SL
):
610 t
= GET_L_REG (rn
) + abs
;
612 return GET_MEMORY_L (t
);
615 t
= GET_MEMORY_L (abs
);
620 t
= GET_MEMORY_W (abs
);
638 int abs
= arg
->literal
;
654 t
= GET_L_REG (rn
) - 1;
661 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
667 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
672 case X (OP_DISP
, SB
):
673 t
= GET_L_REG (rn
) + abs
;
678 case X (OP_DISP
, SW
):
679 t
= GET_L_REG (rn
) + abs
;
684 case X (OP_DISP
, SL
):
685 t
= GET_L_REG (rn
) + abs
;
722 memory_size
= H8300H_MSIZE
;
724 memory_size
= H8300_MSIZE
;
725 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
726 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
727 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
729 /* `msize' must be a power of two */
730 if ((memory_size
& (memory_size
- 1)) != 0)
732 cpu
.mask
= memory_size
- 1;
734 for (i
= 0; i
< 9; i
++)
739 for (i
= 0; i
< 8; i
++)
741 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
742 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
743 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
744 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
745 cpu
.regs
[i
] = 0x00112233;
771 lreg
[i
] = &cpu
.regs
[i
];
774 lreg
[8] = &cpu
.regs
[8];
776 /* initialize the seg registers */
778 sim_set_simcache_size (CSIZE
);
783 control_c (sig
, code
, scp
, addr
)
789 cpu
.state
= SIM_STATE_STOPPED
;
790 cpu
.exception
= SIGINT
;
799 mop (code
, bsize
, sign
)
812 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
813 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
815 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
816 SEXTSHORT (GET_W_REG (code
->src
.reg
));
820 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
821 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
823 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
824 UEXTSHORT (GET_W_REG (code
->src
.reg
));
827 result
= multiplier
* multiplicand
;
831 n
= result
& (bsize
? 0x8000 : 0x80000000);
832 nz
= result
& (bsize
? 0xffff : 0xffffffff);
836 SET_W_REG (code
->dst
.reg
, result
);
840 SET_L_REG (code
->dst
.reg
, result
);
842 /* return ((n==1) << 1) | (nz==1); */
846 #define ONOT(name, how) \
851 rd = GET_B_REG (code->src.reg); \
859 rd = GET_W_REG (code->src.reg); \
866 int hm = 0x80000000; \
867 rd = GET_L_REG (code->src.reg); \
872 #define OSHIFTS(name, how1, how2) \
877 rd = GET_B_REG (code->src.reg); \
878 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
892 rd = GET_W_REG (code->src.reg); \
893 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
906 int hm = 0x80000000; \
907 rd = GET_L_REG (code->src.reg); \
908 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
919 #define OBITOP(name,f, s, op) \
924 if (f) ea = fetch (&code->dst); \
925 m=1<< fetch(&code->src); \
927 if(s) store (&code->dst,ea); goto next; \
934 cpu
.state
= SIM_STATE_STOPPED
;
935 cpu
.exception
= SIGINT
;
940 sim_resume (sd
, step
, siggnal
)
946 int tick_start
= get_now ();
959 prev
= signal (SIGINT
, control_c
);
963 cpu
.state
= SIM_STATE_STOPPED
;
964 cpu
.exception
= SIGTRAP
;
968 cpu
.state
= SIM_STATE_RUNNING
;
974 /* The PC should never be odd. */
988 cidx
= cpu
.cache_idx
[pc
];
989 code
= cpu
.cache
+ cidx
;
992 #define ALUOP(STORE, NAME, HOW) \
993 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
994 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
995 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
998 #define LOGOP(NAME, HOW) \
999 case O(NAME,SB): HOW; goto log8;\
1000 case O(NAME, SW): HOW; goto log16;\
1001 case O(NAME,SL): HOW; goto log32;
1008 printf ("%x %d %s\n", pc
, code
->opcode
,
1009 code
->op
? code
->op
->name
: "**");
1011 cpu
.stats
[code
->opcode
]++;
1015 cycles
+= code
->cycles
;
1017 switch (code
->opcode
)
1021 * This opcode is a fake for when we get to an
1022 * instruction which hasnt been compiled
1029 case O (O_SUBX
, SB
):
1030 rd
= fetch (&code
->dst
);
1031 ea
= fetch (&code
->src
);
1036 case O (O_ADDX
, SB
):
1037 rd
= fetch (&code
->dst
);
1038 ea
= fetch (&code
->src
);
1043 #define EA ea = fetch(&code->src);
1044 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1046 ALUOP (1, O_SUB
, RD_EA
;
1049 ALUOP (1, O_NEG
, EA
;
1055 rd
= GET_B_REG (code
->dst
.reg
);
1056 ea
= fetch (&code
->src
);
1060 rd
= GET_W_REG (code
->dst
.reg
);
1061 ea
= fetch (&code
->src
);
1065 rd
= GET_L_REG (code
->dst
.reg
);
1066 ea
= fetch (&code
->src
);
1071 LOGOP (O_AND
, RD_EA
;
1077 LOGOP (O_XOR
, RD_EA
;
1081 case O (O_MOV_TO_MEM
, SB
):
1082 res
= GET_B_REG (code
->src
.reg
);
1084 case O (O_MOV_TO_MEM
, SW
):
1085 res
= GET_W_REG (code
->src
.reg
);
1087 case O (O_MOV_TO_MEM
, SL
):
1088 res
= GET_L_REG (code
->src
.reg
);
1092 case O (O_MOV_TO_REG
, SB
):
1093 res
= fetch (&code
->src
);
1094 SET_B_REG (code
->dst
.reg
, res
);
1095 goto just_flags_log8
;
1096 case O (O_MOV_TO_REG
, SW
):
1097 res
= fetch (&code
->src
);
1098 SET_W_REG (code
->dst
.reg
, res
);
1099 goto just_flags_log16
;
1100 case O (O_MOV_TO_REG
, SL
):
1101 res
= fetch (&code
->src
);
1102 SET_L_REG (code
->dst
.reg
, res
);
1103 goto just_flags_log32
;
1106 case O (O_ADDS
, SL
):
1107 SET_L_REG (code
->dst
.reg
,
1108 GET_L_REG (code
->dst
.reg
)
1109 + code
->src
.literal
);
1113 case O (O_SUBS
, SL
):
1114 SET_L_REG (code
->dst
.reg
,
1115 GET_L_REG (code
->dst
.reg
)
1116 - code
->src
.literal
);
1120 rd
= fetch (&code
->dst
);
1121 ea
= fetch (&code
->src
);
1124 goto just_flags_alu8
;
1127 rd
= fetch (&code
->dst
);
1128 ea
= fetch (&code
->src
);
1131 goto just_flags_alu16
;
1134 rd
= fetch (&code
->dst
);
1135 ea
= fetch (&code
->src
);
1138 goto just_flags_alu32
;
1142 rd
= GET_B_REG (code
->src
.reg
);
1145 SET_B_REG (code
->src
.reg
, res
);
1146 goto just_flags_inc8
;
1149 rd
= GET_W_REG (code
->dst
.reg
);
1150 ea
= -code
->src
.literal
;
1152 SET_W_REG (code
->dst
.reg
, res
);
1153 goto just_flags_inc16
;
1156 rd
= GET_L_REG (code
->dst
.reg
);
1157 ea
= -code
->src
.literal
;
1159 SET_L_REG (code
->dst
.reg
, res
);
1160 goto just_flags_inc32
;
1164 rd
= GET_B_REG (code
->src
.reg
);
1167 SET_B_REG (code
->src
.reg
, res
);
1168 goto just_flags_inc8
;
1171 rd
= GET_W_REG (code
->dst
.reg
);
1172 ea
= code
->src
.literal
;
1174 SET_W_REG (code
->dst
.reg
, res
);
1175 goto just_flags_inc16
;
1178 rd
= GET_L_REG (code
->dst
.reg
);
1179 ea
= code
->src
.literal
;
1181 SET_L_REG (code
->dst
.reg
, res
);
1182 goto just_flags_inc32
;
1185 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1187 case O (O_ANDC
, SB
):
1189 ea
= code
->src
.literal
;
1195 ea
= code
->src
.literal
;
1199 case O (O_XORC
, SB
):
1201 ea
= code
->src
.literal
;
1242 if (((Z
|| (N
^ V
)) == 0))
1248 if (((Z
|| (N
^ V
)) == 1))
1282 case O (O_SYSCALL
, SB
):
1284 char c
= cpu
.regs
[2];
1285 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1289 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1291 c
= rd
& hm
; v
= 0; rd
<<= 1,
1292 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1294 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1295 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1297 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1298 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1300 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1301 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1 );
1303 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1304 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1306 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1307 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1309 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1310 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1312 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1313 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1317 pc
= fetch (&code
->src
);
1325 pc
= fetch (&code
->src
);
1332 SET_MEMORY_L (tmp
, code
->next_pc
);
1337 SET_MEMORY_W (tmp
, code
->next_pc
);
1344 pc
= code
->src
.literal
;
1355 pc
= GET_MEMORY_L (tmp
);
1360 pc
= GET_MEMORY_W (tmp
);
1369 cpu
.state
= SIM_STATE_STOPPED
;
1370 cpu
.exception
= SIGILL
;
1372 case O (O_SLEEP
, SN
):
1373 /* The format of r0 is defined by devo/include/wait.h. */
1374 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1375 if (WIFEXITED (cpu
.regs
[0]))
1377 cpu
.state
= SIM_STATE_EXITED
;
1378 cpu
.exception
= WEXITSTATUS (cpu
.regs
[0]);
1380 else if (WIFSTOPPED (cpu
.regs
[0]))
1382 cpu
.state
= SIM_STATE_STOPPED
;
1383 cpu
.exception
= WSTOPSIG (cpu
.regs
[0]);
1387 cpu
.state
= SIM_STATE_SIGNALLED
;
1388 cpu
.exception
= WTERMSIG (cpu
.regs
[0]);
1391 /* FIXME: Doesn't this break for breakpoints when r0
1392 contains just the right (er, wrong) value? */
1393 cpu
.state
= SIM_STATE_STOPPED
;
1394 if (! WIFEXITED (cpu
.regs
[0]) && WIFSIGNALED (cpu
.regs
[0]))
1395 cpu
.exception
= SIGILL
;
1397 cpu
.exception
= SIGTRAP
;
1401 cpu
.state
= SIM_STATE_STOPPED
;
1402 cpu
.exception
= SIGTRAP
;
1405 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1406 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1407 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1408 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1409 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1410 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1411 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1413 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1415 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1416 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1417 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1418 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1419 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1420 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1423 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1425 case O (O_MULS
, SB
):
1428 case O (O_MULS
, SW
):
1431 case O (O_MULU
, SB
):
1434 case O (O_MULU
, SW
):
1439 case O (O_DIVU
, SB
):
1441 rd
= GET_W_REG (code
->dst
.reg
);
1442 ea
= GET_B_REG (code
->src
.reg
);
1445 tmp
= (unsigned)rd
% ea
;
1446 rd
= (unsigned)rd
/ ea
;
1448 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1454 case O (O_DIVU
, SW
):
1456 rd
= GET_L_REG (code
->dst
.reg
);
1457 ea
= GET_W_REG (code
->src
.reg
);
1462 tmp
= (unsigned)rd
% ea
;
1463 rd
= (unsigned)rd
/ ea
;
1465 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1469 case O (O_DIVS
, SB
):
1472 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1473 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1476 tmp
= (int) rd
% (int) ea
;
1477 rd
= (int) rd
/ (int) ea
;
1483 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1486 case O (O_DIVS
, SW
):
1488 rd
= GET_L_REG (code
->dst
.reg
);
1489 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1492 tmp
= (int) rd
% (int) ea
;
1493 rd
= (int) rd
/ (int) ea
;
1494 n
= rd
& 0x80000000;
1499 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1502 case O (O_EXTS
, SW
):
1503 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1504 ea
= rd
& 0x80 ? -256 : 0;
1507 case O (O_EXTS
, SL
):
1508 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1509 ea
= rd
& 0x8000 ? -65536 : 0;
1512 case O (O_EXTU
, SW
):
1513 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1517 case O (O_EXTU
, SL
):
1518 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1528 int nregs
, firstreg
, i
;
1530 nregs
= GET_MEMORY_B (pc
+ 1);
1533 firstreg
= GET_MEMORY_B (pc
+ 3);
1535 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1538 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1545 int nregs
, firstreg
, i
;
1547 nregs
= GET_MEMORY_B (pc
+ 1);
1550 firstreg
= GET_MEMORY_B (pc
+ 3);
1552 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1554 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1561 cpu
.state
= SIM_STATE_STOPPED
;
1562 cpu
.exception
= SIGILL
;
1574 /* When a branch works */
1575 pc
= code
->src
.literal
;
1578 /* Set the cond codes from res */
1581 /* Set the flags after an 8 bit inc/dec operation */
1585 v
= (rd
& 0x7f) == 0x7f;
1589 /* Set the flags after an 16 bit inc/dec operation */
1593 v
= (rd
& 0x7fff) == 0x7fff;
1597 /* Set the flags after an 32 bit inc/dec operation */
1599 n
= res
& 0x80000000;
1600 nz
= res
& 0xffffffff;
1601 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1606 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1609 SET_B_REG (code
->src
.reg
, rd
);
1613 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1616 SET_W_REG (code
->src
.reg
, rd
);
1620 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1621 n
= (rd
& 0x80000000);
1622 nz
= rd
& 0xffffffff;
1623 SET_L_REG (code
->src
.reg
, rd
);
1627 store (&code
->dst
, res
);
1629 /* flags after a 32bit logical operation */
1630 n
= res
& 0x80000000;
1631 nz
= res
& 0xffffffff;
1636 store (&code
->dst
, res
);
1638 /* flags after a 16bit logical operation */
1646 store (&code
->dst
, res
);
1654 SET_B_REG (code
->dst
.reg
, res
);
1659 switch (code
->opcode
/ 4)
1662 v
= ((rd
& 0x80) == (ea
& 0x80)
1663 && (rd
& 0x80) != (res
& 0x80));
1667 v
= ((rd
& 0x80) != (-ea
& 0x80)
1668 && (rd
& 0x80) != (res
& 0x80));
1677 SET_W_REG (code
->dst
.reg
, res
);
1681 c
= (res
& 0x10000);
1682 switch (code
->opcode
/ 4)
1685 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1686 && (rd
& 0x8000) != (res
& 0x8000));
1690 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1691 && (rd
& 0x8000) != (res
& 0x8000));
1700 SET_L_REG (code
->dst
.reg
, res
);
1702 n
= res
& 0x80000000;
1703 nz
= res
& 0xffffffff;
1704 switch (code
->opcode
/ 4)
1707 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1708 && (rd
& 0x80000000) != (res
& 0x80000000));
1709 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1713 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1714 && (rd
& 0x80000000) != (res
& 0x80000000));
1715 c
= (unsigned) rd
< (unsigned) -ea
;
1718 v
= (rd
== 0x80000000);
1729 /* if (cpu.regs[8] ) abort(); */
1731 if (--poll_count
< 0)
1733 poll_count
= POLL_QUIT_INTERVAL
;
1734 if ((*sim_callback
->poll_quit
) != NULL
1735 && (*sim_callback
->poll_quit
) (sim_callback
))
1740 while (cpu
.state
== SIM_STATE_RUNNING
);
1741 cpu
.ticks
+= get_now () - tick_start
;
1742 cpu
.cycles
+= cycles
;
1748 signal (SIGINT
, prev
);
1755 /* FIXME: unfinished */
1760 sim_write (sd
, addr
, buffer
, size
)
1763 unsigned char *buffer
;
1771 for (i
= 0; i
< size
; i
++)
1773 if (addr
< memory_size
)
1775 cpu
.memory
[addr
+ i
] = buffer
[i
];
1776 cpu
.cache_idx
[addr
+ i
] = 0;
1779 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1785 sim_read (sd
, addr
, buffer
, size
)
1788 unsigned char *buffer
;
1794 if (addr
< memory_size
)
1795 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1797 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1811 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1812 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1815 #define CCR_REGNUM 8 /* Contains processor status */
1816 #define PC_REGNUM 9 /* Contains program counter */
1818 #define CYCLE_REGNUM 10
1819 #define INST_REGNUM 11
1820 #define TICK_REGNUM 12
1824 sim_store_register (sd
, rn
, value
, length
)
1827 unsigned char *value
;
1833 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1834 shortval
= (value
[0] << 8) | (value
[1]);
1835 intval
= h8300hmode
? longval
: shortval
;
1853 cpu
.regs
[rn
] = intval
;
1859 cpu
.cycles
= longval
;
1863 cpu
.insts
= longval
;
1867 cpu
.ticks
= longval
;
1874 sim_fetch_register (sd
, rn
, buf
, length
)
1918 if (h8300hmode
|| longreg
)
1934 sim_stop_reason (sd
, reason
, sigrc
)
1936 enum sim_stop
*reason
;
1939 #if 0 /* FIXME: This should work but we can't use it.
1940 grep for SLEEP above. */
1943 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
1944 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
1945 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
1949 *reason
= sim_stopped
;
1951 *sigrc
= cpu
.exception
;
1954 /* FIXME: Rename to sim_set_mem_size. */
1960 /* Memory size is fixed. */
1964 sim_set_simcache_size (n
)
1970 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1971 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1977 sim_info (sd
, verbose
)
1981 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1982 double virttime
= cpu
.cycles
/ 10.0e6
;
1984 (*sim_callback
->printf_filtered
) (sim_callback
,
1985 "\n\n#instructions executed %10d\n",
1987 (*sim_callback
->printf_filtered
) (sim_callback
,
1988 "#cycles (v approximate) %10d\n",
1990 (*sim_callback
->printf_filtered
) (sim_callback
,
1991 "#real time taken %10.4f\n",
1993 (*sim_callback
->printf_filtered
) (sim_callback
,
1994 "#virtual time taked %10.4f\n",
1996 if (timetaken
!= 0.0)
1997 (*sim_callback
->printf_filtered
) (sim_callback
,
1998 "#simulation ratio %10.4f\n",
1999 virttime
/ timetaken
);
2000 (*sim_callback
->printf_filtered
) (sim_callback
,
2003 (*sim_callback
->printf_filtered
) (sim_callback
,
2004 "#cache size %10d\n",
2008 /* This to be conditional on `what' (aka `verbose'),
2009 however it was never passed as non-zero. */
2013 for (i
= 0; i
< O_LAST
; i
++)
2016 (*sim_callback
->printf_filtered
) (sim_callback
,
2017 "%d: %d\n", i
, cpu
.stats
[i
]);
2023 /* Indicate whether the cpu is an h8/300 or h8/300h.
2024 FLAG is non-zero for the h8/300h. */
2030 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2031 This function being replaced by a sim_open:ARGV configuration
2037 sim_open (kind
, ptr
, abfd
, argv
)
2039 struct host_callback_struct
*ptr
;
2043 /* FIXME: Much of the code in sim_load can be moved here */
2048 /* fudge our descriptor */
2049 return (SIM_DESC
) 1;
2053 sim_close (sd
, quitting
)
2060 /* Called by gdb to load a program into memory. */
2063 sim_load (sd
, prog
, abfd
, from_tty
)
2071 /* FIXME: The code below that sets a specific variant of the h8/300
2072 being simulated should be moved to sim_open(). */
2074 /* See if the file is for the h8/300 or h8/300h. */
2075 /* ??? This may not be the most efficient way. The z8k simulator
2076 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2080 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2081 if (prog_bfd
!= NULL
)
2083 /* Set the cpu type. We ignore failure from bfd_check_format
2084 and bfd_openr as sim_load_file checks too. */
2085 if (bfd_check_format (prog_bfd
, bfd_object
))
2087 unsigned long mach
= bfd_get_mach (prog_bfd
);
2088 set_h8300h (mach
== bfd_mach_h8300h
2089 || mach
== bfd_mach_h8300s
);
2093 /* If we're using gdb attached to the simulator, then we have to
2094 reallocate memory for the simulator.
2096 When gdb first starts, it calls fetch_registers (among other
2097 functions), which in turn calls init_pointers, which allocates
2100 The problem is when we do that, we don't know whether we're
2101 debugging an h8/300 or h8/300h program.
2103 This is the first point at which we can make that determination,
2104 so we just reallocate memory now; this will also allow us to handle
2105 switching between h8/300 and h8/300h programs without exiting
2108 memory_size
= H8300H_MSIZE
;
2110 memory_size
= H8300_MSIZE
;
2115 free (cpu
.cache_idx
);
2117 free (cpu
.eightbit
);
2119 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2120 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2121 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2123 /* `msize' must be a power of two */
2124 if ((memory_size
& (memory_size
- 1)) != 0)
2126 cpu
.mask
= memory_size
- 1;
2128 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2129 sim_kind
== SIM_OPEN_DEBUG
,
2133 /* Close the bfd if we opened it. */
2134 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2135 bfd_close (prog_bfd
);
2139 /* Close the bfd if we opened it. */
2140 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2141 bfd_close (prog_bfd
);
2146 sim_create_inferior (sd
, abfd
, argv
, env
)
2153 cpu
.pc
= bfd_get_start_address (abfd
);
2160 sim_do_command (sd
, cmd
)
2164 (*sim_callback
->printf_filtered
) (sim_callback
,
2165 "This simulator does not accept any commands.\n");
2169 sim_set_callbacks (ptr
)
2170 struct host_callback_struct
*ptr
;
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