sim/h8300/compile.c

   1 /*
   2  * Simulator for the Hitachi H8/300 architecture.
   3  *
   4  * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   5  *
   6  * This file is part of H8/300 sim
   7  *
   8  *
   9  * THIS SOFTWARE IS NOT COPYRIGHTED
  10  *
  11  * Cygnus offers the following for use in the public domain.  Cygnus makes no
  12  * warranty with regard to the software or its performance and the user
  13  * accepts the software "AS IS" with all faults.
  14  *
  15  * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
  16  * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
  17  * AND FITNESS FOR A PARTICULAR PURPOSE.
  18  */
  19
  20 #include <signal.h>
  21 #include <sys/times.h>
  22 #include <sys/param.h>
  23 #include "ansidecl.h"
  24 #include "sysdep.h"
  25 #include "remote-sim.h"
  26
  27 int debug;
  28
  29
  30 #define X(op, size)  op*4+size
  31
  32 #define SP (h8300hmode ? SL:SW)
  33 #define SB 0
  34 #define SW 1
  35 #define SL 2
  36 #define OP_REG 1
  37 #define OP_DEC 2
  38 #define OP_DISP 3
  39 #define OP_INC 4
  40 #define OP_PCREL 5
  41 #define OP_MEM 6
  42 #define OP_CCR 7
  43 #define OP_IMM 8
  44 #define OP_ABS 10
  45 #define h8_opcodes ops
  46 #define DEFINE_TABLE
  47 #include "opcode/h8300.h"
  48
  49 #include "inst.h"
  50
  51 #define LOW_BYTE(x) ((x) & 0xff)
  52 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
  53 #define P(X,Y) ((X<<8) | Y)
  54
  55 #define BUILDSR()   cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
  56
  57 #define GETSR()             \
  58   c = (cpu.ccr >> 0) & 1;\
  59   v = (cpu.ccr >> 1) & 1;\
  60   nz = !((cpu.ccr >> 2) & 1);\
  61   n = (cpu.ccr >> 3) & 1;
  62
  63 #ifdef __CHAR_IS_SIGNED__
  64 #define SEXTCHAR(x) ((char)(x))
  65 #endif
  66
  67 #ifndef SEXTCHAR
  68 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
  69 #endif
  70
  71 #define UEXTCHAR(x) ((x) & 0xff)
  72 #define UEXTSHORT(x) ((x) & 0xffff)
  73 #define SEXTSHORT(x) ((short)(x))
  74
  75 static cpu_state_type cpu;
  76
  77 int h8300hmode = 0;
  78
  79
  80 static int
  81 get_now ()
  82 {
  83   struct tms b;
  84
  85   return time (0);
  86 #if 0
  87   times (&b);
  88   return b.tms_utime + b.tms_stime;
  89 #endif
  90 }
  91
  92 static int
  93 now_persec ()
  94 {
  95   return 1;
  96 }
  97
  98
  99 static int
 100 bitfrom (x)
 101 {
 102   switch (x & SIZE)
 103     {
 104     case L_8:
 105       return SB;
 106     case L_16:
 107       return SW;
 108     case L_32:
 109       return SL;
 110     case L_P:
 111       return h8300hmode ? SL : SW;
 112     }
 113 }
 114
 115 static
 116 unsigned int
 117 lvalue (x, rn)
 118 {
 119   switch (x / 4)
 120     {
 121     case OP_DISP:
 122       if (rn == 8)
 123         {
 124           return X (OP_IMM, SP);
 125         }
 126       return X (OP_REG, SP);
 127
 128     case OP_MEM:
 129
 130       return X (OP_MEM, SP);
 131     default:
 132       abort ();
 133     }
 134 }
 135
 136 static unsigned int
 137 decode (addr, data, dst)
 138      int addr;
 139      unsigned char *data;
 140      decoded_inst *dst;
 141
 142 {
 143   int rs = 0;
 144   int rd = 0;
 145   int rdisp = 0;
 146   int abs = 0;
 147   int plen = 0;
 148
 149   struct h8_opcode *q = h8_opcodes;
 150   int size = 0;
 151   dst->dst.type = -1;
 152   dst->src.type = -1;
 153   /* Find the exact opcode/arg combo */
 154   while (q->name)
 155     {
 156       op_type *nib;
 157       unsigned int len = 0;
 158
 159       nib = q->data.nib;
 160
 161       while (1)
 162         {
 163           op_type looking_for = *nib;
 164           int thisnib = data[len >> 1];
 165
 166           thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
 167
 168           if (looking_for < 16 && looking_for >= 0)
 169             {
 170               if (looking_for != thisnib)
 171                 goto fail;
 172             }
 173           else
 174             {
 175               if ((int) looking_for & (int) B31)
 176                 {
 177                   if (!(((int) thisnib & 0x8) != 0))
 178                     goto fail;
 179                   looking_for = (op_type) ((int) looking_for & ~(int)
 180                                            B31);
 181                   thisnib &= 0x7;
 182                 }
 183               if ((int) looking_for & (int) B30)
 184                 {
 185                   if (!(((int) thisnib & 0x8) == 0))
 186                     goto fail;
 187                   looking_for = (op_type) ((int) looking_for & ~(int) B30);
 188                 }
 189               if (looking_for & DBIT)
 190                 {
 191                   if ((looking_for & 5) != (thisnib & 5))
 192                     goto fail;
 193                   abs = (thisnib & 0x8) ? 2 : 1;
 194                 }
 195               else if (looking_for & (REG | IND | INC | DEC))
 196                 {
 197                   if (looking_for & REG)
 198                     {
 199                       /*
 200                        * Can work out size from the
 201                        * register
 202                        */
 203                       size = bitfrom (looking_for);
 204                     }
 205                   if (looking_for & SRC)
 206                     {
 207                       rs = thisnib;
 208                     }
 209                   else
 210                     {
 211                       rd = thisnib;
 212                     }
 213                 }
 214               else if (looking_for & L_16)
 215                 {
 216                   abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
 217                   plen = 16;
 218                   if (looking_for & (PCREL | DISP))
 219                     {
 220                       abs = (short) (abs);
 221                     }
 222                 }
 223               else if (looking_for & ABSJMP)
 224                 {
 225                   abs =
 226                     (data[1] << 16)
 227                     | (data[2] << 8)
 228                     | (data[3]);
 229                 }
 230               else if (looking_for & MEMIND)
 231                 {
 232                   abs = data[1];
 233                 }
 234               else if (looking_for & L_32)
 235                 {
 236                   int i = len >> 1;
 237                   abs = (data[i] << 24)
 238                     | (data[i + 1] << 16)
 239                     | (data[i + 2] << 8)
 240                     | (data[i + 3]);
 241
 242                   plen = 32;
 243                 }
 244               else if (looking_for & L_24)
 245                 {
 246                   int i = len >> 1;
 247                   abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
 248                   plen = 24;
 249                 }
 250               else if (looking_for & IGNORE)
 251                 {
 252                   /* nothing to do */
 253                 }
 254               else if (looking_for & DISPREG)
 255                 {
 256                   rdisp = thisnib & 0x7;
 257                 }
 258               else if (looking_for & KBIT)
 259                 {
 260                   switch (thisnib)
 261                     {
 262                     case 9:
 263                       abs = 4;
 264                       break;
 265                     case 8:
 266                       abs = 2;
 267                       break;
 268                     case 0:
 269                       abs = 1;
 270                       break;
 271                     }
 272                 }
 273               else if (looking_for & L_8)
 274                 {
 275                   plen = 8;
 276
 277                   if (looking_for & PCREL)
 278                     {
 279                       abs = SEXTCHAR (data[len >> 1]);
 280                     }
 281                   else
 282                     {
 283                       abs = data[len >> 1] & 0xff;
 284                     }
 285                 }
 286               else if (looking_for & L_3)
 287                 {
 288                   plen = 3;
 289
 290                   abs = thisnib;
 291                 }
 292               else if (looking_for == E)
 293                 {
 294                   dst->op = q;
 295
 296                   /* Fill in the args */
 297                   {
 298                     op_type *args = q->args.nib;
 299                     int hadone = 0;
 300
 301                     while (*args != E)
 302                       {
 303                         int x = *args;
 304                         int rn = (x & DST) ? rd : rs;
 305                         ea_type *p;
 306
 307                         if (x & DST)
 308                           {
 309                             p = &(dst->dst);
 310                           }
 311                         else
 312                           {
 313                             p = &(dst->src);
 314                           }
 315
 316                         if (x & (IMM | KBIT | DBIT))
 317                           {
 318                             p->type = X (OP_IMM, size);
 319                             p->literal = abs;
 320                           }
 321                         else if (x & REG)
 322                           {
 323                             /* Reset the size, some
 324                                ops (like mul) have two sizes */
 325
 326                             size = bitfrom (x);
 327                             p->type = X (OP_REG, size);
 328                             p->reg = rn;
 329                           }
 330                         else if (x & INC)
 331                           {
 332                             p->type = X (OP_INC, size);
 333                             p->reg = rn & 0x7;
 334                           }
 335                         else if (x & DEC)
 336                           {
 337                             p->type = X (OP_DEC, size);
 338                             p->reg = rn & 0x7;
 339                           }
 340                         else if (x & IND)
 341                           {
 342                             p->type = X (OP_DISP, size);
 343                             p->reg = rn & 0x7;
 344                             p->literal = 0;
 345                           }
 346                         else if (x & (ABS | ABSJMP | ABSMOV))
 347                           {
 348                             p->type = X (OP_DISP, size);
 349                             p->literal = abs;
 350                             p->reg = 8;
 351                           }
 352                         else if (x & MEMIND)
 353                           {
 354                             p->type = X (OP_MEM, size);
 355                             p->literal = abs;
 356                           }
 357                         else if (x & PCREL)
 358                           {
 359                             p->type = X (OP_PCREL, size);
 360                             p->literal = abs + addr + 2;
 361                             if (x & L_16)
 362                               p->literal += 2;
 363                           }
 364                         else if (x & ABSJMP)
 365                           {
 366                             p->type = X (OP_IMM, SP);
 367                             p->literal = abs;
 368                           }
 369                         else if (x & DISP)
 370                           {
 371                             p->type = X (OP_DISP, size);
 372                             p->literal = abs;
 373                             p->reg = rdisp & 0x7;
 374                           }
 375                         else if (x & CCR)
 376                           {
 377                             p->type = OP_CCR;
 378                           }
 379                         else
 380                           printf ("Hmmmm %x", x);
 381
 382                         args++;
 383                       }
 384                   }
 385
 386                   /*
 387                      * But a jmp or a jsr gets
 388                      * automagically lvalued, since we
 389                      * branch to their address not their
 390                      * contents
 391                    */
 392                   if (q->how == O (O_JSR, SB)
 393                       || q->how == O (O_JMP, SB))
 394                     {
 395                       dst->src.type = lvalue (dst->src.type, dst->src.reg);
 396                     }
 397
 398                   if (dst->dst.type == -1)
 399                     dst->dst = dst->src;
 400
 401                   dst->opcode = q->how;
 402                   dst->cycles = q->time;
 403
 404                   /* And a jsr to 0xc4 is turned into a magic trap */
 405
 406                   if (dst->opcode == O (O_JSR, SB))
 407                     {
 408                       if (dst->src.literal == 0xc4)
 409                         {
 410                           dst->opcode = O (O_SYSCALL, SB);
 411                         }
 412                     }
 413
 414                   dst->next_pc = addr + len / 2;
 415                   return;
 416                 }
 417               else
 418                 {
 419                   printf ("Dont understand %x \n", looking_for);
 420                 }
 421             }
 422
 423           len++;
 424           nib++;
 425         }
 426
 427     fail:
 428       q++;
 429     }
 430
 431   dst->opcode = O (O_ILL, SB);
 432 }
 433
 434
 435 static void
 436 compile (pc)
 437 {
 438   int idx;
 439
 440   /* find the next cache entry to use */
 441
 442   idx = cpu.cache_top + 1;
 443   cpu.compiles++;
 444   if (idx >= cpu.csize)
 445     {
 446       idx = 1;
 447     }
 448   cpu.cache_top = idx;
 449
 450   /* Throw away its old meaning */
 451   cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
 452
 453   /* set to new address */
 454   cpu.cache[idx].oldpc = pc;
 455
 456   /* fill in instruction info */
 457   decode (pc, cpu.memory + pc, cpu.cache + idx);
 458
 459   /* point to new cache entry */
 460   cpu.cache_idx[pc] = idx;
 461 }
 462
 463
 464 static unsigned char *breg[18];
 465 static unsigned short *wreg[18];
 466 static unsigned int *lreg[18];
 467
 468 #define GET_B_REG(x) *(breg[x])
 469 #define SET_B_REG(x,y) (*(breg[x])) = (y)
 470 #define GET_W_REG(x) *(wreg[x])
 471 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
 472
 473 #define GET_L_REG(x) *(lreg[x])
 474 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
 475
 476 #define GET_MEMORY_L(x) \
 477   ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
 478
 479 #define GET_MEMORY_W(x) \
 480   ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
 481
 482
 483 #define SET_MEMORY_B(x,y) \
 484   (cpu.memory[(x)] = y)
 485
 486 #define SET_MEMORY_W(x,y) \
 487 {register unsigned char *_p = cpu.memory+x;\
 488    register int __y = y;\
 489      _p[0] = (__y)>>8;\
 490        _p[1] =(__y);     }
 491
 492 #define SET_MEMORY_L(x,y)  \
 493 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
 494    _p[0] = (__y)>>24;    _p[1] = (__y)>>16;      _p[2] = (__y)>>8;       _p[3] = (__y)>>0;}
 495
 496 #define GET_MEMORY_B(x)  (cpu.memory[x])
 497
 498 int
 499 fetch (arg, n)
 500      ea_type *arg;
 501 {
 502   int rn = arg->reg;
 503   int abs = arg->literal;
 504   int r;
 505   int t;
 506
 507   switch (arg->type)
 508     {
 509     case X (OP_REG, SB):
 510       return GET_B_REG (rn);
 511     case X (OP_REG, SW):
 512       return GET_W_REG (rn);
 513     case X (OP_REG, SL):
 514       return GET_L_REG (rn);
 515     case X (OP_IMM, SB):
 516     case X (OP_IMM, SW):
 517     case X (OP_IMM, SL):
 518       return abs;
 519     case X (OP_DEC, SB):
 520       abort ();
 521
 522     case X (OP_INC, SB):
 523       t = GET_L_REG (rn);
 524       t &= cpu.mask;
 525       r = GET_MEMORY_B (t);
 526       t++;
 527       t = t & cpu.mask;
 528       SET_L_REG (rn, t);
 529       return r;
 530       break;
 531     case X (OP_INC, SW):
 532       t = GET_L_REG (rn);
 533       t &= cpu.mask;
 534       r = GET_MEMORY_W (t);
 535       t += 2;
 536       t = t & cpu.mask;
 537       SET_L_REG (rn, t);
 538       return r;
 539     case X (OP_INC, SL):
 540       t = GET_L_REG (rn);
 541       t &= cpu.mask;
 542       r = GET_MEMORY_L (t);
 543
 544       t += 4;
 545       t = t & cpu.mask;
 546       SET_L_REG (rn, t);
 547       return r;
 548
 549     case X (OP_DISP, SB):
 550       t = GET_L_REG (rn) + abs;
 551       t &= cpu.mask;
 552       return GET_MEMORY_B (t);
 553
 554     case X (OP_DISP, SW):
 555       t = GET_L_REG (rn) + abs;
 556       t &= cpu.mask;
 557       return GET_MEMORY_W (t);
 558
 559     case X (OP_DISP, SL):
 560       t = GET_L_REG (rn) + abs;
 561       t &= cpu.mask;
 562       return GET_MEMORY_L (t);
 563
 564     case X (OP_MEM, SL):
 565       t = GET_MEMORY_L (abs);
 566       t &= cpu.mask;
 567       return t;
 568
 569     default:
 570       abort ();
 571
 572     }
 573 }
 574
 575
 576 static
 577 void
 578 store (arg, n)
 579      ea_type *arg;
 580      int n;
 581 {
 582   int rn = arg->reg;
 583   int abs = arg->literal;
 584   int t;
 585
 586   switch (arg->type)
 587     {
 588     case X (OP_REG, SB):
 589       SET_B_REG (rn, n);
 590       break;
 591     case X (OP_REG, SW):
 592       SET_W_REG (rn, n);
 593       break;
 594     case X (OP_REG, SL):
 595       SET_L_REG (rn, n);
 596       break;
 597
 598     case X (OP_DEC, SB):
 599       t = GET_L_REG (rn) - 1;
 600       t &= cpu.mask;
 601       SET_L_REG (rn, t);
 602       SET_MEMORY_B (t, n);
 603
 604       break;
 605     case X (OP_DEC, SW):
 606       t = (GET_L_REG (rn) - 2) & cpu.mask;
 607       SET_L_REG (rn, t);
 608       SET_MEMORY_W (t, n);
 609       break;
 610
 611     case X (OP_DEC, SL):
 612       t = (GET_L_REG (rn) - 4) & cpu.mask;
 613       SET_L_REG (rn, t);
 614       SET_MEMORY_L (t, n);
 615       break;
 616
 617     case X (OP_DISP, SB):
 618       t = GET_L_REG (rn) + abs;
 619       t &= cpu.mask;
 620       SET_MEMORY_B (t, n);
 621       break;
 622
 623     case X (OP_DISP, SW):
 624       t = GET_L_REG (rn) + abs;
 625       t &= cpu.mask;
 626       SET_MEMORY_W (t, n);
 627       break;
 628
 629     case X (OP_DISP, SL):
 630       t = GET_L_REG (rn) + abs;
 631       t &= cpu.mask;
 632       SET_MEMORY_L (t, n);
 633       break;
 634     default:
 635       abort ();
 636     }
 637 }
 638
 639
 640 static union
 641 {
 642   short int i;
 643   struct
 644     {
 645       char low;
 646       char high;
 647     }
 648   u;
 649 }
 650
 651 littleendian;
 652
 653 static
 654 void
 655 init_pointers ()
 656 {
 657   static int init;
 658
 659   if (!init)
 660     {
 661       int i;
 662
 663       init = 1;
 664       littleendian.i = 1;
 665
 666       cpu.memory = (unsigned char *) calloc (sizeof (char), MSIZE);
 667       cpu.cache_idx = (unsigned short *) calloc (sizeof (short), MSIZE);
 668       cpu.mask = (1 << MPOWER) - 1;
 669
 670       for (i = 0; i < 9; i++)
 671         {
 672           cpu.regs[i] = 0;
 673         }
 674
 675       for (i = 0; i < 8; i++)
 676         {
 677           unsigned char *p = (unsigned char *) (cpu.regs + i);
 678           unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
 679           unsigned short *q = (unsigned short *) (cpu.regs + i);
 680           unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
 681           cpu.regs[i] = 0x00112233;
 682           while (p < e)
 683             {
 684               if (*p == 0x22)
 685                 {
 686                   breg[i] = p;
 687                 }
 688               if (*p == 0x33)
 689                 {
 690                   breg[i + 8] = p;
 691                 }
 692               p++;
 693             }
 694           while (q < u)
 695             {
 696               if (*q == 0x2233)
 697                 {
 698                   wreg[i] = q;
 699                 }
 700               if (*q == 0x0011)
 701                 {
 702                   wreg[i + 8] = q;
 703                 }
 704               q++;
 705             }
 706           cpu.regs[i] = 0;
 707           lreg[i] = &cpu.regs[i];
 708         }
 709
 710       lreg[8] = &cpu.regs[8];
 711
 712       /* initialize the seg registers */
 713       if (!cpu.cache)
 714         sim_csize (CSIZE);
 715     }
 716 }
 717
 718 static void
 719 control_c (sig, code, scp, addr)
 720      int sig;
 721      int code;
 722      char *scp;
 723      char *addr;
 724 {
 725   cpu.exception = SIGINT;
 726 }
 727
 728 #define C (c != 0)
 729 #define Z (nz == 0)
 730 #define V (v != 0)
 731 #define N (n != 0)
 732
 733 static int
 734 mop (code, bsize, sign)
 735      decoded_inst *code;
 736      int bsize;
 737      int sign;
 738 {
 739   int multiplier;
 740   int multiplicand;
 741   int result;
 742   int n, nz;
 743
 744   if (sign)
 745     {
 746       multiplicand =
 747         bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
 748         SEXTSHORT (GET_W_REG (code->dst.reg));
 749       multiplier =
 750         bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
 751         SEXTSHORT (GET_W_REG (code->src.reg));
 752     }
 753   else
 754     {
 755       multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
 756         UEXTSHORT (GET_W_REG (code->dst.reg));
 757       multiplier =
 758         bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
 759         UEXTSHORT (GET_W_REG (code->src.reg));
 760
 761     }
 762   result = multiplier * multiplicand;
 763
 764   if (sign)
 765     {
 766       n = result & (bsize ? 0x8000 : 0x80000000);
 767       nz = result & (bsize ? 0xffff : 0xffffffff);
 768     }
 769   if (bsize)
 770     {
 771       SET_W_REG (code->dst.reg, result);
 772     }
 773   else
 774     {
 775       SET_L_REG (code->dst.reg, result);
 776     }
 777 /*  return ((n==1) << 1) | (nz==1); */
 778
 779 }
 780
 781 #define OSHIFTS(name, how) \
 782 case O(name, SB):                               \
 783 {                                               \
 784   int t;                                        \
 785   int hm = 0x80;                                \
 786   rd = GET_B_REG (code->src.reg);               \
 787   how;                                          \
 788   goto shift8;                                  \
 789 }                                               \
 790 case O(name, SW):                               \
 791 {                                               \
 792   int t;                                        \
 793   int hm = 0x8000;                              \
 794   rd = GET_W_REG (code->src.reg);               \
 795   how;                                          \
 796   goto shift16;                                 \
 797 }                                               \
 798 case O(name, SL):                               \
 799 {                                               \
 800   int t;                                        \
 801   int hm = 0x80000000;                          \
 802   rd = GET_L_REG (code->src.reg);               \
 803   how;                                          \
 804   goto shift32;                                 \
 805 }
 806
 807 #define OBITOP(name,f, s, op)                   \
 808 case  O(name, SB):                              \
 809 {                                               \
 810   int m;                                        \
 811   int b;                                        \
 812   if (f) ea = fetch (&code->dst);               \
 813   m=1<< fetch(&code->src);                      \
 814   op;                                           \
 815   if(s) store (&code->dst,ea); goto next;       \
 816 }
 817
 818 int
 819 sim_resume (step, siggnal)
 820 {
 821   static int init1;
 822   int cycles = 0;
 823   int insts = 0;
 824   int tick_start = get_now ();
 825   void (*prev) ();
 826   int poll_count = 0;
 827   int res;
 828   int tmp;
 829   int rd;
 830   int ea;
 831   int bit;
 832   int pc;
 833   int c, nz, v, n;
 834
 835   init_pointers ();
 836
 837   prev = signal (SIGINT, control_c);
 838
 839   if (step)
 840     {
 841       cpu.exception = SIGTRAP;
 842     }
 843   else
 844     {
 845       cpu.exception = 0;
 846     }
 847
 848   pc = cpu.pc;
 849
 850   GETSR ();
 851
 852   do
 853     {
 854       int cidx;
 855       decoded_inst *code;
 856
 857     top:
 858       cidx = cpu.cache_idx[pc];
 859       code = cpu.cache + cidx;
 860
 861
 862 #define ALUOP(STORE, NAME, HOW) \
 863     case O(NAME,SB):  HOW; if(STORE)goto alu8;else goto just_flags_alu8;  \
 864     case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
 865     case O(NAME,SL):  HOW; if(STORE)goto alu32;else goto just_flags_alu32;
 866
 867
 868 #define LOGOP(NAME, HOW) \
 869     case O(NAME,SB): HOW; goto log8;\
 870     case O(NAME, SW): HOW; goto log16;\
 871     case O(NAME,SL): HOW; goto log32;
 872
 873
 874
 875 #if ADEBUG
 876       if (debug)
 877         {
 878           printf ("%x %d %s\n", pc, code->opcode,
 879                   code->op ? code->op->name : "**");
 880         }
 881       cpu.stats[code->opcode]++;
 882
 883 #endif
 884
 885       cycles += code->cycles;
 886       insts++;
 887       switch (code->opcode)
 888         {
 889         case 0:
 890           /*
 891            * This opcode is a fake for when we get to an
 892            * instruction which hasnt been compiled
 893            */
 894           compile (pc);
 895           goto top;
 896           break;
 897
 898
 899         case O (O_SUBX, SB):
 900           rd = fetch (&code->dst);
 901           ea = fetch (&code->src);
 902           ea = -(ea + C);
 903           res = rd + ea;
 904           goto alu8;
 905
 906         case O (O_ADDX, SB):
 907           rd = fetch (&code->dst);
 908           ea = fetch (&code->src);
 909           ea = C + ea;
 910           res = rd + ea;
 911           goto alu8;
 912
 913 #define EA    ea = fetch(&code->src);
 914 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
 915
 916           ALUOP (1, O_SUB, RD_EA;
 917                  ea = -ea;
 918                  res = rd + ea);
 919           ALUOP (1, O_NEG, EA;
 920                  ea = -ea;
 921                  rd = 0;
 922                  res = rd + ea);
 923
 924         case O (O_ADD, SB):
 925           rd = GET_B_REG (code->dst.reg);
 926           ea = fetch (&code->src);
 927           res = rd + ea;
 928           goto alu8;
 929         case O (O_ADD, SW):
 930           rd = GET_W_REG (code->dst.reg);
 931           ea = fetch (&code->src);
 932           res = rd + ea;
 933           goto alu16;
 934         case O (O_ADD, SL):
 935           rd = GET_L_REG (code->dst.reg);
 936           ea = fetch (&code->src);
 937           res = rd + ea;
 938           goto alu32;
 939
 940
 941           LOGOP (O_AND, RD_EA;
 942                  res = rd & ea);
 943
 944           LOGOP (O_OR, RD_EA;
 945                  res = rd | ea);
 946
 947           LOGOP (O_XOR, RD_EA;
 948                  res = rd ^ ea);
 949
 950
 951         case O (O_MOV_TO_MEM, SB):
 952           res = GET_B_REG (code->src.reg);
 953           goto log8;
 954         case O (O_MOV_TO_MEM, SW):
 955           res = GET_W_REG (code->src.reg);
 956           goto log16;
 957         case O (O_MOV_TO_MEM, SL):
 958           res = GET_L_REG (code->src.reg);
 959           goto log32;
 960
 961
 962         case O (O_MOV_TO_REG, SB):
 963           res = fetch (&code->src);
 964           SET_B_REG (code->dst.reg, res);
 965           goto just_flags_log8;
 966         case O (O_MOV_TO_REG, SW):
 967           res = fetch (&code->src);
 968           SET_W_REG (code->dst.reg, res);
 969           goto just_flags_log16;
 970         case O (O_MOV_TO_REG, SL):
 971           res = fetch (&code->src);
 972           SET_L_REG (code->dst.reg, res);
 973           goto just_flags_log32;
 974
 975
 976         case O (O_ADDS, SL):
 977           SET_L_REG (code->dst.reg,
 978                      GET_L_REG (code->dst.reg)
 979                      + code->src.literal);
 980
 981           goto next;
 982
 983         case O (O_SUBS, SL):
 984           SET_L_REG (code->dst.reg,
 985                      GET_L_REG (code->dst.reg)
 986                      - code->src.literal);
 987           goto next;
 988
 989         case O (O_CMP, SB):
 990           rd = fetch (&code->dst);
 991           ea = fetch (&code->src);
 992           ea = -ea;
 993           res = rd + ea;
 994           goto just_flags_alu8;
 995
 996         case O (O_CMP, SW):
 997           rd = fetch (&code->dst);
 998           ea = fetch (&code->src);
 999           ea = -ea;
1000           res = rd + ea;
1001           goto just_flags_alu16;
1002
1003         case O (O_CMP, SL):
1004           rd = fetch (&code->dst);
1005           ea = fetch (&code->src);
1006           ea = -ea;
1007           res = rd + ea;
1008           goto just_flags_alu32;
1009
1010
1011         case O (O_DEC, SB):
1012           rd = GET_B_REG (code->src.reg);
1013           ea = -1;
1014           res = rd + ea;
1015           SET_B_REG (code->src.reg, res);
1016           goto just_flags_inc8;
1017
1018         case O (O_DEC, SW):
1019           rd = GET_W_REG (code->dst.reg);
1020           ea = -code->src.literal;
1021           res = rd + ea;
1022           SET_W_REG (code->dst.reg, res);
1023           goto just_flags_inc16;
1024
1025         case O (O_DEC, SL):
1026           rd = GET_L_REG (code->dst.reg);
1027           ea = -code->src.literal;
1028           res = rd + ea;
1029           SET_L_REG (code->dst.reg, res);
1030           goto just_flags_inc32;
1031
1032
1033         case O (O_INC, SB):
1034           rd = GET_B_REG (code->src.reg);
1035           ea = 1;
1036           res = rd + ea;
1037           SET_B_REG (code->src.reg, res);
1038           goto just_flags_inc8;
1039
1040         case O (O_INC, SW):
1041           rd = GET_W_REG (code->dst.reg);
1042           ea = code->src.literal;
1043           res = rd + ea;
1044           SET_W_REG (code->dst.reg, res);
1045           goto just_flags_inc16;
1046
1047         case O (O_INC, SL):
1048           rd = GET_L_REG (code->dst.reg);
1049           ea = code->src.literal;
1050           res = rd + ea;
1051           SET_L_REG (code->dst.reg, res);
1052           goto just_flags_inc32;
1053
1054
1055 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1056
1057         case O (O_ANDC, SB):
1058           GET_CCR (rd);
1059           ea = code->src.literal;
1060           res = rd & ea;
1061           goto setc;
1062
1063         case O (O_ORC, SB):
1064           GET_CCR (rd);
1065           ea = code->src.literal;
1066           res = rd | ea;
1067           goto setc;
1068
1069         case O (O_XORC, SB):
1070           GET_CCR (rd);
1071           ea = code->src.literal;
1072           res = rd ^ ea;
1073           goto setc;
1074
1075
1076         case O (O_BRA, SB):
1077           if (1)
1078             goto condtrue;
1079           goto next;
1080
1081         case O (O_BRN, SB):
1082           if (0)
1083             goto condtrue;
1084           goto next;
1085
1086         case O (O_BHI, SB):
1087           if ((C || Z) == 0)
1088             goto condtrue;
1089           goto next;
1090
1091
1092         case O (O_BLS, SB):
1093           if ((C || Z))
1094             goto condtrue;
1095           goto next;
1096
1097         case O (O_BCS, SB):
1098           if ((C == 1))
1099             goto condtrue;
1100           goto next;
1101
1102         case O (O_BCC, SB):
1103           if ((C == 0))
1104             goto condtrue;
1105           goto next;
1106
1107         case O (O_BEQ, SB):
1108           if (Z)
1109             goto condtrue;
1110           goto next;
1111         case O (O_BGT, SB):
1112           if (((Z || (N ^ V)) == 0))
1113             goto condtrue;
1114           goto next;
1115
1116
1117         case O (O_BLE, SB):
1118           if (((Z || (N ^ V)) == 1))
1119             goto condtrue;
1120           goto next;
1121
1122         case O (O_BGE, SB):
1123           if ((N ^ V) == 0)
1124             goto condtrue;
1125           goto next;
1126         case O (O_BLT, SB):
1127           if ((N ^ V))
1128             goto condtrue;
1129           goto next;
1130         case O (O_BMI, SB):
1131           if ((N))
1132             goto condtrue;
1133           goto next;
1134         case O (O_BNE, SB):
1135           if ((Z == 0))
1136             goto condtrue;
1137           goto next;
1138
1139         case O (O_BPL, SB):
1140           if (N == 0)
1141             goto condtrue;
1142           goto next;
1143         case O (O_BVC, SB):
1144           if ((V == 0))
1145             goto condtrue;
1146           goto next;
1147         case O (O_BVS, SB):
1148           if ((V == 1))
1149             goto condtrue;
1150           goto next;
1151
1152         case O (O_SYSCALL, SB):
1153           printf ("%c", cpu.regs[2]);
1154           goto next;
1155
1156           OSHIFTS (O_NOT, rd = ~rd);
1157           OSHIFTS (O_SHLL, c = rd & hm;
1158                    rd <<= 1);
1159           OSHIFTS (O_SHLR, c = rd & 1;
1160                    rd = (unsigned int) rd >> 1);
1161           OSHIFTS (O_SHAL, c = rd & hm;
1162                    rd <<= 1);
1163           OSHIFTS (O_SHAR, t = rd & hm;
1164                    c = rd & 1;
1165                    rd >>= 1;
1166                    rd |= t;
1167             );
1168           OSHIFTS (O_ROTL, c = rd & hm;
1169                    rd <<= 1;
1170                    rd |= C);
1171           OSHIFTS (O_ROTR, c = rd & 1;
1172                    rd = (unsigned int) rd >> 1;
1173                    if (c) rd |= hm;);
1174           OSHIFTS (O_ROTXL, t = rd & hm;
1175                    rd <<= 1;
1176                    rd |= C;
1177                    c = t;
1178             );
1179           OSHIFTS (O_ROTXR, t = rd & 1;
1180                    rd = (unsigned int) rd >> 1;
1181                    if (C) rd |= hm; c = t;);
1182
1183         case O (O_JMP, SB):
1184           {
1185             pc = fetch (&code->src);
1186             goto end;
1187
1188           }
1189
1190         case O (O_JSR, SB):
1191           {
1192             int tmp;
1193             pc = fetch (&code->src);
1194           call:
1195             tmp = cpu.regs[7];
1196
1197             if (h8300hmode)
1198               {
1199                 tmp -= 4;
1200                 SET_MEMORY_L (tmp, code->next_pc);
1201               }
1202             else
1203               {
1204                 tmp -= 2;
1205                 SET_MEMORY_W (tmp, code->next_pc);
1206               }
1207             cpu.regs[7] = tmp;
1208
1209             goto end;
1210           }
1211         case O (O_BSR, SB):
1212           pc = code->src.literal;
1213           goto call;
1214
1215         case O (O_RTS, SB):
1216           {
1217             int tmp;
1218
1219             tmp = cpu.regs[7];
1220
1221             if (h8300hmode)
1222               {
1223                 pc = GET_MEMORY_L (tmp);
1224                 tmp += 4;
1225               }
1226             else
1227               {
1228                 pc = GET_MEMORY_W (tmp);
1229                 tmp += 2;
1230               }
1231
1232             cpu.regs[7] = tmp;
1233             goto end;
1234           }
1235
1236         case O (O_ILL, SB):
1237           cpu.exception = SIGILL;
1238           goto end;
1239         case O (O_SLEEP, SB):
1240         case O (O_BPT, SB):
1241           cpu.exception = SIGTRAP;
1242           goto end;
1243
1244           OBITOP (O_BNOT, 1, 1, ea ^= m);
1245           OBITOP (O_BTST, 1, 0, nz = ea & m);
1246           OBITOP (O_BCLR, 1, 1, ea &= ~m);
1247           OBITOP (O_BSET, 1, 1, ea |= m);
1248           OBITOP (O_BLD, 1, 0, c = ea & m);
1249           OBITOP (O_BILD, 1, 0, c = !(ea & m));
1250           OBITOP (O_BST, 1, 1, ea &= ~m;
1251                   if (C) ea |= m);
1252           OBITOP (O_BIST, 1, 1, ea &= ~m;
1253                   if (!C) ea |= m);
1254           OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1255           OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1256           OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1257           OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1258           OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1259           OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1260
1261
1262 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1263
1264         case O (O_MULS, SB):
1265           MOP (1, 1);
1266           break;
1267         case O (O_MULS, SW):
1268           MOP (0, 1);
1269           break;
1270         case O (O_MULU, SB):
1271           MOP (1, 0);
1272           break;
1273         case O (O_MULU, SW):
1274           MOP (0, 0);
1275           break;
1276
1277
1278         case O (O_DIVU, SB):
1279           {
1280             rd = GET_W_REG (code->dst.reg);
1281             ea = GET_B_REG (code->src.reg);
1282             if (ea)
1283               {
1284                 tmp = rd % ea;
1285                 rd = rd / ea;
1286               }
1287             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1288             n = ea & 0x80;
1289             nz = ea & 0xff;
1290
1291             goto next;
1292           }
1293         case O (O_DIVU, SW):
1294           {
1295             rd = GET_L_REG (code->dst.reg);
1296             ea = GET_W_REG (code->src.reg);
1297             n = ea & 0x8000;
1298             nz = ea & 0xffff;
1299             if (ea)
1300               {
1301                 tmp = rd % ea;
1302                 rd = rd / ea;
1303               }
1304             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1305             goto next;
1306           }
1307
1308         case O (O_DIVS, SB):
1309           {
1310
1311             rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1312             ea = SEXTCHAR (GET_B_REG (code->src.reg));
1313             if (ea)
1314               {
1315                 tmp = (int) rd % (int) ea;
1316                 rd = (int) rd / (int) ea;
1317                 n = rd & 0x8000;
1318                 nz = 1;
1319               }
1320             else
1321               nz = 0;
1322             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1323             goto next;
1324           }
1325         case O (O_DIVS, SW):
1326           {
1327             rd = GET_L_REG (code->dst.reg);
1328             ea = SEXTSHORT (GET_W_REG (code->src.reg));
1329             if (ea)
1330               {
1331                 tmp = (int) rd % (int) ea;
1332                 rd = (int) rd / (int) ea;
1333                 n = rd & 0x80000000;
1334                 nz = 1;
1335               }
1336             else
1337               nz = 0;
1338             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1339             goto next;
1340           }
1341         case O (O_EXTS, SW):
1342           rd = GET_B_REG (code->src.reg + 8) & 0xff;    /* Yes, src, not dst.  */
1343           ea = rd & 0x80 ? -256 : 0;
1344           res = rd + ea;
1345           goto log16;
1346         case O (O_EXTS, SL):
1347           rd = GET_W_REG (code->src.reg) & 0xffff;
1348           ea = rd & 0x8000 ? -65536 : 0;
1349           res = rd + ea;
1350           goto log32;
1351         case O (O_EXTU, SW):
1352           rd = GET_B_REG (code->src.reg + 8) & 0xff;
1353           ea = 0;
1354           res = rd + ea;
1355           goto log16;
1356         case O (O_EXTU, SL):
1357           rd = GET_W_REG (code->src.reg) & 0xffff;
1358           ea = 0;
1359           res = rd + ea;
1360           goto log32;
1361
1362         case O (O_NOP, SB):
1363           goto next;
1364
1365         default:
1366           cpu.exception = 123;
1367           goto end;
1368
1369         }
1370       abort ();
1371
1372     setc:
1373       cpu.ccr = res;
1374       GETSR ();
1375       goto next;
1376
1377     condtrue:
1378       /* When a branch works */
1379       pc = code->src.literal;
1380       goto end;
1381
1382       /* Set the cond codes from res */
1383     bitop:
1384
1385       /* Set the flags after an 8 bit inc/dec operation */
1386     just_flags_inc8:
1387       n = res & 0x80;
1388       nz = res & 0xff;
1389       v = (rd & 0x7f) == 0x7f;
1390       goto next;
1391
1392
1393       /* Set the flags after an 16 bit inc/dec operation */
1394     just_flags_inc16:
1395       n = res & 0x8000;
1396       nz = res & 0xffff;
1397       v = (rd & 0x7fff) == 0x7fff;
1398       goto next;
1399
1400
1401       /* Set the flags after an 32 bit inc/dec operation */
1402     just_flags_inc32:
1403       n = res & 0x80000000;
1404       nz = res & 0xffffffff;
1405       v = (rd & 0x7fffffff) == 0x7fffffff;
1406       goto next;
1407
1408
1409     shift8:
1410       /* Set flags after an 8 bit shift op, carry set in insn */
1411       n = (rd & 0x80);
1412       v = 0;
1413       nz = rd & 0xff;
1414       SET_B_REG (code->src.reg, rd);
1415       goto next;
1416
1417
1418     shift16:
1419       /* Set flags after an 16 bit shift op, carry set in insn */
1420       n = (rd & 0x8000);
1421       v = 0;
1422       nz = rd & 0xffff;
1423
1424       SET_W_REG (code->src.reg, rd);
1425       goto next;
1426
1427     shift32:
1428       /* Set flags after an 32 bit shift op, carry set in insn */
1429       n = (rd & 0x80000000);
1430       v = 0;
1431       nz = rd & 0xffffffff;
1432       SET_L_REG (code->src.reg, rd);
1433       goto next;
1434
1435     log32:
1436       store (&code->dst, res);
1437     just_flags_log32:
1438       /* flags after a 32bit logical operation */
1439       n = res & 0x80000000;
1440       nz = res & 0xffffffff;
1441       v = 0;
1442       goto next;
1443
1444     log16:
1445       store (&code->dst, res);
1446     just_flags_log16:
1447       /* flags after a 16bit logical operation */
1448       n = res & 0x8000;
1449       nz = res & 0xffff;
1450       v = 0;
1451       goto next;
1452
1453
1454     log8:
1455       store (&code->dst, res);
1456     just_flags_log8:
1457       n = res & 0x80;
1458       nz = res & 0xff;
1459       v = 0;
1460       goto next;
1461
1462     alu8:
1463       SET_B_REG (code->dst.reg, res);
1464     just_flags_alu8:
1465       n = res & 0x80;
1466       nz = res & 0xff;
1467       v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1468       c = (res & 0x100);
1469       goto next;
1470
1471     alu16:
1472       SET_W_REG (code->dst.reg, res);
1473     just_flags_alu16:
1474       n = res & 0x8000;
1475       nz = res & 0xffff;
1476       v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1477       c = (res & 0x10000);
1478       goto next;
1479
1480     alu32:
1481       SET_L_REG (code->dst.reg, res);
1482     just_flags_alu32:
1483       n = res & 0x80000000;
1484       nz = res & 0xffffffff;
1485       v = ((ea & 0x80000000) == (rd & 0x80000000))
1486         && ((ea & 0x80000000) != (res & 0x80000000));
1487       switch (code->opcode / 4)
1488         {
1489         case O_ADD:
1490           c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1491           break;
1492         case O_SUB:
1493         case O_CMP:
1494           c = (unsigned) rd < (unsigned) -ea;
1495           break;
1496         case O_NEG:
1497           c = res != 0;
1498           break;
1499         }
1500       goto next;
1501
1502     next:;
1503       pc = code->next_pc;
1504
1505     end:
1506       ;
1507       /*      if (cpu.regs[8] ) abort(); */
1508
1509 #ifdef __GO32__
1510       /* Poll after every 100th insn, */
1511       if (poll_count++ > 100)
1512         {
1513           poll_count = 0;
1514           if (kbhit ())
1515             {
1516               int c = getkey ();
1517               control_c ();
1518             }
1519         }
1520 #endif
1521
1522     }
1523   while (!cpu.exception);
1524   cpu.ticks += get_now () - tick_start;
1525   cpu.cycles += cycles;
1526   cpu.insts += insts;
1527
1528   cpu.pc = pc;
1529   BUILDSR ();
1530
1531   signal (SIGINT, prev);
1532 }
1533
1534
1535 int
1536 sim_write (addr, buffer, size)
1537      SIM_ADDR addr;
1538      unsigned char *buffer;
1539      int size;
1540 {
1541   int i;
1542
1543   init_pointers ();
1544   if (addr < 0 || addr + size > MSIZE)
1545     return 0;
1546   for (i = 0; i < size; i++)
1547     {
1548       cpu.memory[addr + i] = buffer[i];
1549       cpu.cache_idx[addr + i] = 0;
1550     }
1551   return size;
1552 }
1553
1554 int
1555 sim_read (addr, buffer, size)
1556      SIM_ADDR addr;
1557      unsigned char *buffer;
1558      int size;
1559 {
1560   init_pointers ();
1561   if (addr < 0 || addr + size > MSIZE)
1562     return 0;
1563   memcpy (buffer, cpu.memory + addr, size);
1564   return size;
1565 }
1566
1567
1568 #define R0_REGNUM       0
1569 #define R1_REGNUM       1
1570 #define R2_REGNUM       2
1571 #define R3_REGNUM       3
1572 #define R4_REGNUM       4
1573 #define R5_REGNUM       5
1574 #define R6_REGNUM       6
1575 #define R7_REGNUM       7
1576
1577 #define SP_REGNUM       R7_REGNUM       /* Contains address of top of stack */
1578 #define FP_REGNUM       R6_REGNUM       /* Contains address of executing
1579                                            * stack frame */
1580
1581 #define CCR_REGNUM      8       /* Contains processor status */
1582 #define PC_REGNUM       9       /* Contains program counter */
1583
1584 #define CYCLE_REGNUM    10
1585 #define INST_REGNUM     11
1586 #define TICK_REGNUM     12
1587
1588
1589 int
1590 sim_store_register (rn, value)
1591      int rn;
1592      unsigned char *value;
1593 {
1594   int longval;
1595   int shortval;
1596   int intval;
1597   longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1598   shortval = (value[0] << 8) | (value[1]);
1599   intval = h8300hmode ? longval : shortval;
1600
1601   init_pointers ();
1602   switch (rn)
1603     {
1604     case PC_REGNUM:
1605       cpu.pc = intval;
1606       break;
1607     default:
1608       abort ();
1609     case R0_REGNUM:
1610     case R1_REGNUM:
1611     case R2_REGNUM:
1612     case R3_REGNUM:
1613     case R4_REGNUM:
1614     case R5_REGNUM:
1615     case R6_REGNUM:
1616     case R7_REGNUM:
1617       cpu.regs[rn] = intval;
1618       break;
1619     case CCR_REGNUM:
1620       cpu.ccr = intval;
1621       break;
1622     case CYCLE_REGNUM:
1623       cpu.cycles = longval;
1624       break;
1625
1626     case INST_REGNUM:
1627       cpu.insts = longval;
1628       break;
1629
1630     case TICK_REGNUM:
1631       cpu.ticks = longval;
1632       break;
1633     }
1634   return 0;
1635 }
1636
1637 int
1638 sim_fetch_register (rn, buf)
1639      int rn;
1640      unsigned char *buf;
1641 {
1642   int v;
1643   int longreg = 0;
1644
1645   init_pointers ();
1646
1647   switch (rn)
1648     {
1649     default:
1650       abort ();
1651     case 8:
1652       v = cpu.ccr;
1653       break;
1654     case 9:
1655       v = cpu.pc;
1656       break;
1657     case R0_REGNUM:
1658     case R1_REGNUM:
1659     case R2_REGNUM:
1660     case R3_REGNUM:
1661     case R4_REGNUM:
1662     case R5_REGNUM:
1663     case R6_REGNUM:
1664     case R7_REGNUM:
1665       v = cpu.regs[rn];
1666       break;
1667     case 10:
1668       v = cpu.cycles;
1669       longreg = 1;
1670       break;
1671     case 11:
1672       v = cpu.ticks;
1673       longreg = 1;
1674       break;
1675     case 12:
1676       v = cpu.insts;
1677       longreg = 1;
1678       break;
1679     }
1680   if (h8300hmode || longreg)
1681     {
1682       buf[0] = v >> 24;
1683       buf[1] = v >> 16;
1684       buf[2] = v >> 8;
1685       buf[3] = v >> 0;
1686     }
1687   else
1688     {
1689       buf[0] = v >> 8;
1690       buf[1] = v;
1691     }
1692   return 0;
1693 }
1694
1695 int
1696 sim_trace ()
1697 {
1698   return 0;
1699 }
1700
1701 int
1702 sim_stop_reason (reason, sigrc)
1703      enum sim_stop *reason;
1704      int *sigrc;
1705 {
1706   *reason = sim_stopped;
1707   *sigrc = cpu.exception;
1708   return 0;
1709 }
1710
1711 int
1712 sim_set_pc (n)
1713      SIM_ADDR n;
1714 {
1715   cpu.pc = n;
1716   return 0;
1717 }
1718
1719
1720 sim_csize (n)
1721 {
1722   if (cpu.cache)
1723     free (cpu.cache);
1724   if (n < 2)
1725     n = 2;
1726   cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1727   memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1728   cpu.csize = n;
1729 }
1730
1731
1732 int
1733 sim_info (printf_fn, verbose)
1734      void (*printf_fn) ();
1735      int verbose;
1736
1737 {
1738   double timetaken = (double) cpu.ticks / (double) now_persec ();
1739   double virttime = cpu.cycles / 10.0e6;
1740
1741   printf ("\n\n#instructions executed  %10d\n", cpu.insts);
1742   printf ("#cycles (v approximate) %10d\n", cpu.cycles);
1743   printf ("#real time taken        %10.4f\n", timetaken);
1744   printf ("#virtual time taked     %10.4f\n", virttime);
1745   if (timetaken != 0.0)
1746     printf ("#simulation ratio       %10.4f\n", virttime / timetaken);
1747   printf ("#compiles               %10d\n", cpu.compiles);
1748   printf ("#cache size             %10d\n", cpu.csize);
1749
1750
1751 #ifdef ADEBUG
1752   if (verbose)
1753     {
1754       int i;
1755       for (i = 0; i < O_LAST; i++)
1756         {
1757           if (cpu.stats[i])
1758             printf ("%d: %d\n", i, cpu.stats[i]);
1759         }
1760     }
1761 #endif
1762
1763   return 0;
1764 }
1765
1766 void
1767 set_h8300h ()
1768 {
1769   h8300hmode = 1;
1770 }
1771
1772 int
1773 sim_kill ()
1774 {
1775   return 0;
1776 }
1777
1778 sim_open (name)
1779      char *name;
1780 {
1781   return 0;
1782 }
1783
1784 sim_set_args (argv, env)
1785      char **argv;
1786      char **env;
1787 {
1788   return 0;
1789 }