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2002-03-05 Chris Demetriou <cgd@broadcom.com>
[deliverable/binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Hitachi H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21
22 #include <stdio.h>
23 #include <signal.h>
24 #ifdef HAVE_TIME_H
25 #include <time.h>
26 #endif
27 #ifdef HAVE_STDLIB_H
28 #include <stdlib.h>
29 #endif
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
32 #endif
33 #include "ansidecl.h"
34 #include "bfd.h"
35 #include "callback.h"
36 #include "remote-sim.h"
37
38 #ifndef SIGTRAP
39 # define SIGTRAP 5
40 #endif
41
42 int debug;
43
44 host_callback *sim_callback;
45
46 static SIM_OPEN_KIND sim_kind;
47 static char *myname;
48
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
52 by gdb. */
53 void sim_set_simcache_size PARAMS ((int));
54
55 #define X(op, size) op * 4 + size
56
57 #define SP (h8300hmode ? SL : SW)
58 #define SB 0
59 #define SW 1
60 #define SL 2
61 #define OP_REG 1
62 #define OP_DEC 2
63 #define OP_DISP 3
64 #define OP_INC 4
65 #define OP_PCREL 5
66 #define OP_MEM 6
67 #define OP_CCR 7
68 #define OP_IMM 8
69 #define OP_ABS 10
70 #define h8_opcodes ops
71 #define DEFINE_TABLE
72 #include "opcode/h8300.h"
73
74 #include "inst.h"
75
76 /* The rate at which to call the host's poll_quit callback. */
77
78 #define POLL_QUIT_INTERVAL 0x80000
79
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
82 #define P(X,Y) ((X << 8) | Y)
83
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V << 1) | C;
85
86 #define GETSR() \
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
91
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char) (x))
94 #endif
95
96 #ifndef SEXTCHAR
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
98 #endif
99
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short) (x))
103
104 static cpu_state_type cpu;
105
106 int h8300hmode = 0;
107 int h8300smode = 0;
108
109 static int memory_size;
110
111 static int
112 get_now ()
113 {
114 #ifndef WIN32
115 return time (0);
116 #endif
117 return 0;
118 }
119
120 static int
121 now_persec ()
122 {
123 return 1;
124 }
125
126 static int
127 bitfrom (x)
128 {
129 switch (x & SIZE)
130 {
131 case L_8:
132 return SB;
133 case L_16:
134 return SW;
135 case L_32:
136 return SL;
137 case L_P:
138 return h8300hmode ? SL : SW;
139 }
140 }
141
142 static unsigned int
143 lvalue (x, rn)
144 {
145 switch (x / 4)
146 {
147 case OP_DISP:
148 if (rn == 8)
149 {
150 return X (OP_IMM, SP);
151 }
152 return X (OP_REG, SP);
153
154 case OP_MEM:
155 return X (OP_MEM, SP);
156
157 default:
158 abort ();
159 }
160 }
161
162 static unsigned int
163 decode (addr, data, dst)
164 int addr;
165 unsigned char *data;
166 decoded_inst *dst;
167
168 {
169 int rs = 0;
170 int rd = 0;
171 int rdisp = 0;
172 int abs = 0;
173 int bit = 0;
174 int plen = 0;
175 struct h8_opcode *q;
176 int size = 0;
177
178 dst->dst.type = -1;
179 dst->src.type = -1;
180
181 /* Find the exact opcode/arg combo. */
182 for (q = h8_opcodes; q->name; q++)
183 {
184 op_type *nib = q->data.nib;
185 unsigned int len = 0;
186
187 while (1)
188 {
189 op_type looking_for = *nib;
190 int thisnib = data[len >> 1];
191
192 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
193
194 if (looking_for < 16 && looking_for >= 0)
195 {
196 if (looking_for != thisnib)
197 goto fail;
198 }
199 else
200 {
201 if ((int) looking_for & (int) B31)
202 {
203 if (!(((int) thisnib & 0x8) != 0))
204 goto fail;
205
206 looking_for = (op_type) ((int) looking_for & ~(int) B31);
207 thisnib &= 0x7;
208 }
209
210 if ((int) looking_for & (int) B30)
211 {
212 if (!(((int) thisnib & 0x8) == 0))
213 goto fail;
214
215 looking_for = (op_type) ((int) looking_for & ~(int) B30);
216 }
217
218 if (looking_for & DBIT)
219 {
220 /* Exclude adds/subs by looking at bit 0 and 2, and
221 make sure the operand size, either w or l,
222 matches by looking at bit 1. */
223 if ((looking_for & 7) != (thisnib & 7))
224 goto fail;
225
226 abs = (thisnib & 0x8) ? 2 : 1;
227 }
228 else if (looking_for & (REG | IND | INC | DEC))
229 {
230 if (looking_for & REG)
231 {
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
234 }
235 if (looking_for & SRC)
236 rs = thisnib;
237 else
238 rd = thisnib;
239 }
240 else if (looking_for & L_16)
241 {
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
243 plen = 16;
244 if (looking_for & (PCREL | DISP))
245 {
246 abs = (short) (abs);
247 }
248 }
249 else if (looking_for & ABSJMP)
250 {
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
252 }
253 else if (looking_for & MEMIND)
254 {
255 abs = data[1];
256 }
257 else if (looking_for & L_32)
258 {
259 int i = len >> 1;
260
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
263 | (data[i + 2] << 8)
264 | (data[i + 3]);
265
266 plen = 32;
267 }
268 else if (looking_for & L_24)
269 {
270 int i = len >> 1;
271
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
273 plen = 24;
274 }
275 else if (looking_for & IGNORE)
276 {
277 ;
278 }
279 else if (looking_for & DISPREG)
280 {
281 rdisp = thisnib & 0x7;
282 }
283 else if (looking_for & KBIT)
284 {
285 switch (thisnib)
286 {
287 case 9:
288 abs = 4;
289 break;
290 case 8:
291 abs = 2;
292 break;
293 case 0:
294 abs = 1;
295 break;
296 default:
297 goto fail;
298 }
299 }
300 else if (looking_for & L_8)
301 {
302 plen = 8;
303
304 if (looking_for & PCREL)
305 {
306 abs = SEXTCHAR (data[len >> 1]);
307 }
308 else if (looking_for & ABS8MEM)
309 {
310 plen = 8;
311 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
312 abs |= data[len >> 1] & 0xff;
313 }
314 else
315 {
316 abs = data[len >> 1] & 0xff;
317 }
318 }
319 else if (looking_for & L_3)
320 {
321 plen = 3;
322
323 bit = thisnib;
324 }
325 else if (looking_for == E)
326 {
327 dst->op = q;
328
329 /* Fill in the args. */
330 {
331 op_type *args = q->args.nib;
332 int hadone = 0;
333
334 while (*args != E)
335 {
336 int x = *args;
337 int rn = (x & DST) ? rd : rs;
338 ea_type *p;
339
340 if (x & DST)
341 p = &(dst->dst);
342 else
343 p = &(dst->src);
344
345 if (x & L_3)
346 {
347 p->type = X (OP_IMM, size);
348 p->literal = bit;
349 }
350 else if (x & (IMM | KBIT | DBIT))
351 {
352 p->type = X (OP_IMM, size);
353 p->literal = abs;
354 }
355 else if (x & REG)
356 {
357 /* Reset the size.
358 Some ops (like mul) have two sizes. */
359
360 size = bitfrom (x);
361 p->type = X (OP_REG, size);
362 p->reg = rn;
363 }
364 else if (x & INC)
365 {
366 p->type = X (OP_INC, size);
367 p->reg = rn & 0x7;
368 }
369 else if (x & DEC)
370 {
371 p->type = X (OP_DEC, size);
372 p->reg = rn & 0x7;
373 }
374 else if (x & IND)
375 {
376 p->type = X (OP_DISP, size);
377 p->reg = rn & 0x7;
378 p->literal = 0;
379 }
380 else if (x & (ABS | ABSJMP | ABS8MEM))
381 {
382 p->type = X (OP_DISP, size);
383 p->literal = abs;
384 p->reg = 8;
385 }
386 else if (x & MEMIND)
387 {
388 p->type = X (OP_MEM, size);
389 p->literal = abs;
390 }
391 else if (x & PCREL)
392 {
393 p->type = X (OP_PCREL, size);
394 p->literal = abs + addr + 2;
395 if (x & L_16)
396 p->literal += 2;
397 }
398 else if (x & ABSJMP)
399 {
400 p->type = X (OP_IMM, SP);
401 p->literal = abs;
402 }
403 else if (x & DISP)
404 {
405 p->type = X (OP_DISP, size);
406 p->literal = abs;
407 p->reg = rdisp & 0x7;
408 }
409 else if (x & CCR)
410 {
411 p->type = OP_CCR;
412 }
413 else
414 printf ("Hmmmm %x", x);
415
416 args++;
417 }
418 }
419
420 /* But a jmp or a jsr gets automagically lvalued,
421 since we branch to their address not their
422 contents. */
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
425 {
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
427 }
428
429 if (dst->dst.type == -1)
430 dst->dst = dst->src;
431
432 dst->opcode = q->how;
433 dst->cycles = q->time;
434
435 /* And a jsr to 0xc4 is turned into a magic trap. */
436
437 if (dst->opcode == O (O_JSR, SB))
438 {
439 if (dst->src.literal == 0xc4)
440 {
441 dst->opcode = O (O_SYSCALL, SB);
442 }
443 }
444
445 dst->next_pc = addr + len / 2;
446 return;
447 }
448 else
449 printf ("Don't understand %x \n", looking_for);
450 }
451
452 len++;
453 nib++;
454 }
455
456 fail:
457 ;
458 }
459
460 /* Fell off the end. */
461 dst->opcode = O (O_ILL, SB);
462 }
463
464 static void
465 compile (pc)
466 {
467 int idx;
468
469 /* Find the next cache entry to use. */
470 idx = cpu.cache_top + 1;
471 cpu.compiles++;
472 if (idx >= cpu.csize)
473 {
474 idx = 1;
475 }
476 cpu.cache_top = idx;
477
478 /* Throw away its old meaning. */
479 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
480
481 /* Set to new address. */
482 cpu.cache[idx].oldpc = pc;
483
484 /* Fill in instruction info. */
485 decode (pc, cpu.memory + pc, cpu.cache + idx);
486
487 /* Point to new cache entry. */
488 cpu.cache_idx[pc] = idx;
489 }
490
491
492 static unsigned char *breg[18];
493 static unsigned short *wreg[18];
494 static unsigned int *lreg[18];
495
496 #define GET_B_REG(x) *(breg[x])
497 #define SET_B_REG(x,y) (*(breg[x])) = (y)
498 #define GET_W_REG(x) *(wreg[x])
499 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
500
501 #define GET_L_REG(x) *(lreg[x])
502 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
503
504 #define GET_MEMORY_L(x) \
505 (x < memory_size \
506 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
507 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
508 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
509 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
510
511 #define GET_MEMORY_W(x) \
512 (x < memory_size \
513 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
514 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
515
516
517 #define GET_MEMORY_B(x) \
518 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
519
520 #define SET_MEMORY_L(x,y) \
521 { register unsigned char *_p; register int __y = y; \
522 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
523 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
524 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
525
526 #define SET_MEMORY_W(x,y) \
527 { register unsigned char *_p; register int __y = y; \
528 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
529 _p[0] = (__y)>>8; _p[1] =(__y);}
530
531 #define SET_MEMORY_B(x,y) \
532 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
533
534 int
535 fetch (arg, n)
536 ea_type *arg;
537 {
538 int rn = arg->reg;
539 int abs = arg->literal;
540 int r;
541 int t;
542
543 switch (arg->type)
544 {
545 case X (OP_REG, SB):
546 return GET_B_REG (rn);
547 case X (OP_REG, SW):
548 return GET_W_REG (rn);
549 case X (OP_REG, SL):
550 return GET_L_REG (rn);
551 case X (OP_IMM, SB):
552 case X (OP_IMM, SW):
553 case X (OP_IMM, SL):
554 return abs;
555 case X (OP_DEC, SB):
556 abort ();
557
558 case X (OP_INC, SB):
559 t = GET_L_REG (rn);
560 t &= cpu.mask;
561 r = GET_MEMORY_B (t);
562 t++;
563 t = t & cpu.mask;
564 SET_L_REG (rn, t);
565 return r;
566 break;
567 case X (OP_INC, SW):
568 t = GET_L_REG (rn);
569 t &= cpu.mask;
570 r = GET_MEMORY_W (t);
571 t += 2;
572 t = t & cpu.mask;
573 SET_L_REG (rn, t);
574 return r;
575 case X (OP_INC, SL):
576 t = GET_L_REG (rn);
577 t &= cpu.mask;
578 r = GET_MEMORY_L (t);
579
580 t += 4;
581 t = t & cpu.mask;
582 SET_L_REG (rn, t);
583 return r;
584
585 case X (OP_DISP, SB):
586 t = GET_L_REG (rn) + abs;
587 t &= cpu.mask;
588 return GET_MEMORY_B (t);
589
590 case X (OP_DISP, SW):
591 t = GET_L_REG (rn) + abs;
592 t &= cpu.mask;
593 return GET_MEMORY_W (t);
594
595 case X (OP_DISP, SL):
596 t = GET_L_REG (rn) + abs;
597 t &= cpu.mask;
598 return GET_MEMORY_L (t);
599
600 case X (OP_MEM, SL):
601 t = GET_MEMORY_L (abs);
602 t &= cpu.mask;
603 return t;
604
605 case X (OP_MEM, SW):
606 t = GET_MEMORY_W (abs);
607 t &= cpu.mask;
608 return t;
609
610 default:
611 abort ();
612
613 }
614 }
615
616
617 static void
618 store (arg, n)
619 ea_type *arg;
620 int n;
621 {
622 int rn = arg->reg;
623 int abs = arg->literal;
624 int t;
625
626 switch (arg->type)
627 {
628 case X (OP_REG, SB):
629 SET_B_REG (rn, n);
630 break;
631 case X (OP_REG, SW):
632 SET_W_REG (rn, n);
633 break;
634 case X (OP_REG, SL):
635 SET_L_REG (rn, n);
636 break;
637
638 case X (OP_DEC, SB):
639 t = GET_L_REG (rn) - 1;
640 t &= cpu.mask;
641 SET_L_REG (rn, t);
642 SET_MEMORY_B (t, n);
643
644 break;
645 case X (OP_DEC, SW):
646 t = (GET_L_REG (rn) - 2) & cpu.mask;
647 SET_L_REG (rn, t);
648 SET_MEMORY_W (t, n);
649 break;
650
651 case X (OP_DEC, SL):
652 t = (GET_L_REG (rn) - 4) & cpu.mask;
653 SET_L_REG (rn, t);
654 SET_MEMORY_L (t, n);
655 break;
656
657 case X (OP_DISP, SB):
658 t = GET_L_REG (rn) + abs;
659 t &= cpu.mask;
660 SET_MEMORY_B (t, n);
661 break;
662
663 case X (OP_DISP, SW):
664 t = GET_L_REG (rn) + abs;
665 t &= cpu.mask;
666 SET_MEMORY_W (t, n);
667 break;
668
669 case X (OP_DISP, SL):
670 t = GET_L_REG (rn) + abs;
671 t &= cpu.mask;
672 SET_MEMORY_L (t, n);
673 break;
674 default:
675 abort ();
676 }
677 }
678
679
680 static union
681 {
682 short int i;
683 struct
684 {
685 char low;
686 char high;
687 }
688 u;
689 }
690
691 littleendian;
692
693 static void
694 init_pointers ()
695 {
696 static int init;
697
698 if (!init)
699 {
700 int i;
701
702 init = 1;
703 littleendian.i = 1;
704
705 if (h8300hmode)
706 memory_size = H8300H_MSIZE;
707 else
708 memory_size = H8300_MSIZE;
709 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
710 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
711 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
712
713 /* `msize' must be a power of two. */
714 if ((memory_size & (memory_size - 1)) != 0)
715 abort ();
716 cpu.mask = memory_size - 1;
717
718 for (i = 0; i < 9; i++)
719 {
720 cpu.regs[i] = 0;
721 }
722
723 for (i = 0; i < 8; i++)
724 {
725 unsigned char *p = (unsigned char *) (cpu.regs + i);
726 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
727 unsigned short *q = (unsigned short *) (cpu.regs + i);
728 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
729 cpu.regs[i] = 0x00112233;
730 while (p < e)
731 {
732 if (*p == 0x22)
733 {
734 breg[i] = p;
735 }
736 if (*p == 0x33)
737 {
738 breg[i + 8] = p;
739 }
740 p++;
741 }
742 while (q < u)
743 {
744 if (*q == 0x2233)
745 {
746 wreg[i] = q;
747 }
748 if (*q == 0x0011)
749 {
750 wreg[i + 8] = q;
751 }
752 q++;
753 }
754 cpu.regs[i] = 0;
755 lreg[i] = &cpu.regs[i];
756 }
757
758 lreg[8] = &cpu.regs[8];
759
760 /* Initialize the seg registers. */
761 if (!cpu.cache)
762 sim_set_simcache_size (CSIZE);
763 }
764 }
765
766 static void
767 control_c (sig, code, scp, addr)
768 int sig;
769 int code;
770 char *scp;
771 char *addr;
772 {
773 cpu.state = SIM_STATE_STOPPED;
774 cpu.exception = SIGINT;
775 }
776
777 #define C (c != 0)
778 #define Z (nz == 0)
779 #define V (v != 0)
780 #define N (n != 0)
781
782 static int
783 mop (code, bsize, sign)
784 decoded_inst *code;
785 int bsize;
786 int sign;
787 {
788 int multiplier;
789 int multiplicand;
790 int result;
791 int n, nz;
792
793 if (sign)
794 {
795 multiplicand =
796 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
797 SEXTSHORT (GET_W_REG (code->dst.reg));
798 multiplier =
799 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
800 SEXTSHORT (GET_W_REG (code->src.reg));
801 }
802 else
803 {
804 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
805 UEXTSHORT (GET_W_REG (code->dst.reg));
806 multiplier =
807 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
808 UEXTSHORT (GET_W_REG (code->src.reg));
809
810 }
811 result = multiplier * multiplicand;
812
813 if (sign)
814 {
815 n = result & (bsize ? 0x8000 : 0x80000000);
816 nz = result & (bsize ? 0xffff : 0xffffffff);
817 }
818 if (bsize)
819 {
820 SET_W_REG (code->dst.reg, result);
821 }
822 else
823 {
824 SET_L_REG (code->dst.reg, result);
825 }
826 #if 0
827 return ((n == 1) << 1) | (nz == 1);
828 #endif
829 }
830
831 #define ONOT(name, how) \
832 case O(name, SB): \
833 { \
834 int t; \
835 int hm = 0x80; \
836 rd = GET_B_REG (code->src.reg); \
837 how; \
838 goto shift8; \
839 } \
840 case O(name, SW): \
841 { \
842 int t; \
843 int hm = 0x8000; \
844 rd = GET_W_REG (code->src.reg); \
845 how; \
846 goto shift16; \
847 } \
848 case O(name, SL): \
849 { \
850 int t; \
851 int hm = 0x80000000; \
852 rd = GET_L_REG (code->src.reg); \
853 how; \
854 goto shift32; \
855 }
856
857 #define OSHIFTS(name, how1, how2) \
858 case O(name, SB): \
859 { \
860 int t; \
861 int hm = 0x80; \
862 rd = GET_B_REG (code->src.reg); \
863 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
864 { \
865 how1; \
866 } \
867 else \
868 { \
869 how2; \
870 } \
871 goto shift8; \
872 } \
873 case O(name, SW): \
874 { \
875 int t; \
876 int hm = 0x8000; \
877 rd = GET_W_REG (code->src.reg); \
878 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
879 { \
880 how1; \
881 } \
882 else \
883 { \
884 how2; \
885 } \
886 goto shift16; \
887 } \
888 case O(name, SL): \
889 { \
890 int t; \
891 int hm = 0x80000000; \
892 rd = GET_L_REG (code->src.reg); \
893 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
894 { \
895 how1; \
896 } \
897 else \
898 { \
899 how2; \
900 } \
901 goto shift32; \
902 }
903
904 #define OBITOP(name,f, s, op) \
905 case O(name, SB): \
906 { \
907 int m; \
908 int b; \
909 if (f) ea = fetch (&code->dst); \
910 m=1<< fetch(&code->src); \
911 op; \
912 if(s) store (&code->dst,ea); goto next; \
913 }
914
915 int
916 sim_stop (sd)
917 SIM_DESC sd;
918 {
919 cpu.state = SIM_STATE_STOPPED;
920 cpu.exception = SIGINT;
921 return 1;
922 }
923
924 void
925 sim_resume (sd, step, siggnal)
926 SIM_DESC sd;
927 {
928 static int init1;
929 int cycles = 0;
930 int insts = 0;
931 int tick_start = get_now ();
932 void (*prev) ();
933 int poll_count = 0;
934 int res;
935 int tmp;
936 int rd;
937 int ea;
938 int bit;
939 int pc;
940 int c, nz, v, n;
941 int oldmask;
942 init_pointers ();
943
944 prev = signal (SIGINT, control_c);
945
946 if (step)
947 {
948 cpu.state = SIM_STATE_STOPPED;
949 cpu.exception = SIGTRAP;
950 }
951 else
952 {
953 cpu.state = SIM_STATE_RUNNING;
954 cpu.exception = 0;
955 }
956
957 pc = cpu.pc;
958
959 /* The PC should never be odd. */
960 if (pc & 0x1)
961 abort ();
962
963 GETSR ();
964 oldmask = cpu.mask;
965 if (!h8300hmode)
966 cpu.mask = 0xffff;
967 do
968 {
969 int cidx;
970 decoded_inst *code;
971
972 top:
973 cidx = cpu.cache_idx[pc];
974 code = cpu.cache + cidx;
975
976
977 #define ALUOP(STORE, NAME, HOW) \
978 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
979 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
980 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
981
982
983 #define LOGOP(NAME, HOW) \
984 case O(NAME,SB): HOW; goto log8;\
985 case O(NAME, SW): HOW; goto log16;\
986 case O(NAME,SL): HOW; goto log32;
987
988
989
990 #if ADEBUG
991 if (debug)
992 {
993 printf ("%x %d %s\n", pc, code->opcode,
994 code->op ? code->op->name : "**");
995 }
996 cpu.stats[code->opcode]++;
997
998 #endif
999
1000 cycles += code->cycles;
1001 insts++;
1002 switch (code->opcode)
1003 {
1004 case 0:
1005 /*
1006 * This opcode is a fake for when we get to an
1007 * instruction which hasnt been compiled
1008 */
1009 compile (pc);
1010 goto top;
1011 break;
1012
1013
1014 case O (O_SUBX, SB):
1015 rd = fetch (&code->dst);
1016 ea = fetch (&code->src);
1017 ea = -(ea + C);
1018 res = rd + ea;
1019 goto alu8;
1020
1021 case O (O_ADDX, SB):
1022 rd = fetch (&code->dst);
1023 ea = fetch (&code->src);
1024 ea = C + ea;
1025 res = rd + ea;
1026 goto alu8;
1027
1028 #define EA ea = fetch(&code->src);
1029 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1030
1031 ALUOP (1, O_SUB, RD_EA;
1032 ea = -ea;
1033 res = rd + ea);
1034 ALUOP (1, O_NEG, EA;
1035 ea = -ea;
1036 rd = 0;
1037 res = rd + ea);
1038
1039 case O (O_ADD, SB):
1040 rd = GET_B_REG (code->dst.reg);
1041 ea = fetch (&code->src);
1042 res = rd + ea;
1043 goto alu8;
1044 case O (O_ADD, SW):
1045 rd = GET_W_REG (code->dst.reg);
1046 ea = fetch (&code->src);
1047 res = rd + ea;
1048 goto alu16;
1049 case O (O_ADD, SL):
1050 rd = GET_L_REG (code->dst.reg);
1051 ea = fetch (&code->src);
1052 res = rd + ea;
1053 goto alu32;
1054
1055
1056 LOGOP (O_AND, RD_EA;
1057 res = rd & ea);
1058
1059 LOGOP (O_OR, RD_EA;
1060 res = rd | ea);
1061
1062 LOGOP (O_XOR, RD_EA;
1063 res = rd ^ ea);
1064
1065
1066 case O (O_MOV_TO_MEM, SB):
1067 res = GET_B_REG (code->src.reg);
1068 goto log8;
1069 case O (O_MOV_TO_MEM, SW):
1070 res = GET_W_REG (code->src.reg);
1071 goto log16;
1072 case O (O_MOV_TO_MEM, SL):
1073 res = GET_L_REG (code->src.reg);
1074 goto log32;
1075
1076
1077 case O (O_MOV_TO_REG, SB):
1078 res = fetch (&code->src);
1079 SET_B_REG (code->dst.reg, res);
1080 goto just_flags_log8;
1081 case O (O_MOV_TO_REG, SW):
1082 res = fetch (&code->src);
1083 SET_W_REG (code->dst.reg, res);
1084 goto just_flags_log16;
1085 case O (O_MOV_TO_REG, SL):
1086 res = fetch (&code->src);
1087 SET_L_REG (code->dst.reg, res);
1088 goto just_flags_log32;
1089
1090
1091 case O (O_ADDS, SL):
1092 SET_L_REG (code->dst.reg,
1093 GET_L_REG (code->dst.reg)
1094 + code->src.literal);
1095
1096 goto next;
1097
1098 case O (O_SUBS, SL):
1099 SET_L_REG (code->dst.reg,
1100 GET_L_REG (code->dst.reg)
1101 - code->src.literal);
1102 goto next;
1103
1104 case O (O_CMP, SB):
1105 rd = fetch (&code->dst);
1106 ea = fetch (&code->src);
1107 ea = -ea;
1108 res = rd + ea;
1109 goto just_flags_alu8;
1110
1111 case O (O_CMP, SW):
1112 rd = fetch (&code->dst);
1113 ea = fetch (&code->src);
1114 ea = -ea;
1115 res = rd + ea;
1116 goto just_flags_alu16;
1117
1118 case O (O_CMP, SL):
1119 rd = fetch (&code->dst);
1120 ea = fetch (&code->src);
1121 ea = -ea;
1122 res = rd + ea;
1123 goto just_flags_alu32;
1124
1125
1126 case O (O_DEC, SB):
1127 rd = GET_B_REG (code->src.reg);
1128 ea = -1;
1129 res = rd + ea;
1130 SET_B_REG (code->src.reg, res);
1131 goto just_flags_inc8;
1132
1133 case O (O_DEC, SW):
1134 rd = GET_W_REG (code->dst.reg);
1135 ea = -code->src.literal;
1136 res = rd + ea;
1137 SET_W_REG (code->dst.reg, res);
1138 goto just_flags_inc16;
1139
1140 case O (O_DEC, SL):
1141 rd = GET_L_REG (code->dst.reg);
1142 ea = -code->src.literal;
1143 res = rd + ea;
1144 SET_L_REG (code->dst.reg, res);
1145 goto just_flags_inc32;
1146
1147
1148 case O (O_INC, SB):
1149 rd = GET_B_REG (code->src.reg);
1150 ea = 1;
1151 res = rd + ea;
1152 SET_B_REG (code->src.reg, res);
1153 goto just_flags_inc8;
1154
1155 case O (O_INC, SW):
1156 rd = GET_W_REG (code->dst.reg);
1157 ea = code->src.literal;
1158 res = rd + ea;
1159 SET_W_REG (code->dst.reg, res);
1160 goto just_flags_inc16;
1161
1162 case O (O_INC, SL):
1163 rd = GET_L_REG (code->dst.reg);
1164 ea = code->src.literal;
1165 res = rd + ea;
1166 SET_L_REG (code->dst.reg, res);
1167 goto just_flags_inc32;
1168
1169
1170 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1171
1172 case O (O_ANDC, SB):
1173 GET_CCR (rd);
1174 ea = code->src.literal;
1175 res = rd & ea;
1176 goto setc;
1177
1178 case O (O_ORC, SB):
1179 GET_CCR (rd);
1180 ea = code->src.literal;
1181 res = rd | ea;
1182 goto setc;
1183
1184 case O (O_XORC, SB):
1185 GET_CCR (rd);
1186 ea = code->src.literal;
1187 res = rd ^ ea;
1188 goto setc;
1189
1190
1191 case O (O_BRA, SB):
1192 if (1)
1193 goto condtrue;
1194 goto next;
1195
1196 case O (O_BRN, SB):
1197 if (0)
1198 goto condtrue;
1199 goto next;
1200
1201 case O (O_BHI, SB):
1202 if ((C || Z) == 0)
1203 goto condtrue;
1204 goto next;
1205
1206
1207 case O (O_BLS, SB):
1208 if ((C || Z))
1209 goto condtrue;
1210 goto next;
1211
1212 case O (O_BCS, SB):
1213 if ((C == 1))
1214 goto condtrue;
1215 goto next;
1216
1217 case O (O_BCC, SB):
1218 if ((C == 0))
1219 goto condtrue;
1220 goto next;
1221
1222 case O (O_BEQ, SB):
1223 if (Z)
1224 goto condtrue;
1225 goto next;
1226 case O (O_BGT, SB):
1227 if (((Z || (N ^ V)) == 0))
1228 goto condtrue;
1229 goto next;
1230
1231
1232 case O (O_BLE, SB):
1233 if (((Z || (N ^ V)) == 1))
1234 goto condtrue;
1235 goto next;
1236
1237 case O (O_BGE, SB):
1238 if ((N ^ V) == 0)
1239 goto condtrue;
1240 goto next;
1241 case O (O_BLT, SB):
1242 if ((N ^ V))
1243 goto condtrue;
1244 goto next;
1245 case O (O_BMI, SB):
1246 if ((N))
1247 goto condtrue;
1248 goto next;
1249 case O (O_BNE, SB):
1250 if ((Z == 0))
1251 goto condtrue;
1252 goto next;
1253
1254 case O (O_BPL, SB):
1255 if (N == 0)
1256 goto condtrue;
1257 goto next;
1258 case O (O_BVC, SB):
1259 if ((V == 0))
1260 goto condtrue;
1261 goto next;
1262 case O (O_BVS, SB):
1263 if ((V == 1))
1264 goto condtrue;
1265 goto next;
1266
1267 case O (O_SYSCALL, SB):
1268 {
1269 char c = cpu.regs[2];
1270 sim_callback->write_stdout (sim_callback, &c, 1);
1271 }
1272 goto next;
1273
1274 ONOT (O_NOT, rd = ~rd; v = 0;);
1275 OSHIFTS (O_SHLL,
1276 c = rd & hm; v = 0; rd <<= 1,
1277 c = rd & (hm >> 1); v = 0; rd <<= 2);
1278 OSHIFTS (O_SHLR,
1279 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1280 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1281 OSHIFTS (O_SHAL,
1282 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1283 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1284 OSHIFTS (O_SHAR,
1285 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1286 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1287 OSHIFTS (O_ROTL,
1288 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1290 OSHIFTS (O_ROTR,
1291 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1293 OSHIFTS (O_ROTXL,
1294 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1296 OSHIFTS (O_ROTXR,
1297 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1299
1300 case O (O_JMP, SB):
1301 {
1302 pc = fetch (&code->src);
1303 goto end;
1304
1305 }
1306
1307 case O (O_JSR, SB):
1308 {
1309 int tmp;
1310 pc = fetch (&code->src);
1311 call:
1312 tmp = cpu.regs[7];
1313
1314 if (h8300hmode)
1315 {
1316 tmp -= 4;
1317 SET_MEMORY_L (tmp, code->next_pc);
1318 }
1319 else
1320 {
1321 tmp -= 2;
1322 SET_MEMORY_W (tmp, code->next_pc);
1323 }
1324 cpu.regs[7] = tmp;
1325
1326 goto end;
1327 }
1328 case O (O_BSR, SB):
1329 pc = code->src.literal;
1330 goto call;
1331
1332 case O (O_RTS, SN):
1333 {
1334 int tmp;
1335
1336 tmp = cpu.regs[7];
1337
1338 if (h8300hmode)
1339 {
1340 pc = GET_MEMORY_L (tmp);
1341 tmp += 4;
1342 }
1343 else
1344 {
1345 pc = GET_MEMORY_W (tmp);
1346 tmp += 2;
1347 }
1348
1349 cpu.regs[7] = tmp;
1350 goto end;
1351 }
1352
1353 case O (O_ILL, SB):
1354 cpu.state = SIM_STATE_STOPPED;
1355 cpu.exception = SIGILL;
1356 goto end;
1357 case O (O_SLEEP, SN):
1358 /* FIXME: Doesn't this break for breakpoints when r0
1359 contains just the right (er, wrong) value? */
1360 cpu.state = SIM_STATE_STOPPED;
1361 /* The format of r0 is defined by target newlib. Expand
1362 the macros here instead of looking for .../sys/wait.h. */
1363 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1364 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1365 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1366 cpu.exception = SIGILL;
1367 else
1368 cpu.exception = SIGTRAP;
1369 goto end;
1370 case O (O_BPT, SN):
1371 cpu.state = SIM_STATE_STOPPED;
1372 cpu.exception = SIGTRAP;
1373 goto end;
1374
1375 OBITOP (O_BNOT, 1, 1, ea ^= m);
1376 OBITOP (O_BTST, 1, 0, nz = ea & m);
1377 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1378 OBITOP (O_BSET, 1, 1, ea |= m);
1379 OBITOP (O_BLD, 1, 0, c = ea & m);
1380 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1381 OBITOP (O_BST, 1, 1, ea &= ~m;
1382 if (C) ea |= m);
1383 OBITOP (O_BIST, 1, 1, ea &= ~m;
1384 if (!C) ea |= m);
1385 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1386 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1387 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1388 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1389 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1390 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1391
1392 #define MOP(bsize, signed) \
1393 mop (code, bsize, signed); \
1394 goto next;
1395
1396 case O (O_MULS, SB):
1397 MOP (1, 1);
1398 break;
1399 case O (O_MULS, SW):
1400 MOP (0, 1);
1401 break;
1402 case O (O_MULU, SB):
1403 MOP (1, 0);
1404 break;
1405 case O (O_MULU, SW):
1406 MOP (0, 0);
1407 break;
1408
1409
1410 case O (O_DIVU, SB):
1411 {
1412 rd = GET_W_REG (code->dst.reg);
1413 ea = GET_B_REG (code->src.reg);
1414 if (ea)
1415 {
1416 tmp = (unsigned) rd % ea;
1417 rd = (unsigned) rd / ea;
1418 }
1419 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1420 n = ea & 0x80;
1421 nz = ea & 0xff;
1422
1423 goto next;
1424 }
1425 case O (O_DIVU, SW):
1426 {
1427 rd = GET_L_REG (code->dst.reg);
1428 ea = GET_W_REG (code->src.reg);
1429 n = ea & 0x8000;
1430 nz = ea & 0xffff;
1431 if (ea)
1432 {
1433 tmp = (unsigned) rd % ea;
1434 rd = (unsigned) rd / ea;
1435 }
1436 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1437 goto next;
1438 }
1439
1440 case O (O_DIVS, SB):
1441 {
1442
1443 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1444 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1445 if (ea)
1446 {
1447 tmp = (int) rd % (int) ea;
1448 rd = (int) rd / (int) ea;
1449 n = rd & 0x8000;
1450 nz = 1;
1451 }
1452 else
1453 nz = 0;
1454 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1455 goto next;
1456 }
1457 case O (O_DIVS, SW):
1458 {
1459 rd = GET_L_REG (code->dst.reg);
1460 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1461 if (ea)
1462 {
1463 tmp = (int) rd % (int) ea;
1464 rd = (int) rd / (int) ea;
1465 n = rd & 0x80000000;
1466 nz = 1;
1467 }
1468 else
1469 nz = 0;
1470 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1471 goto next;
1472 }
1473 case O (O_EXTS, SW):
1474 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1475 ea = rd & 0x80 ? -256 : 0;
1476 res = rd + ea;
1477 goto log16;
1478 case O (O_EXTS, SL):
1479 rd = GET_W_REG (code->src.reg) & 0xffff;
1480 ea = rd & 0x8000 ? -65536 : 0;
1481 res = rd + ea;
1482 goto log32;
1483 case O (O_EXTU, SW):
1484 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1485 ea = 0;
1486 res = rd + ea;
1487 goto log16;
1488 case O (O_EXTU, SL):
1489 rd = GET_W_REG (code->src.reg) & 0xffff;
1490 ea = 0;
1491 res = rd + ea;
1492 goto log32;
1493
1494 case O (O_NOP, SN):
1495 goto next;
1496
1497 case O (O_STM, SL):
1498 {
1499 int nregs, firstreg, i;
1500
1501 nregs = GET_MEMORY_B (pc + 1);
1502 nregs >>= 4;
1503 nregs &= 0xf;
1504 firstreg = GET_MEMORY_B (pc + 3);
1505 firstreg &= 0xf;
1506 for (i = firstreg; i <= firstreg + nregs; i++)
1507 {
1508 cpu.regs[7] -= 4;
1509 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1510 }
1511 }
1512 goto next;
1513
1514 case O (O_LDM, SL):
1515 {
1516 int nregs, firstreg, i;
1517
1518 nregs = GET_MEMORY_B (pc + 1);
1519 nregs >>= 4;
1520 nregs &= 0xf;
1521 firstreg = GET_MEMORY_B (pc + 3);
1522 firstreg &= 0xf;
1523 for (i = firstreg; i >= firstreg - nregs; i--)
1524 {
1525 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1526 cpu.regs[7] += 4;
1527 }
1528 }
1529 goto next;
1530
1531 default:
1532 cpu.state = SIM_STATE_STOPPED;
1533 cpu.exception = SIGILL;
1534 goto end;
1535
1536 }
1537 abort ();
1538
1539 setc:
1540 cpu.ccr = res;
1541 GETSR ();
1542 goto next;
1543
1544 condtrue:
1545 /* When a branch works */
1546 pc = code->src.literal;
1547 goto end;
1548
1549 /* Set the cond codes from res */
1550 bitop:
1551
1552 /* Set the flags after an 8 bit inc/dec operation */
1553 just_flags_inc8:
1554 n = res & 0x80;
1555 nz = res & 0xff;
1556 v = (rd & 0x7f) == 0x7f;
1557 goto next;
1558
1559
1560 /* Set the flags after an 16 bit inc/dec operation */
1561 just_flags_inc16:
1562 n = res & 0x8000;
1563 nz = res & 0xffff;
1564 v = (rd & 0x7fff) == 0x7fff;
1565 goto next;
1566
1567
1568 /* Set the flags after an 32 bit inc/dec operation */
1569 just_flags_inc32:
1570 n = res & 0x80000000;
1571 nz = res & 0xffffffff;
1572 v = (rd & 0x7fffffff) == 0x7fffffff;
1573 goto next;
1574
1575
1576 shift8:
1577 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1578 n = (rd & 0x80);
1579 nz = rd & 0xff;
1580 SET_B_REG (code->src.reg, rd);
1581 goto next;
1582
1583 shift16:
1584 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1585 n = (rd & 0x8000);
1586 nz = rd & 0xffff;
1587 SET_W_REG (code->src.reg, rd);
1588 goto next;
1589
1590 shift32:
1591 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1592 n = (rd & 0x80000000);
1593 nz = rd & 0xffffffff;
1594 SET_L_REG (code->src.reg, rd);
1595 goto next;
1596
1597 log32:
1598 store (&code->dst, res);
1599 just_flags_log32:
1600 /* flags after a 32bit logical operation */
1601 n = res & 0x80000000;
1602 nz = res & 0xffffffff;
1603 v = 0;
1604 goto next;
1605
1606 log16:
1607 store (&code->dst, res);
1608 just_flags_log16:
1609 /* flags after a 16bit logical operation */
1610 n = res & 0x8000;
1611 nz = res & 0xffff;
1612 v = 0;
1613 goto next;
1614
1615
1616 log8:
1617 store (&code->dst, res);
1618 just_flags_log8:
1619 n = res & 0x80;
1620 nz = res & 0xff;
1621 v = 0;
1622 goto next;
1623
1624 alu8:
1625 SET_B_REG (code->dst.reg, res);
1626 just_flags_alu8:
1627 n = res & 0x80;
1628 nz = res & 0xff;
1629 c = (res & 0x100);
1630 switch (code->opcode / 4)
1631 {
1632 case O_ADD:
1633 v = ((rd & 0x80) == (ea & 0x80)
1634 && (rd & 0x80) != (res & 0x80));
1635 break;
1636 case O_SUB:
1637 case O_CMP:
1638 v = ((rd & 0x80) != (-ea & 0x80)
1639 && (rd & 0x80) != (res & 0x80));
1640 break;
1641 case O_NEG:
1642 v = (rd == 0x80);
1643 break;
1644 }
1645 goto next;
1646
1647 alu16:
1648 SET_W_REG (code->dst.reg, res);
1649 just_flags_alu16:
1650 n = res & 0x8000;
1651 nz = res & 0xffff;
1652 c = (res & 0x10000);
1653 switch (code->opcode / 4)
1654 {
1655 case O_ADD:
1656 v = ((rd & 0x8000) == (ea & 0x8000)
1657 && (rd & 0x8000) != (res & 0x8000));
1658 break;
1659 case O_SUB:
1660 case O_CMP:
1661 v = ((rd & 0x8000) != (-ea & 0x8000)
1662 && (rd & 0x8000) != (res & 0x8000));
1663 break;
1664 case O_NEG:
1665 v = (rd == 0x8000);
1666 break;
1667 }
1668 goto next;
1669
1670 alu32:
1671 SET_L_REG (code->dst.reg, res);
1672 just_flags_alu32:
1673 n = res & 0x80000000;
1674 nz = res & 0xffffffff;
1675 switch (code->opcode / 4)
1676 {
1677 case O_ADD:
1678 v = ((rd & 0x80000000) == (ea & 0x80000000)
1679 && (rd & 0x80000000) != (res & 0x80000000));
1680 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1681 break;
1682 case O_SUB:
1683 case O_CMP:
1684 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1685 && (rd & 0x80000000) != (res & 0x80000000));
1686 c = (unsigned) rd < (unsigned) -ea;
1687 break;
1688 case O_NEG:
1689 v = (rd == 0x80000000);
1690 c = res != 0;
1691 break;
1692 }
1693 goto next;
1694
1695 next:;
1696 pc = code->next_pc;
1697
1698 end:
1699 ;
1700 #if 0
1701 if (cpu.regs[8])
1702 abort ();
1703 #endif
1704
1705 if (--poll_count < 0)
1706 {
1707 poll_count = POLL_QUIT_INTERVAL;
1708 if ((*sim_callback->poll_quit) != NULL
1709 && (*sim_callback->poll_quit) (sim_callback))
1710 sim_stop (sd);
1711 }
1712
1713 }
1714 while (cpu.state == SIM_STATE_RUNNING);
1715 cpu.ticks += get_now () - tick_start;
1716 cpu.cycles += cycles;
1717 cpu.insts += insts;
1718
1719 cpu.pc = pc;
1720 BUILDSR ();
1721 cpu.mask = oldmask;
1722 signal (SIGINT, prev);
1723 }
1724
1725 int
1726 sim_trace (sd)
1727 SIM_DESC sd;
1728 {
1729 /* FIXME: Unfinished. */
1730 abort ();
1731 }
1732
1733 int
1734 sim_write (sd, addr, buffer, size)
1735 SIM_DESC sd;
1736 SIM_ADDR addr;
1737 unsigned char *buffer;
1738 int size;
1739 {
1740 int i;
1741
1742 init_pointers ();
1743 if (addr < 0)
1744 return 0;
1745 for (i = 0; i < size; i++)
1746 {
1747 if (addr < memory_size)
1748 {
1749 cpu.memory[addr + i] = buffer[i];
1750 cpu.cache_idx[addr + i] = 0;
1751 }
1752 else
1753 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1754 }
1755 return size;
1756 }
1757
1758 int
1759 sim_read (sd, addr, buffer, size)
1760 SIM_DESC sd;
1761 SIM_ADDR addr;
1762 unsigned char *buffer;
1763 int size;
1764 {
1765 init_pointers ();
1766 if (addr < 0)
1767 return 0;
1768 if (addr < memory_size)
1769 memcpy (buffer, cpu.memory + addr, size);
1770 else
1771 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1772 return size;
1773 }
1774
1775
1776 #define R0_REGNUM 0
1777 #define R1_REGNUM 1
1778 #define R2_REGNUM 2
1779 #define R3_REGNUM 3
1780 #define R4_REGNUM 4
1781 #define R5_REGNUM 5
1782 #define R6_REGNUM 6
1783 #define R7_REGNUM 7
1784
1785 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1786 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1787 * stack frame */
1788
1789 #define CCR_REGNUM 8 /* Contains processor status */
1790 #define PC_REGNUM 9 /* Contains program counter */
1791
1792 #define CYCLE_REGNUM 10
1793 #define INST_REGNUM 11
1794 #define TICK_REGNUM 12
1795
1796
1797 int
1798 sim_store_register (sd, rn, value, length)
1799 SIM_DESC sd;
1800 int rn;
1801 unsigned char *value;
1802 int length;
1803 {
1804 int longval;
1805 int shortval;
1806 int intval;
1807 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1808 shortval = (value[0] << 8) | (value[1]);
1809 intval = h8300hmode ? longval : shortval;
1810
1811 init_pointers ();
1812 switch (rn)
1813 {
1814 case PC_REGNUM:
1815 cpu.pc = intval;
1816 break;
1817 default:
1818 abort ();
1819 case R0_REGNUM:
1820 case R1_REGNUM:
1821 case R2_REGNUM:
1822 case R3_REGNUM:
1823 case R4_REGNUM:
1824 case R5_REGNUM:
1825 case R6_REGNUM:
1826 case R7_REGNUM:
1827 cpu.regs[rn] = intval;
1828 break;
1829 case CCR_REGNUM:
1830 cpu.ccr = intval;
1831 break;
1832 case CYCLE_REGNUM:
1833 cpu.cycles = longval;
1834 break;
1835
1836 case INST_REGNUM:
1837 cpu.insts = longval;
1838 break;
1839
1840 case TICK_REGNUM:
1841 cpu.ticks = longval;
1842 break;
1843 }
1844 return -1;
1845 }
1846
1847 int
1848 sim_fetch_register (sd, rn, buf, length)
1849 SIM_DESC sd;
1850 int rn;
1851 unsigned char *buf;
1852 int length;
1853 {
1854 int v;
1855 int longreg = 0;
1856
1857 init_pointers ();
1858
1859 switch (rn)
1860 {
1861 default:
1862 abort ();
1863 case 8:
1864 v = cpu.ccr;
1865 break;
1866 case 9:
1867 v = cpu.pc;
1868 break;
1869 case R0_REGNUM:
1870 case R1_REGNUM:
1871 case R2_REGNUM:
1872 case R3_REGNUM:
1873 case R4_REGNUM:
1874 case R5_REGNUM:
1875 case R6_REGNUM:
1876 case R7_REGNUM:
1877 v = cpu.regs[rn];
1878 break;
1879 case 10:
1880 v = cpu.cycles;
1881 longreg = 1;
1882 break;
1883 case 11:
1884 v = cpu.ticks;
1885 longreg = 1;
1886 break;
1887 case 12:
1888 v = cpu.insts;
1889 longreg = 1;
1890 break;
1891 }
1892 if (h8300hmode || longreg)
1893 {
1894 buf[0] = v >> 24;
1895 buf[1] = v >> 16;
1896 buf[2] = v >> 8;
1897 buf[3] = v >> 0;
1898 }
1899 else
1900 {
1901 buf[0] = v >> 8;
1902 buf[1] = v;
1903 }
1904 return -1;
1905 }
1906
1907 void
1908 sim_stop_reason (sd, reason, sigrc)
1909 SIM_DESC sd;
1910 enum sim_stop *reason;
1911 int *sigrc;
1912 {
1913 #if 0 /* FIXME: This should work but we can't use it.
1914 grep for SLEEP above. */
1915 switch (cpu.state)
1916 {
1917 case SIM_STATE_EXITED : *reason = sim_exited; break;
1918 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1919 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1920 default : abort ();
1921 }
1922 #else
1923 *reason = sim_stopped;
1924 #endif
1925 *sigrc = cpu.exception;
1926 }
1927
1928 /* FIXME: Rename to sim_set_mem_size. */
1929
1930 void
1931 sim_size (n)
1932 int n;
1933 {
1934 /* Memory size is fixed. */
1935 }
1936
1937 void
1938 sim_set_simcache_size (n)
1939 {
1940 if (cpu.cache)
1941 free (cpu.cache);
1942 if (n < 2)
1943 n = 2;
1944 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1945 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1946 cpu.csize = n;
1947 }
1948
1949
1950 void
1951 sim_info (sd, verbose)
1952 SIM_DESC sd;
1953 int verbose;
1954 {
1955 double timetaken = (double) cpu.ticks / (double) now_persec ();
1956 double virttime = cpu.cycles / 10.0e6;
1957
1958 (*sim_callback->printf_filtered) (sim_callback,
1959 "\n\n#instructions executed %10d\n",
1960 cpu.insts);
1961 (*sim_callback->printf_filtered) (sim_callback,
1962 "#cycles (v approximate) %10d\n",
1963 cpu.cycles);
1964 (*sim_callback->printf_filtered) (sim_callback,
1965 "#real time taken %10.4f\n",
1966 timetaken);
1967 (*sim_callback->printf_filtered) (sim_callback,
1968 "#virtual time taked %10.4f\n",
1969 virttime);
1970 if (timetaken != 0.0)
1971 (*sim_callback->printf_filtered) (sim_callback,
1972 "#simulation ratio %10.4f\n",
1973 virttime / timetaken);
1974 (*sim_callback->printf_filtered) (sim_callback,
1975 "#compiles %10d\n",
1976 cpu.compiles);
1977 (*sim_callback->printf_filtered) (sim_callback,
1978 "#cache size %10d\n",
1979 cpu.csize);
1980
1981 #ifdef ADEBUG
1982 /* This to be conditional on `what' (aka `verbose'),
1983 however it was never passed as non-zero. */
1984 if (1)
1985 {
1986 int i;
1987 for (i = 0; i < O_LAST; i++)
1988 {
1989 if (cpu.stats[i])
1990 (*sim_callback->printf_filtered) (sim_callback,
1991 "%d: %d\n", i, cpu.stats[i]);
1992 }
1993 }
1994 #endif
1995 }
1996
1997 /* Indicate whether the cpu is an H8/300 or H8/300H.
1998 FLAG is non-zero for the H8/300H. */
1999
2000 void
2001 set_h8300h (flag)
2002 int flag;
2003 {
2004 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2005 This function being replaced by a sim_open:ARGV configuration
2006 option. */
2007 h8300hmode = flag;
2008 }
2009
2010 SIM_DESC
2011 sim_open (kind, ptr, abfd, argv)
2012 SIM_OPEN_KIND kind;
2013 struct host_callback_struct *ptr;
2014 struct _bfd *abfd;
2015 char **argv;
2016 {
2017 /* FIXME: Much of the code in sim_load can be moved here. */
2018
2019 sim_kind = kind;
2020 myname = argv[0];
2021 sim_callback = ptr;
2022 /* Fudge our descriptor. */
2023 return (SIM_DESC) 1;
2024 }
2025
2026 void
2027 sim_close (sd, quitting)
2028 SIM_DESC sd;
2029 int quitting;
2030 {
2031 /* Nothing to do. */
2032 }
2033
2034 /* Called by gdb to load a program into memory. */
2035
2036 SIM_RC
2037 sim_load (sd, prog, abfd, from_tty)
2038 SIM_DESC sd;
2039 char *prog;
2040 bfd *abfd;
2041 int from_tty;
2042 {
2043 bfd *prog_bfd;
2044
2045 /* FIXME: The code below that sets a specific variant of the H8/300
2046 being simulated should be moved to sim_open(). */
2047
2048 /* See if the file is for the H8/300 or H8/300H. */
2049 /* ??? This may not be the most efficient way. The z8k simulator
2050 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2051 if (abfd != NULL)
2052 prog_bfd = abfd;
2053 else
2054 prog_bfd = bfd_openr (prog, "coff-h8300");
2055 if (prog_bfd != NULL)
2056 {
2057 /* Set the cpu type. We ignore failure from bfd_check_format
2058 and bfd_openr as sim_load_file checks too. */
2059 if (bfd_check_format (prog_bfd, bfd_object))
2060 {
2061 unsigned long mach = bfd_get_mach (prog_bfd);
2062 set_h8300h (mach == bfd_mach_h8300h
2063 || mach == bfd_mach_h8300s);
2064 }
2065 }
2066
2067 /* If we're using gdb attached to the simulator, then we have to
2068 reallocate memory for the simulator.
2069
2070 When gdb first starts, it calls fetch_registers (among other
2071 functions), which in turn calls init_pointers, which allocates
2072 simulator memory.
2073
2074 The problem is when we do that, we don't know whether we're
2075 debugging an H8/300 or H8/300H program.
2076
2077 This is the first point at which we can make that determination,
2078 so we just reallocate memory now; this will also allow us to handle
2079 switching between H8/300 and H8/300H programs without exiting
2080 gdb. */
2081 if (h8300hmode)
2082 memory_size = H8300H_MSIZE;
2083 else
2084 memory_size = H8300_MSIZE;
2085
2086 if (cpu.memory)
2087 free (cpu.memory);
2088 if (cpu.cache_idx)
2089 free (cpu.cache_idx);
2090 if (cpu.eightbit)
2091 free (cpu.eightbit);
2092
2093 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2094 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2095 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2096
2097 /* `msize' must be a power of two. */
2098 if ((memory_size & (memory_size - 1)) != 0)
2099 abort ();
2100 cpu.mask = memory_size - 1;
2101
2102 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2103 sim_kind == SIM_OPEN_DEBUG,
2104 0, sim_write)
2105 == NULL)
2106 {
2107 /* Close the bfd if we opened it. */
2108 if (abfd == NULL && prog_bfd != NULL)
2109 bfd_close (prog_bfd);
2110 return SIM_RC_FAIL;
2111 }
2112
2113 /* Close the bfd if we opened it. */
2114 if (abfd == NULL && prog_bfd != NULL)
2115 bfd_close (prog_bfd);
2116 return SIM_RC_OK;
2117 }
2118
2119 SIM_RC
2120 sim_create_inferior (sd, abfd, argv, env)
2121 SIM_DESC sd;
2122 struct _bfd *abfd;
2123 char **argv;
2124 char **env;
2125 {
2126 if (abfd != NULL)
2127 cpu.pc = bfd_get_start_address (abfd);
2128 else
2129 cpu.pc = 0;
2130 return SIM_RC_OK;
2131 }
2132
2133 void
2134 sim_do_command (sd, cmd)
2135 SIM_DESC sd;
2136 char *cmd;
2137 {
2138 (*sim_callback->printf_filtered) (sim_callback,
2139 "This simulator does not accept any commands.\n");
2140 }
2141
2142 void
2143 sim_set_callbacks (ptr)
2144 struct host_callback_struct *ptr;
2145 {
2146 sim_callback = ptr;
2147 }
GDB Binutils - Deliverables
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