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* compile.c (sim_resume): Fix the handling of bxor.
[deliverable/binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Hitachi H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21
22 #include <stdio.h>
23 #include <signal.h>
24 #ifdef HAVE_TIME_H
25 #include <time.h>
26 #endif
27 #ifdef HAVE_STDLIB_H
28 #include <stdlib.h>
29 #endif
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
32 #endif
33 #include "ansidecl.h"
34 #include "bfd.h"
35 #include "gdb/callback.h"
36 #include "gdb/remote-sim.h"
37 #include "gdb/sim-h8300.h"
38
39 #ifndef SIGTRAP
40 # define SIGTRAP 5
41 #endif
42
43 int debug;
44
45 host_callback *sim_callback;
46
47 static SIM_OPEN_KIND sim_kind;
48 static char *myname;
49
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
53 by gdb. */
54 void sim_set_simcache_size PARAMS ((int));
55
56 #define X(op, size) op * 4 + size
57
58 #define SP (h8300hmode ? SL : SW)
59 #define SB 0
60 #define SW 1
61 #define SL 2
62 #define OP_REG 1
63 #define OP_DEC 2
64 #define OP_DISP 3
65 #define OP_INC 4
66 #define OP_PCREL 5
67 #define OP_MEM 6
68 #define OP_CCR 7
69 #define OP_IMM 8
70 #define OP_ABS 10
71 #define OP_EXR 11
72 #define h8_opcodes ops
73 #define DEFINE_TABLE
74 #include "opcode/h8300.h"
75
76 #include "inst.h"
77
78 /* The rate at which to call the host's poll_quit callback. */
79
80 #define POLL_QUIT_INTERVAL 0x80000
81
82 #define LOW_BYTE(x) ((x) & 0xff)
83 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
84 #define P(X,Y) ((X << 8) | Y)
85
86 #define BUILDSR() \
87 cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \
88 | (N << 3) | (Z << 2) | (V << 1) | C);
89
90 #define BUILDEXR() \
91 if (h8300smode) cpu.exr = (trace<<7) | intMask;
92
93 #define GETSR() \
94 c = (cpu.ccr >> 0) & 1;\
95 v = (cpu.ccr >> 1) & 1;\
96 nz = !((cpu.ccr >> 2) & 1);\
97 n = (cpu.ccr >> 3) & 1;\
98 u = (cpu.ccr >> 4) & 1;\
99 h = (cpu.ccr >> 5) & 1;\
100 ui = ((cpu.ccr >> 6) & 1);\
101 intMaskBit = (cpu.ccr >> 7) & 1;
102
103 #define GETEXR() \
104 if (h8300smode) \
105 { \
106 trace = (cpu.exr >> 7) & 1; \
107 intMask = cpu.exr & 7; \
108 }
109
110 #ifdef __CHAR_IS_SIGNED__
111 #define SEXTCHAR(x) ((char) (x))
112 #endif
113
114 #ifndef SEXTCHAR
115 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
116 #endif
117
118 #define UEXTCHAR(x) ((x) & 0xff)
119 #define UEXTSHORT(x) ((x) & 0xffff)
120 #define SEXTSHORT(x) ((short) (x))
121
122 static cpu_state_type cpu;
123
124 int h8300hmode = 0;
125 int h8300smode = 0;
126
127 static int memory_size;
128
129 static int
130 get_now (void)
131 {
132 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
133 }
134
135 static int
136 now_persec (void)
137 {
138 return 1;
139 }
140
141 static int
142 bitfrom (int x)
143 {
144 switch (x & SIZE)
145 {
146 case L_8:
147 return SB;
148 case L_16:
149 return SW;
150 case L_32:
151 return SL;
152 case L_P:
153 return h8300hmode ? SL : SW;
154 }
155 }
156
157 static unsigned int
158 lvalue (int x, int rn)
159 {
160 switch (x / 4)
161 {
162 case OP_DISP:
163 if (rn == 8)
164 {
165 return X (OP_IMM, SP);
166 }
167 return X (OP_REG, SP);
168
169 case OP_MEM:
170 return X (OP_MEM, SP);
171
172 default:
173 abort (); /* ?? May be something more usefull? */
174 }
175 }
176
177 static unsigned int
178 decode (int addr, unsigned char *data, decoded_inst *dst)
179 {
180 int rs = 0;
181 int rd = 0;
182 int rdisp = 0;
183 int abs = 0;
184 int bit = 0;
185 int plen = 0;
186 struct h8_opcode *q;
187 int size = 0;
188
189 dst->dst.type = -1;
190 dst->src.type = -1;
191
192 /* Find the exact opcode/arg combo. */
193 for (q = h8_opcodes; q->name; q++)
194 {
195 op_type *nib = q->data.nib;
196 unsigned int len = 0;
197
198 while (1)
199 {
200 op_type looking_for = *nib;
201 int thisnib = data[len >> 1];
202
203 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
204
205 if (looking_for < 16 && looking_for >= 0)
206 {
207 if (looking_for != thisnib)
208 goto fail;
209 }
210 else
211 {
212 if ((int) looking_for & (int) B31)
213 {
214 if (!(((int) thisnib & 0x8) != 0))
215 goto fail;
216
217 looking_for = (op_type) ((int) looking_for & ~(int) B31);
218 thisnib &= 0x7;
219 }
220
221 if ((int) looking_for & (int) B30)
222 {
223 if (!(((int) thisnib & 0x8) == 0))
224 goto fail;
225
226 looking_for = (op_type) ((int) looking_for & ~(int) B30);
227 }
228
229 if (looking_for & DBIT)
230 {
231 /* Exclude adds/subs by looking at bit 0 and 2, and
232 make sure the operand size, either w or l,
233 matches by looking at bit 1. */
234 if ((looking_for & 7) != (thisnib & 7))
235 goto fail;
236
237 abs = (thisnib & 0x8) ? 2 : 1;
238 }
239 else if (looking_for & (REG | IND | INC | DEC))
240 {
241 if (looking_for & REG)
242 {
243 /* Can work out size from the register. */
244 size = bitfrom (looking_for);
245 }
246 if (looking_for & SRC)
247 rs = thisnib;
248 else
249 rd = thisnib;
250 }
251 else if (looking_for & L_16)
252 {
253 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
254 plen = 16;
255 if (looking_for & (PCREL | DISP))
256 {
257 abs = (short) (abs);
258 }
259 }
260 else if (looking_for & ABSJMP)
261 {
262 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
263 }
264 else if (looking_for & MEMIND)
265 {
266 abs = data[1];
267 }
268 else if (looking_for & L_32)
269 {
270 int i = len >> 1;
271
272 abs = (data[i] << 24)
273 | (data[i + 1] << 16)
274 | (data[i + 2] << 8)
275 | (data[i + 3]);
276
277 plen = 32;
278 }
279 else if (looking_for & L_24)
280 {
281 int i = len >> 1;
282
283 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
284 plen = 24;
285 }
286 else if (looking_for & IGNORE)
287 {
288 ;
289 }
290 else if (looking_for & DISPREG)
291 {
292 rdisp = thisnib & 0x7;
293 }
294 else if (looking_for & KBIT)
295 {
296 switch (thisnib)
297 {
298 case 9:
299 abs = 4;
300 break;
301 case 8:
302 abs = 2;
303 break;
304 case 0:
305 abs = 1;
306 break;
307 default:
308 goto fail;
309 }
310 }
311 else if (looking_for & L_8)
312 {
313 plen = 8;
314
315 if (looking_for & PCREL)
316 {
317 abs = SEXTCHAR (data[len >> 1]);
318 }
319 else if (looking_for & ABS8MEM)
320 {
321 plen = 8;
322 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
323 abs |= data[len >> 1] & 0xff;
324 }
325 else
326 {
327 abs = data[len >> 1] & 0xff;
328 }
329 }
330 else if (looking_for & L_3)
331 {
332 plen = 3;
333
334 bit = thisnib;
335 }
336 else if (looking_for == E)
337 {
338 dst->op = q;
339
340 /* Fill in the args. */
341 {
342 op_type *args = q->args.nib;
343 int hadone = 0;
344
345 while (*args != E)
346 {
347 int x = *args;
348 int rn = (x & DST) ? rd : rs;
349 ea_type *p;
350
351 if (x & DST)
352 p = &(dst->dst);
353 else
354 p = &(dst->src);
355
356 if (x & L_3)
357 {
358 p->type = X (OP_IMM, size);
359 p->literal = bit;
360 }
361 else if (x & (IMM | KBIT | DBIT))
362 {
363 p->type = X (OP_IMM, size);
364 p->literal = abs;
365 }
366 else if (x & REG)
367 {
368 /* Reset the size.
369 Some ops (like mul) have two sizes. */
370
371 size = bitfrom (x);
372 p->type = X (OP_REG, size);
373 p->reg = rn;
374 }
375 else if (x & INC)
376 {
377 p->type = X (OP_INC, size);
378 p->reg = rn & 0x7;
379 }
380 else if (x & DEC)
381 {
382 p->type = X (OP_DEC, size);
383 p->reg = rn & 0x7;
384 }
385 else if (x & IND)
386 {
387 p->type = X (OP_DISP, size);
388 p->reg = rn & 0x7;
389 p->literal = 0;
390 }
391 else if (x & (ABS | ABSJMP | ABS8MEM))
392 {
393 p->type = X (OP_DISP, size);
394 p->literal = abs;
395 p->reg = 8;
396 }
397 else if (x & MEMIND)
398 {
399 p->type = X (OP_MEM, size);
400 p->literal = abs;
401 }
402 else if (x & PCREL)
403 {
404 p->type = X (OP_PCREL, size);
405 p->literal = abs + addr + 2;
406 if (x & L_16)
407 p->literal += 2;
408 }
409 else if (x & ABSJMP)
410 {
411 p->type = X (OP_IMM, SP);
412 p->literal = abs;
413 }
414 else if (x & DISP)
415 {
416 p->type = X (OP_DISP, size);
417 p->literal = abs;
418 p->reg = rdisp & 0x7;
419 }
420 else if (x & CCR)
421 {
422 p->type = OP_CCR;
423 }
424 else if (x & EXR)
425 {
426 p->type = OP_EXR;
427 }
428 else
429 printf ("Hmmmm %x", x);
430
431 args++;
432 }
433 }
434
435 /* But a jmp or a jsr gets automagically lvalued,
436 since we branch to their address not their
437 contents. */
438 if (q->how == O (O_JSR, SB)
439 || q->how == O (O_JMP, SB))
440 {
441 dst->src.type = lvalue (dst->src.type, dst->src.reg);
442 }
443
444 if (dst->dst.type == -1)
445 dst->dst = dst->src;
446
447 dst->opcode = q->how;
448 dst->cycles = q->time;
449
450 /* And a jsr to 0xc4 is turned into a magic trap. */
451
452 if (dst->opcode == O (O_JSR, SB))
453 {
454 if (dst->src.literal == 0xc4)
455 {
456 dst->opcode = O (O_SYSCALL, SB);
457 }
458 }
459
460 dst->next_pc = addr + len / 2;
461 return;
462 }
463 else
464 printf ("Don't understand %x \n", looking_for);
465 }
466
467 len++;
468 nib++;
469 }
470
471 fail:
472 ;
473 }
474
475 /* Fell off the end. */
476 dst->opcode = O (O_ILL, SB);
477 }
478
479 static void
480 compile (int pc)
481 {
482 int idx;
483
484 /* Find the next cache entry to use. */
485 idx = cpu.cache_top + 1;
486 cpu.compiles++;
487 if (idx >= cpu.csize)
488 {
489 idx = 1;
490 }
491 cpu.cache_top = idx;
492
493 /* Throw away its old meaning. */
494 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
495
496 /* Set to new address. */
497 cpu.cache[idx].oldpc = pc;
498
499 /* Fill in instruction info. */
500 decode (pc, cpu.memory + pc, cpu.cache + idx);
501
502 /* Point to new cache entry. */
503 cpu.cache_idx[pc] = idx;
504 }
505
506
507 static unsigned char *breg[18];
508 static unsigned short *wreg[18];
509 static unsigned int *lreg[18];
510
511 #define GET_B_REG(x) *(breg[x])
512 #define SET_B_REG(x,y) (*(breg[x])) = (y)
513 #define GET_W_REG(x) *(wreg[x])
514 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
515
516 #define GET_L_REG(x) *(lreg[x])
517 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
518
519 #define GET_MEMORY_L(x) \
520 (x < memory_size \
521 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
522 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
523 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
524 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
525
526 #define GET_MEMORY_W(x) \
527 (x < memory_size \
528 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
529 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
530
531
532 #define GET_MEMORY_B(x) \
533 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
534
535 #define SET_MEMORY_L(x,y) \
536 { register unsigned char *_p; register int __y = y; \
537 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
538 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
539 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
540
541 #define SET_MEMORY_W(x,y) \
542 { register unsigned char *_p; register int __y = y; \
543 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
544 _p[0] = (__y)>>8; _p[1] =(__y);}
545
546 #define SET_MEMORY_B(x,y) \
547 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
548
549 static int
550 fetch (ea_type *arg)
551 {
552 int rn = arg->reg;
553 int abs = arg->literal;
554 int r;
555 int t;
556
557 switch (arg->type)
558 {
559 case X (OP_REG, SB):
560 return GET_B_REG (rn);
561 case X (OP_REG, SW):
562 return GET_W_REG (rn);
563 case X (OP_REG, SL):
564 return GET_L_REG (rn);
565 case X (OP_IMM, SB):
566 case X (OP_IMM, SW):
567 case X (OP_IMM, SL):
568 return abs;
569 case X (OP_DEC, SB):
570 abort ();
571
572 case X (OP_INC, SB):
573 t = GET_L_REG (rn);
574 t &= cpu.mask;
575 r = GET_MEMORY_B (t);
576 t++;
577 t = t & cpu.mask;
578 SET_L_REG (rn, t);
579 return r;
580 break;
581 case X (OP_INC, SW):
582 t = GET_L_REG (rn);
583 t &= cpu.mask;
584 r = GET_MEMORY_W (t);
585 t += 2;
586 t = t & cpu.mask;
587 SET_L_REG (rn, t);
588 return r;
589 case X (OP_INC, SL):
590 t = GET_L_REG (rn);
591 t &= cpu.mask;
592 r = GET_MEMORY_L (t);
593
594 t += 4;
595 t = t & cpu.mask;
596 SET_L_REG (rn, t);
597 return r;
598
599 case X (OP_DISP, SB):
600 t = GET_L_REG (rn) + abs;
601 t &= cpu.mask;
602 return GET_MEMORY_B (t);
603
604 case X (OP_DISP, SW):
605 t = GET_L_REG (rn) + abs;
606 t &= cpu.mask;
607 return GET_MEMORY_W (t);
608
609 case X (OP_DISP, SL):
610 t = GET_L_REG (rn) + abs;
611 t &= cpu.mask;
612 return GET_MEMORY_L (t);
613
614 case X (OP_MEM, SL):
615 t = GET_MEMORY_L (abs);
616 t &= cpu.mask;
617 return t;
618
619 case X (OP_MEM, SW):
620 t = GET_MEMORY_W (abs);
621 t &= cpu.mask;
622 return t;
623
624 default:
625 abort (); /* ?? May be something more usefull? */
626
627 }
628 }
629
630
631 static void
632 store (ea_type *arg, int n)
633 {
634 int rn = arg->reg;
635 int abs = arg->literal;
636 int t;
637
638 switch (arg->type)
639 {
640 case X (OP_REG, SB):
641 SET_B_REG (rn, n);
642 break;
643 case X (OP_REG, SW):
644 SET_W_REG (rn, n);
645 break;
646 case X (OP_REG, SL):
647 SET_L_REG (rn, n);
648 break;
649
650 case X (OP_DEC, SB):
651 t = GET_L_REG (rn) - 1;
652 t &= cpu.mask;
653 SET_L_REG (rn, t);
654 SET_MEMORY_B (t, n);
655
656 break;
657 case X (OP_DEC, SW):
658 t = (GET_L_REG (rn) - 2) & cpu.mask;
659 SET_L_REG (rn, t);
660 SET_MEMORY_W (t, n);
661 break;
662
663 case X (OP_DEC, SL):
664 t = (GET_L_REG (rn) - 4) & cpu.mask;
665 SET_L_REG (rn, t);
666 SET_MEMORY_L (t, n);
667 break;
668
669 case X (OP_DISP, SB):
670 t = GET_L_REG (rn) + abs;
671 t &= cpu.mask;
672 SET_MEMORY_B (t, n);
673 break;
674
675 case X (OP_DISP, SW):
676 t = GET_L_REG (rn) + abs;
677 t &= cpu.mask;
678 SET_MEMORY_W (t, n);
679 break;
680
681 case X (OP_DISP, SL):
682 t = GET_L_REG (rn) + abs;
683 t &= cpu.mask;
684 SET_MEMORY_L (t, n);
685 break;
686 default:
687 abort ();
688 }
689 }
690
691
692 static union
693 {
694 short int i;
695 struct
696 {
697 char low;
698 char high;
699 }
700 u;
701 }
702
703 littleendian;
704
705 static void
706 init_pointers (void)
707 {
708 static int init;
709
710 if (!init)
711 {
712 int i;
713
714 init = 1;
715 littleendian.i = 1;
716
717 if (h8300smode)
718 memory_size = H8300S_MSIZE;
719 else if (h8300hmode)
720 memory_size = H8300H_MSIZE;
721 else
722 memory_size = H8300_MSIZE;
723 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
724 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
725 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
726
727 /* `msize' must be a power of two. */
728 if ((memory_size & (memory_size - 1)) != 0)
729 abort ();
730 cpu.mask = memory_size - 1;
731
732 for (i = 0; i < 9; i++)
733 {
734 cpu.regs[i] = 0;
735 }
736
737 for (i = 0; i < 8; i++)
738 {
739 unsigned char *p = (unsigned char *) (cpu.regs + i);
740 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
741 unsigned short *q = (unsigned short *) (cpu.regs + i);
742 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
743 cpu.regs[i] = 0x00112233;
744 while (p < e)
745 {
746 if (*p == 0x22)
747 {
748 breg[i] = p;
749 }
750 if (*p == 0x33)
751 {
752 breg[i + 8] = p;
753 }
754 p++;
755 }
756 while (q < u)
757 {
758 if (*q == 0x2233)
759 {
760 wreg[i] = q;
761 }
762 if (*q == 0x0011)
763 {
764 wreg[i + 8] = q;
765 }
766 q++;
767 }
768 cpu.regs[i] = 0;
769 lreg[i] = &cpu.regs[i];
770 }
771
772 lreg[8] = &cpu.regs[8];
773
774 /* Initialize the seg registers. */
775 if (!cpu.cache)
776 sim_set_simcache_size (CSIZE);
777 }
778 }
779
780 static void
781 control_c (int sig)
782 {
783 cpu.state = SIM_STATE_STOPPED;
784 cpu.exception = SIGINT;
785 }
786
787 #define C (c != 0)
788 #define Z (nz == 0)
789 #define V (v != 0)
790 #define N (n != 0)
791 #define U (u != 0)
792 #define H (h != 0)
793 #define UI (ui != 0)
794 #define I (intMaskBit != 0)
795
796 static int
797 mop (decoded_inst *code, int bsize, int sign)
798 {
799 int multiplier;
800 int multiplicand;
801 int result;
802 int n, nz;
803
804 if (sign)
805 {
806 multiplicand =
807 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
808 SEXTSHORT (GET_W_REG (code->dst.reg));
809 multiplier =
810 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
811 SEXTSHORT (GET_W_REG (code->src.reg));
812 }
813 else
814 {
815 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
816 UEXTSHORT (GET_W_REG (code->dst.reg));
817 multiplier =
818 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
819 UEXTSHORT (GET_W_REG (code->src.reg));
820
821 }
822 result = multiplier * multiplicand;
823
824 if (sign)
825 {
826 n = result & (bsize ? 0x8000 : 0x80000000);
827 nz = result & (bsize ? 0xffff : 0xffffffff);
828 }
829 if (bsize)
830 {
831 SET_W_REG (code->dst.reg, result);
832 }
833 else
834 {
835 SET_L_REG (code->dst.reg, result);
836 }
837 #if 0
838 return ((n == 1) << 1) | (nz == 1);
839 #endif
840 }
841
842 #define ONOT(name, how) \
843 case O (name, SB): \
844 { \
845 int t; \
846 int hm = 0x80; \
847 rd = GET_B_REG (code->src.reg); \
848 how; \
849 goto shift8; \
850 } \
851 case O (name, SW): \
852 { \
853 int t; \
854 int hm = 0x8000; \
855 rd = GET_W_REG (code->src.reg); \
856 how; \
857 goto shift16; \
858 } \
859 case O (name, SL): \
860 { \
861 int t; \
862 int hm = 0x80000000; \
863 rd = GET_L_REG (code->src.reg); \
864 how; \
865 goto shift32; \
866 }
867
868 #define OSHIFTS(name, how1, how2) \
869 case O (name, SB): \
870 { \
871 int t; \
872 int hm = 0x80; \
873 rd = GET_B_REG (code->src.reg); \
874 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
875 { \
876 how1; \
877 } \
878 else \
879 { \
880 how2; \
881 } \
882 goto shift8; \
883 } \
884 case O (name, SW): \
885 { \
886 int t; \
887 int hm = 0x8000; \
888 rd = GET_W_REG (code->src.reg); \
889 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
890 { \
891 how1; \
892 } \
893 else \
894 { \
895 how2; \
896 } \
897 goto shift16; \
898 } \
899 case O (name, SL): \
900 { \
901 int t; \
902 int hm = 0x80000000; \
903 rd = GET_L_REG (code->src.reg); \
904 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
905 { \
906 how1; \
907 } \
908 else \
909 { \
910 how2; \
911 } \
912 goto shift32; \
913 }
914
915 #define OBITOP(name,f, s, op) \
916 case O (name, SB): \
917 { \
918 int m; \
919 int b; \
920 if (f) ea = fetch (&code->dst); \
921 m=1<< fetch (&code->src); \
922 op; \
923 if (s) store (&code->dst,ea); goto next; \
924 }
925
926 int
927 sim_stop (SIM_DESC sd)
928 {
929 cpu.state = SIM_STATE_STOPPED;
930 cpu.exception = SIGINT;
931 return 1;
932 }
933
934 #define R0_REGNUM 0
935 #define R1_REGNUM 1
936 #define R2_REGNUM 2
937 #define R3_REGNUM 3
938 #define R4_REGNUM 4
939 #define R5_REGNUM 5
940 #define R6_REGNUM 6
941 #define R7_REGNUM 7
942
943 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
944 #define FP_REGNUM R6_REGNUM /* Contains address of executing
945 * stack frame */
946
947 #define CCR_REGNUM 8 /* Contains processor status */
948 #define PC_REGNUM 9 /* Contains program counter */
949
950 #define CYCLE_REGNUM 10
951
952 #define EXR_REGNUM 11
953 #define INST_REGNUM 12
954 #define TICK_REGNUM 13
955
956 void
957 sim_resume (SIM_DESC sd, int step, int siggnal)
958 {
959 static int init1;
960 int cycles = 0;
961 int insts = 0;
962 int tick_start = get_now ();
963 void (*prev) ();
964 int poll_count = 0;
965 int res;
966 int tmp;
967 int rd;
968 int ea;
969 int bit;
970 int pc;
971 int c, nz, v, n, u, h, ui, intMaskBit;
972 int trace, intMask;
973 int oldmask;
974 init_pointers ();
975
976 prev = signal (SIGINT, control_c);
977
978 if (step)
979 {
980 cpu.state = SIM_STATE_STOPPED;
981 cpu.exception = SIGTRAP;
982 }
983 else
984 {
985 cpu.state = SIM_STATE_RUNNING;
986 cpu.exception = 0;
987 }
988
989 pc = cpu.pc;
990
991 /* The PC should never be odd. */
992 if (pc & 0x1)
993 abort ();
994
995 GETSR ();
996 GETEXR ();
997
998 oldmask = cpu.mask;
999 if (!h8300hmode)
1000 cpu.mask = 0xffff;
1001 do
1002 {
1003 int cidx;
1004 decoded_inst *code;
1005
1006 top:
1007 cidx = cpu.cache_idx[pc];
1008 code = cpu.cache + cidx;
1009
1010
1011 #define ALUOP(STORE, NAME, HOW) \
1012 case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \
1013 case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \
1014 case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32;
1015
1016
1017 #define LOGOP(NAME, HOW) \
1018 case O (NAME, SB): HOW; goto log8; \
1019 case O (NAME, SW): HOW; goto log16; \
1020 case O (NAME, SL): HOW; goto log32;
1021
1022
1023
1024 #if ADEBUG
1025 if (debug)
1026 {
1027 printf ("%x %d %s\n", pc, code->opcode,
1028 code->op ? code->op->name : "**");
1029 }
1030 cpu.stats[code->opcode]++;
1031
1032 #endif
1033
1034 if (code->opcode)
1035 {
1036 cycles += code->cycles;
1037 insts++;
1038 }
1039
1040 switch (code->opcode)
1041 {
1042 case 0:
1043 /*
1044 * This opcode is a fake for when we get to an
1045 * instruction which hasnt been compiled
1046 */
1047 compile (pc);
1048 goto top;
1049 break;
1050
1051
1052 case O (O_SUBX, SB):
1053 rd = fetch (&code->dst);
1054 ea = fetch (&code->src);
1055 ea = -(ea + C);
1056 res = rd + ea;
1057 goto alu8;
1058
1059 case O (O_ADDX, SB):
1060 rd = fetch (&code->dst);
1061 ea = fetch (&code->src);
1062 ea = C + ea;
1063 res = rd + ea;
1064 goto alu8;
1065
1066 #define EA ea = fetch (&code->src);
1067 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1068
1069 ALUOP (1, O_SUB, RD_EA;
1070 ea = -ea;
1071 res = rd + ea);
1072 ALUOP (1, O_NEG, EA;
1073 ea = -ea;
1074 rd = 0;
1075 res = rd + ea);
1076
1077 case O (O_ADD, SB):
1078 rd = GET_B_REG (code->dst.reg);
1079 ea = fetch (&code->src);
1080 res = rd + ea;
1081 goto alu8;
1082 case O (O_ADD, SW):
1083 rd = GET_W_REG (code->dst.reg);
1084 ea = fetch (&code->src);
1085 res = rd + ea;
1086 goto alu16;
1087 case O (O_ADD, SL):
1088 rd = GET_L_REG (code->dst.reg);
1089 ea = fetch (&code->src);
1090 res = rd + ea;
1091 goto alu32;
1092
1093
1094 LOGOP (O_AND, RD_EA;
1095 res = rd & ea);
1096
1097 LOGOP (O_OR, RD_EA;
1098 res = rd | ea);
1099
1100 LOGOP (O_XOR, RD_EA;
1101 res = rd ^ ea);
1102
1103
1104 case O (O_MOV_TO_MEM, SB):
1105 res = GET_B_REG (code->src.reg);
1106 goto log8;
1107 case O (O_MOV_TO_MEM, SW):
1108 res = GET_W_REG (code->src.reg);
1109 goto log16;
1110 case O (O_MOV_TO_MEM, SL):
1111 res = GET_L_REG (code->src.reg);
1112 goto log32;
1113
1114
1115 case O (O_MOV_TO_REG, SB):
1116 res = fetch (&code->src);
1117 SET_B_REG (code->dst.reg, res);
1118 goto just_flags_log8;
1119 case O (O_MOV_TO_REG, SW):
1120 res = fetch (&code->src);
1121 SET_W_REG (code->dst.reg, res);
1122 goto just_flags_log16;
1123 case O (O_MOV_TO_REG, SL):
1124 res = fetch (&code->src);
1125 SET_L_REG (code->dst.reg, res);
1126 goto just_flags_log32;
1127
1128 case O (O_EEPMOV, SB):
1129 case O (O_EEPMOV, SW):
1130 if (h8300hmode || h8300smode)
1131 {
1132 register unsigned char *_src, *_dst;
1133 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
1134 ? cpu.regs[R4_REGNUM] & 0xffff
1135 : cpu.regs[R4_REGNUM] & 0xff);
1136
1137 _src = (cpu.regs[R5_REGNUM] < memory_size
1138 ? cpu.memory + cpu.regs[R5_REGNUM]
1139 : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff));
1140 if ((_src + count) >= (cpu.memory + memory_size))
1141 {
1142 if ((_src + count) >= (cpu.eightbit + 0x100))
1143 goto illegal;
1144 }
1145 _dst = (cpu.regs[R6_REGNUM] < memory_size
1146 ? cpu.memory + cpu.regs[R6_REGNUM]
1147 : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff));
1148 if ((_dst + count) >= (cpu.memory + memory_size))
1149 {
1150 if ((_dst + count) >= (cpu.eightbit + 0x100))
1151 goto illegal;
1152 }
1153 memcpy (_dst, _src, count);
1154
1155 cpu.regs[R5_REGNUM] += count;
1156 cpu.regs[R6_REGNUM] += count;
1157 cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW))
1158 ? (~0xffff) : (~0xff));
1159 cycles += 2 * count;
1160 goto next;
1161 }
1162 goto illegal;
1163
1164 case O (O_ADDS, SL):
1165 SET_L_REG (code->dst.reg,
1166 GET_L_REG (code->dst.reg)
1167 + code->src.literal);
1168
1169 goto next;
1170
1171 case O (O_SUBS, SL):
1172 SET_L_REG (code->dst.reg,
1173 GET_L_REG (code->dst.reg)
1174 - code->src.literal);
1175 goto next;
1176
1177 case O (O_CMP, SB):
1178 rd = fetch (&code->dst);
1179 ea = fetch (&code->src);
1180 ea = -ea;
1181 res = rd + ea;
1182 goto just_flags_alu8;
1183
1184 case O (O_CMP, SW):
1185 rd = fetch (&code->dst);
1186 ea = fetch (&code->src);
1187 ea = -ea;
1188 res = rd + ea;
1189 goto just_flags_alu16;
1190
1191 case O (O_CMP, SL):
1192 rd = fetch (&code->dst);
1193 ea = fetch (&code->src);
1194 ea = -ea;
1195 res = rd + ea;
1196 goto just_flags_alu32;
1197
1198
1199 case O (O_DEC, SB):
1200 rd = GET_B_REG (code->src.reg);
1201 ea = -1;
1202 res = rd + ea;
1203 SET_B_REG (code->src.reg, res);
1204 goto just_flags_inc8;
1205
1206 case O (O_DEC, SW):
1207 rd = GET_W_REG (code->dst.reg);
1208 ea = -code->src.literal;
1209 res = rd + ea;
1210 SET_W_REG (code->dst.reg, res);
1211 goto just_flags_inc16;
1212
1213 case O (O_DEC, SL):
1214 rd = GET_L_REG (code->dst.reg);
1215 ea = -code->src.literal;
1216 res = rd + ea;
1217 SET_L_REG (code->dst.reg, res);
1218 goto just_flags_inc32;
1219
1220
1221 case O (O_INC, SB):
1222 rd = GET_B_REG (code->src.reg);
1223 ea = 1;
1224 res = rd + ea;
1225 SET_B_REG (code->src.reg, res);
1226 goto just_flags_inc8;
1227
1228 case O (O_INC, SW):
1229 rd = GET_W_REG (code->dst.reg);
1230 ea = code->src.literal;
1231 res = rd + ea;
1232 SET_W_REG (code->dst.reg, res);
1233 goto just_flags_inc16;
1234
1235 case O (O_INC, SL):
1236 rd = GET_L_REG (code->dst.reg);
1237 ea = code->src.literal;
1238 res = rd + ea;
1239 SET_L_REG (code->dst.reg, res);
1240 goto just_flags_inc32;
1241
1242 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1243 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1244
1245 case O (O_LDC, SB):
1246 case O (O_LDC, SW):
1247 res = fetch (&code->src);
1248 goto setc;
1249 case O (O_STC, SB):
1250 case O (O_STC, SW):
1251 if (code->src.type == OP_CCR)
1252 {
1253 GET_CCR (res);
1254 }
1255 else if (code->src.type == OP_EXR && h8300smode)
1256 {
1257 GET_EXR (res);
1258 }
1259 else
1260 goto illegal;
1261 store (&code->dst, res);
1262 goto next;
1263
1264 case O (O_ANDC, SB):
1265 if (code->dst.type == OP_CCR)
1266 {
1267 GET_CCR (rd);
1268 }
1269 else if (code->dst.type == OP_EXR && h8300smode)
1270 {
1271 GET_EXR (rd);
1272 }
1273 else
1274 goto illegal;
1275 ea = code->src.literal;
1276 res = rd & ea;
1277 goto setc;
1278
1279 case O (O_ORC, SB):
1280 if (code->dst.type == OP_CCR)
1281 {
1282 GET_CCR (rd);
1283 }
1284 else if (code->dst.type == OP_EXR && h8300smode)
1285 {
1286 GET_EXR (rd);
1287 }
1288 else
1289 goto illegal;
1290 ea = code->src.literal;
1291 res = rd | ea;
1292 goto setc;
1293
1294 case O (O_XORC, SB):
1295 if (code->dst.type == OP_CCR)
1296 {
1297 GET_CCR (rd);
1298 }
1299 else if (code->dst.type == OP_EXR && h8300smode)
1300 {
1301 GET_EXR (rd);
1302 }
1303 else
1304 goto illegal;
1305 ea = code->src.literal;
1306 res = rd ^ ea;
1307 goto setc;
1308
1309
1310 case O (O_BRA, SB):
1311 if (1)
1312 goto condtrue;
1313 goto next;
1314
1315 case O (O_BRN, SB):
1316 if (0)
1317 goto condtrue;
1318 goto next;
1319
1320 case O (O_BHI, SB):
1321 if ((C || Z) == 0)
1322 goto condtrue;
1323 goto next;
1324
1325
1326 case O (O_BLS, SB):
1327 if ((C || Z))
1328 goto condtrue;
1329 goto next;
1330
1331 case O (O_BCS, SB):
1332 if ((C == 1))
1333 goto condtrue;
1334 goto next;
1335
1336 case O (O_BCC, SB):
1337 if ((C == 0))
1338 goto condtrue;
1339 goto next;
1340
1341 case O (O_BEQ, SB):
1342 if (Z)
1343 goto condtrue;
1344 goto next;
1345 case O (O_BGT, SB):
1346 if (((Z || (N ^ V)) == 0))
1347 goto condtrue;
1348 goto next;
1349
1350
1351 case O (O_BLE, SB):
1352 if (((Z || (N ^ V)) == 1))
1353 goto condtrue;
1354 goto next;
1355
1356 case O (O_BGE, SB):
1357 if ((N ^ V) == 0)
1358 goto condtrue;
1359 goto next;
1360 case O (O_BLT, SB):
1361 if ((N ^ V))
1362 goto condtrue;
1363 goto next;
1364 case O (O_BMI, SB):
1365 if ((N))
1366 goto condtrue;
1367 goto next;
1368 case O (O_BNE, SB):
1369 if ((Z == 0))
1370 goto condtrue;
1371 goto next;
1372
1373 case O (O_BPL, SB):
1374 if (N == 0)
1375 goto condtrue;
1376 goto next;
1377 case O (O_BVC, SB):
1378 if ((V == 0))
1379 goto condtrue;
1380 goto next;
1381 case O (O_BVS, SB):
1382 if ((V == 1))
1383 goto condtrue;
1384 goto next;
1385
1386 case O (O_SYSCALL, SB):
1387 {
1388 char c = cpu.regs[2];
1389 sim_callback->write_stdout (sim_callback, &c, 1);
1390 }
1391 goto next;
1392
1393 ONOT (O_NOT, rd = ~rd; v = 0;);
1394 OSHIFTS (O_SHLL,
1395 c = rd & hm; v = 0; rd <<= 1,
1396 c = rd & (hm >> 1); v = 0; rd <<= 2);
1397 OSHIFTS (O_SHLR,
1398 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1399 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1400 OSHIFTS (O_SHAL,
1401 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1402 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1403 OSHIFTS (O_SHAR,
1404 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1405 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1);
1406 OSHIFTS (O_ROTL,
1407 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1408 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1409 OSHIFTS (O_ROTR,
1410 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1411 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1412 OSHIFTS (O_ROTXL,
1413 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1414 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1415 OSHIFTS (O_ROTXR,
1416 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1417 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1418
1419 case O (O_JMP, SB):
1420 {
1421 pc = fetch (&code->src);
1422 goto end;
1423
1424 }
1425
1426 case O (O_JSR, SB):
1427 {
1428 int tmp;
1429 pc = fetch (&code->src);
1430 call:
1431 tmp = cpu.regs[7];
1432
1433 if (h8300hmode)
1434 {
1435 tmp -= 4;
1436 SET_MEMORY_L (tmp, code->next_pc);
1437 }
1438 else
1439 {
1440 tmp -= 2;
1441 SET_MEMORY_W (tmp, code->next_pc);
1442 }
1443 cpu.regs[7] = tmp;
1444
1445 goto end;
1446 }
1447 case O (O_BSR, SB):
1448 pc = code->src.literal;
1449 goto call;
1450
1451 case O (O_RTS, SN):
1452 {
1453 int tmp;
1454
1455 tmp = cpu.regs[7];
1456
1457 if (h8300hmode)
1458 {
1459 pc = GET_MEMORY_L (tmp);
1460 tmp += 4;
1461 }
1462 else
1463 {
1464 pc = GET_MEMORY_W (tmp);
1465 tmp += 2;
1466 }
1467
1468 cpu.regs[7] = tmp;
1469 goto end;
1470 }
1471
1472 case O (O_ILL, SB):
1473 cpu.state = SIM_STATE_STOPPED;
1474 cpu.exception = SIGILL;
1475 goto end;
1476 case O (O_SLEEP, SN):
1477 /* FIXME: Doesn't this break for breakpoints when r0
1478 contains just the right (er, wrong) value? */
1479 cpu.state = SIM_STATE_STOPPED;
1480 /* The format of r0 is defined by target newlib. Expand
1481 the macros here instead of looking for .../sys/wait.h. */
1482 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1483 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1484 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1485 cpu.exception = SIGILL;
1486 else
1487 cpu.exception = SIGTRAP;
1488 goto end;
1489 case O (O_BPT, SN):
1490 cpu.state = SIM_STATE_STOPPED;
1491 cpu.exception = SIGTRAP;
1492 goto end;
1493
1494 OBITOP (O_BNOT, 1, 1, ea ^= m);
1495 OBITOP (O_BTST, 1, 0, nz = ea & m);
1496 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1497 OBITOP (O_BSET, 1, 1, ea |= m);
1498 OBITOP (O_BLD, 1, 0, c = ea & m);
1499 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1500 OBITOP (O_BST, 1, 1, ea &= ~m;
1501 if (C) ea |= m);
1502 OBITOP (O_BIST, 1, 1, ea &= ~m;
1503 if (!C) ea |= m);
1504 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1505 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1506 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1507 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1508 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0) != C);
1509 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1510
1511 #define MOP(bsize, signed) \
1512 mop (code, bsize, signed); \
1513 goto next;
1514
1515 case O (O_MULS, SB):
1516 MOP (1, 1);
1517 break;
1518 case O (O_MULS, SW):
1519 MOP (0, 1);
1520 break;
1521 case O (O_MULU, SB):
1522 MOP (1, 0);
1523 break;
1524 case O (O_MULU, SW):
1525 MOP (0, 0);
1526 break;
1527
1528 case O (O_TAS, SB):
1529 if (!h8300smode || code->src.type != X (OP_REG, SL))
1530 goto illegal;
1531 switch (code->src.reg)
1532 {
1533 case R0_REGNUM:
1534 case R1_REGNUM:
1535 case R4_REGNUM:
1536 case R5_REGNUM:
1537 break;
1538 default:
1539 goto illegal;
1540 }
1541 res = fetch (&code->src);
1542 store (&code->src, res | 0x80);
1543 goto just_flags_log8;
1544
1545 case O (O_DIVU, SB):
1546 {
1547 rd = GET_W_REG (code->dst.reg);
1548 ea = GET_B_REG (code->src.reg);
1549 if (ea)
1550 {
1551 tmp = (unsigned) rd % ea;
1552 rd = (unsigned) rd / ea;
1553 }
1554 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1555 n = ea & 0x80;
1556 nz = ea & 0xff;
1557
1558 goto next;
1559 }
1560 case O (O_DIVU, SW):
1561 {
1562 rd = GET_L_REG (code->dst.reg);
1563 ea = GET_W_REG (code->src.reg);
1564 n = ea & 0x8000;
1565 nz = ea & 0xffff;
1566 if (ea)
1567 {
1568 tmp = (unsigned) rd % ea;
1569 rd = (unsigned) rd / ea;
1570 }
1571 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1572 goto next;
1573 }
1574
1575 case O (O_DIVS, SB):
1576 {
1577
1578 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1579 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1580 if (ea)
1581 {
1582 tmp = (int) rd % (int) ea;
1583 rd = (int) rd / (int) ea;
1584 n = rd & 0x8000;
1585 nz = 1;
1586 }
1587 else
1588 nz = 0;
1589 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1590 goto next;
1591 }
1592 case O (O_DIVS, SW):
1593 {
1594 rd = GET_L_REG (code->dst.reg);
1595 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1596 if (ea)
1597 {
1598 tmp = (int) rd % (int) ea;
1599 rd = (int) rd / (int) ea;
1600 n = rd & 0x80000000;
1601 nz = 1;
1602 }
1603 else
1604 nz = 0;
1605 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1606 goto next;
1607 }
1608 case O (O_EXTS, SW):
1609 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1610 ea = rd & 0x80 ? -256 : 0;
1611 res = rd + ea;
1612 goto log16;
1613 case O (O_EXTS, SL):
1614 rd = GET_W_REG (code->src.reg) & 0xffff;
1615 ea = rd & 0x8000 ? -65536 : 0;
1616 res = rd + ea;
1617 goto log32;
1618 case O (O_EXTU, SW):
1619 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1620 ea = 0;
1621 res = rd + ea;
1622 goto log16;
1623 case O (O_EXTU, SL):
1624 rd = GET_W_REG (code->src.reg) & 0xffff;
1625 ea = 0;
1626 res = rd + ea;
1627 goto log32;
1628
1629 case O (O_NOP, SN):
1630 goto next;
1631
1632 case O (O_STM, SL):
1633 {
1634 int nregs, firstreg, i;
1635
1636 nregs = GET_MEMORY_B (pc + 1);
1637 nregs >>= 4;
1638 nregs &= 0xf;
1639 firstreg = GET_MEMORY_B (pc + 3);
1640 firstreg &= 0xf;
1641 for (i = firstreg; i <= firstreg + nregs; i++)
1642 {
1643 cpu.regs[7] -= 4;
1644 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1645 }
1646 }
1647 goto next;
1648
1649 case O (O_LDM, SL):
1650 {
1651 int nregs, firstreg, i;
1652
1653 nregs = GET_MEMORY_B (pc + 1);
1654 nregs >>= 4;
1655 nregs &= 0xf;
1656 firstreg = GET_MEMORY_B (pc + 3);
1657 firstreg &= 0xf;
1658 for (i = firstreg; i >= firstreg - nregs; i--)
1659 {
1660 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1661 cpu.regs[7] += 4;
1662 }
1663 }
1664 goto next;
1665
1666 default:
1667 illegal:
1668 cpu.state = SIM_STATE_STOPPED;
1669 cpu.exception = SIGILL;
1670 goto end;
1671
1672 }
1673 abort ();
1674
1675 setc:
1676 if (code->dst.type == OP_CCR)
1677 {
1678 cpu.ccr = res;
1679 GETSR ();
1680 }
1681 else if (code->dst.type == OP_EXR && h8300smode)
1682 {
1683 cpu.exr = res;
1684 GETEXR ();
1685 }
1686 else
1687 goto illegal;
1688
1689 goto next;
1690
1691 condtrue:
1692 /* When a branch works */
1693 pc = code->src.literal;
1694 goto end;
1695
1696 /* Set the cond codes from res */
1697 bitop:
1698
1699 /* Set the flags after an 8 bit inc/dec operation */
1700 just_flags_inc8:
1701 n = res & 0x80;
1702 nz = res & 0xff;
1703 v = (rd & 0x7f) == 0x7f;
1704 goto next;
1705
1706
1707 /* Set the flags after an 16 bit inc/dec operation */
1708 just_flags_inc16:
1709 n = res & 0x8000;
1710 nz = res & 0xffff;
1711 v = (rd & 0x7fff) == 0x7fff;
1712 goto next;
1713
1714
1715 /* Set the flags after an 32 bit inc/dec operation */
1716 just_flags_inc32:
1717 n = res & 0x80000000;
1718 nz = res & 0xffffffff;
1719 v = (rd & 0x7fffffff) == 0x7fffffff;
1720 goto next;
1721
1722
1723 shift8:
1724 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1725 n = (rd & 0x80);
1726 nz = rd & 0xff;
1727 SET_B_REG (code->src.reg, rd);
1728 goto next;
1729
1730 shift16:
1731 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1732 n = (rd & 0x8000);
1733 nz = rd & 0xffff;
1734 SET_W_REG (code->src.reg, rd);
1735 goto next;
1736
1737 shift32:
1738 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1739 n = (rd & 0x80000000);
1740 nz = rd & 0xffffffff;
1741 SET_L_REG (code->src.reg, rd);
1742 goto next;
1743
1744 log32:
1745 store (&code->dst, res);
1746 just_flags_log32:
1747 /* flags after a 32bit logical operation */
1748 n = res & 0x80000000;
1749 nz = res & 0xffffffff;
1750 v = 0;
1751 goto next;
1752
1753 log16:
1754 store (&code->dst, res);
1755 just_flags_log16:
1756 /* flags after a 16bit logical operation */
1757 n = res & 0x8000;
1758 nz = res & 0xffff;
1759 v = 0;
1760 goto next;
1761
1762
1763 log8:
1764 store (&code->dst, res);
1765 just_flags_log8:
1766 n = res & 0x80;
1767 nz = res & 0xff;
1768 v = 0;
1769 goto next;
1770
1771 alu8:
1772 SET_B_REG (code->dst.reg, res);
1773 just_flags_alu8:
1774 n = res & 0x80;
1775 nz = res & 0xff;
1776 c = (res & 0x100);
1777 switch (code->opcode / 4)
1778 {
1779 case O_ADD:
1780 v = ((rd & 0x80) == (ea & 0x80)
1781 && (rd & 0x80) != (res & 0x80));
1782 break;
1783 case O_SUB:
1784 case O_CMP:
1785 v = ((rd & 0x80) != (-ea & 0x80)
1786 && (rd & 0x80) != (res & 0x80));
1787 break;
1788 case O_NEG:
1789 v = (rd == 0x80);
1790 break;
1791 }
1792 goto next;
1793
1794 alu16:
1795 SET_W_REG (code->dst.reg, res);
1796 just_flags_alu16:
1797 n = res & 0x8000;
1798 nz = res & 0xffff;
1799 c = (res & 0x10000);
1800 switch (code->opcode / 4)
1801 {
1802 case O_ADD:
1803 v = ((rd & 0x8000) == (ea & 0x8000)
1804 && (rd & 0x8000) != (res & 0x8000));
1805 break;
1806 case O_SUB:
1807 case O_CMP:
1808 v = ((rd & 0x8000) != (-ea & 0x8000)
1809 && (rd & 0x8000) != (res & 0x8000));
1810 break;
1811 case O_NEG:
1812 v = (rd == 0x8000);
1813 break;
1814 }
1815 goto next;
1816
1817 alu32:
1818 SET_L_REG (code->dst.reg, res);
1819 just_flags_alu32:
1820 n = res & 0x80000000;
1821 nz = res & 0xffffffff;
1822 switch (code->opcode / 4)
1823 {
1824 case O_ADD:
1825 v = ((rd & 0x80000000) == (ea & 0x80000000)
1826 && (rd & 0x80000000) != (res & 0x80000000));
1827 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1828 break;
1829 case O_SUB:
1830 case O_CMP:
1831 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1832 && (rd & 0x80000000) != (res & 0x80000000));
1833 c = (unsigned) rd < (unsigned) -ea;
1834 break;
1835 case O_NEG:
1836 v = (rd == 0x80000000);
1837 c = res != 0;
1838 break;
1839 }
1840 goto next;
1841
1842 next:;
1843 pc = code->next_pc;
1844
1845 end:
1846 ;
1847 #if 0
1848 if (cpu.regs[8])
1849 abort ();
1850 #endif
1851
1852 if (--poll_count < 0)
1853 {
1854 poll_count = POLL_QUIT_INTERVAL;
1855 if ((*sim_callback->poll_quit) != NULL
1856 && (*sim_callback->poll_quit) (sim_callback))
1857 sim_stop (sd);
1858 }
1859
1860 }
1861 while (cpu.state == SIM_STATE_RUNNING);
1862 cpu.ticks += get_now () - tick_start;
1863 cpu.cycles += cycles;
1864 cpu.insts += insts;
1865
1866 cpu.pc = pc;
1867 BUILDSR ();
1868 BUILDEXR ();
1869 cpu.mask = oldmask;
1870 signal (SIGINT, prev);
1871 }
1872
1873 int
1874 sim_trace (SIM_DESC sd)
1875 {
1876 /* FIXME: Unfinished. */
1877 abort ();
1878 }
1879
1880 int
1881 sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1882 {
1883 int i;
1884
1885 init_pointers ();
1886 if (addr < 0)
1887 return 0;
1888 for (i = 0; i < size; i++)
1889 {
1890 if (addr < memory_size)
1891 {
1892 cpu.memory[addr + i] = buffer[i];
1893 cpu.cache_idx[addr + i] = 0;
1894 }
1895 else
1896 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1897 }
1898 return size;
1899 }
1900
1901 int
1902 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1903 {
1904 init_pointers ();
1905 if (addr < 0)
1906 return 0;
1907 if (addr < memory_size)
1908 memcpy (buffer, cpu.memory + addr, size);
1909 else
1910 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1911 return size;
1912 }
1913
1914
1915 int
1916 sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
1917 {
1918 int longval;
1919 int shortval;
1920 int intval;
1921 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1922 shortval = (value[0] << 8) | (value[1]);
1923 intval = h8300hmode ? longval : shortval;
1924
1925 init_pointers ();
1926 switch (rn)
1927 {
1928 case PC_REGNUM:
1929 cpu.pc = intval;
1930 break;
1931 default:
1932 abort ();
1933 case R0_REGNUM:
1934 case R1_REGNUM:
1935 case R2_REGNUM:
1936 case R3_REGNUM:
1937 case R4_REGNUM:
1938 case R5_REGNUM:
1939 case R6_REGNUM:
1940 case R7_REGNUM:
1941 cpu.regs[rn] = intval;
1942 break;
1943 case CCR_REGNUM:
1944 cpu.ccr = intval;
1945 break;
1946 case EXR_REGNUM:
1947 cpu.exr = intval;
1948 break;
1949 case CYCLE_REGNUM:
1950 cpu.cycles = longval;
1951 break;
1952
1953 case INST_REGNUM:
1954 cpu.insts = longval;
1955 break;
1956
1957 case TICK_REGNUM:
1958 cpu.ticks = longval;
1959 break;
1960 }
1961 return -1;
1962 }
1963
1964 int
1965 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
1966 {
1967 int v;
1968 int longreg = 0;
1969
1970 init_pointers ();
1971
1972 if (!h8300smode && rn >= EXR_REGNUM)
1973 rn++;
1974 switch (rn)
1975 {
1976 default:
1977 abort ();
1978 case CCR_REGNUM:
1979 v = cpu.ccr;
1980 break;
1981 case EXR_REGNUM:
1982 v = cpu.exr;
1983 break;
1984 case PC_REGNUM:
1985 v = cpu.pc;
1986 break;
1987 case R0_REGNUM:
1988 case R1_REGNUM:
1989 case R2_REGNUM:
1990 case R3_REGNUM:
1991 case R4_REGNUM:
1992 case R5_REGNUM:
1993 case R6_REGNUM:
1994 case R7_REGNUM:
1995 v = cpu.regs[rn];
1996 break;
1997 case CYCLE_REGNUM:
1998 v = cpu.cycles;
1999 longreg = 1;
2000 break;
2001 case TICK_REGNUM:
2002 v = cpu.ticks;
2003 longreg = 1;
2004 break;
2005 case INST_REGNUM:
2006 v = cpu.insts;
2007 longreg = 1;
2008 break;
2009 }
2010 if (h8300hmode || longreg)
2011 {
2012 buf[0] = v >> 24;
2013 buf[1] = v >> 16;
2014 buf[2] = v >> 8;
2015 buf[3] = v >> 0;
2016 }
2017 else
2018 {
2019 buf[0] = v >> 8;
2020 buf[1] = v;
2021 }
2022 return -1;
2023 }
2024
2025 void
2026 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
2027 {
2028 #if 0 /* FIXME: This should work but we can't use it.
2029 grep for SLEEP above. */
2030 switch (cpu.state)
2031 {
2032 case SIM_STATE_EXITED : *reason = sim_exited; break;
2033 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
2034 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
2035 default : abort ();
2036 }
2037 #else
2038 *reason = sim_stopped;
2039 #endif
2040 *sigrc = cpu.exception;
2041 }
2042
2043 /* FIXME: Rename to sim_set_mem_size. */
2044
2045 void
2046 sim_size (int n)
2047 {
2048 /* Memory size is fixed. */
2049 }
2050
2051 void
2052 sim_set_simcache_size (int n)
2053 {
2054 if (cpu.cache)
2055 free (cpu.cache);
2056 if (n < 2)
2057 n = 2;
2058 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
2059 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
2060 cpu.csize = n;
2061 }
2062
2063
2064 void
2065 sim_info (SIM_DESC sd, int verbose)
2066 {
2067 double timetaken = (double) cpu.ticks / (double) now_persec ();
2068 double virttime = cpu.cycles / 10.0e6;
2069
2070 (*sim_callback->printf_filtered) (sim_callback,
2071 "\n\n#instructions executed %10d\n",
2072 cpu.insts);
2073 (*sim_callback->printf_filtered) (sim_callback,
2074 "#cycles (v approximate) %10d\n",
2075 cpu.cycles);
2076 (*sim_callback->printf_filtered) (sim_callback,
2077 "#real time taken %10.4f\n",
2078 timetaken);
2079 (*sim_callback->printf_filtered) (sim_callback,
2080 "#virtual time taked %10.4f\n",
2081 virttime);
2082 if (timetaken != 0.0)
2083 (*sim_callback->printf_filtered) (sim_callback,
2084 "#simulation ratio %10.4f\n",
2085 virttime / timetaken);
2086 (*sim_callback->printf_filtered) (sim_callback,
2087 "#compiles %10d\n",
2088 cpu.compiles);
2089 (*sim_callback->printf_filtered) (sim_callback,
2090 "#cache size %10d\n",
2091 cpu.csize);
2092
2093 #ifdef ADEBUG
2094 /* This to be conditional on `what' (aka `verbose'),
2095 however it was never passed as non-zero. */
2096 if (1)
2097 {
2098 int i;
2099 for (i = 0; i < O_LAST; i++)
2100 {
2101 if (cpu.stats[i])
2102 (*sim_callback->printf_filtered) (sim_callback,
2103 "%d: %d\n", i, cpu.stats[i]);
2104 }
2105 }
2106 #endif
2107 }
2108
2109 /* Indicate whether the cpu is an H8/300 or H8/300H.
2110 FLAG is non-zero for the H8/300H. */
2111
2112 void
2113 set_h8300h (int h_flag, int s_flag)
2114 {
2115 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2116 This function being replaced by a sim_open:ARGV configuration
2117 option. */
2118 h8300hmode = h_flag;
2119 h8300smode = s_flag;
2120 }
2121
2122 SIM_DESC
2123 sim_open (SIM_OPEN_KIND kind,
2124 struct host_callback_struct *ptr,
2125 struct _bfd *abfd,
2126 char **argv)
2127 {
2128 /* FIXME: Much of the code in sim_load can be moved here. */
2129
2130 sim_kind = kind;
2131 myname = argv[0];
2132 sim_callback = ptr;
2133 /* Fudge our descriptor. */
2134 return (SIM_DESC) 1;
2135 }
2136
2137 void
2138 sim_close (SIM_DESC sd, int quitting)
2139 {
2140 /* Nothing to do. */
2141 }
2142
2143 /* Called by gdb to load a program into memory. */
2144
2145 SIM_RC
2146 sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty)
2147 {
2148 bfd *prog_bfd;
2149
2150 /* FIXME: The code below that sets a specific variant of the H8/300
2151 being simulated should be moved to sim_open(). */
2152
2153 /* See if the file is for the H8/300 or H8/300H. */
2154 /* ??? This may not be the most efficient way. The z8k simulator
2155 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2156 if (abfd != NULL)
2157 prog_bfd = abfd;
2158 else
2159 prog_bfd = bfd_openr (prog, "coff-h8300");
2160 if (prog_bfd != NULL)
2161 {
2162 /* Set the cpu type. We ignore failure from bfd_check_format
2163 and bfd_openr as sim_load_file checks too. */
2164 if (bfd_check_format (prog_bfd, bfd_object))
2165 {
2166 unsigned long mach = bfd_get_mach (prog_bfd);
2167 set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s,
2168 mach == bfd_mach_h8300s);
2169 }
2170 }
2171
2172 /* If we're using gdb attached to the simulator, then we have to
2173 reallocate memory for the simulator.
2174
2175 When gdb first starts, it calls fetch_registers (among other
2176 functions), which in turn calls init_pointers, which allocates
2177 simulator memory.
2178
2179 The problem is when we do that, we don't know whether we're
2180 debugging an H8/300 or H8/300H program.
2181
2182 This is the first point at which we can make that determination,
2183 so we just reallocate memory now; this will also allow us to handle
2184 switching between H8/300 and H8/300H programs without exiting
2185 gdb. */
2186
2187 if (h8300smode)
2188 memory_size = H8300S_MSIZE;
2189 else if (h8300hmode)
2190 memory_size = H8300H_MSIZE;
2191 else
2192 memory_size = H8300_MSIZE;
2193
2194 if (cpu.memory)
2195 free (cpu.memory);
2196 if (cpu.cache_idx)
2197 free (cpu.cache_idx);
2198 if (cpu.eightbit)
2199 free (cpu.eightbit);
2200
2201 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2202 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2203 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2204
2205 /* `msize' must be a power of two. */
2206 if ((memory_size & (memory_size - 1)) != 0)
2207 abort ();
2208 cpu.mask = memory_size - 1;
2209
2210 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2211 sim_kind == SIM_OPEN_DEBUG,
2212 0, sim_write)
2213 == NULL)
2214 {
2215 /* Close the bfd if we opened it. */
2216 if (abfd == NULL && prog_bfd != NULL)
2217 bfd_close (prog_bfd);
2218 return SIM_RC_FAIL;
2219 }
2220
2221 /* Close the bfd if we opened it. */
2222 if (abfd == NULL && prog_bfd != NULL)
2223 bfd_close (prog_bfd);
2224 return SIM_RC_OK;
2225 }
2226
2227 SIM_RC
2228 sim_create_inferior (SIM_DESC sd, struct _bfd *abfd, char **argv, char **env)
2229 {
2230 if (abfd != NULL)
2231 cpu.pc = bfd_get_start_address (abfd);
2232 else
2233 cpu.pc = 0;
2234 return SIM_RC_OK;
2235 }
2236
2237 void
2238 sim_do_command (SIM_DESC sd, char *cmd)
2239 {
2240 (*sim_callback->printf_filtered) (sim_callback,
2241 "This simulator does not accept any commands.\n");
2242 }
2243
2244 void
2245 sim_set_callbacks (struct host_callback_struct *ptr)
2246 {
2247 sim_callback = ptr;
2248 }
GDB Binutils - Deliverables
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