2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
35 #include "gdb/callback.h"
36 #include "gdb/remote-sim.h"
37 #include "gdb/sim-h8300.h"
45 host_callback
*sim_callback
;
47 static SIM_OPEN_KIND sim_kind
;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size
PARAMS ((int));
56 #define X(op, size) op * 4 + size
58 #define SP (h8300hmode ? SL : SW)
72 #define h8_opcodes ops
74 #include "opcode/h8300.h"
78 /* The rate at which to call the host's poll_quit callback. */
80 #define POLL_QUIT_INTERVAL 0x80000
82 #define LOW_BYTE(x) ((x) & 0xff)
83 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
84 #define P(X,Y) ((X << 8) | Y)
86 #define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
87 (N << 3) | (Z << 2) | (V<<1) | C;
90 if (h8300smode) cpu.exr = (trace<<7) | intMask;
93 c = (cpu.ccr >> 0) & 1;\
94 v = (cpu.ccr >> 1) & 1;\
95 nz = !((cpu.ccr >> 2) & 1);\
96 n = (cpu.ccr >> 3) & 1;\
97 u = (cpu.ccr >> 4) & 1;\
98 h = (cpu.ccr >> 5) & 1;\
99 ui = ((cpu.ccr >> 6) & 1);\
100 intMaskBit = (cpu.ccr >> 7) & 1;
104 trace = (cpu.exr >> 7) & 1;\
105 intMask = cpu.exr & 7; }
107 #ifdef __CHAR_IS_SIGNED__
108 #define SEXTCHAR(x) ((char) (x))
112 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
115 #define UEXTCHAR(x) ((x) & 0xff)
116 #define UEXTSHORT(x) ((x) & 0xffff)
117 #define SEXTSHORT(x) ((short) (x))
119 static cpu_state_type cpu
;
124 static int memory_size
;
129 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
150 return h8300hmode
? SL
: SW
;
162 return X (OP_IMM
, SP
);
164 return X (OP_REG
, SP
);
167 return X (OP_MEM
, SP
);
170 abort (); /* ?? May be something more usefull? */
175 decode (addr
, data
, dst
)
193 /* Find the exact opcode/arg combo. */
194 for (q
= h8_opcodes
; q
->name
; q
++)
196 op_type
*nib
= q
->data
.nib
;
197 unsigned int len
= 0;
201 op_type looking_for
= *nib
;
202 int thisnib
= data
[len
>> 1];
204 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
206 if (looking_for
< 16 && looking_for
>= 0)
208 if (looking_for
!= thisnib
)
213 if ((int) looking_for
& (int) B31
)
215 if (!(((int) thisnib
& 0x8) != 0))
218 looking_for
= (op_type
) ((int) looking_for
& ~(int) B31
);
222 if ((int) looking_for
& (int) B30
)
224 if (!(((int) thisnib
& 0x8) == 0))
227 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
230 if (looking_for
& DBIT
)
232 /* Exclude adds/subs by looking at bit 0 and 2, and
233 make sure the operand size, either w or l,
234 matches by looking at bit 1. */
235 if ((looking_for
& 7) != (thisnib
& 7))
238 abs
= (thisnib
& 0x8) ? 2 : 1;
240 else if (looking_for
& (REG
| IND
| INC
| DEC
))
242 if (looking_for
& REG
)
244 /* Can work out size from the register. */
245 size
= bitfrom (looking_for
);
247 if (looking_for
& SRC
)
252 else if (looking_for
& L_16
)
254 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
256 if (looking_for
& (PCREL
| DISP
))
261 else if (looking_for
& ABSJMP
)
263 abs
= (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
265 else if (looking_for
& MEMIND
)
269 else if (looking_for
& L_32
)
273 abs
= (data
[i
] << 24)
274 | (data
[i
+ 1] << 16)
280 else if (looking_for
& L_24
)
284 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
287 else if (looking_for
& IGNORE
)
291 else if (looking_for
& DISPREG
)
293 rdisp
= thisnib
& 0x7;
295 else if (looking_for
& KBIT
)
312 else if (looking_for
& L_8
)
316 if (looking_for
& PCREL
)
318 abs
= SEXTCHAR (data
[len
>> 1]);
320 else if (looking_for
& ABS8MEM
)
323 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
324 abs
|= data
[len
>> 1] & 0xff;
328 abs
= data
[len
>> 1] & 0xff;
331 else if (looking_for
& L_3
)
337 else if (looking_for
== E
)
341 /* Fill in the args. */
343 op_type
*args
= q
->args
.nib
;
349 int rn
= (x
& DST
) ? rd
: rs
;
359 p
->type
= X (OP_IMM
, size
);
362 else if (x
& (IMM
| KBIT
| DBIT
))
364 p
->type
= X (OP_IMM
, size
);
370 Some ops (like mul) have two sizes. */
373 p
->type
= X (OP_REG
, size
);
378 p
->type
= X (OP_INC
, size
);
383 p
->type
= X (OP_DEC
, size
);
388 p
->type
= X (OP_DISP
, size
);
392 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
394 p
->type
= X (OP_DISP
, size
);
400 p
->type
= X (OP_MEM
, size
);
405 p
->type
= X (OP_PCREL
, size
);
406 p
->literal
= abs
+ addr
+ 2;
412 p
->type
= X (OP_IMM
, SP
);
417 p
->type
= X (OP_DISP
, size
);
419 p
->reg
= rdisp
& 0x7;
430 printf ("Hmmmm %x", x
);
436 /* But a jmp or a jsr gets automagically lvalued,
437 since we branch to their address not their
439 if (q
->how
== O (O_JSR
, SB
)
440 || q
->how
== O (O_JMP
, SB
))
442 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
445 if (dst
->dst
.type
== -1)
448 dst
->opcode
= q
->how
;
449 dst
->cycles
= q
->time
;
451 /* And a jsr to 0xc4 is turned into a magic trap. */
453 if (dst
->opcode
== O (O_JSR
, SB
))
455 if (dst
->src
.literal
== 0xc4)
457 dst
->opcode
= O (O_SYSCALL
, SB
);
461 dst
->next_pc
= addr
+ len
/ 2;
465 printf ("Don't understand %x \n", looking_for
);
476 /* Fell off the end. */
477 dst
->opcode
= O (O_ILL
, SB
);
485 /* Find the next cache entry to use. */
486 idx
= cpu
.cache_top
+ 1;
488 if (idx
>= cpu
.csize
)
494 /* Throw away its old meaning. */
495 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
497 /* Set to new address. */
498 cpu
.cache
[idx
].oldpc
= pc
;
500 /* Fill in instruction info. */
501 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
503 /* Point to new cache entry. */
504 cpu
.cache_idx
[pc
] = idx
;
508 static unsigned char *breg
[18];
509 static unsigned short *wreg
[18];
510 static unsigned int *lreg
[18];
512 #define GET_B_REG(x) *(breg[x])
513 #define SET_B_REG(x,y) (*(breg[x])) = (y)
514 #define GET_W_REG(x) *(wreg[x])
515 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
517 #define GET_L_REG(x) *(lreg[x])
518 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
520 #define GET_MEMORY_L(x) \
522 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
523 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
524 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
525 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
527 #define GET_MEMORY_W(x) \
529 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
530 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
533 #define GET_MEMORY_B(x) \
534 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
536 #define SET_MEMORY_L(x,y) \
537 { register unsigned char *_p; register int __y = y; \
538 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
539 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
540 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
542 #define SET_MEMORY_W(x,y) \
543 { register unsigned char *_p; register int __y = y; \
544 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
545 _p[0] = (__y)>>8; _p[1] =(__y);}
547 #define SET_MEMORY_B(x,y) \
548 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
555 int abs
= arg
->literal
;
562 return GET_B_REG (rn
);
564 return GET_W_REG (rn
);
566 return GET_L_REG (rn
);
577 r
= GET_MEMORY_B (t
);
586 r
= GET_MEMORY_W (t
);
594 r
= GET_MEMORY_L (t
);
601 case X (OP_DISP
, SB
):
602 t
= GET_L_REG (rn
) + abs
;
604 return GET_MEMORY_B (t
);
606 case X (OP_DISP
, SW
):
607 t
= GET_L_REG (rn
) + abs
;
609 return GET_MEMORY_W (t
);
611 case X (OP_DISP
, SL
):
612 t
= GET_L_REG (rn
) + abs
;
614 return GET_MEMORY_L (t
);
617 t
= GET_MEMORY_L (abs
);
622 t
= GET_MEMORY_W (abs
);
627 abort (); /* ?? May be something more usefull? */
639 int abs
= arg
->literal
;
655 t
= GET_L_REG (rn
) - 1;
662 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
668 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
673 case X (OP_DISP
, SB
):
674 t
= GET_L_REG (rn
) + abs
;
679 case X (OP_DISP
, SW
):
680 t
= GET_L_REG (rn
) + abs
;
685 case X (OP_DISP
, SL
):
686 t
= GET_L_REG (rn
) + abs
;
722 memory_size
= H8300S_MSIZE
;
724 memory_size
= H8300H_MSIZE
;
726 memory_size
= H8300_MSIZE
;
727 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
728 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
729 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
731 /* `msize' must be a power of two. */
732 if ((memory_size
& (memory_size
- 1)) != 0)
734 cpu
.mask
= memory_size
- 1;
736 for (i
= 0; i
< 9; i
++)
741 for (i
= 0; i
< 8; i
++)
743 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
744 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
745 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
746 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
747 cpu
.regs
[i
] = 0x00112233;
773 lreg
[i
] = &cpu
.regs
[i
];
776 lreg
[8] = &cpu
.regs
[8];
778 /* Initialize the seg registers. */
780 sim_set_simcache_size (CSIZE
);
785 control_c (sig
, code
, scp
, addr
)
791 cpu
.state
= SIM_STATE_STOPPED
;
792 cpu
.exception
= SIGINT
;
802 #define I (intMaskBit != 0)
805 mop (code
, bsize
, sign
)
818 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
819 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
821 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
822 SEXTSHORT (GET_W_REG (code
->src
.reg
));
826 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
827 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
829 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
830 UEXTSHORT (GET_W_REG (code
->src
.reg
));
833 result
= multiplier
* multiplicand
;
837 n
= result
& (bsize
? 0x8000 : 0x80000000);
838 nz
= result
& (bsize
? 0xffff : 0xffffffff);
842 SET_W_REG (code
->dst
.reg
, result
);
846 SET_L_REG (code
->dst
.reg
, result
);
849 return ((n
== 1) << 1) | (nz
== 1);
853 #define ONOT(name, how) \
858 rd = GET_B_REG (code->src.reg); \
866 rd = GET_W_REG (code->src.reg); \
873 int hm = 0x80000000; \
874 rd = GET_L_REG (code->src.reg); \
879 #define OSHIFTS(name, how1, how2) \
884 rd = GET_B_REG (code->src.reg); \
885 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
899 rd = GET_W_REG (code->src.reg); \
900 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
913 int hm = 0x80000000; \
914 rd = GET_L_REG (code->src.reg); \
915 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
926 #define OBITOP(name,f, s, op) \
931 if (f) ea = fetch (&code->dst); \
932 m=1<< fetch (&code->src); \
934 if (s) store (&code->dst,ea); goto next; \
941 cpu
.state
= SIM_STATE_STOPPED
;
942 cpu
.exception
= SIGINT
;
955 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
956 #define FP_REGNUM R6_REGNUM /* Contains address of executing
959 #define CCR_REGNUM 8 /* Contains processor status */
960 #define PC_REGNUM 9 /* Contains program counter */
962 #define CYCLE_REGNUM 10
964 #define EXR_REGNUM 11
965 #define INST_REGNUM 12
966 #define TICK_REGNUM 13
969 sim_resume (sd
, step
, siggnal
)
975 int tick_start
= get_now ();
984 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
989 prev
= signal (SIGINT
, control_c
);
993 cpu
.state
= SIM_STATE_STOPPED
;
994 cpu
.exception
= SIGTRAP
;
998 cpu
.state
= SIM_STATE_RUNNING
;
1004 /* The PC should never be odd. */
1020 cidx
= cpu
.cache_idx
[pc
];
1021 code
= cpu
.cache
+ cidx
;
1024 #define ALUOP(STORE, NAME, HOW) \
1025 case O (NAME,SB): HOW; if (STORE)goto alu8;else goto just_flags_alu8; \
1026 case O (NAME, SW): HOW; if (STORE)goto alu16;else goto just_flags_alu16; \
1027 case O (NAME,SL): HOW; if (STORE)goto alu32;else goto just_flags_alu32;
1030 #define LOGOP(NAME, HOW) \
1031 case O (NAME,SB): HOW; goto log8;\
1032 case O (NAME, SW): HOW; goto log16;\
1033 case O (NAME,SL): HOW; goto log32;
1040 printf ("%x %d %s\n", pc
, code
->opcode
,
1041 code
->op
? code
->op
->name
: "**");
1043 cpu
.stats
[code
->opcode
]++;
1049 cycles
+= code
->cycles
;
1053 switch (code
->opcode
)
1057 * This opcode is a fake for when we get to an
1058 * instruction which hasnt been compiled
1065 case O (O_SUBX
, SB
):
1066 rd
= fetch (&code
->dst
);
1067 ea
= fetch (&code
->src
);
1072 case O (O_ADDX
, SB
):
1073 rd
= fetch (&code
->dst
);
1074 ea
= fetch (&code
->src
);
1079 #define EA ea = fetch (&code->src);
1080 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1082 ALUOP (1, O_SUB
, RD_EA
;
1085 ALUOP (1, O_NEG
, EA
;
1091 rd
= GET_B_REG (code
->dst
.reg
);
1092 ea
= fetch (&code
->src
);
1096 rd
= GET_W_REG (code
->dst
.reg
);
1097 ea
= fetch (&code
->src
);
1101 rd
= GET_L_REG (code
->dst
.reg
);
1102 ea
= fetch (&code
->src
);
1107 LOGOP (O_AND
, RD_EA
;
1113 LOGOP (O_XOR
, RD_EA
;
1117 case O (O_MOV_TO_MEM
, SB
):
1118 res
= GET_B_REG (code
->src
.reg
);
1120 case O (O_MOV_TO_MEM
, SW
):
1121 res
= GET_W_REG (code
->src
.reg
);
1123 case O (O_MOV_TO_MEM
, SL
):
1124 res
= GET_L_REG (code
->src
.reg
);
1128 case O (O_MOV_TO_REG
, SB
):
1129 res
= fetch (&code
->src
);
1130 SET_B_REG (code
->dst
.reg
, res
);
1131 goto just_flags_log8
;
1132 case O (O_MOV_TO_REG
, SW
):
1133 res
= fetch (&code
->src
);
1134 SET_W_REG (code
->dst
.reg
, res
);
1135 goto just_flags_log16
;
1136 case O (O_MOV_TO_REG
, SL
):
1137 res
= fetch (&code
->src
);
1138 SET_L_REG (code
->dst
.reg
, res
);
1139 goto just_flags_log32
;
1141 case O (O_EEPMOV
, SB
):
1142 case O (O_EEPMOV
, SW
):
1143 if (h8300hmode
||h8300smode
)
1145 register unsigned char *_src
,*_dst
;
1146 unsigned int count
= (code
->opcode
== O(O_EEPMOV
, SW
))?cpu
.regs
[R4_REGNUM
]&0xffff:
1147 cpu
.regs
[R4_REGNUM
]&0xff;
1149 _src
= cpu
.regs
[R5_REGNUM
] < memory_size
? cpu
.memory
+cpu
.regs
[R5_REGNUM
] :
1150 cpu
.eightbit
+ (cpu
.regs
[R5_REGNUM
] & 0xff);
1151 if ((_src
+count
)>=(cpu
.memory
+memory_size
))
1153 if ((_src
+count
)>=(cpu
.eightbit
+0x100))
1156 _dst
= cpu
.regs
[R6_REGNUM
] < memory_size
? cpu
.memory
+cpu
.regs
[R6_REGNUM
] :
1157 cpu
.eightbit
+ (cpu
.regs
[R6_REGNUM
] & 0xff);
1158 if ((_dst
+count
)>=(cpu
.memory
+memory_size
))
1160 if ((_dst
+count
)>=(cpu
.eightbit
+0x100))
1163 memcpy(_dst
,_src
,count
);
1165 cpu
.regs
[R5_REGNUM
]+=count
;
1166 cpu
.regs
[R6_REGNUM
]+=count
;
1167 cpu
.regs
[R4_REGNUM
]&=(code
->opcode
== O(O_EEPMOV
, SW
))?(~0xffff):(~0xff);
1173 case O (O_ADDS
, SL
):
1174 SET_L_REG (code
->dst
.reg
,
1175 GET_L_REG (code
->dst
.reg
)
1176 + code
->src
.literal
);
1180 case O (O_SUBS
, SL
):
1181 SET_L_REG (code
->dst
.reg
,
1182 GET_L_REG (code
->dst
.reg
)
1183 - code
->src
.literal
);
1187 rd
= fetch (&code
->dst
);
1188 ea
= fetch (&code
->src
);
1191 goto just_flags_alu8
;
1194 rd
= fetch (&code
->dst
);
1195 ea
= fetch (&code
->src
);
1198 goto just_flags_alu16
;
1201 rd
= fetch (&code
->dst
);
1202 ea
= fetch (&code
->src
);
1205 goto just_flags_alu32
;
1209 rd
= GET_B_REG (code
->src
.reg
);
1212 SET_B_REG (code
->src
.reg
, res
);
1213 goto just_flags_inc8
;
1216 rd
= GET_W_REG (code
->dst
.reg
);
1217 ea
= -code
->src
.literal
;
1219 SET_W_REG (code
->dst
.reg
, res
);
1220 goto just_flags_inc16
;
1223 rd
= GET_L_REG (code
->dst
.reg
);
1224 ea
= -code
->src
.literal
;
1226 SET_L_REG (code
->dst
.reg
, res
);
1227 goto just_flags_inc32
;
1231 rd
= GET_B_REG (code
->src
.reg
);
1234 SET_B_REG (code
->src
.reg
, res
);
1235 goto just_flags_inc8
;
1238 rd
= GET_W_REG (code
->dst
.reg
);
1239 ea
= code
->src
.literal
;
1241 SET_W_REG (code
->dst
.reg
, res
);
1242 goto just_flags_inc16
;
1245 rd
= GET_L_REG (code
->dst
.reg
);
1246 ea
= code
->src
.literal
;
1248 SET_L_REG (code
->dst
.reg
, res
);
1249 goto just_flags_inc32
;
1251 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1252 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1256 res
= fetch (&code
->src
);
1260 if (code
->src
.type
== OP_CCR
)
1264 else if (code
->src
.type
== OP_EXR
&& h8300smode
)
1270 store (&code
->dst
, res
);
1273 case O (O_ANDC
, SB
):
1274 if (code
->dst
.type
== OP_CCR
)
1278 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1284 ea
= code
->src
.literal
;
1289 if (code
->dst
.type
== OP_CCR
)
1293 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1299 ea
= code
->src
.literal
;
1303 case O (O_XORC
, SB
):
1304 if (code
->dst
.type
== OP_CCR
)
1308 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1314 ea
= code
->src
.literal
;
1355 if (((Z
|| (N
^ V
)) == 0))
1361 if (((Z
|| (N
^ V
)) == 1))
1395 case O (O_SYSCALL
, SB
):
1397 char c
= cpu
.regs
[2];
1398 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1402 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1404 c
= rd
& hm
; v
= 0; rd
<<= 1,
1405 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1407 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1408 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1410 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1411 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1413 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1414 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1);
1416 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1417 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1419 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1420 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1422 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1423 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1425 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1426 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1430 pc
= fetch (&code
->src
);
1438 pc
= fetch (&code
->src
);
1445 SET_MEMORY_L (tmp
, code
->next_pc
);
1450 SET_MEMORY_W (tmp
, code
->next_pc
);
1457 pc
= code
->src
.literal
;
1468 pc
= GET_MEMORY_L (tmp
);
1473 pc
= GET_MEMORY_W (tmp
);
1482 cpu
.state
= SIM_STATE_STOPPED
;
1483 cpu
.exception
= SIGILL
;
1485 case O (O_SLEEP
, SN
):
1486 /* FIXME: Doesn't this break for breakpoints when r0
1487 contains just the right (er, wrong) value? */
1488 cpu
.state
= SIM_STATE_STOPPED
;
1489 /* The format of r0 is defined by target newlib. Expand
1490 the macros here instead of looking for .../sys/wait.h. */
1491 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1492 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1493 if (! SIM_WIFEXITED (cpu
.regs
[0]) && SIM_WIFSIGNALED (cpu
.regs
[0]))
1494 cpu
.exception
= SIGILL
;
1496 cpu
.exception
= SIGTRAP
;
1499 cpu
.state
= SIM_STATE_STOPPED
;
1500 cpu
.exception
= SIGTRAP
;
1503 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1504 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1505 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1506 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1507 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1508 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1509 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1511 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1513 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1514 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1515 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1516 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1517 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1518 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1520 #define MOP(bsize, signed) \
1521 mop (code, bsize, signed); \
1524 case O (O_MULS
, SB
):
1527 case O (O_MULS
, SW
):
1530 case O (O_MULU
, SB
):
1533 case O (O_MULU
, SW
):
1538 if (!h8300smode
|| code
->src
.type
!= X (OP_REG
, SL
))
1540 switch (code
->src
.reg
)
1550 res
= fetch (&code
->src
);
1551 store (&code
->src
,res
|0x80);
1552 goto just_flags_log8
;
1554 case O (O_DIVU
, SB
):
1556 rd
= GET_W_REG (code
->dst
.reg
);
1557 ea
= GET_B_REG (code
->src
.reg
);
1560 tmp
= (unsigned) rd
% ea
;
1561 rd
= (unsigned) rd
/ ea
;
1563 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1569 case O (O_DIVU
, SW
):
1571 rd
= GET_L_REG (code
->dst
.reg
);
1572 ea
= GET_W_REG (code
->src
.reg
);
1577 tmp
= (unsigned) rd
% ea
;
1578 rd
= (unsigned) rd
/ ea
;
1580 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1584 case O (O_DIVS
, SB
):
1587 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1588 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1591 tmp
= (int) rd
% (int) ea
;
1592 rd
= (int) rd
/ (int) ea
;
1598 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1601 case O (O_DIVS
, SW
):
1603 rd
= GET_L_REG (code
->dst
.reg
);
1604 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1607 tmp
= (int) rd
% (int) ea
;
1608 rd
= (int) rd
/ (int) ea
;
1609 n
= rd
& 0x80000000;
1614 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1617 case O (O_EXTS
, SW
):
1618 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1619 ea
= rd
& 0x80 ? -256 : 0;
1622 case O (O_EXTS
, SL
):
1623 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1624 ea
= rd
& 0x8000 ? -65536 : 0;
1627 case O (O_EXTU
, SW
):
1628 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1632 case O (O_EXTU
, SL
):
1633 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1643 int nregs
, firstreg
, i
;
1645 nregs
= GET_MEMORY_B (pc
+ 1);
1648 firstreg
= GET_MEMORY_B (pc
+ 3);
1650 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1653 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1660 int nregs
, firstreg
, i
;
1662 nregs
= GET_MEMORY_B (pc
+ 1);
1665 firstreg
= GET_MEMORY_B (pc
+ 3);
1667 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1669 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1677 cpu
.state
= SIM_STATE_STOPPED
;
1678 cpu
.exception
= SIGILL
;
1685 if (code
->dst
.type
== OP_CCR
)
1690 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1701 /* When a branch works */
1702 pc
= code
->src
.literal
;
1705 /* Set the cond codes from res */
1708 /* Set the flags after an 8 bit inc/dec operation */
1712 v
= (rd
& 0x7f) == 0x7f;
1716 /* Set the flags after an 16 bit inc/dec operation */
1720 v
= (rd
& 0x7fff) == 0x7fff;
1724 /* Set the flags after an 32 bit inc/dec operation */
1726 n
= res
& 0x80000000;
1727 nz
= res
& 0xffffffff;
1728 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1733 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1736 SET_B_REG (code
->src
.reg
, rd
);
1740 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1743 SET_W_REG (code
->src
.reg
, rd
);
1747 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1748 n
= (rd
& 0x80000000);
1749 nz
= rd
& 0xffffffff;
1750 SET_L_REG (code
->src
.reg
, rd
);
1754 store (&code
->dst
, res
);
1756 /* flags after a 32bit logical operation */
1757 n
= res
& 0x80000000;
1758 nz
= res
& 0xffffffff;
1763 store (&code
->dst
, res
);
1765 /* flags after a 16bit logical operation */
1773 store (&code
->dst
, res
);
1781 SET_B_REG (code
->dst
.reg
, res
);
1786 switch (code
->opcode
/ 4)
1789 v
= ((rd
& 0x80) == (ea
& 0x80)
1790 && (rd
& 0x80) != (res
& 0x80));
1794 v
= ((rd
& 0x80) != (-ea
& 0x80)
1795 && (rd
& 0x80) != (res
& 0x80));
1804 SET_W_REG (code
->dst
.reg
, res
);
1808 c
= (res
& 0x10000);
1809 switch (code
->opcode
/ 4)
1812 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1813 && (rd
& 0x8000) != (res
& 0x8000));
1817 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1818 && (rd
& 0x8000) != (res
& 0x8000));
1827 SET_L_REG (code
->dst
.reg
, res
);
1829 n
= res
& 0x80000000;
1830 nz
= res
& 0xffffffff;
1831 switch (code
->opcode
/ 4)
1834 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1835 && (rd
& 0x80000000) != (res
& 0x80000000));
1836 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1840 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1841 && (rd
& 0x80000000) != (res
& 0x80000000));
1842 c
= (unsigned) rd
< (unsigned) -ea
;
1845 v
= (rd
== 0x80000000);
1861 if (--poll_count
< 0)
1863 poll_count
= POLL_QUIT_INTERVAL
;
1864 if ((*sim_callback
->poll_quit
) != NULL
1865 && (*sim_callback
->poll_quit
) (sim_callback
))
1870 while (cpu
.state
== SIM_STATE_RUNNING
);
1871 cpu
.ticks
+= get_now () - tick_start
;
1872 cpu
.cycles
+= cycles
;
1879 signal (SIGINT
, prev
);
1886 /* FIXME: Unfinished. */
1891 sim_write (sd
, addr
, buffer
, size
)
1894 unsigned char *buffer
;
1902 for (i
= 0; i
< size
; i
++)
1904 if (addr
< memory_size
)
1906 cpu
.memory
[addr
+ i
] = buffer
[i
];
1907 cpu
.cache_idx
[addr
+ i
] = 0;
1910 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1916 sim_read (sd
, addr
, buffer
, size
)
1919 unsigned char *buffer
;
1925 if (addr
< memory_size
)
1926 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1928 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1934 sim_store_register (sd
, rn
, value
, length
)
1937 unsigned char *value
;
1943 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1944 shortval
= (value
[0] << 8) | (value
[1]);
1945 intval
= h8300hmode
? longval
: shortval
;
1963 cpu
.regs
[rn
] = intval
;
1972 cpu
.cycles
= longval
;
1976 cpu
.insts
= longval
;
1980 cpu
.ticks
= longval
;
1987 sim_fetch_register (sd
, rn
, buf
, length
)
1998 if (!h8300smode
&& rn
>=EXR_REGNUM
)
2036 if (h8300hmode
|| longreg
)
2052 sim_stop_reason (sd
, reason
, sigrc
)
2054 enum sim_stop
*reason
;
2057 #if 0 /* FIXME: This should work but we can't use it.
2058 grep for SLEEP above. */
2061 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
2062 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
2063 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
2067 *reason
= sim_stopped
;
2069 *sigrc
= cpu
.exception
;
2072 /* FIXME: Rename to sim_set_mem_size. */
2078 /* Memory size is fixed. */
2082 sim_set_simcache_size (n
)
2088 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
2089 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
2095 sim_info (sd
, verbose
)
2099 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
2100 double virttime
= cpu
.cycles
/ 10.0e6
;
2102 (*sim_callback
->printf_filtered
) (sim_callback
,
2103 "\n\n#instructions executed %10d\n",
2105 (*sim_callback
->printf_filtered
) (sim_callback
,
2106 "#cycles (v approximate) %10d\n",
2108 (*sim_callback
->printf_filtered
) (sim_callback
,
2109 "#real time taken %10.4f\n",
2111 (*sim_callback
->printf_filtered
) (sim_callback
,
2112 "#virtual time taked %10.4f\n",
2114 if (timetaken
!= 0.0)
2115 (*sim_callback
->printf_filtered
) (sim_callback
,
2116 "#simulation ratio %10.4f\n",
2117 virttime
/ timetaken
);
2118 (*sim_callback
->printf_filtered
) (sim_callback
,
2121 (*sim_callback
->printf_filtered
) (sim_callback
,
2122 "#cache size %10d\n",
2126 /* This to be conditional on `what' (aka `verbose'),
2127 however it was never passed as non-zero. */
2131 for (i
= 0; i
< O_LAST
; i
++)
2134 (*sim_callback
->printf_filtered
) (sim_callback
,
2135 "%d: %d\n", i
, cpu
.stats
[i
]);
2141 /* Indicate whether the cpu is an H8/300 or H8/300H.
2142 FLAG is non-zero for the H8/300H. */
2145 set_h8300h (h_flag
, s_flag
)
2148 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2149 This function being replaced by a sim_open:ARGV configuration
2151 h8300hmode
= h_flag
;
2152 h8300smode
= s_flag
;
2156 sim_open (kind
, ptr
, abfd
, argv
)
2158 struct host_callback_struct
*ptr
;
2162 /* FIXME: Much of the code in sim_load can be moved here. */
2167 /* Fudge our descriptor. */
2168 return (SIM_DESC
) 1;
2172 sim_close (sd
, quitting
)
2176 /* Nothing to do. */
2179 /* Called by gdb to load a program into memory. */
2182 sim_load (sd
, prog
, abfd
, from_tty
)
2190 /* FIXME: The code below that sets a specific variant of the H8/300
2191 being simulated should be moved to sim_open(). */
2193 /* See if the file is for the H8/300 or H8/300H. */
2194 /* ??? This may not be the most efficient way. The z8k simulator
2195 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2199 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2200 if (prog_bfd
!= NULL
)
2202 /* Set the cpu type. We ignore failure from bfd_check_format
2203 and bfd_openr as sim_load_file checks too. */
2204 if (bfd_check_format (prog_bfd
, bfd_object
))
2206 unsigned long mach
= bfd_get_mach (prog_bfd
);
2207 set_h8300h (mach
== bfd_mach_h8300h
|| mach
== bfd_mach_h8300s
,
2208 mach
== bfd_mach_h8300s
);
2212 /* If we're using gdb attached to the simulator, then we have to
2213 reallocate memory for the simulator.
2215 When gdb first starts, it calls fetch_registers (among other
2216 functions), which in turn calls init_pointers, which allocates
2219 The problem is when we do that, we don't know whether we're
2220 debugging an H8/300 or H8/300H program.
2222 This is the first point at which we can make that determination,
2223 so we just reallocate memory now; this will also allow us to handle
2224 switching between H8/300 and H8/300H programs without exiting
2228 memory_size
= H8300S_MSIZE
;
2229 else if (h8300hmode
)
2230 memory_size
= H8300H_MSIZE
;
2232 memory_size
= H8300_MSIZE
;
2237 free (cpu
.cache_idx
);
2239 free (cpu
.eightbit
);
2241 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2242 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2243 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2245 /* `msize' must be a power of two. */
2246 if ((memory_size
& (memory_size
- 1)) != 0)
2248 cpu
.mask
= memory_size
- 1;
2250 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2251 sim_kind
== SIM_OPEN_DEBUG
,
2255 /* Close the bfd if we opened it. */
2256 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2257 bfd_close (prog_bfd
);
2261 /* Close the bfd if we opened it. */
2262 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2263 bfd_close (prog_bfd
);
2268 sim_create_inferior (sd
, abfd
, argv
, env
)
2275 cpu
.pc
= bfd_get_start_address (abfd
);
2282 sim_do_command (sd
, cmd
)
2286 (*sim_callback
->printf_filtered
) (sim_callback
,
2287 "This simulator does not accept any commands.\n");
2291 sim_set_callbacks (ptr
)
2292 struct host_callback_struct
*ptr
;
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