2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
27 #ifdef HAVE_SYS_PARAM_H
28 #include <sys/param.h>
33 #include "gdb/sim-h8300.h"
35 #include "sys/types.h"
43 host_callback
*sim_callback
;
45 static SIM_OPEN_KIND sim_kind
;
48 /* FIXME: Needs to live in header file.
49 This header should also include the things in remote-sim.h.
50 One could move this to remote-sim.h but this function isn't needed
52 static void set_simcache_size (SIM_DESC
, int);
54 #define X(op, size) (op * 4 + size)
56 #define SP (h8300hmode ? SL : SW)
58 #define h8_opcodes ops
60 #include "opcode/h8300.h"
62 /* CPU data object: */
65 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
67 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
69 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
70 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
72 cpu
->delayed_branch
= 0;
77 /* Initialize local simulator state. */
79 sd
->sim_cache_size
= 0;
85 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
91 h8_get_pc (SIM_DESC sd
)
93 return (STATE_CPU (sd
, 0)) -> pc
;
97 h8_set_pc (SIM_DESC sd
, unsigned int val
)
99 (STATE_CPU (sd
, 0)) -> pc
= val
;
103 h8_get_ccr (SIM_DESC sd
)
105 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
109 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
111 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
115 h8_get_exr (SIM_DESC sd
)
117 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
121 h8_set_exr (SIM_DESC sd
, unsigned int val
)
123 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
127 h8_get_sbr (SIM_DESC sd
)
129 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
133 h8_set_sbr (SIM_DESC sd
, int val
)
135 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
139 h8_get_vbr (SIM_DESC sd
)
141 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
145 h8_set_vbr (SIM_DESC sd
, int val
)
147 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
151 h8_get_cache_top (SIM_DESC sd
)
153 return sd
-> cache_top
;
157 h8_set_cache_top (SIM_DESC sd
, int val
)
159 sd
-> cache_top
= val
;
163 h8_get_mask (SIM_DESC sd
)
165 return (STATE_CPU (sd
, 0)) -> mask
;
169 h8_set_mask (SIM_DESC sd
, int val
)
171 (STATE_CPU (sd
, 0)) -> mask
= val
;
175 h8_get_exception (SIM_DESC sd
)
177 return (STATE_CPU (sd
, 0)) -> exception
;
181 h8_set_exception (SIM_DESC sd
, int val
)
183 (STATE_CPU (sd
, 0)) -> exception
= val
;
186 static enum h8300_sim_state
187 h8_get_state (SIM_DESC sd
)
193 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
199 h8_get_cycles (SIM_DESC sd
)
201 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
205 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
207 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
211 h8_get_insts (SIM_DESC sd
)
213 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
217 h8_set_insts (SIM_DESC sd
, unsigned int val
)
219 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
223 h8_get_ticks (SIM_DESC sd
)
225 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
229 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
231 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
235 h8_get_mach (SIM_DESC sd
)
237 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
241 h8_set_mach (SIM_DESC sd
, unsigned int val
)
243 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
247 h8_get_macl (SIM_DESC sd
)
249 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
253 h8_set_macl (SIM_DESC sd
, unsigned int val
)
255 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
259 h8_get_compiles (SIM_DESC sd
)
261 return sd
-> compiles
;
265 h8_increment_compiles (SIM_DESC sd
)
270 static unsigned int *
271 h8_get_reg_buf (SIM_DESC sd
)
273 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
277 h8_get_reg (SIM_DESC sd
, int regnum
)
279 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
283 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
285 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
290 h8_get_stats (SIM_DESC sd
, int idx
)
292 return sd
-> stats
[idx
];
296 h8_increment_stats (SIM_DESC sd
, int idx
)
302 static unsigned short *
303 h8_get_cache_idx_buf (SIM_DESC sd
)
305 return sd
-> cache_idx
;
309 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
311 sd
-> cache_idx
= ptr
;
314 static unsigned short
315 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
317 if (idx
> sd
->memory_size
)
318 return (unsigned short) -1;
319 return sd
-> cache_idx
[idx
];
323 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
325 sd
-> cache_idx
[idx
] = (unsigned short) val
;
328 static unsigned char *
329 h8_get_memory_buf (SIM_DESC sd
)
331 return (STATE_CPU (sd
, 0)) -> memory
;
335 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
337 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
341 h8_get_memory (SIM_DESC sd
, int idx
)
343 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
347 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
349 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
352 static unsigned char *
353 h8_get_eightbit_buf (SIM_DESC sd
)
355 return (STATE_CPU (sd
, 0)) -> eightbit
;
359 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
361 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
365 h8_get_eightbit (SIM_DESC sd
, int idx
)
367 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
371 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
373 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
377 h8_get_delayed_branch (SIM_DESC sd
)
379 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
383 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
385 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
389 h8_get_command_line (SIM_DESC sd
)
391 return (STATE_CPU (sd
, 0)) -> command_line
;
395 h8_set_command_line (SIM_DESC sd
, char ** val
)
397 (STATE_CPU (sd
, 0)) -> command_line
= val
;
401 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
403 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
407 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
409 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
412 /* MAC Saturation Mode */
414 h8_get_macS (SIM_DESC sd
)
416 return (STATE_CPU (sd
, 0)) -> macS
;
420 h8_set_macS (SIM_DESC sd
, int val
)
422 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
427 h8_get_macZ (SIM_DESC sd
)
429 return (STATE_CPU (sd
, 0)) -> macZ
;
433 h8_set_macZ (SIM_DESC sd
, int val
)
435 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
438 /* MAC Negative Flag */
440 h8_get_macN (SIM_DESC sd
)
442 return (STATE_CPU (sd
, 0)) -> macN
;
446 h8_set_macN (SIM_DESC sd
, int val
)
448 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
451 /* MAC Overflow Flag */
453 h8_get_macV (SIM_DESC sd
)
455 return (STATE_CPU (sd
, 0)) -> macV
;
459 h8_set_macV (SIM_DESC sd
, int val
)
461 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
464 /* End CPU data object. */
466 /* The rate at which to call the host's poll_quit callback. */
468 enum { POLL_QUIT_INTERVAL
= 0x80000 };
470 #define LOW_BYTE(x) ((x) & 0xff)
471 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
472 #define P(X, Y) ((X << 8) | Y)
481 #define I (intMaskBit != 0)
483 #define BUILDSR(SD) \
484 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
485 | (N << 3) | (Z << 2) | (V << 1) | C)
488 /* Get Status Register (flags). */ \
489 c = (h8_get_ccr (sd) >> 0) & 1; \
490 v = (h8_get_ccr (sd) >> 1) & 1; \
491 nz = !((h8_get_ccr (sd) >> 2) & 1); \
492 n = (h8_get_ccr (sd) >> 3) & 1; \
493 u = (h8_get_ccr (sd) >> 4) & 1; \
494 h = (h8_get_ccr (sd) >> 5) & 1; \
495 ui = ((h8_get_ccr (sd) >> 6) & 1); \
496 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
499 #ifdef __CHAR_IS_SIGNED__
500 #define SEXTCHAR(x) ((char) (x))
504 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
507 #define UEXTCHAR(x) ((x) & 0xff)
508 #define UEXTSHORT(x) ((x) & 0xffff)
509 #define SEXTSHORT(x) ((short) (x))
515 static int memory_size
;
520 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
542 return h8300hmode
? SL
: SW
;
547 /* Simulate an indirection / dereference.
548 return 0 for success, -1 for failure.
552 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
554 if (val
== NULL
) /* Paranoia. */
560 if (rn
== ZERO_REGNUM
)
561 *val
= X (OP_IMM
, SP
);
563 *val
= X (OP_REG
, SP
);
566 *val
= X (OP_MEM
, SP
);
569 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
587 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
589 int cst
[3] = {0, 0, 0};
590 int reg
[3] = {0, 0, 0};
591 int rdisp
[3] = {0, 0, 0};
593 const struct h8_opcode
*q
;
598 /* Find the exact opcode/arg combo. */
599 for (q
= h8_opcodes
; q
->name
; q
++)
601 op_type
*nib
= q
->data
.nib
;
602 unsigned int len
= 0;
604 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
605 (q
->available
== AV_H8S
&& !h8300smode
) ||
606 (q
->available
== AV_H8H
&& !h8300hmode
))
611 op_type looking_for
= *nib
;
612 int thisnib
= data
[len
/ 2];
614 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
615 opnum
= ((looking_for
& OP3
) ? 2 :
616 (looking_for
& DST
) ? 1 : 0);
618 if (looking_for
< 16 && looking_for
>= 0)
620 if (looking_for
!= thisnib
)
625 if (looking_for
& B31
)
627 if (!((thisnib
& 0x8) != 0))
630 looking_for
= (op_type
) (looking_for
& ~B31
);
633 else if (looking_for
& B30
)
635 if (!((thisnib
& 0x8) == 0))
638 looking_for
= (op_type
) (looking_for
& ~B30
);
641 if (looking_for
& B21
)
643 if (!((thisnib
& 0x4) != 0))
646 looking_for
= (op_type
) (looking_for
& ~B21
);
649 else if (looking_for
& B20
)
651 if (!((thisnib
& 0x4) == 0))
654 looking_for
= (op_type
) (looking_for
& ~B20
);
657 if (looking_for
& B11
)
659 if (!((thisnib
& 0x2) != 0))
662 looking_for
= (op_type
) (looking_for
& ~B11
);
665 else if (looking_for
& B10
)
667 if (!((thisnib
& 0x2) == 0))
670 looking_for
= (op_type
) (looking_for
& ~B10
);
673 if (looking_for
& B01
)
675 if (!((thisnib
& 0x1) != 0))
678 looking_for
= (op_type
) (looking_for
& ~B01
);
681 else if (looking_for
& B00
)
683 if (!((thisnib
& 0x1) == 0))
686 looking_for
= (op_type
) (looking_for
& ~B00
);
689 if (looking_for
& IGNORE
)
691 /* Hitachi has declared that IGNORE must be zero. */
695 else if ((looking_for
& MODE
) == DATA
)
697 ; /* Skip embedded data. */
699 else if ((looking_for
& MODE
) == DBIT
)
701 /* Exclude adds/subs by looking at bit 0 and 2, and
702 make sure the operand size, either w or l,
703 matches by looking at bit 1. */
704 if ((looking_for
& 7) != (thisnib
& 7))
707 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
709 else if ((looking_for
& MODE
) == REG
||
710 (looking_for
& MODE
) == LOWREG
||
711 (looking_for
& MODE
) == IND
||
712 (looking_for
& MODE
) == PREINC
||
713 (looking_for
& MODE
) == POSTINC
||
714 (looking_for
& MODE
) == PREDEC
||
715 (looking_for
& MODE
) == POSTDEC
)
717 reg
[opnum
] = thisnib
;
719 else if (looking_for
& CTRL
)
722 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
723 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
724 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
725 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
726 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
727 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
729 if (((looking_for
& MODE
) == CCR_EXR
&&
730 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
731 ((looking_for
& MODE
) == VBR_SBR
&&
732 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
733 ((looking_for
& MODE
) == MACREG
&&
734 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
736 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
737 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
738 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
741 reg
[opnum
] = thisnib
;
743 else if ((looking_for
& MODE
) == ABS
)
745 /* Absolute addresses are unsigned. */
746 switch (looking_for
& SIZE
)
749 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
753 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
757 (data
[len
/ 2 + 0] << 24) +
758 (data
[len
/ 2 + 1] << 16) +
759 (data
[len
/ 2 + 2] << 8) +
763 printf ("decode: bad size ABS: %d\n",
764 (looking_for
& SIZE
));
768 else if ((looking_for
& MODE
) == DISP
||
769 (looking_for
& MODE
) == PCREL
||
770 (looking_for
& MODE
) == INDEXB
||
771 (looking_for
& MODE
) == INDEXW
||
772 (looking_for
& MODE
) == INDEXL
)
775 switch (looking_for
& SIZE
)
778 cst
[opnum
] = thisnib
& 3;
780 /* DISP2 special treatment. */
781 if ((looking_for
& MODE
) == DISP
)
783 switch (OP_SIZE (q
->how
)) {
795 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
798 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
799 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
802 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
806 (data
[len
/ 2 + 0] << 24) +
807 (data
[len
/ 2 + 1] << 16) +
808 (data
[len
/ 2 + 2] << 8) +
812 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
813 (looking_for
& SIZE
));
817 else if ((looking_for
& SIZE
) == L_16
||
818 (looking_for
& SIZE
) == L_16U
)
820 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
821 /* Immediates are always unsigned. */
822 if ((looking_for
& SIZE
) != L_16U
&&
823 (looking_for
& MODE
) != IMM
)
824 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
826 else if (looking_for
& ABSJMP
)
828 switch (looking_for
& SIZE
) {
830 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
834 (data
[len
/ 2 + 0] << 24) +
835 (data
[len
/ 2 + 1] << 16) +
836 (data
[len
/ 2 + 2] << 8) +
840 printf ("decode: bad size ABSJMP: %d\n",
841 (looking_for
& SIZE
));
845 else if ((looking_for
& MODE
) == MEMIND
)
847 cst
[opnum
] = data
[1];
849 else if ((looking_for
& MODE
) == VECIND
)
851 /* FIXME: Multiplier should be 2 for "normal" mode. */
852 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
853 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
855 else if ((looking_for
& SIZE
) == L_32
)
860 (data
[i
+ 0] << 24) |
861 (data
[i
+ 1] << 16) |
865 else if ((looking_for
& SIZE
) == L_24
)
870 (data
[i
+ 0] << 16) |
874 else if (looking_for
& DISPREG
)
876 rdisp
[opnum
] = thisnib
& 0x7;
878 else if ((looking_for
& MODE
) == KBIT
)
895 else if ((looking_for
& SIZE
) == L_8
)
897 if ((looking_for
& MODE
) == ABS
)
899 /* Will be combined with contents of SBR_REGNUM
900 by fetch (). For all modes except h8sx, this
901 will always contain the value 0xFFFFFF00. */
902 cst
[opnum
] = data
[len
/ 2] & 0xff;
906 cst
[opnum
] = data
[len
/ 2] & 0xff;
909 else if ((looking_for
& SIZE
) == L_2
)
911 cst
[opnum
] = thisnib
& 3;
913 else if ((looking_for
& SIZE
) == L_3
||
914 (looking_for
& SIZE
) == L_3NZ
)
916 cst
[opnum
] = thisnib
& 7;
917 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
920 else if ((looking_for
& SIZE
) == L_4
)
922 cst
[opnum
] = thisnib
& 15;
924 else if ((looking_for
& SIZE
) == L_5
)
926 cst
[opnum
] = data
[len
/ 2] & 0x1f;
928 else if (looking_for
== E
)
933 /* Fill in the args. */
935 op_type
*args
= q
->args
.nib
;
940 nargs
< 3 && *args
!= E
;
946 opnum
= ((x
& OP3
) ? 2 :
955 if ((x
& MODE
) == IMM
||
956 (x
& MODE
) == KBIT
||
959 /* Use the instruction to determine
961 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
962 p
->literal
= cst
[opnum
];
964 else if ((x
& MODE
) == CONST_2
||
965 (x
& MODE
) == CONST_4
||
966 (x
& MODE
) == CONST_8
||
967 (x
& MODE
) == CONST_16
)
969 /* Use the instruction to determine
971 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
973 case CONST_2
: p
->literal
= 2; break;
974 case CONST_4
: p
->literal
= 4; break;
975 case CONST_8
: p
->literal
= 8; break;
976 case CONST_16
: p
->literal
= 16; break;
979 else if ((x
& MODE
) == REG
)
981 p
->type
= X (OP_REG
, bitfrom (x
));
984 else if ((x
& MODE
) == LOWREG
)
986 p
->type
= X (OP_LOWREG
, bitfrom (x
));
989 else if ((x
& MODE
) == PREINC
)
991 /* Use the instruction to determine
993 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
994 p
->reg
= reg
[opnum
] & 0x7;
996 else if ((x
& MODE
) == POSTINC
)
998 /* Use the instruction to determine
1000 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
1001 p
->reg
= reg
[opnum
] & 0x7;
1003 else if ((x
& MODE
) == PREDEC
)
1005 /* Use the instruction to determine
1006 the operand size. */
1007 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
1008 p
->reg
= reg
[opnum
] & 0x7;
1010 else if ((x
& MODE
) == POSTDEC
)
1012 /* Use the instruction to determine
1013 the operand size. */
1014 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
1015 p
->reg
= reg
[opnum
] & 0x7;
1017 else if ((x
& MODE
) == IND
)
1019 /* Note: an indirect is transformed into
1020 a displacement of zero.
1022 /* Use the instruction to determine
1023 the operand size. */
1024 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1025 p
->reg
= reg
[opnum
] & 0x7;
1027 if (OP_KIND (q
->how
) == O_JSR
||
1028 OP_KIND (q
->how
) == O_JMP
)
1029 if (lvalue (sd
, p
->type
, p
->reg
, &p
->type
))
1032 else if ((x
& MODE
) == ABS
)
1034 /* Note: a 16 or 32 bit ABS is transformed into a
1035 displacement from pseudo-register ZERO_REGNUM,
1036 which is always zero. An 8 bit ABS becomes
1037 a displacement from SBR_REGNUM.
1039 /* Use the instruction to determine
1040 the operand size. */
1041 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1042 p
->literal
= cst
[opnum
];
1044 /* 8-bit ABS is displacement from SBR.
1045 16 and 32-bit ABS are displacement from ZERO.
1046 (SBR will always be zero except for h8/sx)
1048 if ((x
& SIZE
) == L_8
)
1049 p
->reg
= SBR_REGNUM
;
1051 p
->reg
= ZERO_REGNUM
;;
1053 else if ((x
& MODE
) == MEMIND
||
1054 (x
& MODE
) == VECIND
)
1056 /* Size doesn't matter. */
1057 p
->type
= X (OP_MEM
, SB
);
1058 p
->literal
= cst
[opnum
];
1059 if (OP_KIND (q
->how
) == O_JSR
||
1060 OP_KIND (q
->how
) == O_JMP
)
1061 if (lvalue (sd
, p
->type
, p
->reg
, &p
->type
))
1064 else if ((x
& MODE
) == PCREL
)
1066 /* Size doesn't matter. */
1067 p
->type
= X (OP_PCREL
, SB
);
1068 p
->literal
= cst
[opnum
];
1070 else if (x
& ABSJMP
)
1072 p
->type
= X (OP_IMM
, SP
);
1073 p
->literal
= cst
[opnum
];
1075 else if ((x
& MODE
) == INDEXB
||
1076 (x
& MODE
) == INDEXW
||
1077 (x
& MODE
) == INDEXL
||
1080 /* Use the instruction to determine
1081 the operand size. */
1084 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1087 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1090 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1093 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1097 p
->literal
= cst
[opnum
];
1098 p
->reg
= rdisp
[opnum
];
1105 p
->type
= X (OP_CCR
, SB
);
1108 p
->type
= X (OP_EXR
, SB
);
1111 p
->type
= X (OP_MACH
, SL
);
1114 p
->type
= X (OP_MACL
, SL
);
1117 p
->type
= X (OP_VBR
, SL
);
1120 p
->type
= X (OP_SBR
, SL
);
1124 else if ((x
& MODE
) == CCR
)
1128 else if ((x
& MODE
) == EXR
)
1133 printf ("Hmmmm 0x%x...\n", x
);
1139 /* Unary operators: treat src and dst as equivalent. */
1140 if (dst
->dst
.type
== -1)
1141 dst
->dst
= dst
->src
;
1142 if (dst
->src
.type
== -1)
1143 dst
->src
= dst
->dst
;
1145 dst
->opcode
= q
->how
;
1146 dst
->cycles
= q
->time
;
1148 /* And jsr's to these locations are turned into
1151 if (OP_KIND (dst
->opcode
) == O_JSR
)
1153 switch (dst
->src
.literal
)
1156 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1159 dst
->opcode
= O (O_SYS_READ
, SB
);
1162 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1165 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1168 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1171 dst
->opcode
= O (O_SYS_STAT
, SB
);
1174 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1177 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1180 /* End of Processing for system calls. */
1183 dst
->next_pc
= addr
+ len
/ 2;
1187 printf ("Don't understand 0x%x \n", looking_for
);
1198 /* Fell off the end. */
1199 dst
->opcode
= O (O_ILL
, SB
);
1203 compile (SIM_DESC sd
, int pc
)
1207 /* Find the next cache entry to use. */
1208 idx
= h8_get_cache_top (sd
) + 1;
1209 h8_increment_compiles (sd
);
1210 if (idx
>= sd
->sim_cache_size
)
1214 h8_set_cache_top (sd
, idx
);
1216 /* Throw away its old meaning. */
1217 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1219 /* Set to new address. */
1220 sd
->sim_cache
[idx
].oldpc
= pc
;
1222 /* Fill in instruction info. */
1223 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1225 /* Point to new cache entry. */
1226 h8_set_cache_idx (sd
, pc
, idx
);
1230 static unsigned char *breg
[32];
1231 static unsigned short *wreg
[16];
1232 static unsigned int *lreg
[18];
1234 #define GET_B_REG(X) *(breg[X])
1235 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1236 #define GET_W_REG(X) *(wreg[X])
1237 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1238 #define GET_L_REG(X) h8_get_reg (sd, X)
1239 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1241 #define GET_MEMORY_L(X) \
1242 ((X) < memory_size \
1243 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1244 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1245 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1246 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1247 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1248 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1250 #define GET_MEMORY_W(X) \
1251 ((X) < memory_size \
1252 ? ((h8_get_memory (sd, (X)+0) << 8) \
1253 | (h8_get_memory (sd, (X)+1) << 0)) \
1254 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1255 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1258 #define GET_MEMORY_B(X) \
1259 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1260 : (h8_get_eightbit (sd, (X) & 0xff)))
1262 #define SET_MEMORY_L(X, Y) \
1263 { register unsigned char *_p; register int __y = (Y); \
1264 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1265 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1266 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1267 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1270 #define SET_MEMORY_W(X, Y) \
1271 { register unsigned char *_p; register int __y = (Y); \
1272 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1273 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1274 _p[0] = __y >> 8; _p[1] = __y; \
1277 #define SET_MEMORY_B(X, Y) \
1278 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1279 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1281 /* Simulate a memory fetch.
1282 Return 0 for success, -1 for failure.
1286 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1289 int abs
= arg
->literal
;
1294 return -1; /* Paranoia. */
1298 /* Indexed register plus displacement mode:
1300 This new family of addressing modes are similar to OP_DISP
1301 (register plus displacement), with two differences:
1302 1) INDEXB uses only the least significant byte of the register,
1303 INDEXW uses only the least significant word, and
1304 INDEXL uses the entire register (just like OP_DISP).
1306 2) The displacement value in abs is multiplied by two
1307 for SW-sized operations, and by four for SL-size.
1309 This gives nine possible variations.
1312 case X (OP_INDEXB
, SB
):
1313 case X (OP_INDEXB
, SW
):
1314 case X (OP_INDEXB
, SL
):
1315 case X (OP_INDEXW
, SB
):
1316 case X (OP_INDEXW
, SW
):
1317 case X (OP_INDEXW
, SL
):
1318 case X (OP_INDEXL
, SB
):
1319 case X (OP_INDEXL
, SW
):
1320 case X (OP_INDEXL
, SL
):
1322 switch (OP_KIND (arg
->type
)) {
1323 case OP_INDEXB
: t
&= 0xff; break;
1324 case OP_INDEXW
: t
&= 0xffff; break;
1328 switch (OP_SIZE (arg
->type
)) {
1330 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1333 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1336 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1341 case X (OP_LOWREG
, SB
):
1342 *val
= GET_L_REG (rn
) & 0xff;
1344 case X (OP_LOWREG
, SW
):
1345 *val
= GET_L_REG (rn
) & 0xffff;
1348 case X (OP_REG
, SB
): /* Register direct, byte. */
1349 *val
= GET_B_REG (rn
);
1351 case X (OP_REG
, SW
): /* Register direct, word. */
1352 *val
= GET_W_REG (rn
);
1354 case X (OP_REG
, SL
): /* Register direct, long. */
1355 *val
= GET_L_REG (rn
);
1357 case X (OP_IMM
, SB
): /* Immediate, byte. */
1358 case X (OP_IMM
, SW
): /* Immediate, word. */
1359 case X (OP_IMM
, SL
): /* Immediate, long. */
1362 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1364 t
&= h8_get_mask (sd
);
1365 r
= GET_MEMORY_B (t
);
1368 t
= t
& h8_get_mask (sd
);
1372 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1374 t
&= h8_get_mask (sd
);
1375 r
= GET_MEMORY_W (t
);
1378 t
= t
& h8_get_mask (sd
);
1382 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1384 t
&= h8_get_mask (sd
);
1385 r
= GET_MEMORY_L (t
);
1388 t
= t
& h8_get_mask (sd
);
1393 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1395 t
&= h8_get_mask (sd
);
1396 r
= GET_MEMORY_B (t
);
1399 t
= t
& h8_get_mask (sd
);
1403 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1405 t
&= h8_get_mask (sd
);
1406 r
= GET_MEMORY_W (t
);
1409 t
= t
& h8_get_mask (sd
);
1413 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1415 t
&= h8_get_mask (sd
);
1416 r
= GET_MEMORY_L (t
);
1419 t
= t
& h8_get_mask (sd
);
1424 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1425 t
= GET_L_REG (rn
) - 1;
1426 t
&= h8_get_mask (sd
);
1428 *val
= GET_MEMORY_B (t
);
1431 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1432 t
= GET_L_REG (rn
) - 2;
1433 t
&= h8_get_mask (sd
);
1435 *val
= GET_MEMORY_W (t
);
1438 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1439 t
= GET_L_REG (rn
) - 4;
1440 t
&= h8_get_mask (sd
);
1442 *val
= GET_MEMORY_L (t
);
1445 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1446 t
= GET_L_REG (rn
) + 1;
1447 t
&= h8_get_mask (sd
);
1449 *val
= GET_MEMORY_B (t
);
1452 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1453 t
= GET_L_REG (rn
) + 2;
1454 t
&= h8_get_mask (sd
);
1456 *val
= GET_MEMORY_W (t
);
1459 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1460 t
= GET_L_REG (rn
) + 4;
1461 t
&= h8_get_mask (sd
);
1463 *val
= GET_MEMORY_L (t
);
1466 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1467 t
= GET_L_REG (rn
) + abs
;
1468 t
&= h8_get_mask (sd
);
1469 *val
= GET_MEMORY_B (t
);
1472 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1473 t
= GET_L_REG (rn
) + abs
;
1474 t
&= h8_get_mask (sd
);
1475 *val
= GET_MEMORY_W (t
);
1478 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1479 t
= GET_L_REG (rn
) + abs
;
1480 t
&= h8_get_mask (sd
);
1481 *val
=GET_MEMORY_L (t
);
1484 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1485 t
= GET_MEMORY_L (abs
);
1486 t
&= h8_get_mask (sd
);
1490 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1491 t
= GET_MEMORY_W (abs
);
1492 t
&= h8_get_mask (sd
);
1496 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1497 case X (OP_PCREL
, SW
):
1498 case X (OP_PCREL
, SL
):
1499 case X (OP_PCREL
, SN
):
1503 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1505 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1508 return 0; /* Success. */
1514 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1516 return fetch_1 (sd
, arg
, val
, 0);
1519 /* Fetch which will be followed by a store to the same location.
1520 The difference being that we don't want to do a post-increment
1521 or post-decrement at this time: we'll do it when we store. */
1524 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1526 return fetch_1 (sd
, arg
, val
, 1);
1529 /* Simulate a memory store.
1530 Return 0 for success, -1 for failure.
1534 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1537 int abs
= arg
->literal
;
1542 /* Indexed register plus displacement mode:
1544 This new family of addressing modes are similar to OP_DISP
1545 (register plus displacement), with two differences:
1546 1) INDEXB uses only the least significant byte of the register,
1547 INDEXW uses only the least significant word, and
1548 INDEXL uses the entire register (just like OP_DISP).
1550 2) The displacement value in abs is multiplied by two
1551 for SW-sized operations, and by four for SL-size.
1553 This gives nine possible variations.
1556 case X (OP_INDEXB
, SB
):
1557 case X (OP_INDEXB
, SW
):
1558 case X (OP_INDEXB
, SL
):
1559 case X (OP_INDEXW
, SB
):
1560 case X (OP_INDEXW
, SW
):
1561 case X (OP_INDEXW
, SL
):
1562 case X (OP_INDEXL
, SB
):
1563 case X (OP_INDEXL
, SW
):
1564 case X (OP_INDEXL
, SL
):
1566 switch (OP_KIND (arg
->type
)) {
1567 case OP_INDEXB
: t
&= 0xff; break;
1568 case OP_INDEXW
: t
&= 0xffff; break;
1572 switch (OP_SIZE (arg
->type
)) {
1574 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1577 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1580 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1585 case X (OP_REG
, SB
): /* Register direct, byte. */
1588 case X (OP_REG
, SW
): /* Register direct, word. */
1591 case X (OP_REG
, SL
): /* Register direct, long. */
1595 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1599 t
&= h8_get_mask (sd
);
1601 SET_MEMORY_B (t
, n
);
1604 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1608 t
&= h8_get_mask (sd
);
1610 SET_MEMORY_W (t
, n
);
1613 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1617 t
&= h8_get_mask (sd
);
1619 SET_MEMORY_L (t
, n
);
1622 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1626 t
&= h8_get_mask (sd
);
1628 SET_MEMORY_B (t
, n
);
1631 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1635 t
&= h8_get_mask (sd
);
1637 SET_MEMORY_W (t
, n
);
1640 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1644 t
&= h8_get_mask (sd
);
1646 SET_MEMORY_L (t
, n
);
1649 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1650 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1651 SET_MEMORY_B (t
, n
);
1652 SET_L_REG (rn
, t
- 1);
1655 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1656 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1657 SET_MEMORY_W (t
, n
);
1658 SET_L_REG (rn
, t
- 2);
1661 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1662 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1663 SET_MEMORY_L (t
, n
);
1664 SET_L_REG (rn
, t
- 4);
1667 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1668 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1669 SET_MEMORY_B (t
, n
);
1670 SET_L_REG (rn
, t
+ 1);
1673 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1674 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1675 SET_MEMORY_W (t
, n
);
1676 SET_L_REG (rn
, t
+ 2);
1679 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1680 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1681 SET_MEMORY_L (t
, n
);
1682 SET_L_REG (rn
, t
+ 4);
1685 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1686 t
= GET_L_REG (rn
) + abs
;
1687 t
&= h8_get_mask (sd
);
1688 SET_MEMORY_B (t
, n
);
1691 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1692 t
= GET_L_REG (rn
) + abs
;
1693 t
&= h8_get_mask (sd
);
1694 SET_MEMORY_W (t
, n
);
1697 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1698 t
= GET_L_REG (rn
) + abs
;
1699 t
&= h8_get_mask (sd
);
1700 SET_MEMORY_L (t
, n
);
1704 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1705 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1706 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1708 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1717 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1719 return store_1 (sd
, arg
, n
, 0);
1722 /* Store which follows a fetch from the same location.
1723 The difference being that we don't want to do a pre-increment
1724 or pre-decrement at this time: it was already done when we fetched. */
1727 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1729 return store_1 (sd
, arg
, n
, 1);
1743 /* Flag to be set whenever a new SIM_DESC object is created. */
1744 static int init_pointers_needed
= 1;
1747 init_pointers (SIM_DESC sd
)
1749 if (init_pointers_needed
)
1756 memory_size
= H8300S_MSIZE
;
1757 else if (h8300hmode
)
1758 memory_size
= H8300H_MSIZE
;
1760 memory_size
= H8300_MSIZE
;
1761 /* `msize' must be a power of two. */
1762 if ((memory_size
& (memory_size
- 1)) != 0)
1764 (*sim_callback
->printf_filtered
)
1766 "init_pointers: bad memory size %d, defaulting to %d.\n",
1767 memory_size
, memory_size
= H8300S_MSIZE
);
1770 if (h8_get_memory_buf (sd
))
1771 free (h8_get_memory_buf (sd
));
1772 if (h8_get_cache_idx_buf (sd
))
1773 free (h8_get_cache_idx_buf (sd
));
1774 if (h8_get_eightbit_buf (sd
))
1775 free (h8_get_eightbit_buf (sd
));
1777 h8_set_memory_buf (sd
, (unsigned char *)
1778 calloc (sizeof (char), memory_size
));
1779 h8_set_cache_idx_buf (sd
, (unsigned short *)
1780 calloc (sizeof (short), memory_size
));
1781 sd
->memory_size
= memory_size
;
1782 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1784 h8_set_mask (sd
, memory_size
- 1);
1786 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1788 for (i
= 0; i
< 8; i
++)
1790 /* FIXME: rewrite using local buffer. */
1791 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1792 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1793 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1794 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1795 h8_set_reg (sd
, i
, 0x00112233);
1810 wreg
[i
] = wreg
[i
+ 8] = 0;
1824 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1825 (*sim_callback
->printf_filtered
) (sim_callback
,
1826 "init_pointers: internal error.\n");
1828 h8_set_reg (sd
, i
, 0);
1829 lreg
[i
] = h8_get_reg_buf (sd
) + i
;
1832 /* Note: sim uses pseudo-register ZERO as a zero register. */
1833 lreg
[ZERO_REGNUM
] = h8_get_reg_buf (sd
) + ZERO_REGNUM
;
1834 init_pointers_needed
= 0;
1836 /* Initialize the seg registers. */
1838 set_simcache_size (sd
, CSIZE
);
1842 /* Grotty global variable for use by control_c signal handler. */
1843 static SIM_DESC control_c_sim_desc
;
1848 sim_engine_set_run_state (control_c_sim_desc
, sim_stopped
, SIGINT
);
1852 sim_stop (SIM_DESC sd
)
1854 /* FIXME: use a real signal value. */
1855 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
1859 #define OBITOP(name, f, s, op) \
1860 case O (name, SB): \
1865 if (fetch (sd, &code->dst, &ea)) \
1867 if (fetch (sd, &code->src, &tmp)) \
1872 if (store (sd, &code->dst,ea)) \
1878 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1883 int tick_start
= get_now ();
1892 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1895 enum sim_stop reason
;
1900 control_c_sim_desc
= sd
;
1901 prev
= signal (SIGINT
, control_c
);
1905 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
1909 sim_engine_set_run_state (sd
, sim_running
, 0);
1912 pc
= h8_get_pc (sd
);
1914 /* The PC should never be odd. */
1917 sim_engine_set_run_state (sd
, sim_stopped
, SIGBUS
);
1921 /* Get Status Register (flags). */
1924 if (h8300smode
) /* Get exr. */
1926 trace
= (h8_get_exr (sd
) >> 7) & 1;
1927 intMask
= h8_get_exr (sd
) & 7;
1930 oldmask
= h8_get_mask (sd
);
1932 h8_set_mask (sd
, 0xffff);
1935 unsigned short cidx
;
1939 cidx
= h8_get_cache_idx (sd
, pc
);
1940 if (cidx
== (unsigned short) -1 ||
1941 cidx
>= sd
->sim_cache_size
)
1944 code
= sd
->sim_cache
+ cidx
;
1949 printf ("%x %d %s\n", pc
, code
->opcode
,
1950 code
->op
? code
->op
->name
: "**");
1952 h8_increment_stats (sd
, code
->opcode
);
1957 cycles
+= code
->cycles
;
1961 switch (code
->opcode
)
1965 * This opcode is a fake for when we get to an
1966 * instruction which hasnt been compiled
1972 case O (O_MOVAB
, SL
):
1973 case O (O_MOVAW
, SL
):
1974 case O (O_MOVAL
, SL
):
1975 /* 1) Evaluate 2nd argument (dst).
1976 2) Mask / zero extend according to whether 1st argument (src)
1977 is INDEXB, INDEXW, or INDEXL.
1978 3) Left-shift the result by 0, 1 or 2, according to size of mova
1979 (mova/b, mova/w, mova/l).
1980 4) Add literal value of 1st argument (src).
1981 5) Store result in 3rd argument (op3).
1984 if (fetch (sd
, &code
->dst
, &ea
))
1987 switch (OP_KIND (code
->src
.type
)) {
1988 case OP_INDEXB
: ea
= ea
& 0xff; break;
1989 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1990 case OP_INDEXL
: break;
1991 default: goto illegal
;
1994 switch (code
->opcode
) {
1995 case O (O_MOVAB
, SL
): break;
1996 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1997 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1998 default: goto illegal
;
2001 ea
= ea
+ code
->src
.literal
;
2003 if (store (sd
, &code
->op3
, ea
))
2008 case O (O_SUBX
, SB
): /* subx, extended sub */
2009 if (fetch2 (sd
, &code
->dst
, &rd
))
2011 if (fetch (sd
, &code
->src
, &ea
))
2017 case O (O_SUBX
, SW
): /* subx, extended sub */
2018 if (fetch2 (sd
, &code
->dst
, &rd
))
2020 if (fetch (sd
, &code
->src
, &ea
))
2026 case O (O_SUBX
, SL
): /* subx, extended sub */
2027 if (fetch2 (sd
, &code
->dst
, &rd
))
2029 if (fetch (sd
, &code
->src
, &ea
))
2035 case O (O_ADDX
, SB
): /* addx, extended add */
2036 if (fetch2 (sd
, &code
->dst
, &rd
))
2038 if (fetch (sd
, &code
->src
, &ea
))
2044 case O (O_ADDX
, SW
): /* addx, extended add */
2045 if (fetch2 (sd
, &code
->dst
, &rd
))
2047 if (fetch (sd
, &code
->src
, &ea
))
2053 case O (O_ADDX
, SL
): /* addx, extended add */
2054 if (fetch2 (sd
, &code
->dst
, &rd
))
2056 if (fetch (sd
, &code
->src
, &ea
))
2062 case O (O_SUB
, SB
): /* sub.b */
2063 /* Fetch rd and ea. */
2064 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2070 case O (O_SUB
, SW
): /* sub.w */
2071 /* Fetch rd and ea. */
2072 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2078 case O (O_SUB
, SL
): /* sub.l */
2079 /* Fetch rd and ea. */
2080 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2086 case O (O_NEG
, SB
): /* neg.b */
2088 if (fetch2 (sd
, &code
->src
, &ea
))
2095 case O (O_NEG
, SW
): /* neg.w */
2097 if (fetch2 (sd
, &code
->src
, &ea
))
2104 case O (O_NEG
, SL
): /* neg.l */
2106 if (fetch2 (sd
, &code
->src
, &ea
))
2113 case O (O_ADD
, SB
): /* add.b */
2114 if (fetch2 (sd
, &code
->dst
, &rd
))
2116 if (fetch (sd
, &code
->src
, &ea
))
2121 case O (O_ADD
, SW
): /* add.w */
2122 if (fetch2 (sd
, &code
->dst
, &rd
))
2124 if (fetch (sd
, &code
->src
, &ea
))
2129 case O (O_ADD
, SL
): /* add.l */
2130 if (fetch2 (sd
, &code
->dst
, &rd
))
2132 if (fetch (sd
, &code
->src
, &ea
))
2137 case O (O_AND
, SB
): /* and.b */
2138 /* Fetch rd and ea. */
2139 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2144 case O (O_AND
, SW
): /* and.w */
2145 /* Fetch rd and ea. */
2146 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2151 case O (O_AND
, SL
): /* and.l */
2152 /* Fetch rd and ea. */
2153 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2158 case O (O_OR
, SB
): /* or.b */
2159 /* Fetch rd and ea. */
2160 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2165 case O (O_OR
, SW
): /* or.w */
2166 /* Fetch rd and ea. */
2167 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2172 case O (O_OR
, SL
): /* or.l */
2173 /* Fetch rd and ea. */
2174 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2179 case O (O_XOR
, SB
): /* xor.b */
2180 /* Fetch rd and ea. */
2181 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2186 case O (O_XOR
, SW
): /* xor.w */
2187 /* Fetch rd and ea. */
2188 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2193 case O (O_XOR
, SL
): /* xor.l */
2194 /* Fetch rd and ea. */
2195 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2201 if (fetch (sd
, &code
->src
, &res
))
2203 if (store (sd
, &code
->dst
, res
))
2205 goto just_flags_log8
;
2207 if (fetch (sd
, &code
->src
, &res
))
2209 if (store (sd
, &code
->dst
, res
))
2211 goto just_flags_log16
;
2213 if (fetch (sd
, &code
->src
, &res
))
2215 if (store (sd
, &code
->dst
, res
))
2217 goto just_flags_log32
;
2219 case O (O_MOVMD
, SB
): /* movmd.b */
2226 rd
= GET_MEMORY_B (GET_L_REG (5));
2227 SET_MEMORY_B (GET_L_REG (6), rd
);
2228 SET_L_REG (5, GET_L_REG (5) + 1);
2229 SET_L_REG (6, GET_L_REG (6) + 1);
2234 case O (O_MOVMD
, SW
): /* movmd.w */
2241 rd
= GET_MEMORY_W (GET_L_REG (5));
2242 SET_MEMORY_W (GET_L_REG (6), rd
);
2243 SET_L_REG (5, GET_L_REG (5) + 2);
2244 SET_L_REG (6, GET_L_REG (6) + 2);
2249 case O (O_MOVMD
, SL
): /* movmd.l */
2256 rd
= GET_MEMORY_L (GET_L_REG (5));
2257 SET_MEMORY_L (GET_L_REG (6), rd
);
2258 SET_L_REG (5, GET_L_REG (5) + 4);
2259 SET_L_REG (6, GET_L_REG (6) + 4);
2264 case O (O_MOVSD
, SB
): /* movsd.b */
2265 /* This instruction implements strncpy, with a conditional branch.
2266 r4 contains n, r5 contains src, and r6 contains dst.
2267 The 16-bit displacement operand is added to the pc
2268 if and only if the end of string is reached before
2269 n bytes are transferred. */
2271 ea
= GET_L_REG (4) & 0xffff;
2277 rd
= GET_MEMORY_B (GET_L_REG (5));
2278 SET_MEMORY_B (GET_L_REG (6), rd
);
2279 SET_L_REG (5, GET_L_REG (5) + 1);
2280 SET_L_REG (6, GET_L_REG (6) + 1);
2287 case O (O_EEPMOV
, SB
): /* eepmov.b */
2288 case O (O_EEPMOV
, SW
): /* eepmov.w */
2289 if (h8300hmode
|| h8300smode
)
2291 register unsigned char *_src
, *_dst
;
2292 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2293 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2294 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2296 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2297 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2298 : h8_get_eightbit_buf (sd
) +
2299 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2300 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2302 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2305 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2306 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2307 : h8_get_eightbit_buf (sd
) +
2308 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2310 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2312 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2315 memcpy (_dst
, _src
, count
);
2317 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2318 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2319 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2320 ((code
->opcode
== O (O_EEPMOV
, SW
))
2321 ? (~0xffff) : (~0xff)));
2322 cycles
+= 2 * count
;
2327 case O (O_ADDS
, SL
): /* adds (.l) */
2329 * This insn only uses register operands, but still
2330 * it would be cleaner to use fetch and store... */
2331 SET_L_REG (code
->dst
.reg
,
2332 GET_L_REG (code
->dst
.reg
)
2333 + code
->src
.literal
);
2337 case O (O_SUBS
, SL
): /* subs (.l) */
2339 * This insn only uses register operands, but still
2340 * it would be cleaner to use fetch and store... */
2341 SET_L_REG (code
->dst
.reg
,
2342 GET_L_REG (code
->dst
.reg
)
2343 - code
->src
.literal
);
2346 case O (O_CMP
, SB
): /* cmp.b */
2347 if (fetch (sd
, &code
->dst
, &rd
))
2349 if (fetch (sd
, &code
->src
, &ea
))
2353 goto just_flags_alu8
;
2355 case O (O_CMP
, SW
): /* cmp.w */
2356 if (fetch (sd
, &code
->dst
, &rd
))
2358 if (fetch (sd
, &code
->src
, &ea
))
2362 goto just_flags_alu16
;
2364 case O (O_CMP
, SL
): /* cmp.l */
2365 if (fetch (sd
, &code
->dst
, &rd
))
2367 if (fetch (sd
, &code
->src
, &ea
))
2371 goto just_flags_alu32
;
2373 case O (O_DEC
, SB
): /* dec.b */
2375 * This insn only uses register operands, but still
2376 * it would be cleaner to use fetch and store... */
2377 rd
= GET_B_REG (code
->src
.reg
);
2380 SET_B_REG (code
->src
.reg
, res
);
2381 goto just_flags_inc8
;
2383 case O (O_DEC
, SW
): /* dec.w */
2385 * This insn only uses register operands, but still
2386 * it would be cleaner to use fetch and store... */
2387 rd
= GET_W_REG (code
->dst
.reg
);
2388 ea
= -code
->src
.literal
;
2390 SET_W_REG (code
->dst
.reg
, res
);
2391 goto just_flags_inc16
;
2393 case O (O_DEC
, SL
): /* dec.l */
2395 * This insn only uses register operands, but still
2396 * it would be cleaner to use fetch and store... */
2397 rd
= GET_L_REG (code
->dst
.reg
);
2398 ea
= -code
->src
.literal
;
2400 SET_L_REG (code
->dst
.reg
, res
);
2401 goto just_flags_inc32
;
2403 case O (O_INC
, SB
): /* inc.b */
2405 * This insn only uses register operands, but still
2406 * it would be cleaner to use fetch and store... */
2407 rd
= GET_B_REG (code
->src
.reg
);
2410 SET_B_REG (code
->src
.reg
, res
);
2411 goto just_flags_inc8
;
2413 case O (O_INC
, SW
): /* inc.w */
2415 * This insn only uses register operands, but still
2416 * it would be cleaner to use fetch and store... */
2417 rd
= GET_W_REG (code
->dst
.reg
);
2418 ea
= code
->src
.literal
;
2420 SET_W_REG (code
->dst
.reg
, res
);
2421 goto just_flags_inc16
;
2423 case O (O_INC
, SL
): /* inc.l */
2425 * This insn only uses register operands, but still
2426 * it would be cleaner to use fetch and store... */
2427 rd
= GET_L_REG (code
->dst
.reg
);
2428 ea
= code
->src
.literal
;
2430 SET_L_REG (code
->dst
.reg
, res
);
2431 goto just_flags_inc32
;
2433 case O (O_LDC
, SB
): /* ldc.b */
2434 if (fetch (sd
, &code
->src
, &res
))
2438 case O (O_LDC
, SW
): /* ldc.w */
2439 if (fetch (sd
, &code
->src
, &res
))
2442 /* Word operand, value from MSB, must be shifted. */
2446 case O (O_LDC
, SL
): /* ldc.l */
2447 if (fetch (sd
, &code
->src
, &res
))
2449 switch (code
->dst
.type
) {
2450 case X (OP_SBR
, SL
):
2451 h8_set_sbr (sd
, res
);
2453 case X (OP_VBR
, SL
):
2454 h8_set_vbr (sd
, res
);
2461 case O (O_STC
, SW
): /* stc.w */
2462 case O (O_STC
, SB
): /* stc.b */
2463 if (code
->src
.type
== X (OP_CCR
, SB
))
2466 res
= h8_get_ccr (sd
);
2468 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2471 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2472 res
= h8_get_exr (sd
);
2477 /* Word operand, value to MSB, must be shifted. */
2478 if (code
->opcode
== X (O_STC
, SW
))
2480 if (store (sd
, &code
->dst
, res
))
2483 case O (O_STC
, SL
): /* stc.l */
2484 switch (code
->src
.type
) {
2485 case X (OP_SBR
, SL
):
2486 res
= h8_get_sbr (sd
);
2488 case X (OP_VBR
, SL
):
2489 res
= h8_get_vbr (sd
);
2494 if (store (sd
, &code
->dst
, res
))
2498 case O (O_ANDC
, SB
): /* andc.b */
2499 if (code
->dst
.type
== X (OP_CCR
, SB
))
2502 rd
= h8_get_ccr (sd
);
2504 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2507 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2508 res
= h8_get_exr (sd
);
2512 ea
= code
->src
.literal
;
2516 case O (O_ORC
, SB
): /* orc.b */
2517 if (code
->dst
.type
== X (OP_CCR
, SB
))
2520 rd
= h8_get_ccr (sd
);
2522 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2525 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2526 rd
= h8_get_exr (sd
);
2530 ea
= code
->src
.literal
;
2534 case O (O_XORC
, SB
): /* xorc.b */
2535 if (code
->dst
.type
== X (OP_CCR
, SB
))
2538 rd
= h8_get_ccr (sd
);
2540 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2543 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2544 rd
= h8_get_exr (sd
);
2548 ea
= code
->src
.literal
;
2552 case O (O_BRAS
, SB
): /* bra/s */
2553 /* This is basically an ordinary branch, with a delay slot. */
2554 if (fetch (sd
, &code
->src
, &res
))
2562 /* Execution continues at next instruction, but
2563 delayed_branch is set up for next cycle. */
2564 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2568 case O (O_BRAB
, SB
): /* bra rd.b */
2569 case O (O_BRAW
, SW
): /* bra rd.w */
2570 case O (O_BRAL
, SL
): /* bra erd.l */
2571 if (fetch (sd
, &code
->src
, &rd
))
2573 switch (OP_SIZE (code
->opcode
)) {
2574 case SB
: rd
&= 0xff; break;
2575 case SW
: rd
&= 0xffff; break;
2576 case SL
: rd
&= 0xffffffff; break;
2578 pc
= code
->next_pc
+ rd
;
2581 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2582 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2583 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2584 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2585 if (fetch (sd
, &code
->dst
, &rd
) ||
2586 fetch (sd
, &code
->src
, &bit
))
2589 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2590 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2592 if ((rd
& (1 << bit
))) /* no branch */
2595 else /* branch/call if set */
2597 if (!(rd
& (1 << bit
))) /* no branch */
2601 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2603 pc
= code
->next_pc
+ res
;
2605 if (code
->opcode
== O (O_BRABC
, SB
) ||
2606 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2614 case O (O_BRA
, SB
): /* bra, branch always */
2619 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2624 case O (O_BHI
, SB
): /* bhi */
2630 case O (O_BLS
, SB
): /* bls */
2635 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2640 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2645 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2649 case O (O_BGT
, SB
): /* bgt */
2650 if (((Z
|| (N
^ V
)) == 0))
2654 case O (O_BLE
, SB
): /* ble */
2655 if (((Z
|| (N
^ V
)) == 1))
2659 case O (O_BGE
, SB
): /* bge */
2663 case O (O_BLT
, SB
): /* blt */
2667 case O (O_BMI
, SB
): /* bmi */
2671 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2676 case O (O_BPL
, SB
): /* bpl */
2680 case O (O_BVC
, SB
): /* bvc */
2684 case O (O_BVS
, SB
): /* bvs */
2689 /* Trap for Command Line setup. */
2690 case O (O_SYS_CMDLINE
, SB
):
2692 int i
= 0; /* Loop counter. */
2693 int j
= 0; /* Loop counter. */
2694 int ind_arg_len
= 0; /* Length of each argument. */
2695 int no_of_args
= 0; /* The no. or cmdline args. */
2696 int current_location
= 0; /* Location of string. */
2697 int old_sp
= 0; /* The Initial Stack Pointer. */
2698 int no_of_slots
= 0; /* No. of slots required on the stack
2699 for storing cmdline args. */
2700 int sp_move
= 0; /* No. of locations by which the stack needs
2702 int new_sp
= 0; /* The final stack pointer location passed
2704 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2705 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2706 args on the stack. */
2707 int char_ptr_size
= 0; /* Size of a character pointer on
2709 int addr_cmdline
= 0; /* Memory location where cmdline has
2711 int size_cmdline
= 0; /* Size of cmdline. */
2713 /* Set the address of 256 free locations where command line is
2715 addr_cmdline
= cmdline_location();
2716 h8_set_reg (sd
, 0, addr_cmdline
);
2718 /* Counting the no. of commandline arguments. */
2719 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2722 /* No. of arguments in the command line. */
2725 /* Current location is just a temporary variable,which we are
2726 setting to the point to the start of our commandline string. */
2727 current_location
= addr_cmdline
;
2729 /* Allocating space for storing pointers of the command line
2731 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2733 /* Setting char_ptr_size to the sizeof (char *) on the different
2735 if (h8300hmode
|| h8300smode
)
2744 for (i
= 0; i
< no_of_args
; i
++)
2748 /* The size of the commandline argument. */
2749 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
) + 1);
2751 /* The total size of the command line string. */
2752 size_cmdline
+= ind_arg_len
;
2754 /* As we have only 256 bytes, we need to provide a graceful
2755 exit. Anyways, a program using command line arguments
2756 where we cannot store all the command line arguments
2757 given may behave unpredictably. */
2758 if (size_cmdline
>= 256)
2760 h8_set_reg (sd
, 0, 0);
2765 /* current_location points to the memory where the next
2766 commandline argument is stored. */
2767 argv_ptrs
[i
] = current_location
;
2768 for (j
= 0; j
< ind_arg_len
; j
++)
2770 SET_MEMORY_B ((current_location
+
2771 (sizeof (char) * j
)),
2772 *(h8_get_cmdline_arg (sd
, i
) +
2773 sizeof (char) * j
));
2776 /* Setting current_location to the starting of next
2778 current_location
+= ind_arg_len
;
2782 /* This is the original position of the stack pointer. */
2783 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2785 /* We need space from the stack to store the pointers to argvs. */
2786 /* As we will infringe on the stack, we need to shift the stack
2787 pointer so that the data is not overwritten. We calculate how
2788 much space is required. */
2789 sp_move
= (no_of_args
) * (char_ptr_size
);
2791 /* The final position of stack pointer, we have thus taken some
2792 space from the stack. */
2793 new_sp
= old_sp
- sp_move
;
2795 /* Temporary variable holding value where the argv pointers need
2797 argv_ptrs_location
= new_sp
;
2799 /* The argv pointers are stored at sequential locations. As per
2801 for (i
= 0; i
< no_of_args
; i
++)
2803 /* Saving the argv pointer. */
2804 if (h8300hmode
|| h8300smode
)
2806 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2810 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2813 /* The next location where the pointer to the next argv
2814 string has to be stored. */
2815 argv_ptrs_location
+= char_ptr_size
;
2818 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2820 if (h8300hmode
|| h8300smode
)
2822 SET_MEMORY_L (old_sp
, 0x0);
2826 SET_MEMORY_W (old_sp
, 0x0);
2829 /* Freeing allocated memory. */
2831 for (i
= 0; i
<= no_of_args
; i
++)
2833 free (h8_get_cmdline_arg (sd
, i
));
2835 free (h8_get_command_line (sd
));
2837 /* The no. of argv arguments are returned in Reg 0. */
2838 h8_set_reg (sd
, 0, no_of_args
);
2839 /* The Pointer to argv in Register 1. */
2840 h8_set_reg (sd
, 1, new_sp
);
2841 /* Setting the stack pointer to the new value. */
2842 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2846 /* System call processing starts. */
2847 case O (O_SYS_OPEN
, SB
):
2849 int len
= 0; /* Length of filename. */
2850 char *filename
; /* Filename would go here. */
2851 char temp_char
; /* Temporary character */
2852 int mode
= 0; /* Mode bits for the file. */
2853 int open_return
; /* Return value of open, file descriptor. */
2854 int i
; /* Loop counter */
2855 int filename_ptr
; /* Pointer to filename in cpu memory. */
2857 /* Setting filename_ptr to first argument of open, */
2858 /* and trying to get mode. */
2859 if (h8300sxmode
|| h8300hmode
|| h8300smode
)
2861 filename_ptr
= GET_L_REG (0);
2862 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2866 filename_ptr
= GET_W_REG (0);
2867 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2870 /* Trying to find the length of the filename. */
2871 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2874 while (temp_char
!= '\0')
2876 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2880 /* Allocating space for the filename. */
2881 filename
= (char *) malloc (sizeof (char) * len
);
2883 /* String copying the filename from memory. */
2884 for (i
= 0; i
< len
; i
++)
2886 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2887 filename
[i
] = temp_char
;
2890 /* Callback to open and return the file descriptor. */
2891 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2893 /* Return value in register 0. */
2894 h8_set_reg (sd
, 0, open_return
);
2896 /* Freeing memory used for filename. */
2901 case O (O_SYS_READ
, SB
):
2903 char *char_ptr
; /* Where characters read would be stored. */
2904 int fd
; /* File descriptor */
2905 int buf_size
; /* BUF_SIZE parameter in read. */
2906 int i
= 0; /* Temporary Loop counter */
2907 int read_return
= 0; /* Return value from callback to
2910 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2911 buf_size
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2913 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2915 /* Callback to read and return the no. of characters read. */
2917 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2919 /* The characters read are stored in cpu memory. */
2920 for (i
= 0; i
< buf_size
; i
++)
2922 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2923 *(char_ptr
+ (sizeof (char) * i
)));
2926 /* Return value in Register 0. */
2927 h8_set_reg (sd
, 0, read_return
);
2929 /* Freeing memory used as buffer. */
2934 case O (O_SYS_WRITE
, SB
):
2936 int fd
; /* File descriptor */
2937 char temp_char
; /* Temporary character */
2938 int len
; /* Length of write, Parameter II to write. */
2939 int char_ptr
; /* Character Pointer, Parameter I of write. */
2940 char *ptr
; /* Where characters to be written are stored.
2942 int write_return
; /* Return value from callback to write. */
2943 int i
= 0; /* Loop counter */
2945 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2946 char_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
2947 len
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2949 /* Allocating space for the characters to be written. */
2950 ptr
= (char *) malloc (sizeof (char) * len
);
2952 /* Fetching the characters from cpu memory. */
2953 for (i
= 0; i
< len
; i
++)
2955 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2959 /* Callback write and return the no. of characters written. */
2960 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2962 /* Return value in Register 0. */
2963 h8_set_reg (sd
, 0, write_return
);
2965 /* Freeing memory used as buffer. */
2970 case O (O_SYS_LSEEK
, SB
):
2972 int fd
; /* File descriptor */
2973 int offset
; /* Offset */
2974 int origin
; /* Origin */
2975 int lseek_return
; /* Return value from callback to lseek. */
2977 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2978 offset
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
2979 origin
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2981 /* Callback lseek and return offset. */
2983 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2985 /* Return value in register 0. */
2986 h8_set_reg (sd
, 0, lseek_return
);
2990 case O (O_SYS_CLOSE
, SB
):
2992 int fd
; /* File descriptor */
2993 int close_return
; /* Return value from callback to close. */
2995 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2997 /* Callback close and return. */
2998 close_return
= sim_callback
->close (sim_callback
, fd
);
3000 /* Return value in register 0. */
3001 h8_set_reg (sd
, 0, close_return
);
3005 case O (O_SYS_FSTAT
, SB
):
3007 int fd
; /* File descriptor */
3008 struct stat stat_rec
; /* Stat record */
3009 int fstat_return
; /* Return value from callback to stat. */
3010 int stat_ptr
; /* Pointer to stat record. */
3011 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3013 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
3015 /* Setting stat_ptr to second argument of stat. */
3016 stat_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
3018 /* Callback stat and return. */
3019 fstat_return
= sim_callback
->fstat (sim_callback
, fd
, &stat_rec
);
3021 /* Have stat_ptr point to starting of stat_rec. */
3022 temp_stat_ptr
= (char *) (&stat_rec
);
3024 /* Setting up the stat structure returned. */
3025 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3027 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3029 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3031 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3033 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3035 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3037 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3039 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3041 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3043 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3045 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3047 /* Return value in register 0. */
3048 h8_set_reg (sd
, 0, fstat_return
);
3052 case O (O_SYS_STAT
, SB
):
3054 int len
= 0; /* Length of filename. */
3055 char *filename
; /* Filename would go here. */
3056 char temp_char
; /* Temporary character */
3057 int filename_ptr
; /* Pointer to filename in cpu memory. */
3058 struct stat stat_rec
; /* Stat record */
3059 int stat_return
; /* Return value from callback to stat */
3060 int stat_ptr
; /* Pointer to stat record. */
3061 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3062 int i
= 0; /* Loop Counter */
3064 /* Setting filename_ptr to first argument of open. */
3065 filename_ptr
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
3067 /* Trying to find the length of the filename. */
3068 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3071 while (temp_char
!= '\0')
3073 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3077 /* Allocating space for the filename. */
3078 filename
= (char *) malloc (sizeof (char) * len
);
3080 /* String copying the filename from memory. */
3081 for (i
= 0; i
< len
; i
++)
3083 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3084 filename
[i
] = temp_char
;
3087 /* Setting stat_ptr to second argument of stat. */
3088 /* stat_ptr = h8_get_reg (sd, 1); */
3089 stat_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
3091 /* Callback stat and return. */
3093 sim_callback
->stat (sim_callback
, filename
, &stat_rec
);
3095 /* Have stat_ptr point to starting of stat_rec. */
3096 temp_stat_ptr
= (char *) (&stat_rec
);
3098 /* Freeing memory used for filename. */
3101 /* Setting up the stat structure returned. */
3102 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3104 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3106 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3108 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3110 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3112 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3114 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3116 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3118 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3120 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3122 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3124 /* Return value in register 0. */
3125 h8_set_reg (sd
, 0, stat_return
);
3128 /* End of system call processing. */
3130 case O (O_NOT
, SB
): /* not.b */
3131 if (fetch2 (sd
, &code
->src
, &rd
))
3137 case O (O_NOT
, SW
): /* not.w */
3138 if (fetch2 (sd
, &code
->src
, &rd
))
3144 case O (O_NOT
, SL
): /* not.l */
3145 if (fetch2 (sd
, &code
->src
, &rd
))
3151 case O (O_SHLL
, SB
): /* shll.b */
3152 case O (O_SHLR
, SB
): /* shlr.b */
3153 if (fetch2 (sd
, &code
->dst
, &rd
))
3156 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3157 ea
= 1; /* unary op */
3158 else /* binary op */
3159 fetch (sd
, &code
->src
, &ea
);
3161 if (code
->opcode
== O (O_SHLL
, SB
))
3164 c
= rd
& (0x80 >> (ea
- 1));
3170 c
= rd
& (1 << (ea
- 1));
3171 rd
= (unsigned char) rd
>> ea
;
3175 case O (O_SHLL
, SW
): /* shll.w */
3176 case O (O_SHLR
, SW
): /* shlr.w */
3177 if (fetch2 (sd
, &code
->dst
, &rd
))
3180 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3181 ea
= 1; /* unary op */
3183 fetch (sd
, &code
->src
, &ea
);
3185 if (code
->opcode
== O (O_SHLL
, SW
))
3188 c
= rd
& (0x8000 >> (ea
- 1));
3194 c
= rd
& (1 << (ea
- 1));
3195 rd
= (unsigned short) rd
>> ea
;
3199 case O (O_SHLL
, SL
): /* shll.l */
3200 case O (O_SHLR
, SL
): /* shlr.l */
3201 if (fetch2 (sd
, &code
->dst
, &rd
))
3204 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3205 ea
= 1; /* unary op */
3207 fetch (sd
, &code
->src
, &ea
);
3209 if (code
->opcode
== O (O_SHLL
, SL
))
3212 c
= rd
& (0x80000000 >> (ea
- 1));
3218 c
= rd
& (1 << (ea
- 1));
3219 rd
= (unsigned int) rd
>> ea
;
3223 case O (O_SHAL
, SB
):
3224 case O (O_SHAR
, SB
):
3225 if (fetch2 (sd
, &code
->dst
, &rd
))
3228 if (code
->src
.type
== X (OP_IMM
, SB
))
3229 fetch (sd
, &code
->src
, &ea
);
3233 if (code
->opcode
== O (O_SHAL
, SB
))
3235 c
= rd
& (0x80 >> (ea
- 1));
3236 res
= rd
>> (7 - ea
);
3237 v
= ((res
& 1) && !(res
& 2))
3238 || (!(res
& 1) && (res
& 2));
3243 c
= rd
& (1 << (ea
- 1));
3245 rd
= ((signed char) rd
) >> ea
;
3249 case O (O_SHAL
, SW
):
3250 case O (O_SHAR
, SW
):
3251 if (fetch2 (sd
, &code
->dst
, &rd
))
3254 if (code
->src
.type
== X (OP_IMM
, SW
))
3255 fetch (sd
, &code
->src
, &ea
);
3259 if (code
->opcode
== O (O_SHAL
, SW
))
3261 c
= rd
& (0x8000 >> (ea
- 1));
3262 res
= rd
>> (15 - ea
);
3263 v
= ((res
& 1) && !(res
& 2))
3264 || (!(res
& 1) && (res
& 2));
3269 c
= rd
& (1 << (ea
- 1));
3271 rd
= ((signed short) rd
) >> ea
;
3275 case O (O_SHAL
, SL
):
3276 case O (O_SHAR
, SL
):
3277 if (fetch2 (sd
, &code
->dst
, &rd
))
3280 if (code
->src
.type
== X (OP_IMM
, SL
))
3281 fetch (sd
, &code
->src
, &ea
);
3285 if (code
->opcode
== O (O_SHAL
, SL
))
3287 c
= rd
& (0x80000000 >> (ea
- 1));
3288 res
= rd
>> (31 - ea
);
3289 v
= ((res
& 1) && !(res
& 2))
3290 || (!(res
& 1) && (res
& 2));
3295 c
= rd
& (1 << (ea
- 1));
3297 rd
= ((signed int) rd
) >> ea
;
3301 case O (O_ROTL
, SB
):
3302 case O (O_ROTR
, SB
):
3303 if (fetch2 (sd
, &code
->dst
, &rd
))
3306 if (code
->src
.type
== X (OP_IMM
, SB
))
3307 fetch (sd
, &code
->src
, &ea
);
3312 if (code
->opcode
== O (O_ROTL
, SB
))
3322 rd
= ((unsigned char) rd
) >> 1;
3330 case O (O_ROTL
, SW
):
3331 case O (O_ROTR
, SW
):
3332 if (fetch2 (sd
, &code
->dst
, &rd
))
3335 if (code
->src
.type
== X (OP_IMM
, SW
))
3336 fetch (sd
, &code
->src
, &ea
);
3341 if (code
->opcode
== O (O_ROTL
, SW
))
3351 rd
= ((unsigned short) rd
) >> 1;
3359 case O (O_ROTL
, SL
):
3360 case O (O_ROTR
, SL
):
3361 if (fetch2 (sd
, &code
->dst
, &rd
))
3364 if (code
->src
.type
== X (OP_IMM
, SL
))
3365 fetch (sd
, &code
->src
, &ea
);
3370 if (code
->opcode
== O (O_ROTL
, SL
))
3372 c
= rd
& 0x80000000;
3380 rd
= ((unsigned int) rd
) >> 1;
3388 case O (O_ROTXL
, SB
):
3389 case O (O_ROTXR
, SB
):
3390 if (fetch2 (sd
, &code
->dst
, &rd
))
3393 if (code
->src
.type
== X (OP_IMM
, SB
))
3394 fetch (sd
, &code
->src
, &ea
);
3399 if (code
->opcode
== O (O_ROTXL
, SB
))
3410 rd
= ((unsigned char) rd
) >> 1;
3419 case O (O_ROTXL
, SW
):
3420 case O (O_ROTXR
, SW
):
3421 if (fetch2 (sd
, &code
->dst
, &rd
))
3424 if (code
->src
.type
== X (OP_IMM
, SW
))
3425 fetch (sd
, &code
->src
, &ea
);
3430 if (code
->opcode
== O (O_ROTXL
, SW
))
3441 rd
= ((unsigned short) rd
) >> 1;
3450 case O (O_ROTXL
, SL
):
3451 case O (O_ROTXR
, SL
):
3452 if (fetch2 (sd
, &code
->dst
, &rd
))
3455 if (code
->src
.type
== X (OP_IMM
, SL
))
3456 fetch (sd
, &code
->src
, &ea
);
3461 if (code
->opcode
== O (O_ROTXL
, SL
))
3463 res
= rd
& 0x80000000;
3472 rd
= ((unsigned int) rd
) >> 1;
3483 case O (O_JMP
, SB
): /* jmp */
3485 fetch (sd
, &code
->src
, &pc
);
3490 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3492 if (fetch (sd
, &code
->src
, &pc
))
3495 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3500 SET_MEMORY_L (tmp
, code
->next_pc
);
3505 SET_MEMORY_W (tmp
, code
->next_pc
);
3507 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3513 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3514 if (fetch (sd
, &code
->src
, &res
))
3516 pc
= code
->next_pc
+ res
;
3519 case O (O_RTE
, SN
): /* rte, return from exception */
3521 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3522 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3524 if (h8300smode
) /* pop exr */
3526 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3531 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3533 pc
= GET_MEMORY_L (tmp
);
3538 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3540 pc
= GET_MEMORY_W (tmp
);
3545 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3548 case O (O_RTS
, SN
): /* rts, return from subroutine */
3550 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3554 pc
= GET_MEMORY_L (tmp
);
3559 pc
= GET_MEMORY_W (tmp
);
3563 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3566 case O (O_ILL
, SB
): /* illegal */
3567 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
3570 case O (O_SLEEP
, SN
): /* sleep */
3571 /* Check for magic numbers in r1 and r2. */
3572 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3573 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3574 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3576 /* This trap comes from _exit, not from gdb. */
3577 sim_engine_set_run_state (sd
, sim_exited
,
3578 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3580 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3582 /* Pass the stop signal up to gdb. */
3583 sim_engine_set_run_state (sd
, sim_stopped
,
3584 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3588 /* Treat it as a sigtrap. */
3589 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3593 case O (O_TRAPA
, SB
): /* trapa */
3594 if (fetch (sd
, &code
->src
, &res
))
3595 goto end
; /* res is vector number. */
3597 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3599 SET_MEMORY_L (tmp
, code
->next_pc
);
3601 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3608 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3611 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3613 /* FIXME: "normal" mode should use 2-byte ptrs. */
3614 pc
= GET_MEMORY_L (0x20 + res
* 4);
3618 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3621 case O (O_BSETEQ
, SB
):
3626 case O (O_BSETNE
, SB
):
3631 case O (O_BCLREQ
, SB
):
3636 case O (O_BCLRNE
, SB
):
3641 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3642 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3644 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3646 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3647 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3648 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3649 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3650 if (C
) ea
|= m
); /* bst */
3651 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3652 if (!C
) ea
|= m
); /* bist */
3653 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3654 if (Z
) ea
|= m
); /* bstz */
3655 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3656 if (!Z
) ea
|= m
); /* bistz */
3657 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3658 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3659 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3660 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3661 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3662 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3664 case O (O_BFLD
, SB
): /* bfld */
3667 if (fetch (sd
, &code
->src
, &bit
))
3672 if (fetch (sd
, &code
->dst
, &ea
))
3682 if (store (sd
, &code
->op3
, ea
))
3687 case O(O_BFST
, SB
): /* bfst */
3688 /* bitfield store */
3689 /* NOTE: the imm8 value is in dst, and the ea value
3690 (which is actually the destination) is in op3.
3691 It has to be that way, to avoid breaking the assembler. */
3693 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3695 if (bit
== 0) /* noop -- nothing to do. */
3698 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3701 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3704 /* Left-shift the register data into position. */
3705 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3708 /* Combine it with the neighboring bits. */
3709 ea
= (ea
& ~bit
) | (rd
& bit
);
3712 if (store2 (sd
, &code
->op3
, ea
))
3716 case O (O_CLRMAC
, SN
): /* clrmac */
3717 h8_set_mach (sd
, 0);
3718 h8_set_macl (sd
, 0);
3719 h8_set_macZ (sd
, 1);
3720 h8_set_macV (sd
, 0);
3721 h8_set_macN (sd
, 0);
3724 case O (O_STMAC
, SL
): /* stmac, 260 */
3725 switch (code
->src
.type
) {
3726 case X (OP_MACH
, SL
):
3727 res
= h8_get_mach (sd
);
3728 if (res
& 0x200) /* sign extend */
3731 case X (OP_MACL
, SL
):
3732 res
= h8_get_macl (sd
);
3734 default: goto illegal
;
3736 nz
= !h8_get_macZ (sd
);
3737 n
= h8_get_macN (sd
);
3738 v
= h8_get_macV (sd
);
3740 if (store (sd
, &code
->dst
, res
))
3745 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3746 if (fetch (sd
, &code
->src
, &rd
))
3749 switch (code
->dst
.type
) {
3750 case X (OP_MACH
, SL
):
3751 rd
&= 0x3ff; /* Truncate to 10 bits */
3752 h8_set_mach (sd
, rd
);
3754 case X (OP_MACL
, SL
):
3755 h8_set_macl (sd
, rd
);
3757 default: goto illegal
;
3759 h8_set_macV (sd
, 0);
3763 if (fetch (sd
, &code
->src
, &rd
) ||
3764 fetch (sd
, &code
->dst
, &res
))
3767 /* Ye gods, this is non-portable!
3768 However, the existing mul/div code is similar. */
3769 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3771 if (h8_get_macS (sd
)) /* Saturating mode */
3773 long long mac
= h8_get_macl (sd
);
3775 if (mac
& 0x80000000) /* sign extend */
3776 mac
|= 0xffffffff00000000LL
;
3779 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3780 h8_set_macV (sd
, 1);
3781 h8_set_macZ (sd
, (mac
== 0));
3782 h8_set_macN (sd
, (mac
< 0));
3783 h8_set_macl (sd
, (int) mac
);
3785 else /* "Less Saturating" mode */
3787 long long mac
= h8_get_mach (sd
);
3789 mac
+= h8_get_macl (sd
);
3791 if (mac
& 0x20000000000LL
) /* sign extend */
3792 mac
|= 0xfffffc0000000000LL
;
3795 if (mac
> 0x1ffffffffffLL
||
3796 mac
< (long long) 0xfffffe0000000000LL
)
3797 h8_set_macV (sd
, 1);
3798 h8_set_macZ (sd
, (mac
== 0));
3799 h8_set_macN (sd
, (mac
< 0));
3800 h8_set_macl (sd
, (int) mac
);
3802 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3806 case O (O_MULS
, SW
): /* muls.w */
3807 if (fetch (sd
, &code
->src
, &ea
) ||
3808 fetch (sd
, &code
->dst
, &rd
))
3811 /* FIXME: is this the right place to be doing sign extend? */
3812 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3816 ea
= SEXTSHORT (ea
);
3818 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3822 if (store (sd
, &code
->dst
, res
))
3827 case O (O_MULS
, SL
): /* muls.l */
3828 if (fetch (sd
, &code
->src
, &ea
) ||
3829 fetch (sd
, &code
->dst
, &rd
))
3832 /* FIXME: is this the right place to be doing sign extend? */
3833 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3839 n
= res
& 0x80000000;
3840 nz
= res
& 0xffffffff;
3841 if (store (sd
, &code
->dst
, res
))
3845 case O (O_MULSU
, SL
): /* muls/u.l */
3846 if (fetch (sd
, &code
->src
, &ea
) ||
3847 fetch (sd
, &code
->dst
, &rd
))
3850 /* FIXME: is this the right place to be doing sign extend? */
3851 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3855 /* Compute upper 32 bits of the 64-bit result. */
3856 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3858 n
= res
& 0x80000000;
3859 nz
= res
& 0xffffffff;
3860 if (store (sd
, &code
->dst
, res
))
3864 case O (O_MULU
, SW
): /* mulu.w */
3865 if (fetch (sd
, &code
->src
, &ea
) ||
3866 fetch (sd
, &code
->dst
, &rd
))
3869 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3871 /* Don't set Z or N. */
3872 if (store (sd
, &code
->dst
, res
))
3877 case O (O_MULU
, SL
): /* mulu.l */
3878 if (fetch (sd
, &code
->src
, &ea
) ||
3879 fetch (sd
, &code
->dst
, &rd
))
3884 /* Don't set Z or N. */
3885 if (store (sd
, &code
->dst
, res
))
3890 case O (O_MULUU
, SL
): /* mulu/u.l */
3891 if (fetch (sd
, &code
->src
, &ea
) ||
3892 fetch (sd
, &code
->dst
, &rd
))
3895 /* Compute upper 32 bits of the 64-bit result. */
3896 res
= (((unsigned long long) (unsigned) ea
) *
3897 ((unsigned long long) (unsigned) rd
)) >> 32;
3899 /* Don't set Z or N. */
3900 if (store (sd
, &code
->dst
, res
))
3905 case O (O_MULXS
, SB
): /* mulxs.b */
3906 if (fetch (sd
, &code
->src
, &ea
) ||
3907 fetch (sd
, &code
->dst
, &rd
))
3910 /* FIXME: is this the right place to be doing sign extend? */
3911 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3917 res
= ea
* SEXTCHAR (rd
);
3921 if (store (sd
, &code
->dst
, res
))
3926 case O (O_MULXS
, SW
): /* mulxs.w */
3927 if (fetch (sd
, &code
->src
, &ea
) ||
3928 fetch (sd
, &code
->dst
, &rd
))
3931 /* FIXME: is this the right place to be doing sign extend? */
3932 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3936 ea
= SEXTSHORT (ea
);
3938 res
= ea
* SEXTSHORT (rd
& 0xffff);
3940 n
= res
& 0x80000000;
3941 nz
= res
& 0xffffffff;
3942 if (store (sd
, &code
->dst
, res
))
3947 case O (O_MULXU
, SB
): /* mulxu.b */
3948 if (fetch (sd
, &code
->src
, &ea
) ||
3949 fetch (sd
, &code
->dst
, &rd
))
3952 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3954 if (store (sd
, &code
->dst
, res
))
3959 case O (O_MULXU
, SW
): /* mulxu.w */
3960 if (fetch (sd
, &code
->src
, &ea
) ||
3961 fetch (sd
, &code
->dst
, &rd
))
3964 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3966 if (store (sd
, &code
->dst
, res
))
3971 case O (O_TAS
, SB
): /* tas (test and set) */
3972 if (!h8300sxmode
) /* h8sx can use any register. */
3973 switch (code
->src
.reg
)
3984 if (fetch (sd
, &code
->src
, &res
))
3986 if (store (sd
, &code
->src
, res
| 0x80))
3989 goto just_flags_log8
;
3991 case O (O_DIVU
, SW
): /* divu.w */
3992 if (fetch (sd
, &code
->src
, &ea
) ||
3993 fetch (sd
, &code
->dst
, &rd
))
3999 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
4003 if (store (sd
, &code
->dst
, res
))
4007 case O (O_DIVU
, SL
): /* divu.l */
4008 if (fetch (sd
, &code
->src
, &ea
) ||
4009 fetch (sd
, &code
->dst
, &rd
))
4012 n
= ea
& 0x80000000;
4013 nz
= ea
& 0xffffffff;
4015 res
= (unsigned) rd
/ ea
;
4019 if (store (sd
, &code
->dst
, res
))
4023 case O (O_DIVS
, SW
): /* divs.w */
4024 if (fetch (sd
, &code
->src
, &ea
) ||
4025 fetch (sd
, &code
->dst
, &rd
))
4028 /* FIXME: is this the right place to be doing sign extend? */
4029 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4035 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
4045 if (store (sd
, &code
->dst
, res
))
4049 case O (O_DIVS
, SL
): /* divs.l */
4050 if (fetch (sd
, &code
->src
, &ea
) ||
4051 fetch (sd
, &code
->dst
, &rd
))
4054 /* FIXME: is this the right place to be doing sign extend? */
4055 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4070 n
= res
& 0x80000000;
4071 if (store (sd
, &code
->dst
, res
))
4075 case O (O_DIVXU
, SB
): /* divxu.b */
4076 if (fetch (sd
, &code
->src
, &ea
) ||
4077 fetch (sd
, &code
->dst
, &rd
))
4080 rd
= UEXTSHORT (rd
);
4087 tmp
= (unsigned) rd
% ea
;
4088 res
= (unsigned) rd
/ ea
;
4096 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4100 case O (O_DIVXU
, SW
): /* divxu.w */
4101 if (fetch (sd
, &code
->src
, &ea
) ||
4102 fetch (sd
, &code
->dst
, &rd
))
4105 ea
= UEXTSHORT (ea
);
4111 tmp
= (unsigned) rd
% ea
;
4112 res
= (unsigned) rd
/ ea
;
4120 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4124 case O (O_DIVXS
, SB
): /* divxs.b */
4125 if (fetch (sd
, &code
->src
, &ea
) ||
4126 fetch (sd
, &code
->dst
, &rd
))
4129 rd
= SEXTSHORT (rd
);
4131 /* FIXME: is this the right place to be doing sign extend? */
4132 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4140 tmp
= (int) rd
% (int) ea
;
4141 res
= (int) rd
/ (int) ea
;
4152 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4156 case O (O_DIVXS
, SW
): /* divxs.w */
4157 if (fetch (sd
, &code
->src
, &ea
) ||
4158 fetch (sd
, &code
->dst
, &rd
))
4161 /* FIXME: is this the right place to be doing sign extend? */
4162 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4166 ea
= SEXTSHORT (ea
);
4170 tmp
= (int) rd
% (int) ea
;
4171 res
= (int) rd
/ (int) ea
;
4181 n
= res
& 0x80000000;
4182 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4186 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4187 if (fetch2 (sd
, &code
->dst
, &rd
))
4189 ea
= rd
& 0x80 ? -256 : 0;
4190 res
= (rd
& 0xff) + ea
;
4193 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4194 if (fetch2 (sd
, &code
->dst
, &rd
))
4196 if (code
->src
.type
== X (OP_IMM
, SL
))
4198 if (fetch (sd
, &code
->src
, &ea
))
4201 if (ea
== 2) /* exts.l #2, nn */
4203 /* Sign-extend from 8-bit to 32-bit. */
4204 ea
= rd
& 0x80 ? -256 : 0;
4205 res
= (rd
& 0xff) + ea
;
4209 /* Sign-extend from 16-bit to 32-bit. */
4210 ea
= rd
& 0x8000 ? -65536 : 0;
4211 res
= (rd
& 0xffff) + ea
;
4214 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4215 if (fetch2 (sd
, &code
->dst
, &rd
))
4218 res
= (rd
& 0xff) + ea
;
4221 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4222 if (fetch2 (sd
, &code
->dst
, &rd
))
4224 if (code
->src
.type
== X (OP_IMM
, SL
))
4226 if (fetch (sd
, &code
->src
, &ea
))
4229 if (ea
== 2) /* extu.l #2, nn */
4231 /* Zero-extend from 8-bit to 32-bit. */
4233 res
= (rd
& 0xff) + ea
;
4237 /* Zero-extend from 16-bit to 32-bit. */
4239 res
= (rd
& 0xffff) + ea
;
4242 case O (O_NOP
, SN
): /* nop */
4245 case O (O_STM
, SL
): /* stm, store to memory */
4247 int nregs
, firstreg
, i
;
4249 nregs
= GET_MEMORY_B (pc
+ 1);
4252 firstreg
= code
->src
.reg
;
4254 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4256 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4257 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4262 case O (O_LDM
, SL
): /* ldm, load from memory */
4263 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4264 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4266 int nregs
, firstreg
, i
;
4268 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4269 firstreg
= code
->dst
.reg
& 0xf;
4270 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4272 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4273 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4276 switch (code
->opcode
) {
4277 case O (O_RTEL
, SN
):
4279 case O (O_RTSL
, SN
):
4288 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4289 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4290 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4291 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4292 res
= res
; /* Value added == 0. */
4293 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4294 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4295 res
= res
+ 0x6; /* Value added == 6. */
4296 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4297 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4298 res
= res
+ 0x6; /* Value added == 6. */
4299 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4300 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4301 res
= res
+ 0x60; /* Value added == 60. */
4302 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4303 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4304 res
= res
+ 0x66; /* Value added == 66. */
4305 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4306 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4307 res
= res
+ 0x66; /* Value added == 66. */
4308 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4309 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4310 res
= res
+ 0x60; /* Value added == 60. */
4311 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4312 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4313 res
= res
+ 0x66; /* Value added == 66. */
4314 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4315 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4316 res
= res
+ 0x66; /* Value added == 66. */
4321 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4322 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4323 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4324 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4325 res
= res
; /* Value added == 0. */
4326 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4327 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4328 res
= res
+ 0xfa; /* Value added == 0xfa. */
4329 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4330 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4331 res
= res
+ 0xa0; /* Value added == 0xa0. */
4332 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4333 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4334 res
= res
+ 0x9a; /* Value added == 0x9a. */
4340 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4345 (*sim_callback
->printf_filtered
) (sim_callback
,
4346 "sim_resume: internal error.\n");
4347 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4351 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4352 code
->dst
.type
== X (OP_CCR
, SW
))
4354 h8_set_ccr (sd
, res
);
4357 else if (h8300smode
&&
4358 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4359 code
->dst
.type
== X (OP_EXR
, SW
)))
4361 h8_set_exr (sd
, res
);
4362 if (h8300smode
) /* Get exr. */
4364 trace
= (h8_get_exr (sd
) >> 7) & 1;
4365 intMask
= h8_get_exr (sd
) & 7;
4374 /* When a branch works */
4375 if (fetch (sd
, &code
->src
, &res
))
4377 if (res
& 1) /* bad address */
4379 pc
= code
->next_pc
+ res
;
4382 /* Set the cond codes from res */
4385 /* Set the flags after an 8 bit inc/dec operation */
4389 v
= (rd
& 0x7f) == 0x7f;
4392 /* Set the flags after an 16 bit inc/dec operation */
4396 v
= (rd
& 0x7fff) == 0x7fff;
4399 /* Set the flags after an 32 bit inc/dec operation */
4401 n
= res
& 0x80000000;
4402 nz
= res
& 0xffffffff;
4403 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4407 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4410 if (store2 (sd
, &code
->dst
, rd
))
4415 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4418 if (store2 (sd
, &code
->dst
, rd
))
4423 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4424 n
= (rd
& 0x80000000);
4425 nz
= rd
& 0xffffffff;
4426 if (store2 (sd
, &code
->dst
, rd
))
4431 if (store2 (sd
, &code
->dst
, res
))
4435 /* flags after a 32bit logical operation */
4436 n
= res
& 0x80000000;
4437 nz
= res
& 0xffffffff;
4442 if (store2 (sd
, &code
->dst
, res
))
4446 /* flags after a 16bit logical operation */
4453 if (store2 (sd
, &code
->dst
, res
))
4463 if (store2 (sd
, &code
->dst
, res
))
4470 switch (code
->opcode
/ 4)
4474 v
= ((rd
& 0x80) == (ea
& 0x80)
4475 && (rd
& 0x80) != (res
& 0x80));
4480 v
= ((rd
& 0x80) != (-ea
& 0x80)
4481 && (rd
& 0x80) != (res
& 0x80));
4488 break; /* No effect on v flag. */
4493 if (store2 (sd
, &code
->dst
, res
))
4499 c
= (res
& 0x10000);
4500 switch (code
->opcode
/ 4)
4504 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4505 && (rd
& 0x8000) != (res
& 0x8000));
4510 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4511 && (rd
& 0x8000) != (res
& 0x8000));
4520 if (store2 (sd
, &code
->dst
, res
))
4524 n
= res
& 0x80000000;
4525 nz
= res
& 0xffffffff;
4526 switch (code
->opcode
/ 4)
4530 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4531 && (rd
& 0x80000000) != (res
& 0x80000000));
4532 c
= ((unsigned) res
< (unsigned) rd
) ||
4533 ((unsigned) res
< (unsigned) ea
);
4538 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4539 && (rd
& 0x80000000) != (res
& 0x80000000));
4540 c
= (unsigned) rd
< (unsigned) -ea
;
4543 v
= (rd
== 0x80000000);
4550 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4553 h8_set_delayed_branch (sd
, 0);
4560 if (--poll_count
< 0)
4562 poll_count
= POLL_QUIT_INTERVAL
;
4563 if ((*sim_callback
->poll_quit
) != NULL
4564 && (*sim_callback
->poll_quit
) (sim_callback
))
4565 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
4567 sim_engine_get_run_state (sd
, &reason
, &sigrc
);
4568 } while (reason
== sim_running
);
4570 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4571 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4572 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4577 h8_set_exr (sd
, (trace
<<7) | intMask
);
4579 h8_set_mask (sd
, oldmask
);
4580 signal (SIGINT
, prev
);
4584 sim_trace (SIM_DESC sd
)
4586 /* FIXME: Unfinished. */
4587 (*sim_callback
->printf_filtered
) (sim_callback
,
4588 "sim_trace: trace not supported.\n");
4589 return 1; /* Done. */
4593 sim_write (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4600 for (i
= 0; i
< size
; i
++)
4602 if (addr
< memory_size
)
4604 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4605 h8_set_cache_idx (sd
, addr
+ i
, 0);
4609 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4616 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4621 if (addr
< memory_size
)
4622 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4624 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4630 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
4635 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4636 shortval
= (value
[0] << 8) | (value
[1]);
4637 intval
= h8300hmode
? longval
: shortval
;
4643 h8_set_pc (sd
, intval
);
4646 (*sim_callback
->printf_filtered
) (sim_callback
,
4647 "sim_store_register: bad regnum %d.\n",
4657 h8_set_reg (sd
, rn
, intval
);
4660 h8_set_ccr (sd
, intval
);
4663 h8_set_exr (sd
, intval
);
4666 h8_set_sbr (sd
, intval
);
4669 h8_set_vbr (sd
, intval
);
4672 h8_set_mach (sd
, intval
);
4675 h8_set_macl (sd
, intval
);
4678 h8_set_cycles (sd
, longval
);
4682 h8_set_insts (sd
, longval
);
4686 h8_set_ticks (sd
, longval
);
4693 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
4700 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4705 (*sim_callback
->printf_filtered
) (sim_callback
,
4706 "sim_fetch_register: bad regnum %d.\n",
4711 v
= h8_get_ccr (sd
);
4714 v
= h8_get_exr (sd
);
4720 v
= h8_get_sbr (sd
);
4723 v
= h8_get_vbr (sd
);
4726 v
= h8_get_mach (sd
);
4729 v
= h8_get_macl (sd
);
4739 v
= h8_get_reg (sd
, rn
);
4742 v
= h8_get_cycles (sd
);
4746 v
= h8_get_ticks (sd
);
4750 v
= h8_get_insts (sd
);
4754 if (h8300hmode
|| longreg
)
4770 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
4772 sim_engine_get_run_state (sd
, reason
, sigrc
);
4775 /* FIXME: Rename to sim_set_mem_size. */
4780 /* Memory size is fixed. */
4784 set_simcache_size (SIM_DESC sd
, int n
)
4787 free (sd
->sim_cache
);
4790 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4791 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4792 sd
->sim_cache_size
= n
;
4797 sim_info (SIM_DESC sd
, int verbose
)
4799 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4800 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4802 (*sim_callback
->printf_filtered
) (sim_callback
,
4803 "\n\n#instructions executed %10d\n",
4805 (*sim_callback
->printf_filtered
) (sim_callback
,
4806 "#cycles (v approximate) %10d\n",
4807 h8_get_cycles (sd
));
4808 (*sim_callback
->printf_filtered
) (sim_callback
,
4809 "#real time taken %10.4f\n",
4811 (*sim_callback
->printf_filtered
) (sim_callback
,
4812 "#virtual time taken %10.4f\n",
4814 if (timetaken
!= 0.0)
4815 (*sim_callback
->printf_filtered
) (sim_callback
,
4816 "#simulation ratio %10.4f\n",
4817 virttime
/ timetaken
);
4818 (*sim_callback
->printf_filtered
) (sim_callback
,
4820 h8_get_compiles (sd
));
4821 (*sim_callback
->printf_filtered
) (sim_callback
,
4822 "#cache size %10d\n",
4823 sd
->sim_cache_size
);
4826 /* This to be conditional on `what' (aka `verbose'),
4827 however it was never passed as non-zero. */
4831 for (i
= 0; i
< O_LAST
; i
++)
4833 if (h8_get_stats (sd
, i
))
4834 (*sim_callback
->printf_filtered
) (sim_callback
, "%d: %d\n",
4835 i
, h8_get_stats (sd
, i
));
4841 /* Indicate whether the cpu is an H8/300 or H8/300H.
4842 FLAG is non-zero for the H8/300H. */
4845 set_h8300h (unsigned long machine
)
4847 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4848 This function being replaced by a sim_open:ARGV configuration
4851 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4854 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4857 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4861 /* Cover function of sim_state_free to free the cpu buffers as well. */
4864 free_state (SIM_DESC sd
)
4866 if (STATE_MODULES (sd
) != NULL
)
4867 sim_module_uninstall (sd
);
4869 /* Fixme: free buffers in _sim_cpu. */
4870 sim_state_free (sd
);
4874 sim_open (SIM_OPEN_KIND kind
,
4875 struct host_callback_struct
*callback
,
4882 sd
= sim_state_alloc (kind
, callback
);
4883 sd
->cpu
= sim_cpu_alloc (sd
, 0);
4884 cpu
= STATE_CPU (sd
, 0);
4885 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4886 sim_state_initialize (sd
, cpu
);
4887 /* sim_cpu object is new, so some initialization is needed. */
4888 init_pointers_needed
= 1;
4890 /* For compatibility (FIXME: is this right?). */
4891 current_alignment
= NONSTRICT_ALIGNMENT
;
4892 current_target_byte_order
= BIG_ENDIAN
;
4894 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4900 /* getopt will print the error message so we just have to exit if
4901 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4902 to call print_filtered. */
4903 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4905 /* Uninstall the modules to avoid memory leaks,
4906 file descriptor leaks, etc. */
4911 /* Check for/establish the a reference program image. */
4912 if (sim_analyze_program (sd
,
4913 (STATE_PROG_ARGV (sd
) != NULL
4914 ? *STATE_PROG_ARGV (sd
)
4915 : NULL
), abfd
) != SIM_RC_OK
)
4921 /* Establish any remaining configuration options. */
4922 if (sim_config (sd
) != SIM_RC_OK
)
4928 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4930 /* Uninstall the modules to avoid memory leaks,
4931 file descriptor leaks, etc. */
4936 /* sim_hw_configure (sd); */
4938 /* FIXME: Much of the code in sim_load can be moved here. */
4942 sim_callback
= callback
;
4947 sim_close (SIM_DESC sd
, int quitting
)
4949 /* Nothing to do. */
4952 /* Called by gdb to load a program into memory. */
4955 sim_load (SIM_DESC sd
, char *prog
, bfd
*abfd
, int from_tty
)
4959 /* FIXME: The code below that sets a specific variant of the H8/300
4960 being simulated should be moved to sim_open(). */
4962 /* See if the file is for the H8/300 or H8/300H. */
4963 /* ??? This may not be the most efficient way. The z8k simulator
4964 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4968 prog_bfd
= bfd_openr (prog
, "coff-h8300");
4969 if (prog_bfd
!= NULL
)
4971 /* Set the cpu type. We ignore failure from bfd_check_format
4972 and bfd_openr as sim_load_file checks too. */
4973 if (bfd_check_format (prog_bfd
, bfd_object
))
4975 set_h8300h (bfd_get_mach (prog_bfd
));
4979 /* If we're using gdb attached to the simulator, then we have to
4980 reallocate memory for the simulator.
4982 When gdb first starts, it calls fetch_registers (among other
4983 functions), which in turn calls init_pointers, which allocates
4986 The problem is when we do that, we don't know whether we're
4987 debugging an H8/300 or H8/300H program.
4989 This is the first point at which we can make that determination,
4990 so we just reallocate memory now; this will also allow us to handle
4991 switching between H8/300 and H8/300H programs without exiting
4995 memory_size
= H8300S_MSIZE
;
4996 else if (h8300hmode
)
4997 memory_size
= H8300H_MSIZE
;
4999 memory_size
= H8300_MSIZE
;
5001 if (h8_get_memory_buf (sd
))
5002 free (h8_get_memory_buf (sd
));
5003 if (h8_get_cache_idx_buf (sd
))
5004 free (h8_get_cache_idx_buf (sd
));
5005 if (h8_get_eightbit_buf (sd
))
5006 free (h8_get_eightbit_buf (sd
));
5008 h8_set_memory_buf (sd
, (unsigned char *)
5009 calloc (sizeof (char), memory_size
));
5010 h8_set_cache_idx_buf (sd
, (unsigned short *)
5011 calloc (sizeof (short), memory_size
));
5012 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
5014 /* `msize' must be a power of two. */
5015 if ((memory_size
& (memory_size
- 1)) != 0)
5017 (*sim_callback
->printf_filtered
) (sim_callback
,
5018 "sim_load: bad memory size.\n");
5021 h8_set_mask (sd
, memory_size
- 1);
5023 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
5024 sim_kind
== SIM_OPEN_DEBUG
,
5028 /* Close the bfd if we opened it. */
5029 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5030 bfd_close (prog_bfd
);
5034 /* Close the bfd if we opened it. */
5035 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5036 bfd_close (prog_bfd
);
5041 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
5048 h8_set_pc (sd
, bfd_get_start_address (abfd
));
5052 /* Command Line support. */
5055 /* Counting the no. of commandline arguments. */
5056 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
5059 /* Allocating memory for the argv pointers. */
5060 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
5061 * (no_of_args
+ 1)));
5063 for (i
= 0; i
< no_of_args
; i
++)
5065 /* Copying the argument string. */
5066 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
5068 h8_set_cmdline_arg (sd
, i
, NULL
);
5075 sim_do_command (SIM_DESC sd
, char *cmd
)
5077 (*sim_callback
->printf_filtered
) (sim_callback
,
5078 "This simulator does not accept any commands.\n");
5082 sim_set_callbacks (struct host_callback_struct
*ptr
)