2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
20 /* This must come before any other includes. */
26 #ifdef HAVE_SYS_PARAM_H
27 #include <sys/param.h>
32 #include "gdb/sim-h8300.h"
34 #include "sys/types.h"
35 #include "sim-options.h"
43 static int memory_size
;
45 #define X(op, size) (op * 4 + size)
47 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
49 #define h8_opcodes ops
51 #include "opcode/h8300.h"
53 /* CPU data object: */
56 h8_get_pc (SIM_DESC sd
)
58 return (STATE_CPU (sd
, 0)) -> pc
;
62 h8_set_pc (SIM_DESC sd
, unsigned int val
)
64 (STATE_CPU (sd
, 0)) -> pc
= val
;
68 h8_get_ccr (SIM_DESC sd
)
70 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
74 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
76 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
80 h8_get_exr (SIM_DESC sd
)
82 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
86 h8_set_exr (SIM_DESC sd
, unsigned int val
)
88 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
92 h8_get_sbr (SIM_DESC sd
)
94 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
98 h8_set_sbr (SIM_DESC sd
, int val
)
100 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
104 h8_get_vbr (SIM_DESC sd
)
106 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
110 h8_set_vbr (SIM_DESC sd
, int val
)
112 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
116 h8_get_mask (SIM_DESC sd
)
118 return (STATE_CPU (sd
, 0)) -> mask
;
122 h8_set_mask (SIM_DESC sd
, int val
)
124 (STATE_CPU (sd
, 0)) -> mask
= val
;
128 h8_get_exception (SIM_DESC sd
)
130 return (STATE_CPU (sd
, 0)) -> exception
;
134 h8_set_exception (SIM_DESC sd
, int val
)
136 (STATE_CPU (sd
, 0)) -> exception
= val
;
139 static enum h8300_sim_state
140 h8_get_state (SIM_DESC sd
)
142 return H8300_SIM_STATE (sd
)->state
;
146 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
148 H8300_SIM_STATE (sd
)->state
= val
;
152 h8_get_cycles (SIM_DESC sd
)
154 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
158 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
160 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
164 h8_get_insts (SIM_DESC sd
)
166 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
170 h8_set_insts (SIM_DESC sd
, unsigned int val
)
172 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
176 h8_get_ticks (SIM_DESC sd
)
178 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
182 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
184 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
188 h8_get_mach (SIM_DESC sd
)
190 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
194 h8_set_mach (SIM_DESC sd
, unsigned int val
)
196 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
200 h8_get_macl (SIM_DESC sd
)
202 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
206 h8_set_macl (SIM_DESC sd
, unsigned int val
)
208 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
211 static unsigned int *
212 h8_get_reg_buf (SIM_DESC sd
)
214 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
218 h8_get_reg (SIM_DESC sd
, int regnum
)
220 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
224 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
226 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
231 h8_get_stats (SIM_DESC sd
, int idx
)
233 return H8300_SIM_STATE (sd
)->stats
[idx
];
237 h8_increment_stats (SIM_DESC sd
, int idx
)
239 H8300_SIM_STATE (sd
)->stats
[idx
] ++;
243 static unsigned char *
244 h8_get_memory_buf (SIM_DESC sd
)
246 return (STATE_CPU (sd
, 0)) -> memory
;
250 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
252 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
256 h8_get_memory (SIM_DESC sd
, int idx
)
258 ASSERT (idx
< memory_size
);
259 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
263 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
265 ASSERT (idx
< memory_size
);
266 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
270 h8_get_delayed_branch (SIM_DESC sd
)
272 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
276 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
278 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
282 h8_get_command_line (SIM_DESC sd
)
284 return (STATE_CPU (sd
, 0)) -> command_line
;
288 h8_set_command_line (SIM_DESC sd
, char ** val
)
290 (STATE_CPU (sd
, 0)) -> command_line
= val
;
294 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
296 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
300 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
302 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
305 /* MAC Saturation Mode */
307 h8_get_macS (SIM_DESC sd
)
309 return (STATE_CPU (sd
, 0)) -> macS
;
314 h8_set_macS (SIM_DESC sd
, int val
)
316 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
322 h8_get_macZ (SIM_DESC sd
)
324 return (STATE_CPU (sd
, 0)) -> macZ
;
328 h8_set_macZ (SIM_DESC sd
, int val
)
330 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
333 /* MAC Negative Flag */
335 h8_get_macN (SIM_DESC sd
)
337 return (STATE_CPU (sd
, 0)) -> macN
;
341 h8_set_macN (SIM_DESC sd
, int val
)
343 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
346 /* MAC Overflow Flag */
348 h8_get_macV (SIM_DESC sd
)
350 return (STATE_CPU (sd
, 0)) -> macV
;
354 h8_set_macV (SIM_DESC sd
, int val
)
356 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
359 /* End CPU data object. */
361 /* The rate at which to call the host's poll_quit callback. */
363 enum { POLL_QUIT_INTERVAL
= 0x80000 };
365 #define LOW_BYTE(x) ((x) & 0xff)
366 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
367 #define P(X, Y) ((X << 8) | Y)
376 #define I (intMaskBit != 0)
378 #define BUILDSR(SD) \
379 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
380 | (N << 3) | (Z << 2) | (V << 1) | C)
383 /* Get Status Register (flags). */ \
384 c = (h8_get_ccr (sd) >> 0) & 1; \
385 v = (h8_get_ccr (sd) >> 1) & 1; \
386 nz = !((h8_get_ccr (sd) >> 2) & 1); \
387 n = (h8_get_ccr (sd) >> 3) & 1; \
388 u = (h8_get_ccr (sd) >> 4) & 1; \
389 h = (h8_get_ccr (sd) >> 5) & 1; \
390 ui = ((h8_get_ccr (sd) >> 6) & 1); \
391 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
394 #ifdef __CHAR_IS_SIGNED__
395 #define SEXTCHAR(x) ((char) (x))
399 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
402 #define UEXTCHAR(x) ((x) & 0xff)
403 #define UEXTSHORT(x) ((x) & 0xffff)
404 #define SEXTSHORT(x) ((short) (x))
408 int h8300_normal_mode
= 0;
414 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
436 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
441 /* Simulate an indirection / dereference.
442 return 0 for success, -1 for failure.
446 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
448 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
450 if (val
== NULL
) /* Paranoia. */
456 if (rn
== ZERO_REGNUM
)
457 *val
= X (OP_IMM
, SP
);
459 *val
= X (OP_REG
, SP
);
462 *val
= X (OP_MEM
, SP
);
465 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
472 cmdline_location(void)
474 if (h8300smode
&& !h8300_normal_mode
)
476 else if (h8300hmode
&& !h8300_normal_mode
)
483 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
485 int cst
[3] = {0, 0, 0};
486 int reg
[3] = {0, 0, 0};
487 int rdisp
[3] = {0, 0, 0};
489 const struct h8_opcode
*q
;
494 /* Find the exact opcode/arg combo. */
495 for (q
= h8_opcodes
; q
->name
; q
++)
497 const op_type
*nib
= q
->data
.nib
;
498 unsigned int len
= 0;
500 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
501 (q
->available
== AV_H8S
&& !h8300smode
) ||
502 (q
->available
== AV_H8H
&& !h8300hmode
))
505 cst
[0] = cst
[1] = cst
[2] = 0;
506 reg
[0] = reg
[1] = reg
[2] = 0;
507 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
511 op_type looking_for
= *nib
;
512 int thisnib
= data
[len
/ 2];
514 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
515 opnum
= ((looking_for
& OP3
) ? 2 :
516 (looking_for
& DST
) ? 1 : 0);
518 if (looking_for
< 16 && looking_for
>= 0)
520 if (looking_for
!= thisnib
)
525 if (looking_for
& B31
)
527 if (!((thisnib
& 0x8) != 0))
530 looking_for
= (op_type
) (looking_for
& ~B31
);
533 else if (looking_for
& B30
)
535 if (!((thisnib
& 0x8) == 0))
538 looking_for
= (op_type
) (looking_for
& ~B30
);
541 if (looking_for
& B21
)
543 if (!((thisnib
& 0x4) != 0))
546 looking_for
= (op_type
) (looking_for
& ~B21
);
549 else if (looking_for
& B20
)
551 if (!((thisnib
& 0x4) == 0))
554 looking_for
= (op_type
) (looking_for
& ~B20
);
557 if (looking_for
& B11
)
559 if (!((thisnib
& 0x2) != 0))
562 looking_for
= (op_type
) (looking_for
& ~B11
);
565 else if (looking_for
& B10
)
567 if (!((thisnib
& 0x2) == 0))
570 looking_for
= (op_type
) (looking_for
& ~B10
);
573 if (looking_for
& B01
)
575 if (!((thisnib
& 0x1) != 0))
578 looking_for
= (op_type
) (looking_for
& ~B01
);
581 else if (looking_for
& B00
)
583 if (!((thisnib
& 0x1) == 0))
586 looking_for
= (op_type
) (looking_for
& ~B00
);
589 if (looking_for
& IGNORE
)
591 /* Hitachi has declared that IGNORE must be zero. */
595 else if ((looking_for
& MODE
) == DATA
)
597 ; /* Skip embedded data. */
599 else if ((looking_for
& MODE
) == DBIT
)
601 /* Exclude adds/subs by looking at bit 0 and 2, and
602 make sure the operand size, either w or l,
603 matches by looking at bit 1. */
604 if ((looking_for
& 7) != (thisnib
& 7))
607 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
609 else if ((looking_for
& MODE
) == REG
||
610 (looking_for
& MODE
) == LOWREG
||
611 (looking_for
& MODE
) == IND
||
612 (looking_for
& MODE
) == PREINC
||
613 (looking_for
& MODE
) == POSTINC
||
614 (looking_for
& MODE
) == PREDEC
||
615 (looking_for
& MODE
) == POSTDEC
)
617 reg
[opnum
] = thisnib
;
619 else if (looking_for
& CTRL
)
622 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
623 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
624 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
625 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
626 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
627 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
629 if (((looking_for
& MODE
) == CCR_EXR
&&
630 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
631 ((looking_for
& MODE
) == VBR_SBR
&&
632 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
633 ((looking_for
& MODE
) == MACREG
&&
634 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
636 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
637 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
638 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
641 reg
[opnum
] = thisnib
;
643 else if ((looking_for
& MODE
) == ABS
)
645 /* Absolute addresses are unsigned. */
646 switch (looking_for
& SIZE
)
649 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
653 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
657 (data
[len
/ 2 + 0] << 24) +
658 (data
[len
/ 2 + 1] << 16) +
659 (data
[len
/ 2 + 2] << 8) +
663 printf ("decode: bad size ABS: %d\n",
664 (looking_for
& SIZE
));
668 else if ((looking_for
& MODE
) == DISP
||
669 (looking_for
& MODE
) == PCREL
||
670 (looking_for
& MODE
) == INDEXB
||
671 (looking_for
& MODE
) == INDEXW
||
672 (looking_for
& MODE
) == INDEXL
)
674 switch (looking_for
& SIZE
)
677 cst
[opnum
] = thisnib
& 3;
680 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
683 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
684 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
687 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
691 (data
[len
/ 2 + 0] << 24) +
692 (data
[len
/ 2 + 1] << 16) +
693 (data
[len
/ 2 + 2] << 8) +
697 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
698 (looking_for
& SIZE
));
702 else if ((looking_for
& SIZE
) == L_16
||
703 (looking_for
& SIZE
) == L_16U
)
705 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
706 /* Immediates are always unsigned. */
707 if ((looking_for
& SIZE
) != L_16U
&&
708 (looking_for
& MODE
) != IMM
)
709 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
711 else if (looking_for
& ABSJMP
)
713 switch (looking_for
& SIZE
) {
715 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
719 (data
[len
/ 2 + 0] << 24) +
720 (data
[len
/ 2 + 1] << 16) +
721 (data
[len
/ 2 + 2] << 8) +
725 printf ("decode: bad size ABSJMP: %d\n",
726 (looking_for
& SIZE
));
730 else if ((looking_for
& MODE
) == MEMIND
)
732 cst
[opnum
] = data
[1];
734 else if ((looking_for
& MODE
) == VECIND
)
736 if(h8300_normal_mode
)
737 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
739 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
740 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
742 else if ((looking_for
& SIZE
) == L_32
)
747 (data
[i
+ 0] << 24) |
748 (data
[i
+ 1] << 16) |
752 else if ((looking_for
& SIZE
) == L_24
)
757 (data
[i
+ 0] << 16) |
761 else if (looking_for
& DISPREG
)
763 rdisp
[opnum
] = thisnib
& 0x7;
765 else if ((looking_for
& MODE
) == KBIT
)
782 else if ((looking_for
& SIZE
) == L_8
)
784 if ((looking_for
& MODE
) == ABS
)
786 /* Will be combined with contents of SBR_REGNUM
787 by fetch (). For all modes except h8sx, this
788 will always contain the value 0xFFFFFF00. */
789 cst
[opnum
] = data
[len
/ 2] & 0xff;
793 cst
[opnum
] = data
[len
/ 2] & 0xff;
796 else if ((looking_for
& SIZE
) == L_2
)
798 cst
[opnum
] = thisnib
& 3;
800 else if ((looking_for
& SIZE
) == L_3
||
801 (looking_for
& SIZE
) == L_3NZ
)
803 cst
[opnum
] = thisnib
& 7;
804 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
807 else if ((looking_for
& SIZE
) == L_4
)
809 cst
[opnum
] = thisnib
& 15;
811 else if ((looking_for
& SIZE
) == L_5
)
813 cst
[opnum
] = data
[len
/ 2] & 0x1f;
815 else if (looking_for
== E
)
820 /* Fill in the args. */
822 const op_type
*args
= q
->args
.nib
;
827 nargs
< 3 && *args
!= E
;
833 opnum
= ((x
& OP3
) ? 2 :
842 if ((x
& MODE
) == IMM
||
843 (x
& MODE
) == KBIT
||
846 /* Use the instruction to determine
848 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
849 p
->literal
= cst
[opnum
];
851 else if ((x
& MODE
) == CONST_2
||
852 (x
& MODE
) == CONST_4
||
853 (x
& MODE
) == CONST_8
||
854 (x
& MODE
) == CONST_16
)
856 /* Use the instruction to determine
858 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
860 case CONST_2
: p
->literal
= 2; break;
861 case CONST_4
: p
->literal
= 4; break;
862 case CONST_8
: p
->literal
= 8; break;
863 case CONST_16
: p
->literal
= 16; break;
866 else if ((x
& MODE
) == REG
)
868 p
->type
= X (OP_REG
, bitfrom (x
));
871 else if ((x
& MODE
) == LOWREG
)
873 p
->type
= X (OP_LOWREG
, bitfrom (x
));
876 else if ((x
& MODE
) == PREINC
)
878 /* Use the instruction to determine
880 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
881 p
->reg
= reg
[opnum
] & 0x7;
883 else if ((x
& MODE
) == POSTINC
)
885 /* Use the instruction to determine
887 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
888 p
->reg
= reg
[opnum
] & 0x7;
890 else if ((x
& MODE
) == PREDEC
)
892 /* Use the instruction to determine
894 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
895 p
->reg
= reg
[opnum
] & 0x7;
897 else if ((x
& MODE
) == POSTDEC
)
899 /* Use the instruction to determine
901 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
902 p
->reg
= reg
[opnum
] & 0x7;
904 else if ((x
& MODE
) == IND
)
906 /* Note: an indirect is transformed into
907 a displacement of zero.
909 /* Use the instruction to determine
911 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
912 p
->reg
= reg
[opnum
] & 0x7;
914 if (OP_KIND (q
->how
) == O_JSR
||
915 OP_KIND (q
->how
) == O_JMP
)
916 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
919 else if ((x
& MODE
) == ABS
)
921 /* Note: a 16 or 32 bit ABS is transformed into a
922 displacement from pseudo-register ZERO_REGNUM,
923 which is always zero. An 8 bit ABS becomes
924 a displacement from SBR_REGNUM.
926 /* Use the instruction to determine
928 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
929 p
->literal
= cst
[opnum
];
931 /* 8-bit ABS is displacement from SBR.
932 16 and 32-bit ABS are displacement from ZERO.
933 (SBR will always be zero except for h8/sx)
935 if ((x
& SIZE
) == L_8
)
938 p
->reg
= ZERO_REGNUM
;;
940 else if ((x
& MODE
) == MEMIND
||
941 (x
& MODE
) == VECIND
)
943 /* Size doesn't matter. */
944 p
->type
= X (OP_MEM
, SB
);
945 p
->literal
= cst
[opnum
];
946 if (OP_KIND (q
->how
) == O_JSR
||
947 OP_KIND (q
->how
) == O_JMP
)
948 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
951 else if ((x
& MODE
) == PCREL
)
953 /* Size doesn't matter. */
954 p
->type
= X (OP_PCREL
, SB
);
955 p
->literal
= cst
[opnum
];
959 p
->type
= X (OP_IMM
, SP
);
960 p
->literal
= cst
[opnum
];
962 else if ((x
& MODE
) == INDEXB
)
964 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
965 p
->literal
= cst
[opnum
];
966 p
->reg
= rdisp
[opnum
];
968 else if ((x
& MODE
) == INDEXW
)
970 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
971 p
->literal
= cst
[opnum
];
972 p
->reg
= rdisp
[opnum
];
974 else if ((x
& MODE
) == INDEXL
)
976 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
977 p
->literal
= cst
[opnum
];
978 p
->reg
= rdisp
[opnum
];
980 else if ((x
& MODE
) == DISP
)
982 /* Yuck -- special for mova args. */
983 if (strncmp (q
->name
, "mova", 4) == 0 &&
986 /* Mova can have a DISP2 dest, with an
987 INDEXB or INDEXW src. The multiplier
988 for the displacement value is determined
989 by the src operand, not by the insn. */
991 switch (OP_KIND (dst
->src
.type
))
994 p
->type
= X (OP_DISP
, SB
);
995 p
->literal
= cst
[opnum
];
998 p
->type
= X (OP_DISP
, SW
);
999 p
->literal
= cst
[opnum
] * 2;
1007 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1008 p
->literal
= cst
[opnum
];
1009 /* DISP2 is special. */
1010 if ((x
& SIZE
) == L_2
)
1011 switch (OP_SIZE (q
->how
))
1014 case SW
: p
->literal
*= 2; break;
1015 case SL
: p
->literal
*= 4; break;
1018 p
->reg
= rdisp
[opnum
];
1025 p
->type
= X (OP_CCR
, SB
);
1028 p
->type
= X (OP_EXR
, SB
);
1031 p
->type
= X (OP_MACH
, SL
);
1034 p
->type
= X (OP_MACL
, SL
);
1037 p
->type
= X (OP_VBR
, SL
);
1040 p
->type
= X (OP_SBR
, SL
);
1044 else if ((x
& MODE
) == CCR
)
1048 else if ((x
& MODE
) == EXR
)
1053 printf ("Hmmmm 0x%x...\n", x
);
1059 /* Unary operators: treat src and dst as equivalent. */
1060 if (dst
->dst
.type
== -1)
1061 dst
->dst
= dst
->src
;
1062 if (dst
->src
.type
== -1)
1063 dst
->src
= dst
->dst
;
1065 dst
->opcode
= q
->how
;
1066 dst
->cycles
= q
->time
;
1068 /* And jsr's to these locations are turned into
1071 if (OP_KIND (dst
->opcode
) == O_JSR
)
1073 switch (dst
->src
.literal
)
1076 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1079 dst
->opcode
= O (O_SYS_READ
, SB
);
1082 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1085 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1088 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1091 dst
->opcode
= O (O_SYS_STAT
, SB
);
1094 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1097 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1100 /* End of Processing for system calls. */
1103 /* Use same register is specified for source
1105 The value of source will be the value after
1106 address calculation. */
1107 if (OP_KIND (dst
->opcode
) != O_CMP
&&
1108 OP_KIND (dst
->src
.type
) == OP_REG
&&
1109 (dst
->src
.reg
& 7) == dst
->dst
.reg
) {
1110 switch (OP_KIND (dst
->dst
.type
))
1113 dst
->src
.type
= X (OP_REG_DEC
,
1114 OP_SIZE (dst
->dst
.type
));
1117 dst
->src
.type
= X (OP_REG_INC
,
1118 OP_SIZE (dst
->dst
.type
));
1121 if (OP_KIND (dst
->opcode
) == O_MOV
)
1122 dst
->src
.type
= X (OP_REG_INC
,
1123 OP_SIZE (dst
->dst
.type
));
1126 if (OP_KIND (dst
->opcode
) == O_MOV
)
1127 dst
->src
.type
= X (OP_REG_DEC
,
1128 OP_SIZE (dst
->dst
.type
));
1132 dst
->next_pc
= addr
+ len
/ 2;
1136 printf ("Don't understand 0x%x \n", looking_for
);
1147 /* Fell off the end. */
1148 dst
->opcode
= O (O_ILL
, SB
);
1151 static unsigned char *breg
[32];
1152 static unsigned short *wreg
[16];
1154 #define GET_B_REG(X) *(breg[X])
1155 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1156 #define GET_W_REG(X) *(wreg[X])
1157 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1158 #define GET_L_REG(X) h8_get_reg (sd, X)
1159 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1161 #define GET_MEMORY_L(X) \
1162 ((X) < memory_size \
1163 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1164 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1167 #define GET_MEMORY_W(X) \
1168 ((X) < memory_size \
1169 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1172 #define GET_MEMORY_B(X) \
1173 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1175 #define SET_MEMORY_L(X, Y) \
1176 { register unsigned char *_p; register int __y = (Y); \
1177 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1178 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1179 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1182 #define SET_MEMORY_W(X, Y) \
1183 { register unsigned char *_p; register int __y = (Y); \
1184 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1185 _p[0] = __y >> 8; _p[1] = __y; \
1188 #define SET_MEMORY_B(X, Y) \
1189 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1191 /* Simulate a memory fetch.
1192 Return 0 for success, -1 for failure.
1196 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1198 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1200 int abs
= arg
->literal
;
1205 return -1; /* Paranoia. */
1209 /* Indexed register plus displacement mode:
1211 This new family of addressing modes are similar to OP_DISP
1212 (register plus displacement), with two differences:
1213 1) INDEXB uses only the least significant byte of the register,
1214 INDEXW uses only the least significant word, and
1215 INDEXL uses the entire register (just like OP_DISP).
1217 2) The displacement value in abs is multiplied by two
1218 for SW-sized operations, and by four for SL-size.
1220 This gives nine possible variations.
1223 case X (OP_INDEXB
, SB
):
1224 case X (OP_INDEXB
, SW
):
1225 case X (OP_INDEXB
, SL
):
1226 case X (OP_INDEXW
, SB
):
1227 case X (OP_INDEXW
, SW
):
1228 case X (OP_INDEXW
, SL
):
1229 case X (OP_INDEXL
, SB
):
1230 case X (OP_INDEXL
, SW
):
1231 case X (OP_INDEXL
, SL
):
1233 switch (OP_KIND (arg
->type
)) {
1234 case OP_INDEXB
: t
&= 0xff; break;
1235 case OP_INDEXW
: t
&= 0xffff; break;
1239 switch (OP_SIZE (arg
->type
)) {
1241 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1244 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1247 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1252 case X (OP_LOWREG
, SB
):
1253 *val
= GET_L_REG (rn
) & 0xff;
1255 case X (OP_LOWREG
, SW
):
1256 *val
= GET_L_REG (rn
) & 0xffff;
1259 case X (OP_REG
, SB
): /* Register direct, byte. */
1260 *val
= GET_B_REG (rn
);
1262 case X (OP_REG
, SW
): /* Register direct, word. */
1263 *val
= GET_W_REG (rn
);
1265 case X (OP_REG
, SL
): /* Register direct, long. */
1266 *val
= GET_L_REG (rn
);
1268 case X (OP_IMM
, SB
): /* Immediate, byte. */
1269 case X (OP_IMM
, SW
): /* Immediate, word. */
1270 case X (OP_IMM
, SL
): /* Immediate, long. */
1273 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1275 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1281 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1283 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1289 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1291 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1298 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1300 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1306 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1308 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1314 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1316 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1323 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1324 t
= GET_L_REG (rn
) - 1;
1326 t
&= h8_get_mask (sd
);
1327 *val
= GET_MEMORY_B (t
);
1330 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1331 t
= GET_L_REG (rn
) - 2;
1333 t
&= h8_get_mask (sd
);
1334 *val
= GET_MEMORY_W (t
);
1337 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1338 t
= GET_L_REG (rn
) - 4;
1340 t
&= h8_get_mask (sd
);
1341 *val
= GET_MEMORY_L (t
);
1344 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1345 t
= GET_L_REG (rn
) + 1;
1347 t
&= h8_get_mask (sd
);
1348 *val
= GET_MEMORY_B (t
);
1351 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1352 t
= GET_L_REG (rn
) + 2;
1354 t
&= h8_get_mask (sd
);
1355 *val
= GET_MEMORY_W (t
);
1358 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1359 t
= GET_L_REG (rn
) + 4;
1361 t
&= h8_get_mask (sd
);
1362 *val
= GET_MEMORY_L (t
);
1365 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1366 t
= GET_L_REG (rn
) + abs
;
1367 t
&= h8_get_mask (sd
);
1368 *val
= GET_MEMORY_B (t
);
1371 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1372 t
= GET_L_REG (rn
) + abs
;
1373 t
&= h8_get_mask (sd
);
1374 *val
= GET_MEMORY_W (t
);
1377 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1378 t
= GET_L_REG (rn
) + abs
;
1379 t
&= h8_get_mask (sd
);
1380 *val
=GET_MEMORY_L (t
);
1383 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1384 t
= GET_MEMORY_L (abs
);
1385 t
&= h8_get_mask (sd
);
1389 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1390 t
= GET_MEMORY_W (abs
);
1391 t
&= h8_get_mask (sd
);
1395 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1396 case X (OP_PCREL
, SW
):
1397 case X (OP_PCREL
, SL
):
1398 case X (OP_PCREL
, SN
):
1402 case X (OP_REG_DEC
, SB
): /* Register direct, affected decrement byte. */
1403 *val
= GET_B_REG (rn
) - 1;
1405 case X (OP_REG_DEC
, SW
): /* Register direct, affected decrement word. */
1406 *val
= GET_W_REG (rn
) - 2;
1408 case X (OP_REG_DEC
, SL
): /* Register direct, affected decrement long. */
1409 *val
= GET_L_REG (rn
) - 4;
1411 case X (OP_REG_INC
, SB
): /* Register direct, affected increment byte. */
1412 *val
= GET_B_REG (rn
) + 1;
1414 case X (OP_REG_INC
, SW
): /* Register direct, affected increment word. */
1415 *val
= GET_W_REG (rn
) + 2;
1417 case X (OP_REG_INC
, SL
): /* Register direct, affected increment long. */
1418 *val
= GET_L_REG (rn
) + 4;
1421 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1423 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1426 return 0; /* Success. */
1432 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1434 return fetch_1 (sd
, arg
, val
, 0);
1437 /* Fetch which will be followed by a store to the same location.
1438 The difference being that we don't want to do a post-increment
1439 or post-decrement at this time: we'll do it when we store. */
1442 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1444 return fetch_1 (sd
, arg
, val
, 1);
1447 /* Simulate a memory store.
1448 Return 0 for success, -1 for failure.
1452 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1454 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1456 int abs
= arg
->literal
;
1461 /* Indexed register plus displacement mode:
1463 This new family of addressing modes are similar to OP_DISP
1464 (register plus displacement), with two differences:
1465 1) INDEXB uses only the least significant byte of the register,
1466 INDEXW uses only the least significant word, and
1467 INDEXL uses the entire register (just like OP_DISP).
1469 2) The displacement value in abs is multiplied by two
1470 for SW-sized operations, and by four for SL-size.
1472 This gives nine possible variations.
1475 case X (OP_INDEXB
, SB
):
1476 case X (OP_INDEXB
, SW
):
1477 case X (OP_INDEXB
, SL
):
1478 case X (OP_INDEXW
, SB
):
1479 case X (OP_INDEXW
, SW
):
1480 case X (OP_INDEXW
, SL
):
1481 case X (OP_INDEXL
, SB
):
1482 case X (OP_INDEXL
, SW
):
1483 case X (OP_INDEXL
, SL
):
1485 switch (OP_KIND (arg
->type
)) {
1486 case OP_INDEXB
: t
&= 0xff; break;
1487 case OP_INDEXW
: t
&= 0xffff; break;
1491 switch (OP_SIZE (arg
->type
)) {
1493 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1496 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1499 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1504 case X (OP_REG
, SB
): /* Register direct, byte. */
1507 case X (OP_REG
, SW
): /* Register direct, word. */
1510 case X (OP_REG
, SL
): /* Register direct, long. */
1514 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1519 t
&= h8_get_mask (sd
);
1520 SET_MEMORY_B (t
, n
);
1523 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1528 t
&= h8_get_mask (sd
);
1529 SET_MEMORY_W (t
, n
);
1532 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1537 t
&= h8_get_mask (sd
);
1538 SET_MEMORY_L (t
, n
);
1541 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1546 t
&= h8_get_mask (sd
);
1547 SET_MEMORY_B (t
, n
);
1550 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1555 t
&= h8_get_mask (sd
);
1556 SET_MEMORY_W (t
, n
);
1559 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1564 t
&= h8_get_mask (sd
);
1565 SET_MEMORY_L (t
, n
);
1568 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1570 SET_L_REG (rn
, t
- 1);
1571 t
&= h8_get_mask (sd
);
1572 SET_MEMORY_B (t
, n
);
1575 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1577 SET_L_REG (rn
, t
- 2);
1578 t
&= h8_get_mask (sd
);
1579 SET_MEMORY_W (t
, n
);
1582 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1584 SET_L_REG (rn
, t
- 4);
1585 t
&= h8_get_mask (sd
);
1586 SET_MEMORY_L (t
, n
);
1589 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1591 SET_L_REG (rn
, t
+ 1);
1592 t
&= h8_get_mask (sd
);
1593 SET_MEMORY_B (t
, n
);
1596 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1598 SET_L_REG (rn
, t
+ 2);
1599 t
&= h8_get_mask (sd
);
1600 SET_MEMORY_W (t
, n
);
1603 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1605 SET_L_REG (rn
, t
+ 4);
1606 t
&= h8_get_mask (sd
);
1607 SET_MEMORY_L (t
, n
);
1610 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1611 t
= GET_L_REG (rn
) + abs
;
1612 t
&= h8_get_mask (sd
);
1613 SET_MEMORY_B (t
, n
);
1616 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1617 t
= GET_L_REG (rn
) + abs
;
1618 t
&= h8_get_mask (sd
);
1619 SET_MEMORY_W (t
, n
);
1622 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1623 t
= GET_L_REG (rn
) + abs
;
1624 t
&= h8_get_mask (sd
);
1625 SET_MEMORY_L (t
, n
);
1629 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1630 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1631 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1633 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1642 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1644 return store_1 (sd
, arg
, n
, 0);
1647 /* Store which follows a fetch from the same location.
1648 The difference being that we don't want to do a pre-increment
1649 or pre-decrement at this time: it was already done when we fetched. */
1652 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1654 return store_1 (sd
, arg
, n
, 1);
1657 /* Flag to be set whenever a new SIM_DESC object is created. */
1658 static int init_pointers_needed
= 1;
1661 init_pointers (SIM_DESC sd
)
1663 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1665 if (init_pointers_needed
)
1669 if (h8300smode
&& !h8300_normal_mode
)
1670 memory_size
= H8300S_MSIZE
;
1671 else if (h8300hmode
&& !h8300_normal_mode
)
1672 memory_size
= H8300H_MSIZE
;
1674 memory_size
= H8300_MSIZE
;
1675 /* `msize' must be a power of two. */
1676 if ((memory_size
& (memory_size
- 1)) != 0)
1680 "init_pointers: bad memory size %d, defaulting to %d.\n",
1681 memory_size
, H8300S_MSIZE
);
1682 memory_size
= H8300S_MSIZE
;
1685 if (h8_get_memory_buf (sd
))
1686 free (h8_get_memory_buf (sd
));
1688 h8_set_memory_buf (sd
, (unsigned char *)
1689 calloc (sizeof (char), memory_size
));
1690 state
->memory_size
= memory_size
;
1692 h8_set_mask (sd
, memory_size
- 1);
1694 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1696 for (i
= 0; i
< 8; i
++)
1698 /* FIXME: rewrite using local buffer. */
1699 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1700 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1701 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1702 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1703 h8_set_reg (sd
, i
, 0x00112233);
1718 wreg
[i
] = wreg
[i
+ 8] = 0;
1732 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1733 sim_io_printf (sd
, "init_pointers: internal error.\n");
1735 h8_set_reg (sd
, i
, 0);
1738 init_pointers_needed
= 0;
1742 #define OBITOP(name, f, s, op) \
1743 case O (name, SB): \
1748 if (fetch (sd, &code->dst, &ea)) \
1750 if (fetch (sd, &code->src, &tmp)) \
1752 m = 1 << (tmp & 7); \
1755 if (store (sd, &code->dst,ea)) \
1761 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1765 int tick_start
= get_now ();
1772 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1776 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1777 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1781 pc
= h8_get_pc (sd
);
1783 /* The PC should never be odd. */
1786 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1790 /* Get Status Register (flags). */
1793 if (h8300smode
) /* Get exr. */
1795 trace
= (h8_get_exr (sd
) >> 7) & 1;
1796 intMask
= h8_get_exr (sd
) & 7;
1799 oldmask
= h8_get_mask (sd
);
1800 if (!h8300hmode
|| h8300_normal_mode
)
1801 h8_set_mask (sd
, 0xffff);
1804 decoded_inst _code
, *code
= &_code
;
1805 memset (code
, 0, sizeof (*code
));
1806 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1812 printf ("%x %d %s\n", pc
, code
->opcode
,
1813 code
->op
? code
->op
->name
: "**");
1815 h8_increment_stats (sd
, code
->opcode
);
1820 cycles
+= code
->cycles
;
1824 switch (code
->opcode
)
1826 case O (O_MOVAB
, SL
):
1827 case O (O_MOVAW
, SL
):
1828 case O (O_MOVAL
, SL
):
1829 /* 1) Evaluate 2nd argument (dst).
1830 2) Mask / zero extend according to whether 1st argument (src)
1831 is INDEXB, INDEXW, or INDEXL.
1832 3) Left-shift the result by 0, 1 or 2, according to size of mova
1833 (mova/b, mova/w, mova/l).
1834 4) Add literal value of 1st argument (src).
1835 5) Store result in 3rd argument (op3).
1838 /* Alas, since this is the only instruction with 3 arguments,
1839 decode doesn't handle them very well. Some fix-up is required.
1841 a) The size of dst is determined by whether src is
1842 INDEXB or INDEXW. */
1844 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1845 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1846 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1847 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1849 /* b) If op3 == null, then this is the short form of the insn.
1850 Dst is the dispreg of src, and op3 is the 32-bit form
1851 of the same register.
1854 if (code
->op3
.type
== 0)
1856 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1857 We get to compose dst and op3 as follows:
1859 op3 is a 32-bit register, ID == src.reg.
1860 dst is the same register, but 8 or 16 bits
1861 depending on whether src is INDEXB or INDEXW.
1864 code
->op3
.type
= X (OP_REG
, SL
);
1865 code
->op3
.reg
= code
->src
.reg
;
1866 code
->op3
.literal
= 0;
1868 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1870 code
->dst
.type
= X (OP_REG
, SB
);
1871 code
->dst
.reg
= code
->op3
.reg
+ 8;
1874 code
->dst
.type
= X (OP_REG
, SW
);
1877 if (fetch (sd
, &code
->dst
, &ea
))
1880 switch (OP_KIND (code
->src
.type
)) {
1881 case OP_INDEXB
: ea
= ea
& 0xff; break;
1882 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1883 case OP_INDEXL
: break;
1884 default: goto illegal
;
1887 switch (code
->opcode
) {
1888 case O (O_MOVAB
, SL
): break;
1889 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1890 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1891 default: goto illegal
;
1894 ea
= ea
+ code
->src
.literal
;
1896 if (store (sd
, &code
->op3
, ea
))
1901 case O (O_SUBX
, SB
): /* subx, extended sub */
1902 if (fetch2 (sd
, &code
->dst
, &rd
))
1904 if (fetch (sd
, &code
->src
, &ea
))
1910 case O (O_SUBX
, SW
): /* subx, extended sub */
1911 if (fetch2 (sd
, &code
->dst
, &rd
))
1913 if (fetch (sd
, &code
->src
, &ea
))
1919 case O (O_SUBX
, SL
): /* subx, extended sub */
1920 if (fetch2 (sd
, &code
->dst
, &rd
))
1922 if (fetch (sd
, &code
->src
, &ea
))
1928 case O (O_ADDX
, SB
): /* addx, extended add */
1929 if (fetch2 (sd
, &code
->dst
, &rd
))
1931 if (fetch (sd
, &code
->src
, &ea
))
1937 case O (O_ADDX
, SW
): /* addx, extended add */
1938 if (fetch2 (sd
, &code
->dst
, &rd
))
1940 if (fetch (sd
, &code
->src
, &ea
))
1946 case O (O_ADDX
, SL
): /* addx, extended add */
1947 if (fetch2 (sd
, &code
->dst
, &rd
))
1949 if (fetch (sd
, &code
->src
, &ea
))
1955 case O (O_SUB
, SB
): /* sub.b */
1956 /* Fetch rd and ea. */
1957 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1963 case O (O_SUB
, SW
): /* sub.w */
1964 /* Fetch rd and ea. */
1965 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1971 case O (O_SUB
, SL
): /* sub.l */
1972 /* Fetch rd and ea. */
1973 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1979 case O (O_NEG
, SB
): /* neg.b */
1981 if (fetch2 (sd
, &code
->src
, &ea
))
1988 case O (O_NEG
, SW
): /* neg.w */
1990 if (fetch2 (sd
, &code
->src
, &ea
))
1997 case O (O_NEG
, SL
): /* neg.l */
1999 if (fetch2 (sd
, &code
->src
, &ea
))
2006 case O (O_ADD
, SB
): /* add.b */
2007 if (fetch2 (sd
, &code
->dst
, &rd
))
2009 if (fetch (sd
, &code
->src
, &ea
))
2014 case O (O_ADD
, SW
): /* add.w */
2015 if (fetch2 (sd
, &code
->dst
, &rd
))
2017 if (fetch (sd
, &code
->src
, &ea
))
2022 case O (O_ADD
, SL
): /* add.l */
2023 if (fetch2 (sd
, &code
->dst
, &rd
))
2025 if (fetch (sd
, &code
->src
, &ea
))
2030 case O (O_AND
, SB
): /* and.b */
2031 /* Fetch rd and ea. */
2032 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2037 case O (O_AND
, SW
): /* and.w */
2038 /* Fetch rd and ea. */
2039 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2044 case O (O_AND
, SL
): /* and.l */
2045 /* Fetch rd and ea. */
2046 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2051 case O (O_OR
, SB
): /* or.b */
2052 /* Fetch rd and ea. */
2053 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2058 case O (O_OR
, SW
): /* or.w */
2059 /* Fetch rd and ea. */
2060 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2065 case O (O_OR
, SL
): /* or.l */
2066 /* Fetch rd and ea. */
2067 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2072 case O (O_XOR
, SB
): /* xor.b */
2073 /* Fetch rd and ea. */
2074 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2079 case O (O_XOR
, SW
): /* xor.w */
2080 /* Fetch rd and ea. */
2081 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2086 case O (O_XOR
, SL
): /* xor.l */
2087 /* Fetch rd and ea. */
2088 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2094 if (fetch (sd
, &code
->src
, &res
))
2096 if (store (sd
, &code
->dst
, res
))
2098 goto just_flags_log8
;
2100 if (fetch (sd
, &code
->src
, &res
))
2102 if (store (sd
, &code
->dst
, res
))
2104 goto just_flags_log16
;
2106 if (fetch (sd
, &code
->src
, &res
))
2108 if (store (sd
, &code
->dst
, res
))
2110 goto just_flags_log32
;
2112 case O (O_MOVMD
, SB
): /* movmd.b */
2119 rd
= GET_MEMORY_B (GET_L_REG (5));
2120 SET_MEMORY_B (GET_L_REG (6), rd
);
2121 SET_L_REG (5, GET_L_REG (5) + 1);
2122 SET_L_REG (6, GET_L_REG (6) + 1);
2127 case O (O_MOVMD
, SW
): /* movmd.w */
2134 rd
= GET_MEMORY_W (GET_L_REG (5));
2135 SET_MEMORY_W (GET_L_REG (6), rd
);
2136 SET_L_REG (5, GET_L_REG (5) + 2);
2137 SET_L_REG (6, GET_L_REG (6) + 2);
2142 case O (O_MOVMD
, SL
): /* movmd.l */
2149 rd
= GET_MEMORY_L (GET_L_REG (5));
2150 SET_MEMORY_L (GET_L_REG (6), rd
);
2151 SET_L_REG (5, GET_L_REG (5) + 4);
2152 SET_L_REG (6, GET_L_REG (6) + 4);
2157 case O (O_MOVSD
, SB
): /* movsd.b */
2158 /* This instruction implements strncpy, with a conditional branch.
2159 r4 contains n, r5 contains src, and r6 contains dst.
2160 The 16-bit displacement operand is added to the pc
2161 if and only if the end of string is reached before
2162 n bytes are transferred. */
2164 ea
= GET_L_REG (4) & 0xffff;
2170 rd
= GET_MEMORY_B (GET_L_REG (5));
2171 SET_MEMORY_B (GET_L_REG (6), rd
);
2172 SET_L_REG (5, GET_L_REG (5) + 1);
2173 SET_L_REG (6, GET_L_REG (6) + 1);
2180 case O (O_EEPMOV
, SB
): /* eepmov.b */
2181 case O (O_EEPMOV
, SW
): /* eepmov.w */
2182 if (h8300hmode
|| h8300smode
)
2184 register unsigned char *_src
, *_dst
;
2185 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2186 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2187 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2189 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2190 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2192 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2193 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2195 memcpy (_dst
, _src
, count
);
2197 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2198 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2199 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2200 ((code
->opcode
== O (O_EEPMOV
, SW
))
2201 ? (~0xffff) : (~0xff)));
2202 cycles
+= 2 * count
;
2207 case O (O_ADDS
, SL
): /* adds (.l) */
2209 * This insn only uses register operands, but still
2210 * it would be cleaner to use fetch and store... */
2211 SET_L_REG (code
->dst
.reg
,
2212 GET_L_REG (code
->dst
.reg
)
2213 + code
->src
.literal
);
2217 case O (O_SUBS
, SL
): /* subs (.l) */
2219 * This insn only uses register operands, but still
2220 * it would be cleaner to use fetch and store... */
2221 SET_L_REG (code
->dst
.reg
,
2222 GET_L_REG (code
->dst
.reg
)
2223 - code
->src
.literal
);
2226 case O (O_CMP
, SB
): /* cmp.b */
2227 if (fetch (sd
, &code
->dst
, &rd
))
2229 if (fetch (sd
, &code
->src
, &ea
))
2233 goto just_flags_alu8
;
2235 case O (O_CMP
, SW
): /* cmp.w */
2236 if (fetch (sd
, &code
->dst
, &rd
))
2238 if (fetch (sd
, &code
->src
, &ea
))
2242 goto just_flags_alu16
;
2244 case O (O_CMP
, SL
): /* cmp.l */
2245 if (fetch (sd
, &code
->dst
, &rd
))
2247 if (fetch (sd
, &code
->src
, &ea
))
2251 goto just_flags_alu32
;
2253 case O (O_DEC
, SB
): /* dec.b */
2255 * This insn only uses register operands, but still
2256 * it would be cleaner to use fetch and store... */
2257 rd
= GET_B_REG (code
->src
.reg
);
2260 SET_B_REG (code
->src
.reg
, res
);
2261 goto just_flags_inc8
;
2263 case O (O_DEC
, SW
): /* dec.w */
2265 * This insn only uses register operands, but still
2266 * it would be cleaner to use fetch and store... */
2267 rd
= GET_W_REG (code
->dst
.reg
);
2268 ea
= -code
->src
.literal
;
2270 SET_W_REG (code
->dst
.reg
, res
);
2271 goto just_flags_inc16
;
2273 case O (O_DEC
, SL
): /* dec.l */
2275 * This insn only uses register operands, but still
2276 * it would be cleaner to use fetch and store... */
2277 rd
= GET_L_REG (code
->dst
.reg
);
2278 ea
= -code
->src
.literal
;
2280 SET_L_REG (code
->dst
.reg
, res
);
2281 goto just_flags_inc32
;
2283 case O (O_INC
, SB
): /* inc.b */
2285 * This insn only uses register operands, but still
2286 * it would be cleaner to use fetch and store... */
2287 rd
= GET_B_REG (code
->src
.reg
);
2290 SET_B_REG (code
->src
.reg
, res
);
2291 goto just_flags_inc8
;
2293 case O (O_INC
, SW
): /* inc.w */
2295 * This insn only uses register operands, but still
2296 * it would be cleaner to use fetch and store... */
2297 rd
= GET_W_REG (code
->dst
.reg
);
2298 ea
= code
->src
.literal
;
2300 SET_W_REG (code
->dst
.reg
, res
);
2301 goto just_flags_inc16
;
2303 case O (O_INC
, SL
): /* inc.l */
2305 * This insn only uses register operands, but still
2306 * it would be cleaner to use fetch and store... */
2307 rd
= GET_L_REG (code
->dst
.reg
);
2308 ea
= code
->src
.literal
;
2310 SET_L_REG (code
->dst
.reg
, res
);
2311 goto just_flags_inc32
;
2313 case O (O_LDC
, SB
): /* ldc.b */
2314 if (fetch (sd
, &code
->src
, &res
))
2318 case O (O_LDC
, SW
): /* ldc.w */
2319 if (fetch (sd
, &code
->src
, &res
))
2322 /* Word operand, value from MSB, must be shifted. */
2326 case O (O_LDC
, SL
): /* ldc.l */
2327 if (fetch (sd
, &code
->src
, &res
))
2329 switch (code
->dst
.type
) {
2330 case X (OP_SBR
, SL
):
2331 h8_set_sbr (sd
, res
);
2333 case X (OP_VBR
, SL
):
2334 h8_set_vbr (sd
, res
);
2341 case O (O_STC
, SW
): /* stc.w */
2342 case O (O_STC
, SB
): /* stc.b */
2343 if (code
->src
.type
== X (OP_CCR
, SB
))
2346 res
= h8_get_ccr (sd
);
2348 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2351 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2352 res
= h8_get_exr (sd
);
2357 /* Word operand, value to MSB, must be shifted. */
2358 if (code
->opcode
== X (O_STC
, SW
))
2360 if (store (sd
, &code
->dst
, res
))
2363 case O (O_STC
, SL
): /* stc.l */
2364 switch (code
->src
.type
) {
2365 case X (OP_SBR
, SL
):
2366 res
= h8_get_sbr (sd
);
2368 case X (OP_VBR
, SL
):
2369 res
= h8_get_vbr (sd
);
2374 if (store (sd
, &code
->dst
, res
))
2378 case O (O_ANDC
, SB
): /* andc.b */
2379 if (code
->dst
.type
== X (OP_CCR
, SB
))
2382 rd
= h8_get_ccr (sd
);
2384 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2387 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2388 rd
= h8_get_exr (sd
);
2392 ea
= code
->src
.literal
;
2396 case O (O_ORC
, SB
): /* orc.b */
2397 if (code
->dst
.type
== X (OP_CCR
, SB
))
2400 rd
= h8_get_ccr (sd
);
2402 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2405 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2406 rd
= h8_get_exr (sd
);
2410 ea
= code
->src
.literal
;
2414 case O (O_XORC
, SB
): /* xorc.b */
2415 if (code
->dst
.type
== X (OP_CCR
, SB
))
2418 rd
= h8_get_ccr (sd
);
2420 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2423 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2424 rd
= h8_get_exr (sd
);
2428 ea
= code
->src
.literal
;
2432 case O (O_BRAS
, SB
): /* bra/s */
2433 /* This is basically an ordinary branch, with a delay slot. */
2434 if (fetch (sd
, &code
->src
, &res
))
2442 /* Execution continues at next instruction, but
2443 delayed_branch is set up for next cycle. */
2444 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2448 case O (O_BRAB
, SB
): /* bra rd.b */
2449 case O (O_BRAW
, SW
): /* bra rd.w */
2450 case O (O_BRAL
, SL
): /* bra erd.l */
2451 if (fetch (sd
, &code
->src
, &rd
))
2453 switch (OP_SIZE (code
->opcode
)) {
2454 case SB
: rd
&= 0xff; break;
2455 case SW
: rd
&= 0xffff; break;
2456 case SL
: rd
&= 0xffffffff; break;
2458 pc
= code
->next_pc
+ rd
;
2461 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2462 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2463 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2464 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2465 if (fetch (sd
, &code
->dst
, &rd
) ||
2466 fetch (sd
, &code
->src
, &bit
))
2469 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2470 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2472 if ((rd
& (1 << bit
))) /* no branch */
2475 else /* branch/call if set */
2477 if (!(rd
& (1 << bit
))) /* no branch */
2481 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2483 pc
= code
->next_pc
+ res
;
2485 if (code
->opcode
== O (O_BRABC
, SB
) ||
2486 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2494 case O (O_BRA
, SB
): /* bra, branch always */
2499 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2504 case O (O_BHI
, SB
): /* bhi */
2510 case O (O_BLS
, SB
): /* bls */
2515 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2520 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2525 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2529 case O (O_BGT
, SB
): /* bgt */
2530 if (((Z
|| (N
^ V
)) == 0))
2534 case O (O_BLE
, SB
): /* ble */
2535 if (((Z
|| (N
^ V
)) == 1))
2539 case O (O_BGE
, SB
): /* bge */
2543 case O (O_BLT
, SB
): /* blt */
2547 case O (O_BMI
, SB
): /* bmi */
2551 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2556 case O (O_BPL
, SB
): /* bpl */
2560 case O (O_BVC
, SB
): /* bvc */
2564 case O (O_BVS
, SB
): /* bvs */
2569 /* Trap for Command Line setup. */
2570 case O (O_SYS_CMDLINE
, SB
):
2572 int i
= 0; /* Loop counter. */
2573 int j
= 0; /* Loop counter. */
2574 int ind_arg_len
= 0; /* Length of each argument. */
2575 int no_of_args
= 0; /* The no. or cmdline args. */
2576 int current_location
= 0; /* Location of string. */
2577 int old_sp
= 0; /* The Initial Stack Pointer. */
2578 int no_of_slots
= 0; /* No. of slots required on the stack
2579 for storing cmdline args. */
2580 int sp_move
= 0; /* No. of locations by which the stack needs
2582 int new_sp
= 0; /* The final stack pointer location passed
2584 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2585 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2586 args on the stack. */
2587 int char_ptr_size
= 0; /* Size of a character pointer on
2589 int addr_cmdline
= 0; /* Memory location where cmdline has
2591 int size_cmdline
= 0; /* Size of cmdline. */
2593 /* Set the address of 256 free locations where command line is
2595 addr_cmdline
= cmdline_location();
2596 h8_set_reg (sd
, 0, addr_cmdline
);
2598 /* Counting the no. of commandline arguments. */
2599 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2602 /* No. of arguments in the command line. */
2605 /* Current location is just a temporary variable,which we are
2606 setting to the point to the start of our commandline string. */
2607 current_location
= addr_cmdline
;
2609 /* Allocating space for storing pointers of the command line
2611 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2613 /* Setting char_ptr_size to the sizeof (char *) on the different
2615 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2624 for (i
= 0; i
< no_of_args
; i
++)
2628 /* The size of the commandline argument. */
2629 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2631 /* The total size of the command line string. */
2632 size_cmdline
+= ind_arg_len
;
2634 /* As we have only 256 bytes, we need to provide a graceful
2635 exit. Anyways, a program using command line arguments
2636 where we cannot store all the command line arguments
2637 given may behave unpredictably. */
2638 if (size_cmdline
>= 256)
2640 h8_set_reg (sd
, 0, 0);
2645 /* current_location points to the memory where the next
2646 commandline argument is stored. */
2647 argv_ptrs
[i
] = current_location
;
2648 for (j
= 0; j
< ind_arg_len
; j
++)
2650 SET_MEMORY_B ((current_location
+
2651 (sizeof (char) * j
)),
2652 *(h8_get_cmdline_arg (sd
, i
) +
2653 sizeof (char) * j
));
2656 /* Setting current_location to the starting of next
2658 current_location
+= ind_arg_len
;
2662 /* This is the original position of the stack pointer. */
2663 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2665 /* We need space from the stack to store the pointers to argvs. */
2666 /* As we will infringe on the stack, we need to shift the stack
2667 pointer so that the data is not overwritten. We calculate how
2668 much space is required. */
2669 sp_move
= (no_of_args
) * (char_ptr_size
);
2671 /* The final position of stack pointer, we have thus taken some
2672 space from the stack. */
2673 new_sp
= old_sp
- sp_move
;
2675 /* Temporary variable holding value where the argv pointers need
2677 argv_ptrs_location
= new_sp
;
2679 /* The argv pointers are stored at sequential locations. As per
2681 for (i
= 0; i
< no_of_args
; i
++)
2683 /* Saving the argv pointer. */
2684 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2686 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2690 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2693 /* The next location where the pointer to the next argv
2694 string has to be stored. */
2695 argv_ptrs_location
+= char_ptr_size
;
2698 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2700 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2702 SET_MEMORY_L (old_sp
, 0x0);
2706 SET_MEMORY_W (old_sp
, 0x0);
2709 /* Freeing allocated memory. */
2711 for (i
= 0; i
<= no_of_args
; i
++)
2713 free (h8_get_cmdline_arg (sd
, i
));
2715 free (h8_get_command_line (sd
));
2717 /* The no. of argv arguments are returned in Reg 0. */
2718 h8_set_reg (sd
, 0, no_of_args
);
2719 /* The Pointer to argv in Register 1. */
2720 h8_set_reg (sd
, 1, new_sp
);
2721 /* Setting the stack pointer to the new value. */
2722 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2726 /* System call processing starts. */
2727 case O (O_SYS_OPEN
, SB
):
2729 int len
= 0; /* Length of filename. */
2730 char *filename
; /* Filename would go here. */
2731 char temp_char
; /* Temporary character */
2732 int mode
= 0; /* Mode bits for the file. */
2733 int open_return
; /* Return value of open, file descriptor. */
2734 int i
; /* Loop counter */
2735 int filename_ptr
; /* Pointer to filename in cpu memory. */
2737 /* Setting filename_ptr to first argument of open, */
2738 /* and trying to get mode. */
2739 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2741 filename_ptr
= GET_L_REG (0);
2742 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2746 filename_ptr
= GET_W_REG (0);
2747 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2750 /* Trying to find the length of the filename. */
2751 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2754 while (temp_char
!= '\0')
2756 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2760 /* Allocating space for the filename. */
2761 filename
= (char *) malloc (sizeof (char) * len
);
2763 /* String copying the filename from memory. */
2764 for (i
= 0; i
< len
; i
++)
2766 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2767 filename
[i
] = temp_char
;
2770 /* Callback to open and return the file descriptor. */
2771 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2773 /* Return value in register 0. */
2774 h8_set_reg (sd
, 0, open_return
);
2776 /* Freeing memory used for filename. */
2781 case O (O_SYS_READ
, SB
):
2783 char *char_ptr
; /* Where characters read would be stored. */
2784 int fd
; /* File descriptor */
2785 int buf_size
; /* BUF_SIZE parameter in read. */
2786 int i
= 0; /* Temporary Loop counter */
2787 int read_return
= 0; /* Return value from callback to
2790 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2791 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2793 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2795 /* Callback to read and return the no. of characters read. */
2797 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2799 /* The characters read are stored in cpu memory. */
2800 for (i
= 0; i
< buf_size
; i
++)
2802 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2803 *(char_ptr
+ (sizeof (char) * i
)));
2806 /* Return value in Register 0. */
2807 h8_set_reg (sd
, 0, read_return
);
2809 /* Freeing memory used as buffer. */
2814 case O (O_SYS_WRITE
, SB
):
2816 int fd
; /* File descriptor */
2817 char temp_char
; /* Temporary character */
2818 int len
; /* Length of write, Parameter II to write. */
2819 int char_ptr
; /* Character Pointer, Parameter I of write. */
2820 char *ptr
; /* Where characters to be written are stored.
2822 int write_return
; /* Return value from callback to write. */
2823 int i
= 0; /* Loop counter */
2825 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2826 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2827 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2829 /* Allocating space for the characters to be written. */
2830 ptr
= (char *) malloc (sizeof (char) * len
);
2832 /* Fetching the characters from cpu memory. */
2833 for (i
= 0; i
< len
; i
++)
2835 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2839 /* Callback write and return the no. of characters written. */
2840 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2842 /* Return value in Register 0. */
2843 h8_set_reg (sd
, 0, write_return
);
2845 /* Freeing memory used as buffer. */
2850 case O (O_SYS_LSEEK
, SB
):
2852 int fd
; /* File descriptor */
2853 int offset
; /* Offset */
2854 int origin
; /* Origin */
2855 int lseek_return
; /* Return value from callback to lseek. */
2857 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2858 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2859 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2861 /* Callback lseek and return offset. */
2863 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2865 /* Return value in register 0. */
2866 h8_set_reg (sd
, 0, lseek_return
);
2870 case O (O_SYS_CLOSE
, SB
):
2872 int fd
; /* File descriptor */
2873 int close_return
; /* Return value from callback to close. */
2875 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2877 /* Callback close and return. */
2878 close_return
= sim_callback
->close (sim_callback
, fd
);
2880 /* Return value in register 0. */
2881 h8_set_reg (sd
, 0, close_return
);
2885 case O (O_SYS_FSTAT
, SB
):
2887 int fd
; /* File descriptor */
2888 struct stat stat_rec
; /* Stat record */
2889 int fstat_return
; /* Return value from callback to stat. */
2890 int stat_ptr
; /* Pointer to stat record. */
2891 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2893 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2895 /* Setting stat_ptr to second argument of stat. */
2896 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2898 /* Callback stat and return. */
2899 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2902 /* Have stat_ptr point to starting of stat_rec. */
2903 temp_stat_ptr
= (char *) (&stat_rec
);
2905 /* Setting up the stat structure returned. */
2906 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2908 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2910 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2912 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2914 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2916 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2918 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2920 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2922 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2924 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2926 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2928 /* Return value in register 0. */
2929 h8_set_reg (sd
, 0, fstat_return
);
2933 case O (O_SYS_STAT
, SB
):
2935 int len
= 0; /* Length of filename. */
2936 char *filename
; /* Filename would go here. */
2937 char temp_char
; /* Temporary character */
2938 int filename_ptr
; /* Pointer to filename in cpu memory. */
2939 struct stat stat_rec
; /* Stat record */
2940 int stat_return
; /* Return value from callback to stat */
2941 int stat_ptr
; /* Pointer to stat record. */
2942 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2943 int i
= 0; /* Loop Counter */
2945 /* Setting filename_ptr to first argument of open. */
2946 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2948 /* Trying to find the length of the filename. */
2949 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2952 while (temp_char
!= '\0')
2954 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2958 /* Allocating space for the filename. */
2959 filename
= (char *) malloc (sizeof (char) * len
);
2961 /* String copying the filename from memory. */
2962 for (i
= 0; i
< len
; i
++)
2964 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2965 filename
[i
] = temp_char
;
2968 /* Setting stat_ptr to second argument of stat. */
2969 /* stat_ptr = h8_get_reg (sd, 1); */
2970 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2972 /* Callback stat and return. */
2974 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2976 /* Have stat_ptr point to starting of stat_rec. */
2977 temp_stat_ptr
= (char *) (&stat_rec
);
2979 /* Freeing memory used for filename. */
2982 /* Setting up the stat structure returned. */
2983 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2985 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2987 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2989 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2991 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2993 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2995 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2997 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2999 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3001 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3003 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3005 /* Return value in register 0. */
3006 h8_set_reg (sd
, 0, stat_return
);
3009 /* End of system call processing. */
3011 case O (O_NOT
, SB
): /* not.b */
3012 if (fetch2 (sd
, &code
->src
, &rd
))
3018 case O (O_NOT
, SW
): /* not.w */
3019 if (fetch2 (sd
, &code
->src
, &rd
))
3025 case O (O_NOT
, SL
): /* not.l */
3026 if (fetch2 (sd
, &code
->src
, &rd
))
3032 case O (O_SHLL
, SB
): /* shll.b */
3033 case O (O_SHLR
, SB
): /* shlr.b */
3034 if (fetch2 (sd
, &code
->dst
, &rd
))
3037 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3038 ea
= 1; /* unary op */
3039 else /* binary op */
3040 fetch (sd
, &code
->src
, &ea
);
3042 if (code
->opcode
== O (O_SHLL
, SB
))
3045 c
= rd
& (0x80 >> (ea
- 1));
3051 c
= rd
& (1 << (ea
- 1));
3052 rd
= (unsigned char) rd
>> ea
;
3056 case O (O_SHLL
, SW
): /* shll.w */
3057 case O (O_SHLR
, SW
): /* shlr.w */
3058 if (fetch2 (sd
, &code
->dst
, &rd
))
3061 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3062 ea
= 1; /* unary op */
3064 fetch (sd
, &code
->src
, &ea
);
3066 if (code
->opcode
== O (O_SHLL
, SW
))
3069 c
= rd
& (0x8000 >> (ea
- 1));
3075 c
= rd
& (1 << (ea
- 1));
3076 rd
= (unsigned short) rd
>> ea
;
3080 case O (O_SHLL
, SL
): /* shll.l */
3081 case O (O_SHLR
, SL
): /* shlr.l */
3082 if (fetch2 (sd
, &code
->dst
, &rd
))
3085 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3086 ea
= 1; /* unary op */
3088 fetch (sd
, &code
->src
, &ea
);
3090 if (code
->opcode
== O (O_SHLL
, SL
))
3093 c
= rd
& (0x80000000 >> (ea
- 1));
3099 c
= rd
& (1 << (ea
- 1));
3100 rd
= (unsigned int) rd
>> ea
;
3104 case O (O_SHAL
, SB
):
3105 case O (O_SHAR
, SB
):
3106 if (fetch2 (sd
, &code
->dst
, &rd
))
3109 if (code
->src
.type
== X (OP_IMM
, SB
))
3110 fetch (sd
, &code
->src
, &ea
);
3114 if (code
->opcode
== O (O_SHAL
, SB
))
3116 c
= rd
& (0x80 >> (ea
- 1));
3117 res
= rd
>> (7 - ea
);
3118 v
= ((res
& 1) && !(res
& 2))
3119 || (!(res
& 1) && (res
& 2));
3124 c
= rd
& (1 << (ea
- 1));
3126 rd
= ((signed char) rd
) >> ea
;
3130 case O (O_SHAL
, SW
):
3131 case O (O_SHAR
, SW
):
3132 if (fetch2 (sd
, &code
->dst
, &rd
))
3135 if (code
->src
.type
== X (OP_IMM
, SW
))
3136 fetch (sd
, &code
->src
, &ea
);
3140 if (code
->opcode
== O (O_SHAL
, SW
))
3142 c
= rd
& (0x8000 >> (ea
- 1));
3143 res
= rd
>> (15 - ea
);
3144 v
= ((res
& 1) && !(res
& 2))
3145 || (!(res
& 1) && (res
& 2));
3150 c
= rd
& (1 << (ea
- 1));
3152 rd
= ((signed short) rd
) >> ea
;
3156 case O (O_SHAL
, SL
):
3157 case O (O_SHAR
, SL
):
3158 if (fetch2 (sd
, &code
->dst
, &rd
))
3161 if (code
->src
.type
== X (OP_IMM
, SL
))
3162 fetch (sd
, &code
->src
, &ea
);
3166 if (code
->opcode
== O (O_SHAL
, SL
))
3168 c
= rd
& (0x80000000 >> (ea
- 1));
3169 res
= rd
>> (31 - ea
);
3170 v
= ((res
& 1) && !(res
& 2))
3171 || (!(res
& 1) && (res
& 2));
3176 c
= rd
& (1 << (ea
- 1));
3178 rd
= ((signed int) rd
) >> ea
;
3182 case O (O_ROTL
, SB
):
3183 case O (O_ROTR
, SB
):
3184 if (fetch2 (sd
, &code
->dst
, &rd
))
3187 if (code
->src
.type
== X (OP_IMM
, SB
))
3188 fetch (sd
, &code
->src
, &ea
);
3193 if (code
->opcode
== O (O_ROTL
, SB
))
3203 rd
= ((unsigned char) rd
) >> 1;
3211 case O (O_ROTL
, SW
):
3212 case O (O_ROTR
, SW
):
3213 if (fetch2 (sd
, &code
->dst
, &rd
))
3216 if (code
->src
.type
== X (OP_IMM
, SW
))
3217 fetch (sd
, &code
->src
, &ea
);
3222 if (code
->opcode
== O (O_ROTL
, SW
))
3232 rd
= ((unsigned short) rd
) >> 1;
3240 case O (O_ROTL
, SL
):
3241 case O (O_ROTR
, SL
):
3242 if (fetch2 (sd
, &code
->dst
, &rd
))
3245 if (code
->src
.type
== X (OP_IMM
, SL
))
3246 fetch (sd
, &code
->src
, &ea
);
3251 if (code
->opcode
== O (O_ROTL
, SL
))
3253 c
= rd
& 0x80000000;
3261 rd
= ((unsigned int) rd
) >> 1;
3269 case O (O_ROTXL
, SB
):
3270 case O (O_ROTXR
, SB
):
3271 if (fetch2 (sd
, &code
->dst
, &rd
))
3274 if (code
->src
.type
== X (OP_IMM
, SB
))
3275 fetch (sd
, &code
->src
, &ea
);
3280 if (code
->opcode
== O (O_ROTXL
, SB
))
3291 rd
= ((unsigned char) rd
) >> 1;
3300 case O (O_ROTXL
, SW
):
3301 case O (O_ROTXR
, SW
):
3302 if (fetch2 (sd
, &code
->dst
, &rd
))
3305 if (code
->src
.type
== X (OP_IMM
, SW
))
3306 fetch (sd
, &code
->src
, &ea
);
3311 if (code
->opcode
== O (O_ROTXL
, SW
))
3322 rd
= ((unsigned short) rd
) >> 1;
3331 case O (O_ROTXL
, SL
):
3332 case O (O_ROTXR
, SL
):
3333 if (fetch2 (sd
, &code
->dst
, &rd
))
3336 if (code
->src
.type
== X (OP_IMM
, SL
))
3337 fetch (sd
, &code
->src
, &ea
);
3342 if (code
->opcode
== O (O_ROTXL
, SL
))
3344 res
= rd
& 0x80000000;
3353 rd
= ((unsigned int) rd
) >> 1;
3364 case O (O_JMP
, SB
): /* jmp */
3366 fetch (sd
, &code
->src
, &pc
);
3371 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3373 if (fetch (sd
, &code
->src
, &pc
))
3376 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3378 if (h8300hmode
&& !h8300_normal_mode
)
3381 SET_MEMORY_L (tmp
, code
->next_pc
);
3386 SET_MEMORY_W (tmp
, code
->next_pc
);
3388 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3394 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3395 if (fetch (sd
, &code
->src
, &res
))
3397 pc
= code
->next_pc
+ res
;
3400 case O (O_RTE
, SN
): /* rte, return from exception */
3402 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3403 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3405 if (h8300smode
) /* pop exr */
3407 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3410 if (h8300hmode
&& !h8300_normal_mode
)
3412 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3414 pc
= GET_MEMORY_L (tmp
);
3419 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3421 pc
= GET_MEMORY_W (tmp
);
3426 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3429 case O (O_RTS
, SN
): /* rts, return from subroutine */
3431 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3433 if (h8300hmode
&& !h8300_normal_mode
)
3435 pc
= GET_MEMORY_L (tmp
);
3440 pc
= GET_MEMORY_W (tmp
);
3444 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3447 case O (O_ILL
, SB
): /* illegal */
3448 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3451 case O (O_SLEEP
, SN
): /* sleep */
3452 /* Check for magic numbers in r1 and r2. */
3453 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3454 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3455 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3457 /* This trap comes from _exit, not from gdb. */
3458 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3459 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3462 /* Unfortunately this won't really work, because
3463 when we take a breakpoint trap, R0 has a "random",
3464 user-defined value. Don't see any immediate solution. */
3465 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3467 /* Pass the stop signal up to gdb. */
3468 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3469 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3474 /* Treat it as a sigtrap. */
3475 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3479 case O (O_TRAPA
, SB
): /* trapa */
3480 if (fetch (sd
, &code
->src
, &res
))
3481 goto end
; /* res is vector number. */
3483 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3484 if(h8300_normal_mode
)
3487 SET_MEMORY_W (tmp
, code
->next_pc
);
3489 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3494 SET_MEMORY_L (tmp
, code
->next_pc
);
3496 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3504 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3507 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3509 if(h8300_normal_mode
)
3510 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3512 pc
= GET_MEMORY_L (0x20 + res
* 4);
3516 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3519 case O (O_BSETEQ
, SB
):
3524 case O (O_BSETNE
, SB
):
3529 case O (O_BCLREQ
, SB
):
3534 case O (O_BCLRNE
, SB
):
3539 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3540 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3542 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3544 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3545 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3546 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3547 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3548 if (C
) ea
|= m
); /* bst */
3549 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3550 if (!C
) ea
|= m
); /* bist */
3551 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3552 if (Z
) ea
|= m
); /* bstz */
3553 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3554 if (!Z
) ea
|= m
); /* bistz */
3555 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3556 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3557 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3558 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3559 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3560 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3562 case O (O_BFLD
, SB
): /* bfld */
3565 if (fetch (sd
, &code
->src
, &bit
))
3570 if (fetch (sd
, &code
->dst
, &ea
))
3580 if (store (sd
, &code
->op3
, ea
))
3585 case O(O_BFST
, SB
): /* bfst */
3586 /* bitfield store */
3587 /* NOTE: the imm8 value is in dst, and the ea value
3588 (which is actually the destination) is in op3.
3589 It has to be that way, to avoid breaking the assembler. */
3591 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3593 if (bit
== 0) /* noop -- nothing to do. */
3596 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3599 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3602 /* Left-shift the register data into position. */
3603 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3606 /* Combine it with the neighboring bits. */
3607 ea
= (ea
& ~bit
) | (rd
& bit
);
3610 if (store2 (sd
, &code
->op3
, ea
))
3614 case O (O_CLRMAC
, SN
): /* clrmac */
3615 h8_set_mach (sd
, 0);
3616 h8_set_macl (sd
, 0);
3617 h8_set_macZ (sd
, 1);
3618 h8_set_macV (sd
, 0);
3619 h8_set_macN (sd
, 0);
3622 case O (O_STMAC
, SL
): /* stmac, 260 */
3623 switch (code
->src
.type
) {
3624 case X (OP_MACH
, SL
):
3625 res
= h8_get_mach (sd
);
3626 if (res
& 0x200) /* sign extend */
3629 case X (OP_MACL
, SL
):
3630 res
= h8_get_macl (sd
);
3632 default: goto illegal
;
3634 nz
= !h8_get_macZ (sd
);
3635 n
= h8_get_macN (sd
);
3636 v
= h8_get_macV (sd
);
3638 if (store (sd
, &code
->dst
, res
))
3643 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3644 if (fetch (sd
, &code
->src
, &rd
))
3647 switch (code
->dst
.type
) {
3648 case X (OP_MACH
, SL
):
3649 rd
&= 0x3ff; /* Truncate to 10 bits */
3650 h8_set_mach (sd
, rd
);
3652 case X (OP_MACL
, SL
):
3653 h8_set_macl (sd
, rd
);
3655 default: goto illegal
;
3657 h8_set_macV (sd
, 0);
3661 if (fetch (sd
, &code
->src
, &rd
) ||
3662 fetch (sd
, &code
->dst
, &res
))
3665 /* Ye gods, this is non-portable!
3666 However, the existing mul/div code is similar. */
3667 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3669 if (h8_get_macS (sd
)) /* Saturating mode */
3671 long long mac
= h8_get_macl (sd
);
3673 if (mac
& 0x80000000) /* sign extend */
3674 mac
|= 0xffffffff00000000LL
;
3677 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3678 h8_set_macV (sd
, 1);
3679 h8_set_macZ (sd
, (mac
== 0));
3680 h8_set_macN (sd
, (mac
< 0));
3681 h8_set_macl (sd
, (int) mac
);
3683 else /* "Less Saturating" mode */
3685 long long mac
= h8_get_mach (sd
);
3687 mac
+= h8_get_macl (sd
);
3689 if (mac
& 0x20000000000LL
) /* sign extend */
3690 mac
|= 0xfffffc0000000000LL
;
3693 if (mac
> 0x1ffffffffffLL
||
3694 mac
< (long long) 0xfffffe0000000000LL
)
3695 h8_set_macV (sd
, 1);
3696 h8_set_macZ (sd
, (mac
== 0));
3697 h8_set_macN (sd
, (mac
< 0));
3698 h8_set_macl (sd
, (int) mac
);
3700 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3704 case O (O_MULS
, SW
): /* muls.w */
3705 if (fetch (sd
, &code
->src
, &ea
) ||
3706 fetch (sd
, &code
->dst
, &rd
))
3709 ea
= SEXTSHORT (ea
);
3710 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3714 if (store (sd
, &code
->dst
, res
))
3719 case O (O_MULS
, SL
): /* muls.l */
3720 if (fetch (sd
, &code
->src
, &ea
) ||
3721 fetch (sd
, &code
->dst
, &rd
))
3726 n
= res
& 0x80000000;
3727 nz
= res
& 0xffffffff;
3728 if (store (sd
, &code
->dst
, res
))
3732 case O (O_MULSU
, SL
): /* muls/u.l */
3733 if (fetch (sd
, &code
->src
, &ea
) ||
3734 fetch (sd
, &code
->dst
, &rd
))
3737 /* Compute upper 32 bits of the 64-bit result. */
3738 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3740 n
= res
& 0x80000000;
3741 nz
= res
& 0xffffffff;
3742 if (store (sd
, &code
->dst
, res
))
3746 case O (O_MULU
, SW
): /* mulu.w */
3747 if (fetch (sd
, &code
->src
, &ea
) ||
3748 fetch (sd
, &code
->dst
, &rd
))
3751 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3753 /* Don't set Z or N. */
3754 if (store (sd
, &code
->dst
, res
))
3759 case O (O_MULU
, SL
): /* mulu.l */
3760 if (fetch (sd
, &code
->src
, &ea
) ||
3761 fetch (sd
, &code
->dst
, &rd
))
3766 /* Don't set Z or N. */
3767 if (store (sd
, &code
->dst
, res
))
3772 case O (O_MULUU
, SL
): /* mulu/u.l */
3773 if (fetch (sd
, &code
->src
, &ea
) ||
3774 fetch (sd
, &code
->dst
, &rd
))
3777 /* Compute upper 32 bits of the 64-bit result. */
3778 res
= (((unsigned long long) (unsigned) ea
) *
3779 ((unsigned long long) (unsigned) rd
)) >> 32;
3781 /* Don't set Z or N. */
3782 if (store (sd
, &code
->dst
, res
))
3787 case O (O_MULXS
, SB
): /* mulxs.b */
3788 if (fetch (sd
, &code
->src
, &ea
) ||
3789 fetch (sd
, &code
->dst
, &rd
))
3793 res
= ea
* SEXTCHAR (rd
);
3797 if (store (sd
, &code
->dst
, res
))
3802 case O (O_MULXS
, SW
): /* mulxs.w */
3803 if (fetch (sd
, &code
->src
, &ea
) ||
3804 fetch (sd
, &code
->dst
, &rd
))
3807 ea
= SEXTSHORT (ea
);
3808 res
= ea
* SEXTSHORT (rd
& 0xffff);
3810 n
= res
& 0x80000000;
3811 nz
= res
& 0xffffffff;
3812 if (store (sd
, &code
->dst
, res
))
3817 case O (O_MULXU
, SB
): /* mulxu.b */
3818 if (fetch (sd
, &code
->src
, &ea
) ||
3819 fetch (sd
, &code
->dst
, &rd
))
3822 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3824 if (store (sd
, &code
->dst
, res
))
3829 case O (O_MULXU
, SW
): /* mulxu.w */
3830 if (fetch (sd
, &code
->src
, &ea
) ||
3831 fetch (sd
, &code
->dst
, &rd
))
3834 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3836 if (store (sd
, &code
->dst
, res
))
3841 case O (O_TAS
, SB
): /* tas (test and set) */
3842 if (!h8300sxmode
) /* h8sx can use any register. */
3843 switch (code
->src
.reg
)
3854 if (fetch (sd
, &code
->src
, &res
))
3856 if (store (sd
, &code
->src
, res
| 0x80))
3859 goto just_flags_log8
;
3861 case O (O_DIVU
, SW
): /* divu.w */
3862 if (fetch (sd
, &code
->src
, &ea
) ||
3863 fetch (sd
, &code
->dst
, &rd
))
3869 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3873 if (store (sd
, &code
->dst
, res
))
3877 case O (O_DIVU
, SL
): /* divu.l */
3878 if (fetch (sd
, &code
->src
, &ea
) ||
3879 fetch (sd
, &code
->dst
, &rd
))
3882 n
= ea
& 0x80000000;
3883 nz
= ea
& 0xffffffff;
3885 res
= (unsigned) rd
/ ea
;
3889 if (store (sd
, &code
->dst
, res
))
3893 case O (O_DIVS
, SW
): /* divs.w */
3894 if (fetch (sd
, &code
->src
, &ea
) ||
3895 fetch (sd
, &code
->dst
, &rd
))
3900 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3910 if (store (sd
, &code
->dst
, res
))
3914 case O (O_DIVS
, SL
): /* divs.l */
3915 if (fetch (sd
, &code
->src
, &ea
) ||
3916 fetch (sd
, &code
->dst
, &rd
))
3930 n
= res
& 0x80000000;
3931 if (store (sd
, &code
->dst
, res
))
3935 case O (O_DIVXU
, SB
): /* divxu.b */
3936 if (fetch (sd
, &code
->src
, &ea
) ||
3937 fetch (sd
, &code
->dst
, &rd
))
3940 rd
= UEXTSHORT (rd
);
3947 tmp
= (unsigned) rd
% ea
;
3948 res
= (unsigned) rd
/ ea
;
3956 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3960 case O (O_DIVXU
, SW
): /* divxu.w */
3961 if (fetch (sd
, &code
->src
, &ea
) ||
3962 fetch (sd
, &code
->dst
, &rd
))
3965 ea
= UEXTSHORT (ea
);
3971 tmp
= (unsigned) rd
% ea
;
3972 res
= (unsigned) rd
/ ea
;
3980 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3984 case O (O_DIVXS
, SB
): /* divxs.b */
3985 if (fetch (sd
, &code
->src
, &ea
) ||
3986 fetch (sd
, &code
->dst
, &rd
))
3989 rd
= SEXTSHORT (rd
);
3994 tmp
= (int) rd
% (int) ea
;
3995 res
= (int) rd
/ (int) ea
;
4006 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4010 case O (O_DIVXS
, SW
): /* divxs.w */
4011 if (fetch (sd
, &code
->src
, &ea
) ||
4012 fetch (sd
, &code
->dst
, &rd
))
4015 ea
= SEXTSHORT (ea
);
4019 tmp
= (int) rd
% (int) ea
;
4020 res
= (int) rd
/ (int) ea
;
4030 n
= res
& 0x80000000;
4031 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4035 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4036 if (fetch2 (sd
, &code
->dst
, &rd
))
4038 ea
= rd
& 0x80 ? -256 : 0;
4039 res
= (rd
& 0xff) + ea
;
4042 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4043 if (fetch2 (sd
, &code
->dst
, &rd
))
4045 if (code
->src
.type
== X (OP_IMM
, SL
))
4047 if (fetch (sd
, &code
->src
, &ea
))
4050 if (ea
== 2) /* exts.l #2, nn */
4052 /* Sign-extend from 8-bit to 32-bit. */
4053 ea
= rd
& 0x80 ? -256 : 0;
4054 res
= (rd
& 0xff) + ea
;
4058 /* Sign-extend from 16-bit to 32-bit. */
4059 ea
= rd
& 0x8000 ? -65536 : 0;
4060 res
= (rd
& 0xffff) + ea
;
4063 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4064 if (fetch2 (sd
, &code
->dst
, &rd
))
4067 res
= (rd
& 0xff) + ea
;
4070 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4071 if (fetch2 (sd
, &code
->dst
, &rd
))
4073 if (code
->src
.type
== X (OP_IMM
, SL
))
4075 if (fetch (sd
, &code
->src
, &ea
))
4078 if (ea
== 2) /* extu.l #2, nn */
4080 /* Zero-extend from 8-bit to 32-bit. */
4082 res
= (rd
& 0xff) + ea
;
4086 /* Zero-extend from 16-bit to 32-bit. */
4088 res
= (rd
& 0xffff) + ea
;
4091 case O (O_NOP
, SN
): /* nop */
4094 case O (O_STM
, SL
): /* stm, store to memory */
4096 int nregs
, firstreg
, i
;
4098 nregs
= GET_MEMORY_B (pc
+ 1);
4101 firstreg
= code
->src
.reg
;
4103 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4105 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4106 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4111 case O (O_LDM
, SL
): /* ldm, load from memory */
4112 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4113 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4115 int nregs
, firstreg
, i
;
4117 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4118 firstreg
= code
->dst
.reg
& 0xf;
4119 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4121 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4122 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4125 switch (code
->opcode
) {
4126 case O (O_RTEL
, SN
):
4128 case O (O_RTSL
, SN
):
4137 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4138 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4139 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4140 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4141 res
= res
; /* Value added == 0. */
4142 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4143 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4144 res
= res
+ 0x6; /* Value added == 6. */
4145 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4146 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4147 res
= res
+ 0x6; /* Value added == 6. */
4148 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4149 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4150 res
= res
+ 0x60; /* Value added == 60. */
4151 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4152 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4153 res
= res
+ 0x66; /* Value added == 66. */
4154 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4155 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4156 res
= res
+ 0x66; /* Value added == 66. */
4157 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4158 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4159 res
= res
+ 0x60; /* Value added == 60. */
4160 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4161 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4162 res
= res
+ 0x66; /* Value added == 66. */
4163 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4164 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4165 res
= res
+ 0x66; /* Value added == 66. */
4170 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4171 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4172 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4173 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4174 res
= res
; /* Value added == 0. */
4175 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4176 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4177 res
= res
+ 0xfa; /* Value added == 0xfa. */
4178 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4179 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4180 res
= res
+ 0xa0; /* Value added == 0xa0. */
4181 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4182 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4183 res
= res
+ 0x9a; /* Value added == 0x9a. */
4189 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4194 sim_io_printf (sd
, "sim_resume: internal error.\n");
4195 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4199 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4200 code
->dst
.type
== X (OP_CCR
, SW
))
4202 h8_set_ccr (sd
, res
);
4205 else if (h8300smode
&&
4206 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4207 code
->dst
.type
== X (OP_EXR
, SW
)))
4209 h8_set_exr (sd
, res
);
4210 if (h8300smode
) /* Get exr. */
4212 trace
= (h8_get_exr (sd
) >> 7) & 1;
4213 intMask
= h8_get_exr (sd
) & 7;
4222 /* When a branch works */
4223 if (fetch (sd
, &code
->src
, &res
))
4225 if (res
& 1) /* bad address */
4227 pc
= code
->next_pc
+ res
;
4230 /* Set the cond codes from res */
4233 /* Set the flags after an 8 bit inc/dec operation */
4237 v
= (rd
& 0x7f) == 0x7f;
4240 /* Set the flags after an 16 bit inc/dec operation */
4244 v
= (rd
& 0x7fff) == 0x7fff;
4247 /* Set the flags after an 32 bit inc/dec operation */
4249 n
= res
& 0x80000000;
4250 nz
= res
& 0xffffffff;
4251 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4255 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4258 if (store2 (sd
, &code
->dst
, rd
))
4263 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4266 if (store2 (sd
, &code
->dst
, rd
))
4271 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4272 n
= (rd
& 0x80000000);
4273 nz
= rd
& 0xffffffff;
4274 if (store2 (sd
, &code
->dst
, rd
))
4279 if (store2 (sd
, &code
->dst
, res
))
4283 /* flags after a 32bit logical operation */
4284 n
= res
& 0x80000000;
4285 nz
= res
& 0xffffffff;
4290 if (store2 (sd
, &code
->dst
, res
))
4294 /* flags after a 16bit logical operation */
4301 if (store2 (sd
, &code
->dst
, res
))
4311 if (store2 (sd
, &code
->dst
, res
))
4318 switch (code
->opcode
/ 4)
4322 v
= ((rd
& 0x80) == (ea
& 0x80)
4323 && (rd
& 0x80) != (res
& 0x80));
4328 v
= ((rd
& 0x80) != (-ea
& 0x80)
4329 && (rd
& 0x80) != (res
& 0x80));
4336 break; /* No effect on v flag. */
4341 if (store2 (sd
, &code
->dst
, res
))
4347 c
= (res
& 0x10000);
4348 switch (code
->opcode
/ 4)
4352 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4353 && (rd
& 0x8000) != (res
& 0x8000));
4358 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4359 && (rd
& 0x8000) != (res
& 0x8000));
4368 if (store2 (sd
, &code
->dst
, res
))
4372 n
= res
& 0x80000000;
4373 nz
= res
& 0xffffffff;
4374 switch (code
->opcode
/ 4)
4378 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4379 && (rd
& 0x80000000) != (res
& 0x80000000));
4380 c
= ((unsigned) res
< (unsigned) rd
) ||
4381 ((unsigned) res
< (unsigned) ea
);
4386 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4387 && (rd
& 0x80000000) != (res
& 0x80000000));
4388 c
= (unsigned) rd
< (unsigned) -ea
;
4391 v
= (rd
== 0x80000000);
4398 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4401 h8_set_delayed_branch (sd
, 0);
4409 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4410 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4411 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4416 h8_set_exr (sd
, (trace
<<7) | intMask
);
4418 h8_set_mask (sd
, oldmask
);
4422 sim_engine_run (SIM_DESC sd
,
4423 int next_cpu_nr
, /* ignore */
4424 int nr_cpus
, /* ignore */
4429 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4431 cpu
= STATE_CPU (sd
, 0);
4435 step_once (sd
, cpu
);
4436 if (sim_events_tick (sd
))
4437 sim_events_process (sd
);
4442 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4449 for (i
= 0; i
< size
; i
++)
4451 if (addr
< memory_size
)
4453 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4462 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4467 if (addr
+ size
< memory_size
)
4468 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4475 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4480 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4481 shortval
= (value
[0] << 8) | (value
[1]);
4482 intval
= h8300hmode
? longval
: shortval
;
4484 init_pointers (CPU_STATE (cpu
));
4488 if(h8300_normal_mode
)
4489 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4509 cpu
->regs
[rn
] = intval
;
4514 cpu
->regs
[rn
] = longval
;
4521 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4526 init_pointers (CPU_STATE (cpu
));
4528 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4563 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4564 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4581 sim_info (SIM_DESC sd
, int verbose
)
4583 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4584 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4585 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4587 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4588 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4589 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4590 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4591 if (timetaken
!= 0.0)
4592 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4595 /* This to be conditional on `what' (aka `verbose'),
4596 however it was never passed as non-zero. */
4600 for (i
= 0; i
< O_LAST
; i
++)
4602 if (h8_get_stats (sd
, i
))
4603 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4609 /* Indicate whether the cpu is an H8/300 or H8/300H.
4610 FLAG is non-zero for the H8/300H. */
4613 set_h8300h (unsigned long machine
)
4615 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4616 This function being replaced by a sim_open:ARGV configuration
4619 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4621 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4624 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4627 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4630 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4631 h8300_normal_mode
= 1;
4634 /* H8300-specific options.
4635 TODO: These really should be merged into the common model modules. */
4643 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4644 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4646 switch ((H8300_OPTIONS
) opt
)
4649 set_h8300h (bfd_mach_h8300h
);
4652 set_h8300h (bfd_mach_h8300s
);
4654 case OPTION_H8300SX
:
4655 set_h8300h (bfd_mach_h8300sx
);
4659 /* We'll actually never get here; the caller handles the error
4661 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4668 static const OPTION h8300_options
[] =
4670 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4671 'h', NULL
, "Indicate the CPU is H8/300H",
4672 h8300_option_handler
},
4673 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4674 'S', NULL
, "Indicate the CPU is H8S",
4675 h8300_option_handler
},
4676 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4677 'x', NULL
, "Indicate the CPU is H8SX",
4678 h8300_option_handler
},
4679 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4683 h8300_pc_get (sim_cpu
*cpu
)
4689 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4694 /* Cover function of sim_state_free to free the cpu buffers as well. */
4697 free_state (SIM_DESC sd
)
4699 if (STATE_MODULES (sd
) != NULL
)
4700 sim_module_uninstall (sd
);
4702 /* Fixme: free buffers in _sim_cpu. */
4703 sim_state_free (sd
);
4707 sim_open (SIM_OPEN_KIND kind
,
4708 struct host_callback_struct
*callback
,
4716 sd
= sim_state_alloc_extra (kind
, callback
, sizeof (struct h8300_sim_state
));
4718 /* The cpu data is kept in a separately allocated chunk of memory. */
4719 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4725 cpu
= STATE_CPU (sd
, 0);
4726 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4727 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4728 /* sim_cpu object is new, so some initialization is needed. */
4729 init_pointers_needed
= 1;
4731 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4737 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4743 /* The parser will print an error message for us, so we silently return. */
4744 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4746 /* Uninstall the modules to avoid memory leaks,
4747 file descriptor leaks, etc. */
4752 /* Check for/establish the a reference program image. */
4753 if (sim_analyze_program (sd
,
4754 (STATE_PROG_ARGV (sd
) != NULL
4755 ? *STATE_PROG_ARGV (sd
)
4756 : NULL
), abfd
) != SIM_RC_OK
)
4762 /* Establish any remaining configuration options. */
4763 if (sim_config (sd
) != SIM_RC_OK
)
4769 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4771 /* Uninstall the modules to avoid memory leaks,
4772 file descriptor leaks, etc. */
4777 /* CPU specific initialization. */
4778 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4780 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4782 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4783 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4784 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4785 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4788 /* sim_hw_configure (sd); */
4790 /* FIXME: Much of the code in sim_load can be moved here. */
4795 /* Called by gdb to load a program into memory. */
4798 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4800 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4803 /* FIXME: The code below that sets a specific variant of the H8/300
4804 being simulated should be moved to sim_open(). */
4806 /* See if the file is for the H8/300 or H8/300H. */
4807 /* ??? This may not be the most efficient way. The z8k simulator
4808 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4812 prog_bfd
= bfd_openr (prog
, NULL
);
4813 if (prog_bfd
!= NULL
)
4815 /* Set the cpu type. We ignore failure from bfd_check_format
4816 and bfd_openr as sim_load_file checks too. */
4817 if (bfd_check_format (prog_bfd
, bfd_object
))
4819 set_h8300h (bfd_get_mach (prog_bfd
));
4823 /* If we're using gdb attached to the simulator, then we have to
4824 reallocate memory for the simulator.
4826 When gdb first starts, it calls fetch_registers (among other
4827 functions), which in turn calls init_pointers, which allocates
4830 The problem is when we do that, we don't know whether we're
4831 debugging an H8/300 or H8/300H program.
4833 This is the first point at which we can make that determination,
4834 so we just reallocate memory now; this will also allow us to handle
4835 switching between H8/300 and H8/300H programs without exiting
4838 if (h8300smode
&& !h8300_normal_mode
)
4839 memory_size
= H8300S_MSIZE
;
4840 else if (h8300hmode
&& !h8300_normal_mode
)
4841 memory_size
= H8300H_MSIZE
;
4843 memory_size
= H8300_MSIZE
;
4845 if (h8_get_memory_buf (sd
))
4846 free (h8_get_memory_buf (sd
));
4848 h8_set_memory_buf (sd
, (unsigned char *)
4849 calloc (sizeof (char), memory_size
));
4850 state
->memory_size
= memory_size
;
4852 /* `msize' must be a power of two. */
4853 if ((memory_size
& (memory_size
- 1)) != 0)
4855 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4858 h8_set_mask (sd
, memory_size
- 1);
4860 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4861 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4865 /* Close the bfd if we opened it. */
4866 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4867 bfd_close (prog_bfd
);
4871 /* Close the bfd if we opened it. */
4872 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4873 bfd_close (prog_bfd
);
4878 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4879 char * const *argv
, char * const *env
)
4886 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4890 /* Command Line support. */
4893 /* Counting the no. of commandline arguments. */
4894 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4897 /* Allocating memory for the argv pointers. */
4898 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4899 * (no_of_args
+ 1)));
4901 for (i
= 0; i
< no_of_args
; i
++)
4903 /* Copying the argument string. */
4904 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4906 h8_set_cmdline_arg (sd
, i
, NULL
);