sim/h8300/compile.c

   1 /*
   2  * Simulator for the Hitachi H8/300 architecture.
   3  *
   4  * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   5  *
   6  * This file is part of H8/300 sim
   7  *
   8  *
   9  * THIS SOFTWARE IS NOT COPYRIGHTED
  10  *
  11  * Cygnus offers the following for use in the public domain.  Cygnus makes no
  12  * warranty with regard to the software or its performance and the user
  13  * accepts the software "AS IS" with all faults.
  14  *
  15  * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
  16  * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
  17  * AND FITNESS FOR A PARTICULAR PURPOSE.
  18  */
  19
  20 #include "config.h"
  21
  22 #include <signal.h>
  23 #ifdef HAVE_TIME_H
  24 #include <time.h>
  25 #endif
  26 #ifdef HAVE_STDLIB_H
  27 #include <stdlib.h>
  28 #endif
  29 #include <sys/param.h>
  30 #include "ansidecl.h"
  31 #include "callback.h"
  32 #include "remote-sim.h"
  33 #include "bfd.h"
  34
  35 int debug;
  36
  37
  38 #define X(op, size)  op*4+size
  39
  40 #define SP (h8300hmode ? SL:SW)
  41 #define SB 0
  42 #define SW 1
  43 #define SL 2
  44 #define OP_REG 1
  45 #define OP_DEC 2
  46 #define OP_DISP 3
  47 #define OP_INC 4
  48 #define OP_PCREL 5
  49 #define OP_MEM 6
  50 #define OP_CCR 7
  51 #define OP_IMM 8
  52 #define OP_ABS 10
  53 #define h8_opcodes ops
  54 #define DEFINE_TABLE
  55 #include "opcode/h8300.h"
  56
  57 #include "inst.h"
  58
  59 #define LOW_BYTE(x) ((x) & 0xff)
  60 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
  61 #define P(X,Y) ((X<<8) | Y)
  62
  63 #define BUILDSR()   cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
  64
  65 #define GETSR()             \
  66   c = (cpu.ccr >> 0) & 1;\
  67   v = (cpu.ccr >> 1) & 1;\
  68   nz = !((cpu.ccr >> 2) & 1);\
  69   n = (cpu.ccr >> 3) & 1;
  70
  71 #ifdef __CHAR_IS_SIGNED__
  72 #define SEXTCHAR(x) ((char)(x))
  73 #endif
  74
  75 #ifndef SEXTCHAR
  76 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
  77 #endif
  78
  79 #define UEXTCHAR(x) ((x) & 0xff)
  80 #define UEXTSHORT(x) ((x) & 0xffff)
  81 #define SEXTSHORT(x) ((short)(x))
  82
  83 static cpu_state_type cpu;
  84
  85 int h8300hmode = 0;
  86
  87 static int memory_size;
  88
  89
  90 static int
  91 get_now ()
  92 {
  93 #ifndef WIN32
  94   return time (0);
  95 #endif
  96   return 0;
  97 }
  98
  99 static int
 100 now_persec ()
 101 {
 102   return 1;
 103 }
 104
 105
 106 static int
 107 bitfrom (x)
 108 {
 109   switch (x & SIZE)
 110     {
 111     case L_8:
 112       return SB;
 113     case L_16:
 114       return SW;
 115     case L_32:
 116       return SL;
 117     case L_P:
 118       return h8300hmode ? SL : SW;
 119     }
 120 }
 121
 122 static
 123 unsigned int
 124 lvalue (x, rn)
 125 {
 126   switch (x / 4)
 127     {
 128     case OP_DISP:
 129       if (rn == 8)
 130         {
 131           return X (OP_IMM, SP);
 132         }
 133       return X (OP_REG, SP);
 134
 135     case OP_MEM:
 136
 137       return X (OP_MEM, SP);
 138     default:
 139       abort ();
 140     }
 141 }
 142
 143 static unsigned int
 144 decode (addr, data, dst)
 145      int addr;
 146      unsigned char *data;
 147      decoded_inst *dst;
 148
 149 {
 150   int rs = 0;
 151   int rd = 0;
 152   int rdisp = 0;
 153   int abs = 0;
 154   int plen = 0;
 155
 156   struct h8_opcode *q = h8_opcodes;
 157   int size = 0;
 158   dst->dst.type = -1;
 159   dst->src.type = -1;
 160   /* Find the exact opcode/arg combo */
 161   while (q->name)
 162     {
 163       op_type *nib;
 164       unsigned int len = 0;
 165
 166       nib = q->data.nib;
 167
 168       while (1)
 169         {
 170           op_type looking_for = *nib;
 171           int thisnib = data[len >> 1];
 172
 173           thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
 174
 175           if (looking_for < 16 && looking_for >= 0)
 176             {
 177               if (looking_for != thisnib)
 178                 goto fail;
 179             }
 180           else
 181             {
 182               if ((int) looking_for & (int) B31)
 183                 {
 184                   if (!(((int) thisnib & 0x8) != 0))
 185                     goto fail;
 186                   looking_for = (op_type) ((int) looking_for & ~(int)
 187                                            B31);
 188                   thisnib &= 0x7;
 189                 }
 190               if ((int) looking_for & (int) B30)
 191                 {
 192                   if (!(((int) thisnib & 0x8) == 0))
 193                     goto fail;
 194                   looking_for = (op_type) ((int) looking_for & ~(int) B30);
 195                 }
 196               if (looking_for & DBIT)
 197                 {
 198                   if ((looking_for & 5) != (thisnib & 5))
 199                     goto fail;
 200                   abs = (thisnib & 0x8) ? 2 : 1;
 201                 }
 202               else if (looking_for & (REG | IND | INC | DEC))
 203                 {
 204                   if (looking_for & REG)
 205                     {
 206                       /*
 207                        * Can work out size from the
 208                        * register
 209                        */
 210                       size = bitfrom (looking_for);
 211                     }
 212                   if (looking_for & SRC)
 213                     {
 214                       rs = thisnib;
 215                     }
 216                   else
 217                     {
 218                       rd = thisnib;
 219                     }
 220                 }
 221               else if (looking_for & L_16)
 222                 {
 223                   abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
 224                   plen = 16;
 225                   if (looking_for & (PCREL | DISP))
 226                     {
 227                       abs = (short) (abs);
 228                     }
 229                 }
 230               else if (looking_for & ABSJMP)
 231                 {
 232                   abs =
 233                     (data[1] << 16)
 234                     | (data[2] << 8)
 235                     | (data[3]);
 236                 }
 237               else if (looking_for & MEMIND)
 238                 {
 239                   abs = data[1];
 240                 }
 241               else if (looking_for & L_32)
 242                 {
 243                   int i = len >> 1;
 244                   abs = (data[i] << 24)
 245                     | (data[i + 1] << 16)
 246                     | (data[i + 2] << 8)
 247                     | (data[i + 3]);
 248
 249                   plen = 32;
 250                 }
 251               else if (looking_for & L_24)
 252                 {
 253                   int i = len >> 1;
 254                   abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
 255                   plen = 24;
 256                 }
 257               else if (looking_for & IGNORE)
 258                 {
 259                   /* nothing to do */
 260                 }
 261               else if (looking_for & DISPREG)
 262                 {
 263                   rdisp = thisnib & 0x7;
 264                 }
 265               else if (looking_for & KBIT)
 266                 {
 267                   switch (thisnib)
 268                     {
 269                     case 9:
 270                       abs = 4;
 271                       break;
 272                     case 8:
 273                       abs = 2;
 274                       break;
 275                     case 0:
 276                       abs = 1;
 277                       break;
 278                     }
 279                 }
 280               else if (looking_for & L_8)
 281                 {
 282                   plen = 8;
 283
 284                   if (looking_for & PCREL)
 285                     {
 286                       abs = SEXTCHAR (data[len >> 1]);
 287                     }
 288                   else
 289                     {
 290                       abs = data[len >> 1] & 0xff;
 291                     }
 292                 }
 293               else if (looking_for & L_3)
 294                 {
 295                   plen = 3;
 296
 297                   abs = thisnib;
 298                 }
 299               else if (looking_for == E)
 300                 {
 301                   dst->op = q;
 302
 303                   /* Fill in the args */
 304                   {
 305                     op_type *args = q->args.nib;
 306                     int hadone = 0;
 307
 308                     while (*args != E)
 309                       {
 310                         int x = *args;
 311                         int rn = (x & DST) ? rd : rs;
 312                         ea_type *p;
 313
 314                         if (x & DST)
 315                           {
 316                             p = &(dst->dst);
 317                           }
 318                         else
 319                           {
 320                             p = &(dst->src);
 321                           }
 322
 323                         if (x & (IMM | KBIT | DBIT))
 324                           {
 325                             p->type = X (OP_IMM, size);
 326                             p->literal = abs;
 327                           }
 328                         else if (x & REG)
 329                           {
 330                             /* Reset the size, some
 331                                ops (like mul) have two sizes */
 332
 333                             size = bitfrom (x);
 334                             p->type = X (OP_REG, size);
 335                             p->reg = rn;
 336                           }
 337                         else if (x & INC)
 338                           {
 339                             p->type = X (OP_INC, size);
 340                             p->reg = rn & 0x7;
 341                           }
 342                         else if (x & DEC)
 343                           {
 344                             p->type = X (OP_DEC, size);
 345                             p->reg = rn & 0x7;
 346                           }
 347                         else if (x & IND)
 348                           {
 349                             p->type = X (OP_DISP, size);
 350                             p->reg = rn & 0x7;
 351                             p->literal = 0;
 352                           }
 353                         else if (x & (ABS | ABSJMP | ABSMOV))
 354                           {
 355                             p->type = X (OP_DISP, size);
 356                             p->literal = abs;
 357                             p->reg = 8;
 358                           }
 359                         else if (x & MEMIND)
 360                           {
 361                             p->type = X (OP_MEM, size);
 362                             p->literal = abs;
 363                           }
 364                         else if (x & PCREL)
 365                           {
 366                             p->type = X (OP_PCREL, size);
 367                             p->literal = abs + addr + 2;
 368                             if (x & L_16)
 369                               p->literal += 2;
 370                           }
 371                         else if (x & ABSJMP)
 372                           {
 373                             p->type = X (OP_IMM, SP);
 374                             p->literal = abs;
 375                           }
 376                         else if (x & DISP)
 377                           {
 378                             p->type = X (OP_DISP, size);
 379                             p->literal = abs;
 380                             p->reg = rdisp & 0x7;
 381                           }
 382                         else if (x & CCR)
 383                           {
 384                             p->type = OP_CCR;
 385                           }
 386                         else
 387                           printf ("Hmmmm %x", x);
 388
 389                         args++;
 390                       }
 391                   }
 392
 393                   /*
 394                      * But a jmp or a jsr gets
 395                      * automagically lvalued, since we
 396                      * branch to their address not their
 397                      * contents
 398                    */
 399                   if (q->how == O (O_JSR, SB)
 400                       || q->how == O (O_JMP, SB))
 401                     {
 402                       dst->src.type = lvalue (dst->src.type, dst->src.reg);
 403                     }
 404
 405                   if (dst->dst.type == -1)
 406                     dst->dst = dst->src;
 407
 408                   dst->opcode = q->how;
 409                   dst->cycles = q->time;
 410
 411                   /* And a jsr to 0xc4 is turned into a magic trap */
 412
 413                   if (dst->opcode == O (O_JSR, SB))
 414                     {
 415                       if (dst->src.literal == 0xc4)
 416                         {
 417                           dst->opcode = O (O_SYSCALL, SB);
 418                         }
 419                     }
 420
 421                   dst->next_pc = addr + len / 2;
 422                   return;
 423                 }
 424               else
 425                 {
 426                   printf ("Dont understand %x \n", looking_for);
 427                 }
 428             }
 429
 430           len++;
 431           nib++;
 432         }
 433
 434     fail:
 435       q++;
 436     }
 437
 438   dst->opcode = O (O_ILL, SB);
 439 }
 440
 441
 442 static void
 443 compile (pc)
 444 {
 445   int idx;
 446
 447   /* find the next cache entry to use */
 448
 449   idx = cpu.cache_top + 1;
 450   cpu.compiles++;
 451   if (idx >= cpu.csize)
 452     {
 453       idx = 1;
 454     }
 455   cpu.cache_top = idx;
 456
 457   /* Throw away its old meaning */
 458   cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
 459
 460   /* set to new address */
 461   cpu.cache[idx].oldpc = pc;
 462
 463   /* fill in instruction info */
 464   decode (pc, cpu.memory + pc, cpu.cache + idx);
 465
 466   /* point to new cache entry */
 467   cpu.cache_idx[pc] = idx;
 468 }
 469
 470
 471 static unsigned char *breg[18];
 472 static unsigned short *wreg[18];
 473 static unsigned int *lreg[18];
 474
 475 #define GET_B_REG(x) *(breg[x])
 476 #define SET_B_REG(x,y) (*(breg[x])) = (y)
 477 #define GET_W_REG(x) *(wreg[x])
 478 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
 479
 480 #define GET_L_REG(x) *(lreg[x])
 481 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
 482
 483 #define GET_MEMORY_L(x) \
 484   ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
 485
 486 #define GET_MEMORY_W(x) \
 487   ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
 488
 489
 490 #define SET_MEMORY_B(x,y) \
 491   (cpu.memory[(x)] = y)
 492
 493 #define SET_MEMORY_W(x,y) \
 494 {register unsigned char *_p = cpu.memory+x;\
 495    register int __y = y;\
 496      _p[0] = (__y)>>8;\
 497        _p[1] =(__y);     }
 498
 499 #define SET_MEMORY_L(x,y)  \
 500 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
 501    _p[0] = (__y)>>24;    _p[1] = (__y)>>16;      _p[2] = (__y)>>8;       _p[3] = (__y)>>0;}
 502
 503 #define GET_MEMORY_B(x)  (cpu.memory[x])
 504
 505 int
 506 fetch (arg, n)
 507      ea_type *arg;
 508 {
 509   int rn = arg->reg;
 510   int abs = arg->literal;
 511   int r;
 512   int t;
 513
 514   switch (arg->type)
 515     {
 516     case X (OP_REG, SB):
 517       return GET_B_REG (rn);
 518     case X (OP_REG, SW):
 519       return GET_W_REG (rn);
 520     case X (OP_REG, SL):
 521       return GET_L_REG (rn);
 522     case X (OP_IMM, SB):
 523     case X (OP_IMM, SW):
 524     case X (OP_IMM, SL):
 525       return abs;
 526     case X (OP_DEC, SB):
 527       abort ();
 528
 529     case X (OP_INC, SB):
 530       t = GET_L_REG (rn);
 531       t &= cpu.mask;
 532       r = GET_MEMORY_B (t);
 533       t++;
 534       t = t & cpu.mask;
 535       SET_L_REG (rn, t);
 536       return r;
 537       break;
 538     case X (OP_INC, SW):
 539       t = GET_L_REG (rn);
 540       t &= cpu.mask;
 541       r = GET_MEMORY_W (t);
 542       t += 2;
 543       t = t & cpu.mask;
 544       SET_L_REG (rn, t);
 545       return r;
 546     case X (OP_INC, SL):
 547       t = GET_L_REG (rn);
 548       t &= cpu.mask;
 549       r = GET_MEMORY_L (t);
 550
 551       t += 4;
 552       t = t & cpu.mask;
 553       SET_L_REG (rn, t);
 554       return r;
 555
 556     case X (OP_DISP, SB):
 557       t = GET_L_REG (rn) + abs;
 558       t &= cpu.mask;
 559       return GET_MEMORY_B (t);
 560
 561     case X (OP_DISP, SW):
 562       t = GET_L_REG (rn) + abs;
 563       t &= cpu.mask;
 564       return GET_MEMORY_W (t);
 565
 566     case X (OP_DISP, SL):
 567       t = GET_L_REG (rn) + abs;
 568       t &= cpu.mask;
 569       return GET_MEMORY_L (t);
 570
 571     case X (OP_MEM, SL):
 572       t = GET_MEMORY_L (abs);
 573       t &= cpu.mask;
 574       return t;
 575
 576     default:
 577       abort ();
 578
 579     }
 580 }
 581
 582
 583 static
 584 void
 585 store (arg, n)
 586      ea_type *arg;
 587      int n;
 588 {
 589   int rn = arg->reg;
 590   int abs = arg->literal;
 591   int t;
 592
 593   switch (arg->type)
 594     {
 595     case X (OP_REG, SB):
 596       SET_B_REG (rn, n);
 597       break;
 598     case X (OP_REG, SW):
 599       SET_W_REG (rn, n);
 600       break;
 601     case X (OP_REG, SL):
 602       SET_L_REG (rn, n);
 603       break;
 604
 605     case X (OP_DEC, SB):
 606       t = GET_L_REG (rn) - 1;
 607       t &= cpu.mask;
 608       SET_L_REG (rn, t);
 609       SET_MEMORY_B (t, n);
 610
 611       break;
 612     case X (OP_DEC, SW):
 613       t = (GET_L_REG (rn) - 2) & cpu.mask;
 614       SET_L_REG (rn, t);
 615       SET_MEMORY_W (t, n);
 616       break;
 617
 618     case X (OP_DEC, SL):
 619       t = (GET_L_REG (rn) - 4) & cpu.mask;
 620       SET_L_REG (rn, t);
 621       SET_MEMORY_L (t, n);
 622       break;
 623
 624     case X (OP_DISP, SB):
 625       t = GET_L_REG (rn) + abs;
 626       t &= cpu.mask;
 627       SET_MEMORY_B (t, n);
 628       break;
 629
 630     case X (OP_DISP, SW):
 631       t = GET_L_REG (rn) + abs;
 632       t &= cpu.mask;
 633       SET_MEMORY_W (t, n);
 634       break;
 635
 636     case X (OP_DISP, SL):
 637       t = GET_L_REG (rn) + abs;
 638       t &= cpu.mask;
 639       SET_MEMORY_L (t, n);
 640       break;
 641     default:
 642       abort ();
 643     }
 644 }
 645
 646
 647 static union
 648 {
 649   short int i;
 650   struct
 651     {
 652       char low;
 653       char high;
 654     }
 655   u;
 656 }
 657
 658 littleendian;
 659
 660 static
 661 void
 662 init_pointers ()
 663 {
 664   static int init;
 665
 666   if (!init)
 667     {
 668       int i;
 669
 670       init = 1;
 671       littleendian.i = 1;
 672
 673       if (h8300hmode)
 674         memory_size = H8300H_MSIZE;
 675       else
 676         memory_size = H8300_MSIZE;
 677       cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
 678       cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
 679
 680       /* `msize' must be a power of two */
 681       if ((memory_size & (memory_size - 1)) != 0)
 682         abort ();
 683       cpu.mask = memory_size - 1;
 684
 685       for (i = 0; i < 9; i++)
 686         {
 687           cpu.regs[i] = 0;
 688         }
 689
 690       for (i = 0; i < 8; i++)
 691         {
 692           unsigned char *p = (unsigned char *) (cpu.regs + i);
 693           unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
 694           unsigned short *q = (unsigned short *) (cpu.regs + i);
 695           unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
 696           cpu.regs[i] = 0x00112233;
 697           while (p < e)
 698             {
 699               if (*p == 0x22)
 700                 {
 701                   breg[i] = p;
 702                 }
 703               if (*p == 0x33)
 704                 {
 705                   breg[i + 8] = p;
 706                 }
 707               p++;
 708             }
 709           while (q < u)
 710             {
 711               if (*q == 0x2233)
 712                 {
 713                   wreg[i] = q;
 714                 }
 715               if (*q == 0x0011)
 716                 {
 717                   wreg[i + 8] = q;
 718                 }
 719               q++;
 720             }
 721           cpu.regs[i] = 0;
 722           lreg[i] = &cpu.regs[i];
 723         }
 724
 725       lreg[8] = &cpu.regs[8];
 726
 727       /* initialize the seg registers */
 728       if (!cpu.cache)
 729         sim_csize (CSIZE);
 730     }
 731 }
 732
 733 static void
 734 control_c (sig, code, scp, addr)
 735      int sig;
 736      int code;
 737      char *scp;
 738      char *addr;
 739 {
 740   cpu.exception = SIGINT;
 741 }
 742
 743 #define C (c != 0)
 744 #define Z (nz == 0)
 745 #define V (v != 0)
 746 #define N (n != 0)
 747
 748 static int
 749 mop (code, bsize, sign)
 750      decoded_inst *code;
 751      int bsize;
 752      int sign;
 753 {
 754   int multiplier;
 755   int multiplicand;
 756   int result;
 757   int n, nz;
 758
 759   if (sign)
 760     {
 761       multiplicand =
 762         bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
 763         SEXTSHORT (GET_W_REG (code->dst.reg));
 764       multiplier =
 765         bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
 766         SEXTSHORT (GET_W_REG (code->src.reg));
 767     }
 768   else
 769     {
 770       multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
 771         UEXTSHORT (GET_W_REG (code->dst.reg));
 772       multiplier =
 773         bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
 774         UEXTSHORT (GET_W_REG (code->src.reg));
 775
 776     }
 777   result = multiplier * multiplicand;
 778
 779   if (sign)
 780     {
 781       n = result & (bsize ? 0x8000 : 0x80000000);
 782       nz = result & (bsize ? 0xffff : 0xffffffff);
 783     }
 784   if (bsize)
 785     {
 786       SET_W_REG (code->dst.reg, result);
 787     }
 788   else
 789     {
 790       SET_L_REG (code->dst.reg, result);
 791     }
 792 /*  return ((n==1) << 1) | (nz==1); */
 793
 794 }
 795
 796 #define OSHIFTS(name, how) \
 797 case O(name, SB):                               \
 798 {                                               \
 799   int t;                                        \
 800   int hm = 0x80;                                \
 801   rd = GET_B_REG (code->src.reg);               \
 802   how;                                          \
 803   goto shift8;                                  \
 804 }                                               \
 805 case O(name, SW):                               \
 806 {                                               \
 807   int t;                                        \
 808   int hm = 0x8000;                              \
 809   rd = GET_W_REG (code->src.reg);               \
 810   how;                                          \
 811   goto shift16;                                 \
 812 }                                               \
 813 case O(name, SL):                               \
 814 {                                               \
 815   int t;                                        \
 816   int hm = 0x80000000;                          \
 817   rd = GET_L_REG (code->src.reg);               \
 818   how;                                          \
 819   goto shift32;                                 \
 820 }
 821
 822 #define OBITOP(name,f, s, op)                   \
 823 case  O(name, SB):                              \
 824 {                                               \
 825   int m;                                        \
 826   int b;                                        \
 827   if (f) ea = fetch (&code->dst);               \
 828   m=1<< fetch(&code->src);                      \
 829   op;                                           \
 830   if(s) store (&code->dst,ea); goto next;       \
 831 }
 832
 833 void
 834 sim_resume (step, siggnal)
 835 {
 836   static int init1;
 837   int cycles = 0;
 838   int insts = 0;
 839   int tick_start = get_now ();
 840   void (*prev) ();
 841   int poll_count = 0;
 842   int res;
 843   int tmp;
 844   int rd;
 845   int ea;
 846   int bit;
 847   int pc;
 848   int c, nz, v, n;
 849   int oldmask;
 850   init_pointers ();
 851
 852   prev = signal (SIGINT, control_c);
 853
 854   if (step)
 855     {
 856       cpu.exception = SIGTRAP;
 857     }
 858   else
 859     {
 860       cpu.exception = 0;
 861     }
 862
 863   pc = cpu.pc;
 864
 865   GETSR ();
 866   oldmask = cpu.mask;
 867   if (!h8300hmode)
 868     cpu.mask = 0xffff;
 869   do
 870     {
 871       int cidx;
 872       decoded_inst *code;
 873
 874     top:
 875       cidx = cpu.cache_idx[pc];
 876       code = cpu.cache + cidx;
 877
 878
 879 #define ALUOP(STORE, NAME, HOW) \
 880     case O(NAME,SB):  HOW; if(STORE)goto alu8;else goto just_flags_alu8;  \
 881     case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
 882     case O(NAME,SL):  HOW; if(STORE)goto alu32;else goto just_flags_alu32;
 883
 884
 885 #define LOGOP(NAME, HOW) \
 886     case O(NAME,SB): HOW; goto log8;\
 887     case O(NAME, SW): HOW; goto log16;\
 888     case O(NAME,SL): HOW; goto log32;
 889
 890
 891
 892 #if ADEBUG
 893       if (debug)
 894         {
 895           printf ("%x %d %s\n", pc, code->opcode,
 896                   code->op ? code->op->name : "**");
 897         }
 898       cpu.stats[code->opcode]++;
 899
 900 #endif
 901
 902       cycles += code->cycles;
 903       insts++;
 904       switch (code->opcode)
 905         {
 906         case 0:
 907           /*
 908            * This opcode is a fake for when we get to an
 909            * instruction which hasnt been compiled
 910            */
 911           compile (pc);
 912           goto top;
 913           break;
 914
 915
 916         case O (O_SUBX, SB):
 917           rd = fetch (&code->dst);
 918           ea = fetch (&code->src);
 919           ea = -(ea + C);
 920           res = rd + ea;
 921           goto alu8;
 922
 923         case O (O_ADDX, SB):
 924           rd = fetch (&code->dst);
 925           ea = fetch (&code->src);
 926           ea = C + ea;
 927           res = rd + ea;
 928           goto alu8;
 929
 930 #define EA    ea = fetch(&code->src);
 931 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
 932
 933           ALUOP (1, O_SUB, RD_EA;
 934                  ea = -ea;
 935                  res = rd + ea);
 936           ALUOP (1, O_NEG, EA;
 937                  ea = -ea;
 938                  rd = 0;
 939                  res = rd + ea);
 940
 941         case O (O_ADD, SB):
 942           rd = GET_B_REG (code->dst.reg);
 943           ea = fetch (&code->src);
 944           res = rd + ea;
 945           goto alu8;
 946         case O (O_ADD, SW):
 947           rd = GET_W_REG (code->dst.reg);
 948           ea = fetch (&code->src);
 949           res = rd + ea;
 950           goto alu16;
 951         case O (O_ADD, SL):
 952           rd = GET_L_REG (code->dst.reg);
 953           ea = fetch (&code->src);
 954           res = rd + ea;
 955           goto alu32;
 956
 957
 958           LOGOP (O_AND, RD_EA;
 959                  res = rd & ea);
 960
 961           LOGOP (O_OR, RD_EA;
 962                  res = rd | ea);
 963
 964           LOGOP (O_XOR, RD_EA;
 965                  res = rd ^ ea);
 966
 967
 968         case O (O_MOV_TO_MEM, SB):
 969           res = GET_B_REG (code->src.reg);
 970           goto log8;
 971         case O (O_MOV_TO_MEM, SW):
 972           res = GET_W_REG (code->src.reg);
 973           goto log16;
 974         case O (O_MOV_TO_MEM, SL):
 975           res = GET_L_REG (code->src.reg);
 976           goto log32;
 977
 978
 979         case O (O_MOV_TO_REG, SB):
 980           res = fetch (&code->src);
 981           SET_B_REG (code->dst.reg, res);
 982           goto just_flags_log8;
 983         case O (O_MOV_TO_REG, SW):
 984           res = fetch (&code->src);
 985           SET_W_REG (code->dst.reg, res);
 986           goto just_flags_log16;
 987         case O (O_MOV_TO_REG, SL):
 988           res = fetch (&code->src);
 989           SET_L_REG (code->dst.reg, res);
 990           goto just_flags_log32;
 991
 992
 993         case O (O_ADDS, SL):
 994           SET_L_REG (code->dst.reg,
 995                      GET_L_REG (code->dst.reg)
 996                      + code->src.literal);
 997
 998           goto next;
 999
1000         case O (O_SUBS, SL):
1001           SET_L_REG (code->dst.reg,
1002                      GET_L_REG (code->dst.reg)
1003                      - code->src.literal);
1004           goto next;
1005
1006         case O (O_CMP, SB):
1007           rd = fetch (&code->dst);
1008           ea = fetch (&code->src);
1009           ea = -ea;
1010           res = rd + ea;
1011           goto just_flags_alu8;
1012
1013         case O (O_CMP, SW):
1014           rd = fetch (&code->dst);
1015           ea = fetch (&code->src);
1016           ea = -ea;
1017           res = rd + ea;
1018           goto just_flags_alu16;
1019
1020         case O (O_CMP, SL):
1021           rd = fetch (&code->dst);
1022           ea = fetch (&code->src);
1023           ea = -ea;
1024           res = rd + ea;
1025           goto just_flags_alu32;
1026
1027
1028         case O (O_DEC, SB):
1029           rd = GET_B_REG (code->src.reg);
1030           ea = -1;
1031           res = rd + ea;
1032           SET_B_REG (code->src.reg, res);
1033           goto just_flags_inc8;
1034
1035         case O (O_DEC, SW):
1036           rd = GET_W_REG (code->dst.reg);
1037           ea = -code->src.literal;
1038           res = rd + ea;
1039           SET_W_REG (code->dst.reg, res);
1040           goto just_flags_inc16;
1041
1042         case O (O_DEC, SL):
1043           rd = GET_L_REG (code->dst.reg);
1044           ea = -code->src.literal;
1045           res = rd + ea;
1046           SET_L_REG (code->dst.reg, res);
1047           goto just_flags_inc32;
1048
1049
1050         case O (O_INC, SB):
1051           rd = GET_B_REG (code->src.reg);
1052           ea = 1;
1053           res = rd + ea;
1054           SET_B_REG (code->src.reg, res);
1055           goto just_flags_inc8;
1056
1057         case O (O_INC, SW):
1058           rd = GET_W_REG (code->dst.reg);
1059           ea = code->src.literal;
1060           res = rd + ea;
1061           SET_W_REG (code->dst.reg, res);
1062           goto just_flags_inc16;
1063
1064         case O (O_INC, SL):
1065           rd = GET_L_REG (code->dst.reg);
1066           ea = code->src.literal;
1067           res = rd + ea;
1068           SET_L_REG (code->dst.reg, res);
1069           goto just_flags_inc32;
1070
1071
1072 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1073
1074         case O (O_ANDC, SB):
1075           GET_CCR (rd);
1076           ea = code->src.literal;
1077           res = rd & ea;
1078           goto setc;
1079
1080         case O (O_ORC, SB):
1081           GET_CCR (rd);
1082           ea = code->src.literal;
1083           res = rd | ea;
1084           goto setc;
1085
1086         case O (O_XORC, SB):
1087           GET_CCR (rd);
1088           ea = code->src.literal;
1089           res = rd ^ ea;
1090           goto setc;
1091
1092
1093         case O (O_BRA, SB):
1094           if (1)
1095             goto condtrue;
1096           goto next;
1097
1098         case O (O_BRN, SB):
1099           if (0)
1100             goto condtrue;
1101           goto next;
1102
1103         case O (O_BHI, SB):
1104           if ((C || Z) == 0)
1105             goto condtrue;
1106           goto next;
1107
1108
1109         case O (O_BLS, SB):
1110           if ((C || Z))
1111             goto condtrue;
1112           goto next;
1113
1114         case O (O_BCS, SB):
1115           if ((C == 1))
1116             goto condtrue;
1117           goto next;
1118
1119         case O (O_BCC, SB):
1120           if ((C == 0))
1121             goto condtrue;
1122           goto next;
1123
1124         case O (O_BEQ, SB):
1125           if (Z)
1126             goto condtrue;
1127           goto next;
1128         case O (O_BGT, SB):
1129           if (((Z || (N ^ V)) == 0))
1130             goto condtrue;
1131           goto next;
1132
1133
1134         case O (O_BLE, SB):
1135           if (((Z || (N ^ V)) == 1))
1136             goto condtrue;
1137           goto next;
1138
1139         case O (O_BGE, SB):
1140           if ((N ^ V) == 0)
1141             goto condtrue;
1142           goto next;
1143         case O (O_BLT, SB):
1144           if ((N ^ V))
1145             goto condtrue;
1146           goto next;
1147         case O (O_BMI, SB):
1148           if ((N))
1149             goto condtrue;
1150           goto next;
1151         case O (O_BNE, SB):
1152           if ((Z == 0))
1153             goto condtrue;
1154           goto next;
1155
1156         case O (O_BPL, SB):
1157           if (N == 0)
1158             goto condtrue;
1159           goto next;
1160         case O (O_BVC, SB):
1161           if ((V == 0))
1162             goto condtrue;
1163           goto next;
1164         case O (O_BVS, SB):
1165           if ((V == 1))
1166             goto condtrue;
1167           goto next;
1168
1169         case O (O_SYSCALL, SB):
1170           printf ("%c", cpu.regs[2]);
1171           goto next;
1172
1173           OSHIFTS (O_NOT, rd = ~rd);
1174           OSHIFTS (O_SHLL, c = rd & hm;
1175                    rd <<= 1);
1176           OSHIFTS (O_SHLR, c = rd & 1;
1177                    rd = (unsigned int) rd >> 1);
1178           OSHIFTS (O_SHAL, c = rd & hm;
1179                    rd <<= 1);
1180           OSHIFTS (O_SHAR, t = rd & hm;
1181                    c = rd & 1;
1182                    rd >>= 1;
1183                    rd |= t;
1184                    );
1185           OSHIFTS (O_ROTL, c = rd & hm;
1186                    rd <<= 1;
1187                    rd |= C);
1188           OSHIFTS (O_ROTR, c = rd & 1;
1189                    rd = (unsigned int) rd >> 1;
1190                    if (c) rd |= hm;);
1191           OSHIFTS (O_ROTXL, t = rd & hm;
1192                    rd <<= 1;
1193                    rd |= C;
1194                    c = t;
1195                    );
1196           OSHIFTS (O_ROTXR, t = rd & 1;
1197                    rd = (unsigned int) rd >> 1;
1198                    if (C) rd |= hm; c = t;);
1199
1200         case O (O_JMP, SB):
1201           {
1202             pc = fetch (&code->src);
1203             goto end;
1204
1205           }
1206
1207         case O (O_JSR, SB):
1208           {
1209             int tmp;
1210             pc = fetch (&code->src);
1211           call:
1212             tmp = cpu.regs[7];
1213
1214             if (h8300hmode)
1215               {
1216                 tmp -= 4;
1217                 SET_MEMORY_L (tmp, code->next_pc);
1218               }
1219             else
1220               {
1221                 tmp -= 2;
1222                 SET_MEMORY_W (tmp, code->next_pc);
1223               }
1224             cpu.regs[7] = tmp;
1225
1226             goto end;
1227           }
1228         case O (O_BSR, SB):
1229           pc = code->src.literal;
1230           goto call;
1231
1232         case O (O_RTS, SB):
1233           {
1234             int tmp;
1235
1236             tmp = cpu.regs[7];
1237
1238             if (h8300hmode)
1239               {
1240                 pc = GET_MEMORY_L (tmp);
1241                 tmp += 4;
1242               }
1243             else
1244               {
1245                 pc = GET_MEMORY_W (tmp);
1246                 tmp += 2;
1247               }
1248
1249             cpu.regs[7] = tmp;
1250             goto end;
1251           }
1252
1253         case O (O_ILL, SB):
1254           cpu.exception = SIGILL;
1255           goto end;
1256         case O (O_SLEEP, SB):
1257           if ((short) cpu.regs[0] == -255)
1258             cpu.exception = SIGILL;
1259           else
1260             cpu.exception = SIGTRAP;
1261           goto end;
1262         case O (O_BPT, SB):
1263           cpu.exception = SIGTRAP;
1264           goto end;
1265
1266           OBITOP (O_BNOT, 1, 1, ea ^= m);
1267           OBITOP (O_BTST, 1, 0, nz = ea & m);
1268           OBITOP (O_BCLR, 1, 1, ea &= ~m);
1269           OBITOP (O_BSET, 1, 1, ea |= m);
1270           OBITOP (O_BLD, 1, 0, c = ea & m);
1271           OBITOP (O_BILD, 1, 0, c = !(ea & m));
1272           OBITOP (O_BST, 1, 1, ea &= ~m;
1273                   if (C) ea |= m);
1274           OBITOP (O_BIST, 1, 1, ea &= ~m;
1275                   if (!C) ea |= m);
1276           OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1277           OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1278           OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1279           OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1280           OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1281           OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1282
1283
1284 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1285
1286         case O (O_MULS, SB):
1287           MOP (1, 1);
1288           break;
1289         case O (O_MULS, SW):
1290           MOP (0, 1);
1291           break;
1292         case O (O_MULU, SB):
1293           MOP (1, 0);
1294           break;
1295         case O (O_MULU, SW):
1296           MOP (0, 0);
1297           break;
1298
1299
1300         case O (O_DIVU, SB):
1301           {
1302             rd = GET_W_REG (code->dst.reg);
1303             ea = GET_B_REG (code->src.reg);
1304             if (ea)
1305               {
1306                 tmp = rd % ea;
1307                 rd = rd / ea;
1308               }
1309             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1310             n = ea & 0x80;
1311             nz = ea & 0xff;
1312
1313             goto next;
1314           }
1315         case O (O_DIVU, SW):
1316           {
1317             rd = GET_L_REG (code->dst.reg);
1318             ea = GET_W_REG (code->src.reg);
1319             n = ea & 0x8000;
1320             nz = ea & 0xffff;
1321             if (ea)
1322               {
1323                 tmp = rd % ea;
1324                 rd = rd / ea;
1325               }
1326             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1327             goto next;
1328           }
1329
1330         case O (O_DIVS, SB):
1331           {
1332
1333             rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1334             ea = SEXTCHAR (GET_B_REG (code->src.reg));
1335             if (ea)
1336               {
1337                 tmp = (int) rd % (int) ea;
1338                 rd = (int) rd / (int) ea;
1339                 n = rd & 0x8000;
1340                 nz = 1;
1341               }
1342             else
1343               nz = 0;
1344             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1345             goto next;
1346           }
1347         case O (O_DIVS, SW):
1348           {
1349             rd = GET_L_REG (code->dst.reg);
1350             ea = SEXTSHORT (GET_W_REG (code->src.reg));
1351             if (ea)
1352               {
1353                 tmp = (int) rd % (int) ea;
1354                 rd = (int) rd / (int) ea;
1355                 n = rd & 0x80000000;
1356                 nz = 1;
1357               }
1358             else
1359               nz = 0;
1360             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1361             goto next;
1362           }
1363         case O (O_EXTS, SW):
1364           rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst.  */
1365           ea = rd & 0x80 ? -256 : 0;
1366           res = rd + ea;
1367           goto log16;
1368         case O (O_EXTS, SL):
1369           rd = GET_W_REG (code->src.reg) & 0xffff;
1370           ea = rd & 0x8000 ? -65536 : 0;
1371           res = rd + ea;
1372           goto log32;
1373         case O (O_EXTU, SW):
1374           rd = GET_B_REG (code->src.reg + 8) & 0xff;
1375           ea = 0;
1376           res = rd + ea;
1377           goto log16;
1378         case O (O_EXTU, SL):
1379           rd = GET_W_REG (code->src.reg) & 0xffff;
1380           ea = 0;
1381           res = rd + ea;
1382           goto log32;
1383
1384         case O (O_NOP, SB):
1385           goto next;
1386
1387         default:
1388           cpu.exception = SIGILL;
1389           goto end;
1390
1391         }
1392       abort ();
1393
1394     setc:
1395       cpu.ccr = res;
1396       GETSR ();
1397       goto next;
1398
1399     condtrue:
1400       /* When a branch works */
1401       pc = code->src.literal;
1402       goto end;
1403
1404       /* Set the cond codes from res */
1405     bitop:
1406
1407       /* Set the flags after an 8 bit inc/dec operation */
1408     just_flags_inc8:
1409       n = res & 0x80;
1410       nz = res & 0xff;
1411       v = (rd & 0x7f) == 0x7f;
1412       goto next;
1413
1414
1415       /* Set the flags after an 16 bit inc/dec operation */
1416     just_flags_inc16:
1417       n = res & 0x8000;
1418       nz = res & 0xffff;
1419       v = (rd & 0x7fff) == 0x7fff;
1420       goto next;
1421
1422
1423       /* Set the flags after an 32 bit inc/dec operation */
1424     just_flags_inc32:
1425       n = res & 0x80000000;
1426       nz = res & 0xffffffff;
1427       v = (rd & 0x7fffffff) == 0x7fffffff;
1428       goto next;
1429
1430
1431     shift8:
1432       /* Set flags after an 8 bit shift op, carry set in insn */
1433       n = (rd & 0x80);
1434       v = 0;
1435       nz = rd & 0xff;
1436       SET_B_REG (code->src.reg, rd);
1437       goto next;
1438
1439
1440     shift16:
1441       /* Set flags after an 16 bit shift op, carry set in insn */
1442       n = (rd & 0x8000);
1443       v = 0;
1444       nz = rd & 0xffff;
1445
1446       SET_W_REG (code->src.reg, rd);
1447       goto next;
1448
1449     shift32:
1450       /* Set flags after an 32 bit shift op, carry set in insn */
1451       n = (rd & 0x80000000);
1452       v = 0;
1453       nz = rd & 0xffffffff;
1454       SET_L_REG (code->src.reg, rd);
1455       goto next;
1456
1457     log32:
1458       store (&code->dst, res);
1459     just_flags_log32:
1460       /* flags after a 32bit logical operation */
1461       n = res & 0x80000000;
1462       nz = res & 0xffffffff;
1463       v = 0;
1464       goto next;
1465
1466     log16:
1467       store (&code->dst, res);
1468     just_flags_log16:
1469       /* flags after a 16bit logical operation */
1470       n = res & 0x8000;
1471       nz = res & 0xffff;
1472       v = 0;
1473       goto next;
1474
1475
1476     log8:
1477       store (&code->dst, res);
1478     just_flags_log8:
1479       n = res & 0x80;
1480       nz = res & 0xff;
1481       v = 0;
1482       goto next;
1483
1484     alu8:
1485       SET_B_REG (code->dst.reg, res);
1486     just_flags_alu8:
1487       n = res & 0x80;
1488       nz = res & 0xff;
1489       v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80));
1490       c = (res & 0x100);
1491       goto next;
1492
1493     alu16:
1494       SET_W_REG (code->dst.reg, res);
1495     just_flags_alu16:
1496       n = res & 0x8000;
1497       nz = res & 0xffff;
1498       v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000));
1499       c = (res & 0x10000);
1500       goto next;
1501
1502     alu32:
1503       SET_L_REG (code->dst.reg, res);
1504     just_flags_alu32:
1505       n = res & 0x80000000;
1506       nz = res & 0xffffffff;
1507       v = ((ea & 0x80000000) == (rd & 0x80000000))
1508         && ((ea & 0x80000000) != (res & 0x80000000));
1509       switch (code->opcode / 4)
1510         {
1511         case O_ADD:
1512           c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1513           break;
1514         case O_SUB:
1515         case O_CMP:
1516           c = (unsigned) rd < (unsigned) -ea;
1517           break;
1518         case O_NEG:
1519           c = res != 0;
1520           break;
1521         }
1522       goto next;
1523
1524     next:;
1525       pc = code->next_pc;
1526
1527     end:
1528       ;
1529       /*      if (cpu.regs[8] ) abort(); */
1530
1531 #if defined (WIN32)
1532       /* Poll after every 100th insn, */
1533       if (poll_count++ > 100)
1534         {
1535           poll_count = 0;
1536           if (win32pollquit())
1537             {
1538               control_c();
1539             }
1540         }
1541 #endif
1542 #if defined(__GO32__)
1543       /* Poll after every 100th insn, */
1544       if (poll_count++ > 100)
1545         {
1546           poll_count = 0;
1547           if (kbhit ())
1548             {
1549               int c = getkey ();
1550               control_c ();
1551             }
1552         }
1553 #endif
1554
1555     }
1556   while (!cpu.exception);
1557   cpu.ticks += get_now () - tick_start;
1558   cpu.cycles += cycles;
1559   cpu.insts += insts;
1560
1561   cpu.pc = pc;
1562   BUILDSR ();
1563   cpu.mask = oldmask;
1564   signal (SIGINT, prev);
1565 }
1566
1567
1568 int
1569 sim_write (addr, buffer, size)
1570      SIM_ADDR addr;
1571      unsigned char *buffer;
1572      int size;
1573 {
1574   int i;
1575
1576   init_pointers ();
1577   if (addr < 0 || addr + size > memory_size)
1578     return 0;
1579   for (i = 0; i < size; i++)
1580     {
1581       cpu.memory[addr + i] = buffer[i];
1582       cpu.cache_idx[addr + i] = 0;
1583     }
1584   return size;
1585 }
1586
1587 int
1588 sim_read (addr, buffer, size)
1589      SIM_ADDR addr;
1590      unsigned char *buffer;
1591      int size;
1592 {
1593   init_pointers ();
1594   if (addr < 0 || addr + size > memory_size)
1595     return 0;
1596   memcpy (buffer, cpu.memory + addr, size);
1597   return size;
1598 }
1599
1600
1601 #define R0_REGNUM       0
1602 #define R1_REGNUM       1
1603 #define R2_REGNUM       2
1604 #define R3_REGNUM       3
1605 #define R4_REGNUM       4
1606 #define R5_REGNUM       5
1607 #define R6_REGNUM       6
1608 #define R7_REGNUM       7
1609
1610 #define SP_REGNUM       R7_REGNUM       /* Contains address of top of stack */
1611 #define FP_REGNUM       R6_REGNUM       /* Contains address of executing
1612                                            * stack frame */
1613
1614 #define CCR_REGNUM      8       /* Contains processor status */
1615 #define PC_REGNUM       9       /* Contains program counter */
1616
1617 #define CYCLE_REGNUM    10
1618 #define INST_REGNUM     11
1619 #define TICK_REGNUM     12
1620
1621
1622 void
1623 sim_store_register (rn, value)
1624      int rn;
1625      unsigned char *value;
1626 {
1627   int longval;
1628   int shortval;
1629   int intval;
1630   longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1631   shortval = (value[0] << 8) | (value[1]);
1632   intval = h8300hmode ? longval : shortval;
1633
1634   init_pointers ();
1635   switch (rn)
1636     {
1637     case PC_REGNUM:
1638       cpu.pc = intval;
1639       break;
1640     default:
1641       abort ();
1642     case R0_REGNUM:
1643     case R1_REGNUM:
1644     case R2_REGNUM:
1645     case R3_REGNUM:
1646     case R4_REGNUM:
1647     case R5_REGNUM:
1648     case R6_REGNUM:
1649     case R7_REGNUM:
1650       cpu.regs[rn] = intval;
1651       break;
1652     case CCR_REGNUM:
1653       cpu.ccr = intval;
1654       break;
1655     case CYCLE_REGNUM:
1656       cpu.cycles = longval;
1657       break;
1658
1659     case INST_REGNUM:
1660       cpu.insts = longval;
1661       break;
1662
1663     case TICK_REGNUM:
1664       cpu.ticks = longval;
1665       break;
1666     }
1667 }
1668
1669 void
1670 sim_fetch_register (rn, buf)
1671      int rn;
1672      unsigned char *buf;
1673 {
1674   int v;
1675   int longreg = 0;
1676
1677   init_pointers ();
1678
1679   switch (rn)
1680     {
1681     default:
1682       abort ();
1683     case 8:
1684       v = cpu.ccr;
1685       break;
1686     case 9:
1687       v = cpu.pc;
1688       break;
1689     case R0_REGNUM:
1690     case R1_REGNUM:
1691     case R2_REGNUM:
1692     case R3_REGNUM:
1693     case R4_REGNUM:
1694     case R5_REGNUM:
1695     case R6_REGNUM:
1696     case R7_REGNUM:
1697       v = cpu.regs[rn];
1698       break;
1699     case 10:
1700       v = cpu.cycles;
1701       longreg = 1;
1702       break;
1703     case 11:
1704       v = cpu.ticks;
1705       longreg = 1;
1706       break;
1707     case 12:
1708       v = cpu.insts;
1709       longreg = 1;
1710       break;
1711     }
1712   if (h8300hmode || longreg)
1713     {
1714       buf[0] = v >> 24;
1715       buf[1] = v >> 16;
1716       buf[2] = v >> 8;
1717       buf[3] = v >> 0;
1718     }
1719   else
1720     {
1721       buf[0] = v >> 8;
1722       buf[1] = v;
1723     }
1724 }
1725
1726 void
1727 sim_stop_reason (reason, sigrc)
1728      enum sim_stop *reason;
1729      int *sigrc;
1730 {
1731   *reason = sim_stopped;
1732   *sigrc = cpu.exception;
1733 }
1734
1735 sim_csize (n)
1736 {
1737   if (cpu.cache)
1738     free (cpu.cache);
1739   if (n < 2)
1740     n = 2;
1741   cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1742   memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1743   cpu.csize = n;
1744 }
1745
1746
1747 void
1748 sim_info (verbose)
1749      int verbose;
1750 {
1751   double timetaken = (double) cpu.ticks / (double) now_persec ();
1752   double virttime = cpu.cycles / 10.0e6;
1753
1754   printf_filtered ("\n\n#instructions executed  %10d\n", cpu.insts);
1755   printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1756   printf_filtered ("#real time taken        %10.4f\n", timetaken);
1757   printf_filtered ("#virtual time taked     %10.4f\n", virttime);
1758   if (timetaken != 0.0)
1759     printf_filtered ("#simulation ratio       %10.4f\n", virttime / timetaken);
1760   printf_filtered ("#compiles               %10d\n", cpu.compiles);
1761   printf_filtered ("#cache size             %10d\n", cpu.csize);
1762
1763 #ifdef ADEBUG
1764   if (verbose)
1765     {
1766       int i;
1767       for (i = 0; i < O_LAST; i++)
1768         {
1769           if (cpu.stats[i])
1770             printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1771         }
1772     }
1773 #endif
1774 }
1775
1776 /* Indicate whether the cpu is an h8/300 or h8/300h.
1777    FLAG is non-zero for the h8/300h.  */
1778
1779 void
1780 set_h8300h (flag)
1781      int flag;
1782 {
1783   h8300hmode = flag;
1784 }
1785
1786 void
1787 sim_kill ()
1788 {
1789   /* nothing to do */
1790 }
1791
1792 void
1793 sim_open (args)
1794      char *args;
1795 {
1796   /* nothing to do */
1797 }
1798
1799 void
1800 sim_close (quitting)
1801      int quitting;
1802 {
1803   /* nothing to do */
1804 }
1805
1806 /* Called by gdb to load a program into memory.  */
1807
1808 int
1809 sim_load (prog, from_tty)
1810      char *prog;
1811      int from_tty;
1812 {
1813   bfd *abfd;
1814
1815   /* See if the file is for the h8/300 or h8/300h.  */
1816   /* ??? This may not be the most efficient way.  The z8k simulator
1817      does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO).  */
1818   if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1819     {
1820       if (bfd_check_format (abfd, bfd_object))
1821         set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h);
1822       bfd_close (abfd);
1823     }
1824
1825   /* Return non-zero so gdb will handle it.  */
1826   return 1;
1827 }
1828
1829 void
1830 sim_create_inferior (start_address, argv, env)
1831      SIM_ADDR start_address;
1832      char **argv;
1833      char **env;
1834 {
1835   cpu.pc = start_address;
1836 }
1837
1838 void
1839 sim_do_command (cmd)
1840      char *cmd;
1841 {
1842   printf_filtered ("This simulator does not accept any commands.\n");
1843 }
1844
1845
1846
1847 void
1848 sim_set_callbacks (ptr)
1849 struct host_callback_struct *ptr;
1850 {
1851
1852 }
1853