sim/h8300/p1.c

   1 /* H8/300 simulator
   2    Copyright 1992 Free Software Foundation, Inc.
   3
   4    Contributed by Cygnus Support.
   5    Written by Steve Chamberlain   (sac@cygnus.com).
   6
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program; if not, write to the Free Software
  20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 #include <stdio.h>
  23 #include <stdlib.h>
  24 #include <signal.h>
  25
  26 #define SET_WORD_MEM(x,y)  {mem[x] = (y)>>8;mem[x+1] = y;}
  27 #define SET_BYTE_MEM(x,y)  mem[x]=y
  28
  29 #define WORD_MEM(x)  ((mem[x]<<8) | (mem[x+1]))
  30 #define BYTE_MEM(x)  mem[x]
  31
  32
  33 #define PC 9
  34 #define CCR 8
  35
  36 struct state
  37 {
  38   int cycles;
  39   unsigned short int reg[10];
  40   unsigned char *(bregp[16]);
  41   unsigned char *(bregp_NNNNxxxx[256]);
  42   unsigned char *(bregp_xxxxNNNN[256]);
  43   unsigned short int *(wregp_xNNNxxxx[256]);
  44   unsigned short int *(wregp_xxxxxNNN[256]);
  45 }
  46
  47 saved_state;
  48
  49 #define V (v!=0)
  50 #define C (c!=0)
  51 #define N (n!=0)
  52 #define Z (z!=0)
  53
  54 #define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4;  c = x & 0x1;
  55 #define GET_CCR() ((N << 3) |  (Z<<2) | (V<<1) | C)
  56
  57 int exception;
  58
  59 static unsigned char *mem;
  60
  61
  62 static union
  63 {
  64   short int i;
  65   struct
  66     {
  67       char low;
  68       char high;
  69     }
  70
  71   u;
  72 }
  73
  74 littleendian;
  75
  76 static void
  77 meminit ()
  78 {
  79   if (!mem)
  80     {
  81       int tmp;
  82
  83       mem = calloc (1024, 64);
  84       littleendian.i = 1;
  85       /* initialze the array of pointers to byte registers */
  86       for (tmp = 0; tmp < 8; tmp++)
  87         {
  88           if (littleendian.u.high)
  89             {
  90               saved_state.bregp[tmp] = (unsigned char *) (saved_state.reg + tmp);
  91               saved_state.bregp[tmp + 8] = saved_state.bregp[tmp] + 1;
  92             }
  93           else
  94             {
  95               saved_state.bregp[tmp + 8] = (unsigned char *) (saved_state.reg + tmp);
  96               saved_state.bregp[tmp] = saved_state.bregp[tmp + 8] + 1;
  97             }
  98         }
  99
 100       /* we keep two 256 sized pointers to byte regs, one for when we
 101        want to look at the reg descibed by bits NNNNxxxx and one for
 102        when we want to look at xxxxNNNN */
 103       for (tmp = 0; tmp < 256; tmp++)
 104         {
 105           saved_state.bregp_NNNNxxxx[tmp] = saved_state.bregp[(tmp >> 4) & 0xf];
 106           saved_state.bregp_xxxxNNNN[tmp] = saved_state.bregp[tmp & 0xf];
 107         }
 108       /* We keep two 256 sized pointers to word regs, one for regs in
 109        xNNNxxxx and one for regs in xxxxxNNNN */
 110       for (tmp = 0; tmp < 256; tmp++)
 111         {
 112           saved_state.wregp_xNNNxxxx[tmp] = &saved_state.reg[(tmp >> 4) & 0x7];
 113           saved_state.wregp_xxxxxNNN[tmp] = &saved_state.reg[tmp & 0x7];
 114         }
 115
 116     }
 117 }
 118
 119
 120 void
 121 control_c (sig, code, scp, addr)
 122      int sig;
 123      int code;
 124      char *scp;
 125      char *addr;
 126 {
 127   exception = SIGINT;
 128 }
 129
 130 void
 131 sim_store_register (reg, val)
 132 int reg;
 133 int val;
 134 {
 135   saved_state.reg[reg] = val;
 136 }
 137
 138 void
 139 sim_fetch_register (reg, buf)
 140 int reg;
 141 char *buf;
 142 {
 143   meminit();
 144   buf[0] = saved_state.reg[reg] >> 8;
 145   buf[1] = saved_state.reg[reg];
 146 }
 147
 148 void
 149 sim_write (to, from, len)
 150      int to;
 151      char *from;
 152      int len;
 153 {
 154   meminit ();
 155   memcpy (mem + to, from, len);
 156 }
 157
 158 void
 159 sim_read (from, to, len)
 160      int from;
 161      char *to;
 162
 163      int len;
 164 {
 165   meminit ();
 166   memcpy (to, mem + from, len);
 167 }
 168
 169 int
 170 sim_stop_signal ()
 171 {
 172   return exception;
 173 }
 174
 175 void
 176 sim_resume (step, sig)
 177 int step;
 178 int sig;
 179 {
 180   int lval;
 181   int tmp;
 182   int b0;
 183   int b1;
 184   unsigned char **blow;
 185   unsigned char **bhigh;
 186   unsigned short **wlow;
 187   unsigned short **whigh;
 188   unsigned char *npc;
 189   int rn;
 190   unsigned short int *reg;
 191   unsigned char **bregp;
 192   void (*prev) ();
 193   unsigned char *pc;
 194
 195   int srca;
 196   int srcb;
 197   int dst;
 198   int cycles = saved_state.cycles;
 199
 200   int n;
 201   int v;
 202   int z;
 203   int c;
 204
 205   SET_CCR (saved_state.reg[CCR]);
 206   pc = saved_state.reg[PC] + mem;
 207
 208   reg = saved_state.reg;
 209   bregp = saved_state.bregp;
 210   blow = saved_state.bregp_xxxxNNNN;
 211   bhigh = saved_state.bregp_NNNNxxxx;
 212
 213   wlow = saved_state.wregp_xxxxxNNN;
 214   whigh = saved_state.wregp_xNNNxxxx;
 215
 216   prev = signal (SIGINT, control_c);
 217   meminit();
 218   if (step)
 219     exception = SIGTRAP;
 220   else
 221     {
 222       exception = sig;
 223     }
 224   do
 225     {
 226       b0 = pc[0];
 227       b1 = pc[1];
 228
 229