1 /* Main header for the Hitachi h8/300 architecture. */
10 /* These define the size of main memory for the simulator.
12 Note the size of main memory for the H8/300H is only 256k. Keeping it
13 small makes the simulator run much faster and consume less memory.
15 The linker knows about the limited size of the simulator's main memory
16 on the H8/300H (via the h8300h.sc linker script). So if you change
17 H8300H_MSIZE, be sure to fix the linker script too.
19 Also note that there's a separate "eightbit" area aside from main
20 memory. For simplicity, the simulator assumes any data memory reference
21 outside of main memory refers to the eightbit area (in theory, this
22 can only happen when simulating H8/300H programs). We make no attempt
23 to catch overlapping addresses, wrapped addresses, etc etc. */
25 #define H8300_MSIZE (1 << 16)
28 Next 2 macros are ugly for any workstation, but while they're work.
29 Memory size MUST be configurable. */
30 #define H8300H_MSIZE (1 << 24)
31 #define H8300S_MSIZE (1 << 24)
45 SP_REGNUM
= R7_REGNUM
, /* Contains address of top of stack */
46 FP_REGNUM
= R6_REGNUM
, /* Contains address of executing
48 CCR_REGNUM
= 8, /* Contains processor status */
49 PC_REGNUM
= 9, /* Contains program counter */
64 OP_REG
, /* Register direct. */
65 OP_LOWREG
, /* Special reg syntax for "bra". */
66 OP_DISP
, /* Register indirect w/displacement. */
67 /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
68 OP_PREDEC
, /* Register indirect w/pre-decrement. */
69 OP_POSTDEC
, /* Register indirect w/post-decrement. */
70 OP_PREINC
, /* Register indirect w/pre-increment. */
71 OP_POSTINC
, /* Register indirect w/post-increment. */
72 OP_PCREL
, /* PC Relative. */
73 OP_MEM
, /* Absolute memory address. */
74 OP_CCR
, /* Condition Code Register. */
75 OP_IMM
, /* Immediate value. */
76 /*OP_ABS*/ /* Un-used (duplicates op_mem?). */
77 OP_EXR
, /* EXtended control Register. */
78 OP_SBR
, /* Vector Base Register. */
79 OP_VBR
, /* Short-address Base Register. */
80 OP_MACH
, /* Multiply Accumulator - high. */
81 OP_MACL
, /* Multiply Accumulator - low. */
82 /* FIXME: memory indirect? */
83 OP_INDEXB
, /* Byte index mode */
84 OP_INDEXW
, /* Word index mode */
85 OP_INDEXL
/* Long index mode */
88 #include "sim-basics.h"
91 typedef unsigned32 sim_cia
;
95 /* Structure used to describe addressing */
104 /* Struct for instruction decoder. */
115 struct h8_opcode
*op
;
120 unsigned int regs
[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
123 int macS
; /* MAC Saturating mode */
124 int macV
; /* MAC Overflow */
125 int macN
; /* MAC Negative */
126 int macZ
; /* MAC Zero */
129 char **command_line
; /* Pointer to command line arguments. */
131 unsigned char *memory
;
132 unsigned char *eightbit
;
138 /* The sim_state struct. */
140 struct _sim_cpu
*cpu
;
141 unsigned int sim_cache_size
;
142 decoded_inst
*sim_cache
;
143 unsigned short *cache_idx
;
144 unsigned long memory_size
;
153 /* The current state of the processor; registers, memory, etc. */
155 #define CIA_GET(CPU) (cpu_get_pc (CPU))
156 #define CIA_SET(CPU, VAL) (cpu_set_pc ((CPU), (VAL)))
157 #define STATE_CPU(SD, N) ((SD)->cpu) /* Single Processor. */
158 #define cpu_set_pc(CPU, VAL) (((CPU)->pc) = (VAL))
159 #define cpu_get_pc(CPU) (((CPU)->pc))
161 /* Magic numbers used to distinguish an exit from a breakpoint. */
162 #define LIBC_EXIT_MAGIC1 0xdead
163 #define LIBC_EXIT_MAGIC2 0xbeef
164 /* Local version of macros for decoding exit status.
165 (included here rather than try to find target version of wait.h)
167 #define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
168 #define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
169 #define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
170 #define SIM_WSTOPSIG(V) ((V) & 0x7f)
172 #endif /* SIM_MAIN_H */
This page took 0.03366 seconds and 4 git commands to generate.