1 /* CPU family header for i960base.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #ifndef CPU_I960BASE_H
26 #define CPU_I960BASE_H
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 1
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
49 #define GET_H_CC() CPU (h_cc)
50 #define SET_H_CC(x) (CPU (h_cc) = (x))
52 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
55 /* Cover fns for register access. */
56 USI
i960base_h_pc_get (SIM_CPU
*);
57 void i960base_h_pc_set (SIM_CPU
*, USI
);
58 SI
i960base_h_gr_get (SIM_CPU
*, UINT
);
59 void i960base_h_gr_set (SIM_CPU
*, UINT
, SI
);
60 SI
i960base_h_cc_get (SIM_CPU
*);
61 void i960base_h_cc_set (SIM_CPU
*, SI
);
63 /* These must be hand-written. */
64 extern CPUREG_FETCH_FN i960base_fetch_register
;
65 extern CPUREG_STORE_FN i960base_store_register
;
75 /* Instruction argument buffer. */
78 struct { /* no operands */
86 unsigned char out_br_src1
;
92 unsigned char in_br_src2
;
98 unsigned char in_br_src1
;
99 unsigned char in_br_src2
;
106 unsigned char out_dst
;
107 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
114 unsigned char in_src1
;
115 unsigned char out_dst
;
116 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
123 unsigned char in_src2
;
124 unsigned char out_dst
;
125 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
132 unsigned char in_src1
;
133 unsigned char in_src2
;
134 unsigned char out_dst
;
135 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
142 unsigned char in_abase
;
143 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1
;
144 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2
;
145 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3
;
146 unsigned char in_st_src
;
147 } sfmt_stq_indirect_offset
;
153 unsigned char in_abase
;
154 unsigned char out_dst
;
155 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
156 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2
;
157 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3
;
158 } sfmt_ldq_indirect_offset
;
166 unsigned char in_abase
;
167 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1
;
168 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2
;
169 unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3
;
170 unsigned char in_index
;
171 unsigned char in_st_src
;
172 } sfmt_stq_indirect_index_disp
;
180 unsigned char in_abase
;
181 unsigned char in_index
;
182 unsigned char out_dst
;
183 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
184 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2
;
185 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3
;
186 } sfmt_ldq_indirect_index_disp
;
192 unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_1
;
193 unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_2
;
194 unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_3
;
195 unsigned char in_src1
;
196 unsigned char out_dst
;
197 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1
;
198 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2
;
199 unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3
;
203 unsigned char in_h_gr_0
;
204 unsigned char in_h_gr_1
;
205 unsigned char in_h_gr_10
;
206 unsigned char in_h_gr_11
;
207 unsigned char in_h_gr_12
;
208 unsigned char in_h_gr_13
;
209 unsigned char in_h_gr_14
;
210 unsigned char in_h_gr_15
;
211 unsigned char in_h_gr_2
;
212 unsigned char in_h_gr_3
;
213 unsigned char in_h_gr_31
;
214 unsigned char in_h_gr_4
;
215 unsigned char in_h_gr_5
;
216 unsigned char in_h_gr_6
;
217 unsigned char in_h_gr_7
;
218 unsigned char in_h_gr_8
;
219 unsigned char in_h_gr_9
;
220 unsigned char out_h_gr_0
;
221 unsigned char out_h_gr_1
;
222 unsigned char out_h_gr_10
;
223 unsigned char out_h_gr_11
;
224 unsigned char out_h_gr_12
;
225 unsigned char out_h_gr_13
;
226 unsigned char out_h_gr_14
;
227 unsigned char out_h_gr_15
;
228 unsigned char out_h_gr_2
;
229 unsigned char out_h_gr_3
;
230 unsigned char out_h_gr_31
;
231 unsigned char out_h_gr_4
;
232 unsigned char out_h_gr_5
;
233 unsigned char out_h_gr_6
;
234 unsigned char out_h_gr_7
;
235 unsigned char out_h_gr_8
;
236 unsigned char out_h_gr_9
;
241 unsigned char in_abase
;
242 unsigned char in_h_gr_0
;
243 unsigned char in_h_gr_1
;
244 unsigned char in_h_gr_10
;
245 unsigned char in_h_gr_11
;
246 unsigned char in_h_gr_12
;
247 unsigned char in_h_gr_13
;
248 unsigned char in_h_gr_14
;
249 unsigned char in_h_gr_15
;
250 unsigned char in_h_gr_2
;
251 unsigned char in_h_gr_3
;
252 unsigned char in_h_gr_31
;
253 unsigned char in_h_gr_4
;
254 unsigned char in_h_gr_5
;
255 unsigned char in_h_gr_6
;
256 unsigned char in_h_gr_7
;
257 unsigned char in_h_gr_8
;
258 unsigned char in_h_gr_9
;
259 unsigned char out_h_gr_0
;
260 unsigned char out_h_gr_1
;
261 unsigned char out_h_gr_10
;
262 unsigned char out_h_gr_11
;
263 unsigned char out_h_gr_12
;
264 unsigned char out_h_gr_13
;
265 unsigned char out_h_gr_14
;
266 unsigned char out_h_gr_15
;
267 unsigned char out_h_gr_2
;
268 unsigned char out_h_gr_3
;
269 unsigned char out_h_gr_31
;
270 unsigned char out_h_gr_4
;
271 unsigned char out_h_gr_5
;
272 unsigned char out_h_gr_6
;
273 unsigned char out_h_gr_7
;
274 unsigned char out_h_gr_8
;
275 unsigned char out_h_gr_9
;
276 } sfmt_callx_indirect_offset
;
278 /* Writeback handler. */
280 /* Pointer to argbuf entry for insn whose results need writing back. */
281 const struct argbuf
*abuf
;
283 /* x-before handler */
285 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
288 /* x-after handler */
292 /* This entry is used to terminate each pbb. */
294 /* Number of insns in pbb. */
296 /* Next pbb to execute. */
298 SCACHE
*branch_target
;
303 /* The ARGBUF struct. */
305 /* These are the baseclass definitions. */
310 /* ??? Temporary hack for skip insns. */
313 /* cpu specific data follows */
316 union sem_fields fields
;
321 ??? SCACHE used to contain more than just argbuf. We could delete the
322 type entirely and always just use ARGBUF, but for future concerns and as
323 a level of abstraction it is left in. */
326 struct argbuf argbuf
;
329 /* Macros to simplify extraction, reading and semantic code.
330 These define and assign the local vars that contain the insn's fields. */
332 #define EXTRACT_IFMT_EMPTY_VARS \
334 #define EXTRACT_IFMT_EMPTY_CODE \
337 #define EXTRACT_IFMT_MULO_VARS \
348 #define EXTRACT_IFMT_MULO_CODE \
350 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
351 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
352 f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
353 f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
354 f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
355 f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
356 f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
357 f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
358 f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
360 #define EXTRACT_IFMT_MULO1_VARS \
371 #define EXTRACT_IFMT_MULO1_CODE \
373 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
374 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
375 f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
376 f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
377 f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
378 f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
379 f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
380 f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
381 f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
383 #define EXTRACT_IFMT_MULO2_VARS \
394 #define EXTRACT_IFMT_MULO2_CODE \
396 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
397 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
398 f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
399 f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
400 f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
401 f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
402 f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
403 f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
404 f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
406 #define EXTRACT_IFMT_MULO3_VARS \
417 #define EXTRACT_IFMT_MULO3_CODE \
419 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
420 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
421 f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
422 f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
423 f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
424 f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
425 f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
426 f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
427 f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
429 #define EXTRACT_IFMT_LDA_OFFSET_VARS \
437 #define EXTRACT_IFMT_LDA_OFFSET_CODE \
439 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
440 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
441 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
442 f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
443 f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
444 f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
446 #define EXTRACT_IFMT_LDA_INDIRECT_VARS \
455 #define EXTRACT_IFMT_LDA_INDIRECT_CODE \
457 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
458 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
459 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
460 f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
461 f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
462 f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
463 f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
465 #define EXTRACT_IFMT_LDA_DISP_VARS \
474 /* Contents of trailing part of insn. */ \
477 #define EXTRACT_IFMT_LDA_DISP_CODE \
479 word_1 = GETIMEMUSI (current_cpu, pc + 4); \
480 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
481 f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
482 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
483 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
484 f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
485 f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
486 f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
487 f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
489 #define EXTRACT_IFMT_ST_OFFSET_VARS \
497 #define EXTRACT_IFMT_ST_OFFSET_CODE \
499 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
500 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
501 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
502 f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
503 f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
504 f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
506 #define EXTRACT_IFMT_ST_INDIRECT_VARS \
515 #define EXTRACT_IFMT_ST_INDIRECT_CODE \
517 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
518 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
519 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
520 f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
521 f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
522 f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
523 f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
525 #define EXTRACT_IFMT_ST_DISP_VARS \
534 /* Contents of trailing part of insn. */ \
537 #define EXTRACT_IFMT_ST_DISP_CODE \
539 word_1 = GETIMEMUSI (current_cpu, pc + 4); \
540 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
541 f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
542 f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
543 f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
544 f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
545 f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
546 f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
547 f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
549 #define EXTRACT_IFMT_CMPOBE_REG_VARS \
557 #define EXTRACT_IFMT_CMPOBE_REG_CODE \
559 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
560 f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
561 f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
562 f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
563 f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
564 f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
566 #define EXTRACT_IFMT_CMPOBE_LIT_VARS \
574 #define EXTRACT_IFMT_CMPOBE_LIT_CODE \
576 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
577 f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
578 f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
579 f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
580 f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
581 f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
583 #define EXTRACT_IFMT_BNO_VARS \
588 #define EXTRACT_IFMT_BNO_CODE \
590 f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
591 f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); \
592 f_ctrl_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
594 /* Collection of various things for the trace handler to use. */
596 typedef struct trace_record
{
601 #endif /* CPU_I960BASE_H */