1 /* i960 simulator support code
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #define WANT_CPU_I960BASE
28 /* The contents of BUF are in target byte order. */
31 i960base_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
,
35 SETTWI (buf
, a_i960_h_gr_get (current_cpu
, rn
));
40 SETTWI (buf
, a_i960_h_pc_get (current_cpu
));
50 /* The contents of BUF are in target byte order. */
53 i960base_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
,
57 a_i960_h_gr_set (current_cpu
, rn
, GETTWI (buf
));
62 a_i960_h_pc_set (current_cpu
, GETTWI (buf
));
71 /* Cover fns for mach independent register accesses. */
74 a_i960_h_gr_get (SIM_CPU
*current_cpu
, UINT regno
)
76 switch (MACH_NUM (CPU_MACH (current_cpu
)))
78 #ifdef HAVE_CPU_I960BASE
79 case MACH_I960_KA_SA
:
81 return i960base_h_gr_get (current_cpu
, regno
);
89 a_i960_h_gr_set (SIM_CPU
*current_cpu
, UINT regno
, SI newval
)
91 switch (MACH_NUM (CPU_MACH (current_cpu
)))
93 #ifdef HAVE_CPU_I960BASE
94 case MACH_I960_KA_SA
:
96 i960base_h_gr_set (current_cpu
, regno
, newval
);
105 a_i960_h_pc_get (SIM_CPU
*current_cpu
)
107 switch (MACH_NUM (CPU_MACH (current_cpu
)))
109 #ifdef HAVE_CPU_I960BASE
110 case MACH_I960_KA_SA
:
112 return i960base_h_pc_get (current_cpu
);
120 a_i960_h_pc_set (SIM_CPU
*current_cpu
, IADDR newval
)
122 switch (MACH_NUM (CPU_MACH (current_cpu
)))
124 #ifdef HAVE_CPU_I960BASE
125 case MACH_I960_KA_SA
:
127 i960base_h_pc_set (current_cpu
, newval
);
135 #if WITH_PROFILE_MODEL_P
137 /* FIXME: Some of these should be inline or macros. Later. */
139 /* Initialize cycle counting for an insn.
140 FIRST_P is non-zero if this is the first insn in a set of parallel
144 i960base_model_insn_before (SIM_CPU
*cpu
, int first_p
)
148 /* Record the cycles computed for an insn.
149 LAST_P is non-zero if this is the last insn in a set of parallel insns,
150 and we update the total cycle count.
151 CYCLES is the cycle count of the insn. */
154 i960base_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
158 /* Initialize cycle counting for an insn.
159 FIRST_P is non-zero if this is the first insn in a set of parallel
163 i960_model_init_insn_cycles (SIM_CPU
*cpu
, int first_p
)
167 /* Record the cycles computed for an insn.
168 LAST_P is non-zero if this is the last insn in a set of parallel insns,
169 and we update the total cycle count. */
172 i960_model_update_insn_cycles (SIM_CPU
*cpu
, int last_p
)
177 i960_model_record_cycles (SIM_CPU
*cpu
, unsigned long cycles
)
182 i960base_model_mark_get_h_gr (SIM_CPU
*cpu
, ARGBUF
*abuf
)
187 i960base_model_mark_set_h_gr (SIM_CPU
*cpu
, ARGBUF
*abuf
)
191 #endif /* WITH_PROFILE_MODEL_P */
194 i960base_model_i960KA_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
195 int unit_num
, int referenced
)
197 return idesc
->timing
->units
[unit_num
].done
;
201 i960base_model_i960CA_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
202 int unit_num
, int referenced
)
204 return idesc
->timing
->units
[unit_num
].done
;
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