Minor formatting fixes
[deliverable/binutils-gdb.git] / sim / i960 / i960.c
1 /* i960 simulator support code
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 #define WANT_CPU
22 #define WANT_CPU_I960BASE
23
24 #include "sim-main.h"
25 #include "cgen-mem.h"
26 #include "cgen-ops.h"
27
28 /* The contents of BUF are in target byte order. */
29
30 int
31 i960base_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
32 int len)
33 {
34 if (rn < 32)
35 SETTWI (buf, a_i960_h_gr_get (current_cpu, rn));
36 else
37 switch (rn)
38 {
39 case PC_REGNUM :
40 SETTWI (buf, a_i960_h_pc_get (current_cpu));
41 break;
42 default :
43 return 0;
44 }
45
46 return -1; /*FIXME*/
47
48 }
49
50 /* The contents of BUF are in target byte order. */
51
52 int
53 i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
54 int len)
55 {
56 if (rn < 32)
57 a_i960_h_gr_set (current_cpu, rn, GETTWI (buf));
58 else
59 switch (rn)
60 {
61 case PC_REGNUM :
62 a_i960_h_pc_set (current_cpu, GETTWI (buf));
63 break;
64 default :
65 return 0;
66 }
67
68 return -1; /*FIXME*/
69 }
70 \f
71 /* Cover fns for mach independent register accesses. */
72
73 SI
74 a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
75 {
76 switch (MACH_NUM (CPU_MACH (current_cpu)))
77 {
78 #ifdef HAVE_CPU_I960BASE
79 case MACH_I960_KA_SA :
80 case MACH_I960_CA :
81 return i960base_h_gr_get (current_cpu, regno);
82 #endif
83 default :
84 abort ();
85 }
86 }
87
88 void
89 a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
90 {
91 switch (MACH_NUM (CPU_MACH (current_cpu)))
92 {
93 #ifdef HAVE_CPU_I960BASE
94 case MACH_I960_KA_SA :
95 case MACH_I960_CA :
96 i960base_h_gr_set (current_cpu, regno, newval);
97 break;
98 #endif
99 default :
100 abort ();
101 }
102 }
103
104 IADDR
105 a_i960_h_pc_get (SIM_CPU *current_cpu)
106 {
107 switch (MACH_NUM (CPU_MACH (current_cpu)))
108 {
109 #ifdef HAVE_CPU_I960BASE
110 case MACH_I960_KA_SA :
111 case MACH_I960_CA :
112 return i960base_h_pc_get (current_cpu);
113 #endif
114 default :
115 abort ();
116 }
117 }
118
119 void
120 a_i960_h_pc_set (SIM_CPU *current_cpu, IADDR newval)
121 {
122 switch (MACH_NUM (CPU_MACH (current_cpu)))
123 {
124 #ifdef HAVE_CPU_I960BASE
125 case MACH_I960_KA_SA :
126 case MACH_I960_CA :
127 i960base_h_pc_set (current_cpu, newval);
128 break;
129 #endif
130 default :
131 abort ();
132 }
133 }
134 \f
135 #if WITH_PROFILE_MODEL_P
136
137 /* FIXME: Some of these should be inline or macros. Later. */
138
139 /* Initialize cycle counting for an insn.
140 FIRST_P is non-zero if this is the first insn in a set of parallel
141 insns. */
142
143 void
144 i960base_model_insn_before (SIM_CPU *cpu, int first_p)
145 {
146 }
147
148 /* Record the cycles computed for an insn.
149 LAST_P is non-zero if this is the last insn in a set of parallel insns,
150 and we update the total cycle count.
151 CYCLES is the cycle count of the insn. */
152
153 void
154 i960base_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
155 {
156 }
157
158 /* Initialize cycle counting for an insn.
159 FIRST_P is non-zero if this is the first insn in a set of parallel
160 insns. */
161
162 void
163 i960_model_init_insn_cycles (SIM_CPU *cpu, int first_p)
164 {
165 }
166
167 /* Record the cycles computed for an insn.
168 LAST_P is non-zero if this is the last insn in a set of parallel insns,
169 and we update the total cycle count. */
170
171 void
172 i960_model_update_insn_cycles (SIM_CPU *cpu, int last_p)
173 {
174 }
175
176 void
177 i960_model_record_cycles (SIM_CPU *cpu, unsigned long cycles)
178 {
179 }
180
181 void
182 i960base_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
183 {
184 }
185
186 void
187 i960base_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
188 {
189 }
190
191 #endif /* WITH_PROFILE_MODEL_P */
192 \f
193 int
194 i960base_model_i960KA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
195 int unit_num, int referenced)
196 {
197 return idesc->timing->units[unit_num].done;
198 }
199
200 int
201 i960base_model_i960CA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
202 int unit_num, int referenced)
203 {
204 return idesc->timing->units[unit_num].done;
205 }
This page took 0.037562 seconds and 4 git commands to generate.